STK20C04-WF35
更新时间：2024-09-18 06:16:20
品牌：SIMTEK
描述：512 x 8 nvSRAM QuantumTrap⑩ CMOS Nonvolatile Static RAM
概述
规格参数
数据手册STK20C04-WF35 概述
512 x 8 nvSRAM QuantumTrap⑩ CMOS Nonvolatile Static RAM 512 ×8的nvSRAM QuantumTrap⑩ CMOS非易失性静态RAM SRAM
STK20C04-WF35 规格参数
| 是否Rohs认证： | 符合 | 生命周期： | Obsolete |
| 包装说明： | DIP, DIP28,.6 | Reach Compliance Code： | unknown |
| ECCN代码： | EAR99 | HTS代码： | 8542.32.00.41 |
| 风险等级： | 5.79 | Is Samacsys： | N |
| 最长访问时间： | 35 ns | JESD-30 代码： | R-PDIP-T28 |
| JESD-609代码： | e3 | 长度： | 36.83 mm |
| 内存密度： | 4096 bit | 内存集成电路类型： | NON-VOLATILE SRAM |
| 内存宽度： | 8 | 功能数量： | 1 |
| 端子数量： | 28 | 字数： | 512 words |
| 字数代码： | 512 | 工作模式： | ASYNCHRONOUS |
| 最高工作温度： | 70 °C | 最低工作温度： | |
| 组织： | 512X8 | 封装主体材料： | PLASTIC/EPOXY |
| 封装代码： | DIP | 封装等效代码： | DIP28,.6 |
| 封装形状： | RECTANGULAR | 封装形式： | IN-LINE |
| 并行/串行： | PARALLEL | 峰值回流温度（摄氏度）： | 260 |
| 电源： | 5 V | 认证状态： | Not Qualified |
| 座面最大高度： | 4.57 mm | 最大待机电流： | 0.00075 A |
| 子类别： | SRAMs | 最大压摆率： | 0.075 mA |
| 最大供电电压 (Vsup)： | 5.5 V | 最小供电电压 (Vsup)： | 4.5 V |
| 标称供电电压 (Vsup)： | 5 V | 表面贴装： | NO |
| 技术： | CMOS | 温度等级： | COMMERCIAL |
| 端子面层： | Matte Tin (Sn) | 端子形式： | THROUGH-HOLE |
| 端子节距： | 2.54 mm | 端子位置： | DUAL |
| 处于峰值回流温度下的最长时间： | NOT SPECIFIED | 宽度： | 15.24 mm |
| Base Number Matches： | 1 |
STK20C04-WF35 数据手册
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PDF下载STK20C04
512 x 8 nvSRAM
QuantumTrap™ CMOS
Nonvolatile Static RAM
Obsolete - Not Recommend for new Designs
FEATURES
DESCRIPTION
• 25ns, 35ns and 45ns Access Times
• STORE to Nonvolatile Elements Initiated by
Hardware
• RECALL to SRAM Initiated by Hardware or
Power Restore
• Automatic STORE Timing
• 10mA Typical ICC at 200ns Cycle Time
• Unlimited READ, WRITE and RECALL Cycles
• 1,000,000 STORE Cycles to Nonvolatile Ele-
ments
• 100-Year Data Retention over Full Industrial
Temperature Range
• Commercial and Industrial Temperatures
The Simtek STK20C04 is a fast static RAM with a non-
volatile element incorporated in each static memory
cell. The SRAM can be read and written an unlimited
number of times, while independent nonvolatile data
resides in nonvolatile elements. Data may easily be
transferred from the SRAM to the Nonvolatile Elements
(the STORE operation), or from the Nonvolatile Ele-
ments to the SRAM (the RECALL operation), using the
NE pin. Transfers from the Nonvolatile Elements to the
SRAM (the RECALL operation) also take place auto-
matically on restoration of power. The STK20C04
combines the high performance and ease of use of a
fast SRAM with nonvolatile data integrity.
The STK20C04 features industry-standard pinout for
nonvolatile RAMs in a 28-pin 600 mil plastic DIP.
PIN CONFIGURATIONS
BLOCK DIAGRAM
1
NE
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
W
NC
2
Quantum Trap
16 x 256
NC
3
A
A
A
A
A
7
4
A
6
5
4
3
2
8
5
NC
NC
G
NC
E
6
STORE
7
A
A
A
A
5
6
7
8
8
A
9
A
STATIC RAM
ARRAY
1
0
RECALL
10
11
12
13
14
A
DQ
DQ
7
6
5
DQ
0
16 x 256
DQ
DQ
1
2
DQ
DQ
DQ
4
3
V
SS
28 - 600 PDIP
PIN NAMES
DQ0
DQ1
DQ2
DQ3
DQ4
COLUMN I/O
STORE/
RECALL
CONTROL
A
- A
Address Inputs
Write Enable
Data In/Out
0
8
COLUMN DEC
W
DQ - DQ
0
7
E
Chip Enable
Output Enable
Nonvolatile Enable
Power (+ 5V)
Ground
DQ5
DQ6
DQ7
A3 A4
A0 A1 A2
G
NE
G
NE
E
V
V
CC
W
SS
March 2006
1
Document Control # ML0001 rev 0.2
STK20C04
a
ABSOLUTE MAXIMUM RATINGS
Note a: Stresses greater than those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at condi-
tions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rat-
ing conditions for extended periods may affect reliability.
Voltage on Input Relative to Ground. . . . . . . . . . . . . .–0.5V to 7.0V
Voltage on Input Relative to VSS . . . . . . . . . . –0.6V to (VCC + 0.5V)
Voltage on DQ0-7. . . . . . . . . . . . . . . . . . . . . . –0.5V to (VCC + 0.5V)
Temperature under Bias . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W
DC Output Current (1 output at a time, 1s duration). . . . . . . . 15mA
DC CHARACTERISTICS
(V = 5.0V 10%)
CC
COMMERCIAL
INDUSTRIAL
SYMBOL
PARAMETER
UNITS
NOTES
MIN
MAX
MIN
MAX
b
I
Average V
Current
85
75
65
90
75
65
mA
mA
mA
t
t
t
= 25ns
= 35ns
= 45ns
CC
CC
AVAV
AVAV
AVAV
1
c
I
I
Average V
Average V
Current during STORE
3
3
mA
mA
All Inputs Don’t Care, V = max
CC
CC
CC
CC
CC
2
3
b
Current at t
AVAV
= 200ns
W ≥ (V
– 0.2V)
CC
All Others Cycling, CMOS Levels
10
10
5V, 25°C, Typical
d
d
I
Average V Current
25
21
18
26
22
19
mA
mA
mA
t
t
t
= 25ns, E ≥ V
= 35ns, E ≥ V
= 45ns, E ≥ V
SB
SB
CC
(Standby, Cycling TTL Input Levels)
AVAV
AVAV
AVAV
IH
IH
IH
1
2
I
I
I
V
Standby Current
E ≥ (V
– 0.2V)
CC
CC
750
1
750
1
μA
μA
μA
(Standby, Stable CMOS Input Levels)
All Others V ≤ 0.2V or ≥ (V – 0.2V)
IN CC
Input Leakage Current
V
V
= max
CC
ILK
= V to V
IN
SS CC
Off-State Output Leakage Current
V
V
= max
CC
OLK
5
5
= V to V , E or G ≥ V
IN
SS CC IH
V
V
V
V
T
Input Logic “1” Voltage
Input Logic “0” Voltage
Output Logic “1” Voltage
Output Logic “0” Voltage
Operating Temperature
2.2
V
+ .5
2.2
– .5
V
+ .5
V
V
All Inputs
All Inputs
IH
CC
CC
V
– .5
0.8
V
0.8
IL
SS
SS
2.4
2.4
V
I
I
=–4mA
= 8mA
OH
OL
OUT
OUT
0.4
70
0.4
85
V
0
–40
°C
A
Note b: ICC and ICC3 are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
Note c: ICC1 is the average current required for the duration of the STORE cycle (tSTORE ).
Note d: E ≥2VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out.
AC TEST CONDITIONS
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 3V
Input Rise and Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤ 5ns
Input and Output Timing Reference Levels . . . . . . . . . . . . . . . 1.5V
5.0V
Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .See Figure 1
e
480 Ohms
CAPACITANCE
(TA = 25°C, f = 1.0MHz)
SYMBOL
PARAMETER
MAX
UNITS
CONDITIONS
ΔV = 0 to 3V
ΔV = 0 to 3V
OUTPUT
30 pF
C
Input Capacitance
Output Capacitance
8
7
pF
IN
INCLUDING
SCOPE AND
FIXTURE
255 Ohms
C
pF
OUT
Note e: These parameters are guaranteed but not tested.
Figure 1: AC Output Loading
March 2006
2
Document Control # ML0001 rev 0.2
STK20C04
SRAM READ CYCLES #1 & #2
(V = 5.0V 10%)
CC
SYMBOLS
NO.
STK20C04-25 STK20C04-35 STK20C04-45
PARAMETER
UNITS
#1, #2
Alt.
MIN
MAX
MIN
MAX
MIN
MAX
1
2
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Chip Enable Access Time
25
35
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ELQV
ACS
f
Read Cycle Time
25
35
45
AVAV
RC
AA
g
3
Address Access Time
25
10
35
15
45
20
AVQV
4
Output Enable to Data Valid
Output Hold after Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
GLQV
OE
OH
LZ
g
5
5
5
5
5
5
5
AXQX
6
ELQX
h
7
10
10
25
13
13
35
15
15
45
EHQZ
HZ
8
0
0
0
0
0
0
GLQX
OLZ
OHZ
PA
h
9
GHQZ
e
10
11
ELICCH
EHICCL
d, e
PS
Note f: W must be high during SRAM READ cycles and low during SRAM WRITE cycles. NE must be high during entire cycle.
Note g: I/O state assumes E, G < VIL, W > VIH , and NE ≥ VIH; device is continuously selected.
Note h: Measured + 200mV from steady state output voltage.
f, g
SRAM READ CYCLE #1: Address Controlled
2
t
AVAV
ADDRESS
3
t
AVQV
5
t
AXQX
DQ (DATA OUT)
DATA VALID
f
SRAM READ CYCLE #2: E Controlled
2
t
AVAV
ADDRESS
1
11
EHICCL
t
ELQV
t
6
E
t
ELQX
7
t
EHQZ
G
9
t
4
GHQZ
t
GLQV
8
t
GLQX
DQ (DATA OUT)
DATA VALID
10
ELICCH
t
ACTIVE
STANDBY
I
CC
March 2006
3
Document Control # ML0001 rev 0.2
STK20C04
SRAM WRITE CYCLES #1 & #2
(V = 5.0V 10%)
CC
SYMBOLS
NO.
STK20C04-25
STK20C04-35
STK20C04-45
PARAMETER
UNITS
#1
#2
Alt.
MIN
25
20
20
10
0
MAX
MIN
35
25
25
12
0
MAX
MIN
45
30
30
15
0
MAX
12
13
14
15
16
17
18
19
20
21
t
t
t
WC
Write Cycle Time
Write Pulse Width
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
AVAV
t
t
t
WLWH
WLEH
WP
CW
DW
t
t
t
t
Chip Enable to End of Write
Data Set-up to End of Write
Data Hold after End of Write
Address Set-up to End of Write
Address Set-up to Start of Write
Address Hold after End of Write
Write Enable to Output Disable
Output Active after End of Write
ELWH
DVWH
WHDX
ELEH
DVEH
EHDX
t
t
t
t
t
DH
t
t
t
20
0
25
0
30
0
AVWH
AVEH
AW
t
t
t
AS
AVWL
AVEL
t
t
t
0
0
0
WHAX
h, i
EHAX
WR
t
t
10
13
15
WLQZ
WZ
t
t
5
5
5
WHQX
OW
Note i: If W is low when E goes low, the outputs remain in the high-impedance state.
Note j: E or W must be ≥ VIH during address transitions. NE ≥ VIH
.
j
SRAM WRITE CYCLE #1: W Controlled
12
AVAV
t
ADDRESS
19
WHAX
14
ELWH
t
t
E
17
AVWH
t
18
AVWL
t
13
WLWH
t
W
16
WHDX
15
DVWH
t
t
DATA IN
DATA VALID
20
WLQZ
t
21
WHQX
t
HIGH IMPEDANCE
DATA OUT
PREVIOUS DATA
j
SRAM WRITE CYCLE #2: E Controlled
12
AVAV
t
ADDRESS
18
AVEL
19
t
EHAX
14
ELEH
t
t
E
17
AVEH
t
13
WLEH
t
W
16
EHDX
15
DVEH
t
t
DATA IN
DATA VALID
HIGH IMPEDANCE
DATA OUT
March 2006
4
Document Control # ML0001 rev 0.2
STK20C04
MODE SELECTION
E
H
L
L
L
L
W
X
H
L
G
X
L
NE
X
MODE
Not Selected
POWER
Standby
Active
H
H
L
Read SRAM
X
L
Write SRAM
Active
k
H
L
Nonvolatile RECALL
Nonvolatile STORE
Active
H
L
I
CC
2
L
L
L
H
L
H
L
X
No Operation
Active
Note k: An automatic RECALL takes place at power up, starting when VCC exceeds 4.25V and taking tRESTORE
.
STORE CYCLES #1 & #2
(V = 5.0V 10%)
CC
SYMBOLS
NO.
PARAMETER
MIN
MAX
UNITS
#1
#2
Alt.
l
22
23
24
25
26
27
28
t
t
t
t
t
t
STORE Cycle Time
10
ms
ns
ns
ns
ns
ns
ns
WLQX
ELQX
ELNH
STORE
WC
m
STORE Initiation Cycle Time
Output Disable Set-up to NE Fall
Output Disable Set-up to E Fall
NE Set-up
20
0
WLNH
tGHNL
t
t
0
GHEL
t
t
0
NLWL
NLEL
Chip Enable Set-up
0
ELWL
t
Write Enable Set-up
0
WLEL
Note l: Measured with W and NE both returned high, and G returned low. STORE cycles are inhibited below 4.0V.
Note m: Once tWC has been satisfied by NE, G, W and E, the STORE cycle is completed automatically. Any of NE, G, W or E may be used to terminate
the STORE initiation cycle.
Note n: If E is low for any period of time in which W is high while G and NE are low, then a RECALL cycle may be initiated.
n
STORE CYCLE #1: W Controlled
NE
24
GHNL
26
NLWL
23
WLNH
G
t
t
t
W
27
ELWL
t
E
22
WLQX
t
HIGH IMPEDANCE
DQ (DATA OUT)
n
STORE CYCLE #2: E Controlled
26
t
NLEL
NE
25
GHEL
t
G
28
WLEL
t
W
E
23
ELNH
t
22
ELQX
t
HIGH IMPEDANCE
DQ (DATA OUT)
March 2006
5
Document Control # ML0001 rev 0.2
STK20C04
STORE INHIBIT/POWER-UP RECALL
(V = 5.0V + 10%)
CC
SYMBOLS
STK20C04
NO.
PARAMETER
UNITS NOTES
Standard
MIN
MAX
550
10
29
30
31
32
t
t
Power-up RECALL Duration
STORE Cycle Duration
μs
ms
V
o
RESTORE
STORE
V
V
Low Voltage Trigger Level
Low Voltage Reset Level
4.0
4.5
SWITCH
3.6
V
RESET
Note o: tRESTORE starts from the time VCC rises above VSWITCH
.
STORE INHIBIT/POWER-UP RECALL
V
CC
5V
31
V
SWITCH
32
RESET
V
STORE INHIBIT
POWER-UP RECALL
29
RESTORE
t
DQ (DATA OUT)
POWER-UP
BROWN OUT
BROWN OUT
BROWN OUT
RECALL
STORE INHIBIT
STORE INHIBIT
STORE INHIBIT
NO RECALL
NO RECALL
RECALL WHEN
(V DID NOT GO
(V DID NOT GO
V
RETURNS
CC
CC
CC
BELOW V
)
BELOW V
)
ABOVE V
SWITCH
RESET
RESET
March 2006
6
Document Control # ML0001 rev 0.2
STK20C04
RECALL CYCLES #1, #2 & #3
(V = 5.0V 10%)
CC
SYMBOLS
NO.
PARAMETER
MIN
MAX
UNITS
#1
#2
#3
p
33
34
35
36
37
38
39
40
t
t
t
t
t
t
t
t
t
t
t
RECALL Cycle Time
20
μs
ns
ns
ns
ns
ns
ns
μs
NLQX
ELQXR
ELNHR
NLEL
GLQXR
GLNH
NLGL
q
RECALL Initiation Cycle Time
NE Set-up
20
0
NLNH
tGLNL
Output Enable Set-up
Write Enable Set-up
0
GLEL
t
t
t
t
t
t
0
WHNL
ELNL
NLQZ
WHEL
GLEL
WHGL
Chip Enable Set-up
0
ELGL
NE Fall to Outputs Inactive
Power-up RECALL Duration
20
550
RESTORE
Note p: Measured with W and NE both high, and G and E low.
Note q: Once tNLNH has been satisfied by NE, G, W and E, the RECALL cycle is completed automatically. Any of NE, G or E may be used to terminate
the RECALL initiation cycle.
Note r: If W is low at any point in which both E and NE are low and G is high, then a STORE cycle will be initiated instead of a RECALL.
n
RECALL CYCLE #1: NE Controlled
34
NLNH
t
NE
G
36
GLNL
t
W
E
37
WHNL
t
38
ELNL
33
NLQX
t
t
39
NLQZ
t
HIGH IMPEDANCE
DQ (DATA OUT)
n
RECALL CYCLE #2: E Controlled
35
t
NLEL
NE
36
GLEL
t
G
W
E
37
WHEL
34
ELNHR
t
t
33
ELQXR
t
HIGH IMPEDANCE
DQ (DATA OUT)
n, r
RECALL CYCLE #3: G Controlled
35
t
NLGL
NE
G
34
GLNH
t
37
t
WHGL
W
E
38
ELGL
t
33
GLQXR
t
HIGH IMPEDANCE
DQ (DATA OUT)
March 2006
7
Document Control # ML0001 rev 0.2
STK20C04
March 2006
8
Document Control # ML0001 rev 0.2
STK20C04
DEVICE OPERATION
The STK20C04 has two modes of operation: SRAM
NONVOLATILE STORE
mode and nonvolatile mode, determined by the
state of the NE pin. When in SRAM mode, the mem-
ory operates as a standard fast static RAM. While in
nonvolatile mode, data is transferred in parallel from
SRAM to Nonvolatile Elements or from Nonvolatile
Elements to SRAM.
A STORE cycle is performed when NE, E and W and
low and G is high. While any sequence that
achieves this state will initiate a STORE, only W initi-
ation (STORE cycle #1) and E initiation (STORE cycle
#2) are practical without risking an unintentional
SRAM WRITE that would disturb SRAM data. During a
STORE cycle, previous nonvolatile data is erased
and the SRAM contents are then programmed into
nonvolatile elements. Once a STORE cycle is initi-
ated, further input and output are disabled and the
DQ0-7 pins are tri-stated until the cycle is complete.
NOISE CONSIDERATIONS
Note that the STK20C04 is a high-speed memory
and so must have a high-frequency bypass capaci-
tor of approximately 0.1μF connected between VCC
and VSS, using leads and traces that are as short as
possible. As with all high-speed CMOS ICs, normal
careful routing of power, ground and signals will
help prevent noise problems.
If E and G are low and W and NE are high at the end
of the cycle, a READ will be performed and the out-
puts will go active, signaling the end of the STORE.
NONVOLATILE RECALL
SRAM READ
A RECALL cycle is performed when E, G and NE are
low and W is high. Like the STORE cycle, RECALL is
initiated when the last of the four clock signals goes
to the RECALL state. Once initiated, the RECALL
cycle will take tNLQX to complete, during which all
inputs are ignored. When the RECALL completes,
any READ or WRITE state on the input pins will take
effect.
The STK20C04 performs a READ cycle whenever E
and G are low and NE and W are high. The address
specified on pins A0-8 determines which of the 512
data bytes will be accessed. When the READ is initi-
ated by an address transition, the outputs will be
valid after a delay of tAVQV (READ cycle #1). If the
READ is initiated by E or G, the outputs will be valid
at tELQV or at tGLQV, whichever is later (READ cycle #2).
The data outputs will repeatedly respond to address
changes within the tAVQV access time without the need
for transitions on any control input pins, and will
remain valid until another address change or until E
or G is brought high or W or NE is brought low.
Internally, RECALL is a two-step procedure. First, the
SRAM data is cleared, and second, the nonvolatile
information is transferred into the SRAM cells. The
RECALL operation in no way alters the data in the
nonvolatile cells. The nonvolatile data can be
recalled an unlimited number of times.
SRAM WRITE
As with the STORE cycle, a transition must occur on
any one control pin to cause a RECALL, preventing
inadvertent multi-triggering. On power up, once VCC
exceeds 4.25V, a RECALL cycle is automatically ini-
tiated. Due to this automatic RECALL, SRAM opera-
tion cannot commence until tRESTORE after VCC
exceeds 4.25V.
A WRITE cycle is performed whenever E and W are
low and NE is high. The address inputs must be sta-
ble prior to entering the WRITE cycle and must
remain stable until either E or W goes high at the
end of the cycle. The data on pins DQ0-7 will be writ-
ten into the memory if it is valid tDVWH before the end
of a W controlled WRITE or tDVEH before the end of an
E controlled WRITE.
POWER-UP RECALL
It is recommended that G be kept high during the
entire WRITE cycle to avoid data bus contention on
the common I/O lines. If G is left low, internal circuitry
will turn off the output buffers tWLQZ after W goes low.
During power up, or after any low-power condition
(VCC < 3.0V), an internal RECALL request will be
latched. When VCC once again exceeds 4.25V, a
RECALL cycle will automatically be initiated and will
take tRESTORE to complete.
March 2006
9
Document Control # ML0001 rev 0.2
STK20C04
If the STK20C04 is in a WRITE state at the end of
power-up RECALL, the SRAM data will be corrupted.
To help avoid this situation, a 10K Ohm resistor
should be connected either between W and system
LOW AVERAGE ACTIVE POWER
The STK20C04 draws significantly less current
when it is cycled at times longer than 55ns. Figure 2
shows the relationship between ICC and READ cycle
time. Worst-case current consumption is shown for
both CMOS and TTL input levels (commercial tem-
perature range, VCC = 5.5V, 100% duty cycle on
chip enable). Figure 3 shows the same relationship
for WRITE cycles. If the chip enable duty cycle is
less than 100%, only standby current is drawn
when the chip is disabled. The overall average cur-
rent drawn by the STK20C04 depends on the fol-
lowing items: 1) CMOS vs. TTL input levels; 2) the
duty cycle of chip enable; 3) the overall cycle rate
for accesses; 4) the ratio of READs to WRITEs; 5)
the operating temperature; 6) the VCC level; and 7) I/
O loading.
VCC or between E and system VCC.
HARDWARE PROTECT
The STK20C04 offers two levels of protection to
suppress inadvertent STORE cycles. If the control
signals (E, G, W and NE) remain in the STORE con-
dition at the end of a STORE cycle, a second
STORE cycle will not be started. The STORE (or
RECALL) will be initiated only after a transition on
any one of these signals to the required state. In
addition to multi-trigger protection, STOREs are
inhibited when VCC is below 4.0V, protecting
against inadvertent STOREs.
100
80
100
80
60
60
TTL
CMOS
40
40
TTL
20
20
CMOS
200
0
0
50
100
150
50
100
150
200
Cycle Time (ns)
Cycle Time (ns)
Figure 2: ICC (max) Reads
Figure 3: ICC (max) Writes
March 2006
10
Document Control # ML0001 rev 0.2
STK20C04
ORDERING INFORMATION
- W F 45 I
STK20C04
Temperature Range
Blank = Commercial (0 to 70°C)
I = Industrial (–40 to 85°C)
Access Time
25 = 25ns
35 = 35ns
45 = 45ns
Lead Finish
Blank = 85%Sn/15%Pb
F = 100% Sn (Matte Tin)
Package
W = Plastic 28-pin 600 mil DIP
March 2006
11
Document Control # ML0001 rev 0.2
Document Revision History
Revision
0.0
Date
Summary
December 2002
September 2003
February 2006
Replaced 30 nsec device with 25 nsec device.
Added lead-free lead finish
0.1
0.2
Marked as Obsolete, Not recommended for new design.
STK20C04-WF35 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| STK20C04-WF35I | SIMTEK | 512 x 8 nvSRAM QuantumTrap⑩ CMOS Nonvolatile Static RAM | 获取价格 |
|
| STK20C04-WF35I | CYPRESS | Non-Volatile SRAM, 512X8, 35ns, CMOS, PDIP28, 0.600 INCH, PLASTIC, DIP-28 | 获取价格 |
|
| STK20C04-WF45 | SIMTEK | 512 x 8 nvSRAM QuantumTrap⑩ CMOS Nonvolatile Static RAM | 获取价格 |
|
| STK20C04-WF45 | CYPRESS | 512X8 NON-VOLATILE SRAM, 45ns, PDIP28, 0.600 INCH, PLASTIC, DIP-28 | 获取价格 |
|
| STK20C04-WF45I | SIMTEK | 512 x 8 nvSRAM QuantumTrap⑩ CMOS Nonvolatile Static RAM | 获取价格 |
|
| STK20C04-WF45I | CYPRESS | 512X8 NON-VOLATILE SRAM, 45ns, PDIP28, 0.600 INCH, PLASTIC, DIP-28 | 获取价格 |
|
| STK20N06 | STMICROELECTRONICS | 20A, 60V, 0.07ohm, N-CHANNEL, Si, POWER, MOSFET | 获取价格 |
|
| STK20N06(SOT-194) | STMICROELECTRONICS | Power Field-Effect Transistor, 20A I(D), 60V, 0.07ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET | 获取价格 |
|
| STK20N06{SOT-194} | STMICROELECTRONICS | 20A, 60V, 0.07ohm, N-CHANNEL, Si, POWER, MOSFET | 获取价格 |
|
| STK20N3LLH5 | STMICROELECTRONICS | N-channel 30 V, 0.006 Ω, 20 A, PolarPAK® STripFET™V Power MOSFET | 获取价格 |
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