STK22C48-P45I [SIMTEK]
Non-Volatile SRAM, 2KX8, 45ns, CMOS, PDIP28, 0.300 INCH, PLASTIC, DIP-28;
| 型号： | STK22C48-P45I |
| 厂家： | 
SIMTEK CORPORATION |
| 描述： | Non-Volatile SRAM, 2KX8, 45ns, CMOS, PDIP28, 0.300 INCH, PLASTIC, DIP-28 静态存储器 光电二极管 |
| 文件： | 总10页 (文件大小：107K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STK22C48
2K x 8 AutoStore™ nvSRAM
QuantumTrap™ CMOS
Nonvolatile Static RAM
FEATURES
DESCRIPTION
• 20ns, 25ns, 35ns and 45ns Access Times
The Simtek STK22C48 is a fast static RAM with a
nonvolatile, electrically erasable PROM element
incorporated in each static memory cell. The SRAM
can be read and written an unlimited number of
times, while independent, nonvolatile data resides in
EEPROM. Data transfers from the SRAM to the
EEPROM (the STORE operation) can take place
automatically on power down. A 68µF or larger
capacitor tied from VCAP to ground guarantees the
STORE operation, regardless of power-down slew
rate or loss of power from “hot swapping”. Transfers
from the EEPROM to the SRAM (the RECALL opera-
tion) take place automatically on restoration of
power. A hardware STORE may be initiated with the
HSB pin.
• “Hands-off” Automatic STORE with External
68µF Capacitor on Power Down
• STORE to EEPROM Initiated by Hardware or
AutoStore™ on Power Down
• Automatic RECALL on Power Up
• 10mA Typical ICC at 200ns Cycle Time
• Unlimited READ, WRITE and RECALL Cycles
• 1,000,000 STORE Cycles to EEPROM
• 100-Year Data Retention in EEPROM
• Single 5V + 10% Operation
• Not Sensitive to Power On/Off Ramp Rates
• No Data Loss from Undershoot
• Commercial and Industrial Temperatures
• 28-Pin DIP and SOIC Packages
BLOCK DIAGRAM
PIN CONFIGURATIONS
V
CCX
V
CAP
V
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CAP
NC
CCX
W
2
3
A
A
A
A
A
HSB
7
6
5
4
3
2
4
A
POWER
CONTROL
8
EEPROM ARRAY
32 x 512
A
9
NC
G
5
6
7
8
A
A
E
10
A5
A6
A7
A8
A9
STORE
STORE/
RECALL
CONTROL
9
A
1
0
HSB
A
10
11
12
13
14
DQ
DQ
DQ
DQ
DQ
7
6
5
4
3
STATIC RAM
28 - 300 PDIP
28 - 600 PDIP
28 - 300 SOIC
28 - 350 SOIC
DQ
DQ
DQ
V
RECALL
0
1
2
ARRAY
32 x 512
SS
PIN NAMES
DQ
0
COLUMN I/O
DQ
A
- A
Address Inputs
1
0
10
COLUMN DEC
DQ
2
DQ -DQ
0
Data In/Out
7
DQ
3
E
Chip Enable
DQ
4
W
Write Enable
Output Enable
Hardware Store Busy (I/O)
Power (+ 5V)
Capacitor
DQ
5
A
10
A A A A A
4
2
3
0
1
DQ
G
G
6
DQ
7
HSB
E
V
V
V
CCX
CAP
SS
W
Ground
July 1999
3-21
STK22C48
a
ABSOLUTE MAXIMUM RATINGS
Note a: Stresses greater than those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at con-
ditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rat-
ing conditions for extended periods may affect reliability.
Voltage on Input Relative to VSS . . . . . . . . . .–0.6V to (V + 0.5V)
CC
Voltage on DQ0-7 or HSB . . . . . . . . . . . . . . . .–0.5V to (V + 0.5V)
CC
Temperature under Bias. . . . . . . . . . . . . . . . . . . . . .–55°C to 125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .–65°C to 150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W
DC Output Current (1 output at a time, 1s duration) . . . . . . . 15mA
b, f
DC CHARACTERISTICS
(V = 5.0V 10%)
CC
COMMERCIAL
INDUSTRIAL
SYMBOL
PARAMETER
Average V Current
UNITS
NOTES
MIN
MAX
MIN
MAX
c
I
95
85
75
65
N/A
90
75
mA
mA
mA
mA
t
t
t
t
= 20ns
= 25ns
= 35ns
= 45ns
CC
CC
AVAV
AVAV
AVAV
AVAV
1
65
d
c
I
I
Average V Current during STORE
3
3
mA
mA
All Inputs Don’t Care, V = max
CC
CC
CC
2
3
Average V Current at t
CC
= 200ns
W ≥ (V – 0.2V)
CC
AVAV
CC
10
10
5V, 25°C, Typical
All Others Cycling, CMOS Levels
d
4
I
I
Average V
AutoStore™ Cycle
Current during
All Inputs Don’t Care
CC
CAP
2
2
mA
e
e
Average V Current
CC
(Standby, Cycling TTL Input Levels)
30
25
21
18
N/A
26
22
mA
mA
mA
mA
t
t
t
t
= 20ns, E ≥ V
= 25ns, E ≥ V
= 35ns, E ≥ V
= 45ns, E ≥ V
SB
AVAV
AVAV
AVAV
AVAV
IH
IH
IH
IH
1
19
I
I
I
V
Standby Current
E ≥ (V – 0.2V)
CC
SB
CC
2
1.5
1
1.5
1
mA
µA
µA
(Standby, Stable CMOS Input Levels)
All Others V ≤ 0.2V or ≥ (V – 0.2V)
IN CC
Input Leakage Current
V = max
CC
ILK
V
= V to V
CC
IN
SS
Off-State Output Leakage Current
V = max
CC
OLK
5
5
V
= V to V , E or G ≥ V
IH
IN
SS
CC
V
V
V
V
V
T
Input Logic “1” Voltage
2.2
V
+ .5
2.2
– .5
V + .5
CC
V
V
All Inputs
All Inputs
IH
CC
Input Logic “0” Voltage
V
– .5
0.8
V
0.8
IL
SS
SS
Output Logic “1” Voltage
Output Logic “0” Voltage
Logic “0” Voltage on HSB Output
Operating Temperature
2.4
2.4
V
I
I
I
=– 4mA except HSB
= 8mA except HSB
= 3mA
OH
OL
BL
OUT
OUT
OUT
0.4
0.4
70
0.4
0.4
85
V
V
0
–40
°C
A
Note b: The STK22C48-20 requires V = 5.0V 5% supply to operate at specified speed.
CC
Note c: ICC and ICC are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
Note d: ICC1 and ICC3 are the average currents required for the duration of the respective STORE cycles (tSTORE ).
2
4
Note e: E ≥ VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out.
Note f: reference levels throughout this datasheet refer to V if that is where the power supply connection is made, or V
V
if V
is con-
CCX
CC
CCX
CAP
nected to ground.
5.0V
AC TEST CONDITIONS
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to 3V
Input Rise and Fall Times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .≤ 5ns
Input and Output Timing Reference Levels . . . . . . . . . . . . . . . 1.5V
Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1
480 Ohms
OUTPUT
30 pF
255 Ohms
g
CAPACITANCE
(T = 25°C, f = 1.0MHz)
INCLUDING
SCOPE AND
FIXTURE
A
SYMBOL
PARAMETER
MAX
UNITS
CONDITIONS
∆V = 0 to 3V
∆V = 0 to 3V
C
IN
Input Capacitance
Output Capacitance
8
7
pF
C
pF
OUT
Figure 1: AC Output Loading
Note g: These parameters are guaranteed but not tested.
July 1999
3-22
STK22C48
b, f
SRAM READ CYCLES #1 & #2
(V = 5.0V 10%)
CC
SYMBOLS
STK22C48-20
STK22C48-25
STK22C48-35
STK22C48-45
NO.
PARAMETER
UNITS
#1, #2
Alt.
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
1
2
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Chip Enable Access Time
Read Cycle Time
20
25
35
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ELQV
ACS
RC
AA
h
20
25
35
45
AVAV
i
3
Address Access Time
22
8
25
10
35
15
45
20
AVQV
4
Output Enable to Data Valid
Output Hold after Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
GLQV
OE
OH
LZ
i
5
5
5
5
5
5
5
5
5
AXQX
6
ELQX
j
7
7
7
10
10
25
13
13
35
15
15
45
EHQZ
HZ
8
0
0
0
0
0
0
0
0
GLQX
OLZ
OHZ
PA
j
9
GHQZ
g
g
10
11
ELICCH
EHICCL
25
PS
Note h: W and HSB must be high during SRAM READ cycles.
Note i: Device is continuously selected with E and G both low.
Note j: Measured 200mV from steady state output voltage.
h, i
SRAM READ CYCLE #1: Address Controlled
2
AVAV
t
ADDRESS
3
AVQV
t
5
t
AXQX
DQ (DATA OUT)
DATA VALID
h
SRAM READ CYCLE #2: E Controlled
2
t
AVAV
ADDRESS
E
1
11
t
ELQV
t
EHICCL
6
t
ELQX
7
t
EHQZ
G
9
t
4
GHQZ
t
GLQV
8
t
GLQX
Q (DATA OUT)
DATA VALID
10
ELICCH
t
ACTIVE
STANDBY
I
CC
July 1999
3-23
STK22C48
b, f
SRAM WRITE CYCLES #1 & #2
(V = 5.0V 10%)
CC
SYMBOLS
STK22C48-20 STK22C48-25 STK22C48-35 STK22C48-45
NO.
PARAMETER
UNITS
#1
#2
Alt.
MIN
20
15
15
8
MAX
MIN
25
20
20
10
0
MAX
MIN
35
25
25
12
0
MAX
MIN
45
30
30
15
0
MAX
12
13
14
15
16
17
18
19
20
21
t
t
t
WC
Write Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
AVAV
t
t
t
Write Pulse Width
WLWH
WLEH
WP
CW
DW
t
t
t
t
Chip Enable to End of Write
Data Set-up to End of Write
Data Hold after End of Write
Address Set-up to End of Write
Address Set-up to Start of Write
Address Hold after End of Write
Write Enable to Output Disable
Output Active after End of Write
ELWH
DVWH
WHDX
ELEH
DVEH
EHDX
t
t
t
t
t
0
DH
AW
t
t
t
15
0
20
0
25
0
30
0
AVWH
AVEH
t
t
t
AS
AVWL
AVEL
t
t
t
0
0
0
0
WHAX
EHAX
WR
j, k
t
t
7
10
13
15
WLQZ
WZ
t
t
5
5
5
5
WHQX
OW
Note k: If W is low when E goes low, the outputs remain in the high-impedance state.
Note l: E or W must be ≥ VIH during address transitions.
Note m: HSB must be high during SRAM WRITE cycles.
l, m
SRAM WRITE CYCLE #1: W Controlled
12
t
AVAV
ADDRESS
19
WHAX
14
ELWH
t
t
E
17
AVWH
t
18
AVWL
t
13
WLWH
W
t
15
DVWH
16
WHDX
t
t
DATA IN
DATA VALID
20
WLQZ
t
21
WHQX
t
HIGH IMPEDANCE
DATA OUT
PREVIOUS DATA
l, m
SRAM WRITE CYCLE #2: E Controlled
12
AVAV
t
ADDRESS
14
ELEH
18
AVEL
19
EHAX
t
t
t
E
17
AVEH
t
13
WLEH
t
W
15
DVEH
16
EHDX
t
t
DATA IN
DATA VALID
HIGH IMPEDANCE
DATA OUT
July 1999
3-24
STK22C48
HARDWARE MODE SELECTION
E
H
L
W
X
H
L
HSB
A
- A (hex)
0
MODE
Not Selected
I/O
POWER
NOTES
12
H
X
X
X
X
Output High Z
Output Data
Input Data
Standby
Active
H
Read SRAM
o
n
L
H
Write SRAM
Active
X
X
L
Nonvolatile STORE
Output High Z
l
CC
2
Note n: HSB STORE operation occurs only if an SRAM write has been done since the last nonvolatile cycle. After the STORE (if any) completes, the
part will go into standby mode, inhibiting all operations until HSB rises.
Note o: I/O state assumes G < V . Activation of nonvolatile cycles does not depend on state of G.
IL
b, f
HARDWARE STORE CYCLE
(V = 5.0V 10%)
CC
SYMBOLS
NO.
STK22C48
PARAMETER
UNITS NOTES
Standard
Alternate
MIN
1
MAX
22
23
24
25
26
t
t
t
t
t
t
t
t
STORE Cycle Duration
10
ms
µs
ns
ns
ns
j, p
j, q
p, r
STORE
DELAY
RECOVER
HLHX
HLHZ
HLQZ
HHQX
Time Allowed to Complete SRAM Cycle
Hardware STORE High to Inhibit Off
Hardware STORE Pulse Width
700
300
15
Hardware STORE Low to Store Busy
HLBL
Note p: E and G low for output behavior.
Note q: E and G low and W high for output behavior.
Note r: is only applicable after t is complete.
t
RECOVER
STORE
HARDWARE STORE CYCLE
25
HLHX
t
HSB (IN)
24
RECOVER
t
22
STORE
t
26
HLBL
t
HSB (OUT)
HIGH IMPEDANCE
HIGH IMPEDANCE
DATA VALID
23
DELAY
t
DQ (DATA OUT)
DATA VALID
July 1999
3-25
STK22C48
b, f
AutoStore™ / POWER-UP RECALL
(V = 5.0V 10%)
CC
SYMBOLS
NO.
STK22C48
PARAMETER
UNITS NOTES
Standard
Alternate
MIN
MAX
550
10
27
28
29
30
31
32
t
Power-up RECALL Duration
STORE Cycle Duration
µs
ms
ns
µs
V
s
p, q, t
m
RESTORE
t
t
t
t
STORE
VSBL
HLHZ
BLQZ
Low Voltage Trigger (V
) to HSB Low
300
SWITCH
t
Time Allowed to Complete SRAM Cycle
Low Voltage Trigger Level
1
p
DELAY
V
V
4.0
4.5
3.9
SWITCH
Low Voltage Reset Level
V
RESET
Note s:
t
starts from the time V rises above V
.
RESTORE
CC
SWITCH
Note t: HSB is asserted low for 1µs when V
drops through V
. If an SRAM write has not taken place since the last nonvolatile cycle, HSB will
SWITCH
CAP
be released and no STORE will take place.
AutoStore™ / POWER-UP RECALL
V
CC
31
SWITCH
V
32
V
RESET
TM
AutoStore
POWER-UP RECALL
29
VSBL
28
STORE
27
RESTORE
t
t
t
HSB
30
DELAY
t
W
DQ (DATA OUT)
POWER-UP
BROWN OUT
BROWN OUT
BROWN OUT
RECALL
NO STORE
AutoStore™
AutoStore™
(NO SRAM WRITES)
NO RECALL
NO RECALL
RECALL WHEN
(V DID NOT GO
(V DID NOT GO
V
RETURNS
CC
CC
CC
BELOW V
)
BELOW V
)
ABOVE V
SWITCH
RESET
RESET
July 1999
3-26
STK22C48
DEVICE OPERATION
The STK22C48 has two separate modes of opera-
POWER-UP RECALL
tion: SRAM mode and nonvolatile mode. In SRAM
mode, the memory operates as a standard fast
static RAM. In nonvolatile mode, data is transferred
from SRAM to EEPROM (the STORE operation) or
from EEPROM to SRAM (the RECALL operation). In
this mode SRAM functions are disabled.
During power up, or after any low-power condition
(VCAP < VRESET), an internal RECALL request will be
latched. When VCAP once again exceeds the sense
voltage of VSWITCH, a RECALL cycle will automatically
be initiated and will take tRESTORE to complete.
If the STK22C48 is in a WRITE state at the end of
power-up RECALL, the SRAM data will be corrupted.
To help avoid this situation, a 10K Ohm resistor
should be connected either between W and system
NOISE CONSIDERATIONS
The STK22C48 is a high-speed memory and so
must have a high-frequency bypass capacitor of
approximately 0.1µF connected between VCAP and
VSS, using leads and traces that are as short as pos-
sible. As with all high-speed CMOS ICs, normal care-
ful routing of power, ground and signals will help
prevent noise problems.
VCC or between E and system VCC.
AutoStore™ OPERATION
The STK22C48 can be powered in one of three
modes.
SRAM READ
During normal AutoStore™ operation, the
STK22C48 will draw current from VCCX to charge a
capacitor connected to the VCAP pin. This stored
charge will be used by the chip to perform a single
STORE operation. After power up, when the voltage
on the VCAP pin drops below VSWITCH, the part will
automatically disconnect the VCAP pin from VCCX and
initiate a STORE operation.
The STK22C48 performs a READ cycle whenever E
and G are low and W and HSB are high. The
address specified on pins A0-10 determines which of
the 2,048 data bytes will be accessed. When the
READ is initiated by an address transition, the out-
puts will be valid after a delay of tAVQV (READ cycle
#1). If the READ is initiated by E or G, the outputs will
be valid at tELQV or at tGLQV, whichever is later (READ
cycle #2). The data outputs will repeatedly respond
to address changes within the tAVQV access time with-
out the need for transitions on any control input pins,
and will remain valid until another address change or
until E or G is brought high, or W or HSB is brought
low.
Figure 2 shows the proper connection of capacitors
for automatic store operation. A charge storage
capacitor having a capacity of between 68µF and
220µF ( 20%) rated at 6V should be provided.
In system power mode (Figure 3), both VCCX and
VCAP are connected to the + 5V power supply without
the 68µF capacitor. In this mode the AutoStore™
function of the STK22C48 will operate on the stored
system charge as power goes down. The user must,
however, guarantee that VCCX does not drop below
3.6V during the 10ms STORE cycle.
SRAM WRITE
A WRITE cycle is performed whenever E and W are
low and HSB is high. The address inputs must be
stable prior to entering the WRITE cycle and must
remain stable until either E or W goes high at the
end of the cycle. The data on the common I/O pins
DQ0-7 will be written into the memory if it is valid tDVWH
before the end of a W controlled WRITE or tDVEH
before the end of an E controlled WRITE.
If an automatic STORE on power loss is not required,
then VCCX can be tied to ground and + 5V applied to
VCAP (Figure 4). This is the AutoStore™ Inhibit
mode, in which the AutoStore™ function is disabled.
If the STK22C48 is operated in this configuration,
references to VCCX should be changed to VCAP
throughout this data sheet. In this mode, STORE
operations may be triggered with the HSB pin. It is
not permissable to change between these three
options “on the fly”.
It is recommended that G be kept high during the
entire WRITE cycle to avoid data bus contention on
common I/O lines. If G is left low, internal circuitry
will turn off the output buffers tWLQZ after W goes low.
July 1999
3-27
STK22C48
In order to prevent unneeded STORE operations,
automatic STOREs as well as those initiated by
externally driving HSB low will be ignored unless at
least one WRITE operation has taken place since the
most recent STORE or RECALL cycle. An optional
pull-up resistor is shown connected to HSB. This
can be used to signal the system that the
AutoStore™ cycle is in progress.
operate in this mode the HSB pin should be con-
nected together to the HSB pins from the other
STK22C48s. An external pull-up resistor to + 5V is
required since HSB acts as an open drain pull down.
The VCAP pins from the other STK22C48 parts can
be tied together and share a single capacitor. The
capacitor size must be scaled by the number of
devices connected to it. When any one of the
STK22C48s detects a power loss and asserts HSB,
the common HSB pin will cause all parts to request
a STORE cycle (a STORE will take place in those
STK22C48s that have been written since the last
nonvolatile cycle).
HSB OPERATION
The STK22C48 provides the HSB pin for controlling
and acknowledging the STORE operations. The HSB
pin is used to request a hardware STORE cycle.
When the HSB pin is driven low, the STK22C48 will
During any STORE operation, regardless of how it
was initiated, the STK22C48 will continue to drive
the HSB pin low, releasing it only when the STORE is
complete. Upon completion of the STORE operation
the STK22C48 will remain disabled until the HSB
pin returns high.
conditionally initiate a STORE operation after tDELAY
;
an actual STORE cycle will only begin if a WRITE to
the SRAM took place since the last STORE or
RECALL cycle. The HSB pin acts as an open drain
driver that is internally driven low to indicate a busy
condition while the STORE (initiated by any means)
is in progress.
If HSB is not used, it should be left unconnected.
SRAM READ and WRITE operations that are in
progress when HSB is driven low by any means are
given time to complete before the STORE operation
is initiated. After HSB goes low, the STK22C48 will
PREVENTING STORES
The STORE function can be disabled on the fly by
holding HSB high with a driver capable of sourcing
30mA at a VOH of at least 2.2V, as it will have to
overpower the internal pull-down device that drives
HSB low for 20µs at the onset of a STORE. When
the STK22C48 is connected for AutoStore™ opera-
tion (system VCC connected to VCCX and a 68µF
capacitor on VCAP) and VCC crosses VSWITCH on the
way down, the STK22C48 will attempt to pull HSB
low; if HSB doesn’t actually get below VIL, the part
continue SRAM operations for tDELAY. During tDELAY
,
multiple SRAM READ operations may take place. If a
WRITE is in progress when HSB is pulled low it will
be allowed a time, tDELAY, to complete. However, any
SRAM WRITE cycles requested after HSB goes low
will be inhibited until HSB returns high.
The HSB pin can be used to synchronize multiple
STK22C48s while using a single larger capacitor. To
1
28
27
26
1
28
27
26
1
28
27
26
+
15
14
14
15
15
14
Figure 2: AutoStore™ Mode
Figure 3: System Power Mode
Figure 4: AutoStore™
Inhibit Mode
*If HSB is not used, it should be left unconnected.
July 1999
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STK22C48
will stop trying to pull HSB low and abort the STORE
attempt.
LOW AVERAGE ACTIVE POWER
The STK22C48 draws significantly less current
when it is cycled at times longer than 50ns. Figure 5
shows the relationship between ICC and READ cycle
time. Worst-case current consumption is shown for
both CMOS and TTL input levels (commercial tem-
perature range, VCC = 5.5V, 100% duty cycle on chip
enable). Figure 6 shows the same relationship for
WRITE cycles. If the chip enable duty cycle is less
than 100%, only standby current is drawn when the
chip is disabled. The overall average current drawn
by the STK22C48 depends on the following items:
1) CMOS vs. TTL input levels; 2) the duty cycle of
chip enable; 3) the overall cycle rate for accesses;
4) the ratio of READs to WRITEs; 5) the operating
HARDWARE PROTECT
The STK22C48 offers hardware protection against
inadvertent STORE operation and SRAM WRITEs dur-
ing low-voltage conditions. When VCAP < VSWITCH, all
externally initiated STORE operations and SRAM
WRITEs are inhibited.
AutoStore™ can be completely disabled by tying
VCCX to ground and applying + 5V to VCAP . This is the
AutoStore™ Inhibit mode; in this mode STOREs are
only initiated by explicit request using the HSB pin.
temperature; 6) the V level; and 7) I/O loading.
cc
100
80
100
80
60
60
TTL
CMOS
40
40
TTL
20
20
CMOS
150 200
0
0
50
100
Cycle Time (ns)
50
100
150
200
Cycle Time (ns)
Figure 5: Icc (max) Reads
Figure 6: Icc (max) Writes
July 1999
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STK22C48
ORDERING INFORMATION
STK22C48 - P 45 I
Temperature Range
Blank = Commercial (0 to 70°C)
I = Industrial (-40 to 85°C)
Access Time
20 = 20ns (Commercial only)
25 = 25ns
35 = 35ns
45 = 45ns
Package
P = Plastic 28-pin 300 mil DIP
W = Plastic 28-pin 600 mil DIP
N = Plastic 28-pin 300 mil SOIC
S = Plastic 28-pin 350 mil SIOC
July 1999
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