U621708DK07G1 [SIMTEK]
Standard SRAM, 128KX8, 70ns, CMOS, PDIP32, 0.600 INCH, LEAD FREE, PLASTIC, DIP-32;型号: | U621708DK07G1 |
厂家: | SIMTEK CORPORATION |
描述: | Standard SRAM, 128KX8, 70ns, CMOS, PDIP32, 0.600 INCH, LEAD FREE, PLASTIC, DIP-32 静态存储器 光电二极管 内存集成电路 |
文件: | 总10页 (文件大小:165K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
U621708
128K x 8 SRAM
Features
Description
The U621708 is a static RAM
manufactured using a CMOS pro-
cess technology with the following
operating modes:
S 131072 x 8 bit static CMOS RAM
S 70 ns Access Time
S Common data inputs and
data outputs
available at the outputs DQ0-DQ7.
After the address change, the data
outputs go High-Z until the new
information is available. The data
outputs have no preferred state. If
the memory is driven by CMOS
levels in the active state, and if
there is no change of the address,
data input and control signals W or
G, the operating current (IO = 0 mA)
drops to the value of the operating
current in the Standby mode. The
Read cycle is finished by the falling
edge of E2 or W, or by the rising
edge of E1, respectively.
- Read
- Write
- Standby
S Three-state outputs
S Typ. operating supply current
70 ns: 15 mA
- Data Retention
The memory array is based on a
6-Transistor cell.
S Standby current < 1 mA at 85°C
S TTL/CMOS-compatible
S Power supply voltage 5 V
S Operating temperature range
0 °C to 70 °C
The circuit is activated by the rising
edge of E2 (at E1 = L), or the falling
edge of E1 (at E2 = H). The
address and control inputs open
simultaneously. According to the
information of W and G, the data
inputs, or outputs, are active.
During the active state (E1 = L and
E2 = H) each address change
leads to a new Read cycle. In a
Read cycle, the data outputs are
activated by the falling edge of G,
afterwards the data word will be
-40 °C to 85 °C
S QS 9000 Quality Standard
S ESD protection > 750 V
(MIL STD 883C M3015.7)
S Latch-up immunity >100 mA
S Package: PDIP32 (600 mil)
SOP32 (450 mil)
Data retention is guaranteed down
to 2 V. With the exception of E1
and E2, all inputs consist of NOR
gates, so that no pull-up/pull-down
resistors are required.
TSOP I 32
sTSOP I 32
Pin Configuration
Pin Description
1
32
31
30
29
28
27
26
25
24
23
22
21
20
VCC
A15
E2
1
32
31
30
29
28
27
26
25
24
23
22
21
20
G
n.c.
A16
A14
A12
A7
A11
A9
2
2
A10
E1
3
A8
3
4
A13
W
4
W
DQ7
DQ6
DQ5
DQ4
DQ3
Signal Name Signal Description
5
A13
A8
5
A0 - A16
DQ0 - DQ7
Address Inputs
Data In/Out
A6
6
E2
6
A5
7
A9
A15
VCC
n.c.
A16
A14
A12
A7
7
Chip Enable 1
Chip Enable 2
Output Enable
Write Enable
Power Supply Voltage
Ground
E1
E2
G
TSOP
PDIP
SOP
A4
8
A11
8
sTSOP
A3
9
9
G
A10
VSS
DQ2
A2
10
11
12
13
14
15
16
10
11
12
13
14
15
16
W
A1
E1
DQ7
DQ1
DQ0
VCC
VSS
n.c.
A0
DQ0
DQ1
DQ2
VSS
DQ6
DQ5
DQ4
DQ3
A0
A1
A2
A3
not connected
19
18
17
A6
19
18
17
A5
A4
Top View
Top View
1
September 1, 2004
U621708
Block Diagram
A0
A1
A2
A3
A4
A5
A6
A7
A8
A16
Memory Cell
Array
1024 Rows x
128 x 8 Columns
A10
A11
A12
DQ0
DQ1
DQ2
Sense Amplifier/
A13
A14
A9
Write Control Logic
DQ3
DQ4
DQ5
A15
Address
Change
Detector
Clock
DQ6
DQ7
Generator
VCC
VSS
E1 E2
W
G
Truth Table
Operating Mode
E1
E2
W
G
DQ0 - DQ7
*
H
L
L
L
L
*
*
*
*
*
High-Z
High-Z
Standby/not selected
Internal Read
Read
H
H
H
H
H
L
H
L
*
High-Z
Data Outputs Low-Z
Data Inputs High-Z
Write
H or L
*
2
September 1, 2004
U621708
Characteristics
All voltages are referenced to VSS = 0 V (ground).
All characteristics are valid in the power supply voltage range and in the operating temperature range specified.
Dynamic measurements are based on a rise and fall time of ≤ 5 ns, measured between 10 % and 90 % of VI, as well as
input levels of VIL = 0 V and VIH = 3 V. The timing reference level of all input and output signals is 1.5 V,
with the exception of the tdis-times and ten-times, in which cases transition is measured ±200 mV from steady-state voltage.
a
Absolute Maximum Ratings
Symbol
Min.
Max.
Unit
Power Supply Voltage
Input Voltage
VCC
VI
-0.5
-0.5
-0.5
-
7
VCC + 0.5
VCC + 0.5
1
V
V
b
b
Output Voltage
VO
PD
Ta
V
Power Dissipation
Operating Temperature
W
°C
C-Type
K-Type
0
70
85
-40
Storage Temperature
Tstg
-65
150
°C
Output Short-Circuit Current
| IOS
|
200
mA
c
at VCC = 5 V and VO = 0 V
a
Stresses greater than those listed under „Absolute Maximum Ratings“ may cause permanent damage to the device. This is a stress rating
only, and functional operation of the device at condition above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability
b
c
Maximum voltage is 7 V
Not more than 1 output should be shorted at the same time. Duration of the short circuit should not exceed 30 s.
Recommended
Symbol
VCC
Conditions
Min.
4.5
Max.
5.5
Unit
V
Operating Conditions
Power Supply Voltage
*
Input Low Voltage
VIL
-0.3
2.2
0.8
V
Input High Voltage
VIH
VCC + 0.3
V
d
-2 V at Pulse Width 10 ns
September 1, 2004
3
U621708
Electrical Characteristics
Symbol
Conditions
Min.
Max.
Unit
Supply Current - Operating Mode
ICC(OP)
VCC
VIL
= 5.5 V
= 0.8 V
= 2.2 V
30
mA
VIH
Supply Current - Standby Mode
(CMOS level)
ICC(SB)
VCC
= 5.5 V
1
mA
mA
V
= V
= VCC - 0.2 V
E1
E2
VCC
= V
Supply Current - Standby Mode
(TTL level)
ICC(SB)1
= 5.5 V
= 2.2 V
10
V
E1
E2
Output High Voltage
Output Low Voltage
VOH
VOL
VCC
IOH
VCC
IOL
= 4.5 V
2.4
V
V
= -4.0 mA
= 4.5 V
0.4
2
= 8.0 mA
Input High Leakage Current
Input Low Leakage Current
IIH
IIL
VCC
VIH
VCC
VIL
= 5.5 V
= 5.5 V
= 5.5 V
µA
µA
-2
8
=
0 V
Output High Current
Output Low Current
IOH
IOL
VCC
VOH
VCC
VOL
= 4.5 V
= 2.4 V
= 4.5 V
= 0.4 V
-4
2
mA
mA
Output Leakage Current
High at Three-State Outputs
IOHZ
IOLZ
VCC
VOH
VCC
VOL
= 5.5 V
= 5.5 V
= 5.5 V
µA
µA
Low at Three-State Outputs
-2
=
0 V
4
September 1, 2004
U621708
Symbol
Alt.
tRC
tAA
tACE
tOE
70
Switching Characteristics
Read Cycle
Unit
Min.
Max.
IEC
tcR
Read Cycle Time
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time to Data Valid
Chip Enable Access Time to Data Valid
G LOW to Data Valid
ta(A)
70
70
25
15
15
ta(E)
ta(G)
tdis(E)
tdis(G)
ten(E)
ten(G)
tv(A)
E1 HIGH or E2 LOW to Output in High-Z
G HIGH to Output in High-Z
tHZCE
tHZOE
tLZCE
tLZOE
tOH
E1 LOW or E2 HIGH to Output in Low-Z
G LOW to Output in Low-Z
10
5
Output Hold Time from Address Change
E1 LOW or E2 HIGH to Power-Up Time
E1 HIGH or E2 LOW to Power-Down Time
10
0
tPU
tPD
70
Symbol
70
Switching Characteristics
Write Cycle
Unit
Alt.
tWC
IEC
tcW
Min.
70
35
35
0
Max.
Write Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Pulse Width
tWP
tw(W)
tsu(W)
tsu(A)
Write Setup Time
tWP
Address Setup Time
tAS
t
Address Valid to End of Write
Chip Enable Setup Time
Pulse Width Chip Enable to End of Write
Data Setup Time
tAW
35
40
40
25
0
su(A-WH)
tCW
tsu(E)
tCW
tw(E)
tsu(D)
th(D)
tDS
Data Hold Time
tDH
Address Hold from End of Write
W LOW to Output in High-Z
G HIGH to Output in High-Z
W HIGH to Output in Low-Z
G LOW to Output in Low-Z
W to Chip Enable Setup Time
tAH
th(A)
0
tHZWE
tHZOE
tLZWE
tLZOE
tdis(W)
tdis(G)
ten(W)
ten(G)
20
15
5
5
t
t
10
WE
su(W-E)
September 1, 2004
5
U621708
Data Retention Mode
Data Retention
Characteristics
Symbol
Conditions
Min. Typ. Max.
Unit
Alt.
IEC
VCC(DR)
Data Retention Supply Voltage
Data Retention Supply Current
2
5.5
0.6
V
V
V
= 3 V
= V
ICC(DR)
mA
CC(DR)
=V
- 0.2 V
CC(DR)
E1
E2
Data Retention Setup Time
Operating Recovery Time
tCDR
tR
tsu(DR) See Data Retention
0
ns
ns
Waveforms (below)
trec
tcR
Data Retention Mode E1 - controlled
VCC
E1
4.5 V
V
CC(DR) ≥ 2 V
2.2 V
2.2 V
tsu(DR)
Data Retention
trec
0 V
V
V
≥ V
- 0.2 V or V
E1(DR)
≤ 0.2 V
E2(DR)
CC(DR)
CC(DR)
E2(DR)
+ 0.3 V
CC(DR)
- 0.2 V ≤ V
≤ V
Data Retention Mode E2 - controlled
VCC
4.5 V
0 V
V
CC(DR) ≥ 2 V
E2
tDR
Data Retention
trec
0.8 V
0.8 V
V
V
≥ V
- 0.2 V or V
≤ 0.2 V
E1(DR)
E2(DR)
CC(DR)
E1(DR)
≤ 0.2 V
6
September 1, 2004
U621708
Test Configuration for Functional Check
5 V
A0
VCC
A1
A2
A3
A4
DQ0
DQ1
A5
481
A6
VIH
VIL
DQ2
DQ3
A7
A8
A9
DQ4
DQ5
DQ6
DQ7
A10
A11
A12
A13
A14
A15
A16
VO
30 pF e
E1
E2
W
255
VSS
G
e
In measurement of t
,t
, t
, t
, t
the capacitance is 5 pF.
dis(E) dis(W) en(E) en(W) en(G)
Capacitance
Conditions
Symbol
Min.
Max.
Unit
Input Capacitance
VCC
VI
f
= 5.0 V
= VSS
CI
7
7
pF
= 1 MHz
= 25 °C
Output Capacitance
Co
pF
T
a
All pins not under test must be connected with ground by capacitors.
Ordering Code
Example
U621708
S
K
07
Type
Leadfree Option
blank= Standard Package
Package
G1 = Leadfree Green Package f
D = PDIP32 (600 mil)
S = SOP32 (450 mil)
T = TSOP I 32
T1 = sTSOP I 32
Access Time
07 = 70 ns
Operating Temperature Range
C = 0 to 70 °C
K = -40 to 85 °C
f on special request
Device Marking (example)
ZMD
Product specification
Date of manufacture
U621708SK
(The first 2 digits indicating
the year, and the last 2
digits the calendar week.)
07
C 0425
G1
Assembly location and
trace code
1 ZZ
Internal Code
Leadfree Green Package
September 1, 2004
7
U621708
Read Cycle 1: Ai-controlled (during Read Cycle : E1 = G = VIL, W = E2 = VIH)
tcR
Ai
Address Valid
ta(A)
DQi
Output Data Valid
Previous Data Valid
tv(A)
Output
Read Cycle 2: G-, E1, E2-controlled (during Read Cycle: W = VIH)
tcR
Ai
Addresses Valid
ta(E)
ten(E)
tsu(A)
E1
tdis(E)
tdis(E)
ta(E)
tsu(A)
ten(E)
E2
G
ta(G)
tdis(G)
ten(G)
High-Z
DQi
Output Data Valid
*
Output
tPU
*
tPD
ICC(OP)
ICC(SB)
50 %
50 %
* The same applies to E1
Write Cycle1: W-controlled
tcW
Ai
Addresses Valid
tsu(E)
th(A)
E1
tsu(E)
E2
W
tsu(W-E)
tsu(W-E)
tsu(A)
tw(W)
tsu(D)
th(D)
DQi
Input Data Valid
tdis(W)
Input
ten(W)
High-Z
DQi
Output
G
8
September 1, 2004
U621708
Write Cycle 2: E1-controlled
tcW
Ai
Addresses Valid
tw(E)
tsu(A)
th(A)
E1
tsu(E)
E2
W
tsu(W)
th(D)
tsu(D)
DQi
Input
Input Data Valid
tdis(W)
tdis(G)
ten(E)
DQi
Output
High-Z
G
Write Cycle 3 (E2-controlled)
tcW
Addresses Valid
tsu(E)
Ai
th(A)
E1
E2
W
tw(E)
tsu(A)
tsu(W)
tsu(D)
th(D)
Input Data Valid
tdis(W)
DQi
ten(E)
Input
High-Z
tdis(G)
DQi
Output
G
undefined
L- to H-level
H- to L-level
The information describes the type of component and shall not be considered as assured characteristics.Terms of
delivery and rights to change design reserved.
September 1, 2004
9
U621708
LIFE SUPPORT POLICY
ZMD products are not designed, intended, or authorized for use as components in systems intended for surgical
implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the ZMD product could create a situation where personal injury or death may occur.
Components used in life-support devices or systems must be expressly authorized by ZMD for such purpose.
LIMITED WARRANTY
The information in this document has been carefully checked and is believed to be reliable. However Zentrum
Mikroelektronik Dresden AG (ZMD) makes no guarantee or warranty concerning the accuracy of said information
and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon it.
The information in this document describes the type of component and shall not be considered as assured charac-
teristics.
ZMD does not guarantee that the use of any information contained herein will not infringe upon the patent, trade-
mark, copyright, mask work right or other rights of third parties, and no patent or licence is implied hereby. This
document does not in any way extent ZMD’s warranty on any product beyond that set forth in its standard terms and
conditions of sale.
ZMD reserves terms of delivery and reserves the right to make changes in the products or specifications, or both,
presented in this publication at any time and without notice.
September 1, 2004
Zentrum Mikroelektronik Dresden AG
Grenzstraße 28 • D-01109 Dresden • P. O. B. 80 01 34 • D-01101 Dresden • Germany
Phone: +49 351 8822 306 • Fax: +49 351 8822 337 • Email: memory@zmd.de • http://www.zmd.de
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