U637H256D1C25G1 [SIMTEK]
Non-Volatile SRAM, 32KX8, 25ns, CMOS, PDIP28, 0.600 INCH, PLASTIC, DIP-28;
| 型号： | U637H256D1C25G1 |
| 厂家： | 
SIMTEK CORPORATION |
| 描述： | Non-Volatile SRAM, 32KX8, 25ns, CMOS, PDIP28, 0.600 INCH, PLASTIC, DIP-28 静态存储器 光电二极管 |
| 文件： | 总13页 (文件大小：224K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
U637H256
CapStore 32K x 8 nvSRAM
Features
Description
The U637H256 has two separate SRAM with nonvolatile data inte-
! High-performance CMOS non-
volatile static RAM 32768 x 8 bits modes of operation: SRAM mode grity.
! 25 ns Access Time
and nonvolatile mode. In SRAM STORE cycles also may be initia-
! 10 ns Output Enable Access
Time
mode, the memory operates as an ted under user control via a soft-
ordinary static RAM. In nonvolatile ware sequence.
! ICC = 15 mA typ. at 200 ns Cycle
Time
operation, data is transferred in Once a STORE cycle is initiated,
parallel from SRAM to EEPROM or further input or output are disabled
from EEPROM to SRAM. In this until the cycle is completed.
mode SRAM functions are disab- Because a sequence of addresses
! Unlimited Read and Write Cycles
to SRAM
! Automatic STORE to EEPROM
on Power Down using charge
stored in an integrated capacitor
! Software initiated STORE
! Automatic STORE Timing
! 105 STORE cycles to EEPROM
! 10 years data retention in
EEPROM
led.
is used for STORE initiation, it is
The U637H256 is a fast static RAM important that no other read or
(25 ns) with a nonvolatile electri- write accesses intervene in the
cally erasable PROM (EEPROM) sequence or the sequence will be
element incorporated in each static aborted.
memory cell. The SRAM can be RECALL cycles may also be initia-
read and written an unlimited num- ted by a software sequence.
ber of times, while independent Internally, RECALL is a two step
! Automatic RECALL on Power Up nonvolatile
data
resides
in procedure. First, the SRAM data is
! Software RECALL Initiation
! Unlimited RECALL cycles from
EEPROM
EEPROM. Data transfers from the cleared and second, the nonvola-
SRAM to the EEPROM (the tile information is transferred into
STORE operation) take place auto- the SRAM cells.
! Single 5 V ± 10 % Operation
! Operating temperature range:
0 to 70 °C
matically upon power down using The RECALL operation in no way
charge stored in an integrated alters the data in the EEPROM
capacitor. Transfers from the cells. The nonvolatile data can be
EEPROM to the SRAM (the recalled an unlimited number of
RECALL operation) take place times.
-40 to 85 °C
! QS 9000 Quality Standard
! ESD protection > 2000 V
(MIL STD 883C M3015.7)
! Package: PDIP28 (600 mil)
automatically on power up. The
U637H256 combines the high per-
formance and ease of use of a fast
The U637H256 is pin compatible
with standard SRAMs and stan-
dard battery backed SRAMs.
Pin Description
Pin Configuration
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
VCC
W
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
Signal Name Signal Description
A0 - A14
DQ0 - DQ7
Address Inputs
Data In/Out
Chip Enable
E
PDIP
Output Enable
Write Enable
Power Supply Voltage
Ground
G
W
VCC
VSS
DQ0
DQ1
DQ2
VSS
16
15
Top View
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April 13, 2004
U637H256
Block Diagram
EEPROM Array
512 x (64 x 8)
VCC
VSS
A5
STORE
RECALL
A6
SRAM
Array
A7
Power
VCC
A8
Control
A9
A11
A12
A13
A14
512 Rows x
64 x 8 Columns
Store/
Recall
Control
DQ0
DQ1
Column I/O
DQ2
DQ3
DQ4
DQ5
DQ6
Column Decoder
Software
Detect
A0 - A13
A0 A1 A2 A3 A4A10
G
DQ7
E
W
Truth Table forSRAM Operations
Operating Mode
E
W
G
DQ0 - DQ7
Standby/not selected
Internal Read
Read
H
L
L
L
High-Z
High-Z
*
*
H
H
H
L
L
Data Outputs Low-Z
Data Inputs High-Z
Write
*
* H or L
Characteristics
All voltages are referenced to VSS = 0 V (ground).
All characteristics are valid in the power supply voltage range and in the operating temperature range specified.
Dynamic measurements are based on a rise and fall time of ≤ 5 ns, measured between 10 % and 90 % of VI, as well as
input levels of VIL = 0 V and VIH = 3 V. The timing reference level of all input and output signals is 1.5 V,
with the exception of the tdis-times and ten-times, in which cases transition is measured ± 200 mV from steady-state voltage.
Absolute Maximum Ratingsa
Symbol
Min.
Max.
Unit
Power Supply Voltage
Input Voltage
VCC
VI
-0.5
-0.3
-0.3
7
V
V
VCC+0.5
VCC+0.5
1
Output Voltage
VO
PD
Ta
V
Power Dissipation
W
Operating Temperature
C-Type
K-Type
0
70
85
°C
°C
-40
Storage Temperature
Tstg
-65
150
°C
a: Stresses greater than those listed under „Absolute Maximum Ratings“ may cause permanent damage to the device. This is a stress
rating only, and functional operation of the device at condition above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
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April 13, 2004
U637H256
Recommended
Symbol
Conditions
Min.
Max.
Unit
Operating Conditions
Power Supply Voltage
Input Low Voltage
Input High Voltage
VCC
VIL
4.5
-0.3
2.2
5.5
0.8
V
V
V
-2 V at Pulse Width
10 ns permitted
VIH
VCC+0.3
C-Type
K-Type
DC Characteristics
Symbol
Conditions
Unit
Min. Max. Min. Max.
Operating Supply Currentb
ICC1
VCC
VIL
VIH
tc
= 5.5 V
= 0.8 V
= 2.2 V
= 25 ns
95
100
mA
Average Supply Current duringc
STORE
ICC2
VCC
E
= 5.5 V
6
7
mA
mA
≤ 0.2 V
W
≥ VCC-0.2 V
≤ 0.2 V
VIL
VIH
≥ VCC-0.2 V
Operating Supply Currentb
at tcR = 200 ns
ICC3
VCC
W
= 5.5 V
20
20
≥ VCC-0.2 V
≤ 0.2 V
(Cycling CMOS Input Levels)
VIL
VIH
≥ VCC-0.2 V
Standby Supply Currentd
(Cycling TTL Input Levels)
ICC(SB)1
VCC
E
= 5.5 V
= VIH
40
3
42
3
mA
mA
tc
= 25 ns
Standby Supply Curentd
ICC(SB)
VCC
E
= 5.5 V
(Stable CMOS Input Levels)
≥ VCC-0.2 V
≤ 0.2 V
VIL
VIH
≥ VCC-0.2 V
b: ICC1 and ICC3 are depedent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
The current ICC1 is measured for WRITE/READ - ratio of 1/2.
c: ICC2 is the average current required for the duration of the SoftStore STORE cycle.
d: Bringing E ≥ VIH will not produce standby current levels until a software initiated nonvolatile cycle in progress has timed out.
See MODE SELECTION table. The current ICC(SB)1 is measured for WRITE/READ - ratio of 1/2.
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April 13, 2004
U637H256
C-Type
K-Type
DC Characteristics
Symbol
Conditions
Unit
Min. Max. Min. Max.
VCC
IOH
IOL
= 4.5 V
=-4 mA
= 8 mA
Output High Voltage
Output Low Voltage
VOH
VOL
2.4
8
2.4
8
V
V
0.4
-4
0.4
-4
VCC
VOH
VOL
= 4.5 V
= 2.4 V
= 0.4 V
Output High Current
Output Low Current
IOH
IOL
mA
mA
Input Leakage Current
VCC
= 5.5 V
High
Low
IIH
IIL
VIH
VIL
= 5.5 V
1
1
1
1
µA
µA
=
0 V
-1
-1
-1
-1
Output Leakage Current
VCC
= 5.5 V
High at Three-State- Output
Low at Three-State- Output
IOHZ
IOLZ
VOH
VOL
= 5.5 V
µA
µA
=
0 V
SRAM Memory Operations
Symbol
Switching Characteristics
No.
Min.
Max.
Unit
Read Cycle
Alt.
IEC
1
2
3
4
5
6
7
8
9
Read Cycle Timef
tAVAV
tAVQV
tELQV
tGLQV
tEHQZ
tGHQZ
tELQX
tGLQX
tAXQX
tcR
ta(A)
ta(E)
ta(G)
tdis(E)
tdis(G)
ten(E)
ten(G)
tv(A)
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time to Data Validg
Chip Enable Access Time to Data Valid
Output Enable Access Time to Data Valid
E HIGH to Output in High-Zh
25
25
10
10
10
G HIGH to Output in High-Zh
E LOW to Output in Low-Z
5
0
3
0
G LOW to Output in Low-Z
Output Hold Time after Address Change
10 Chip Enable to Power Activee
11 Chip Disable to Power Standbyd, e
tELICCH
tEHICCL
tPU
tPD
25
e: Parameter guaranteed but not tested.
f: Device is continuously selected with E and G both Low.
g: Address valid prior to or coincident with E transition LOW.
h: Measured ± 200 mV from steady state output voltage.
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April 13, 2004
U637H256
f
=
=
Read Cycle 1: Ai-controlled (during Read cycle: E
G
V , W = V )
IL
IH
tcR
(1)
Ai
Address Valid
ta(A)
(2)
DQi
Previous Data Valid
Output
Output Data Valid
tv(A)
(9)
g
Read Cycle 2: G-, E-controlled (during Read cycle: W = V )
IH
tcR
(1)
Ai
E
Address Valid
ta(A)
ta(E)
(2)
(3)
tdis(E)
(5)
t
PD (11)
ten(E)
(7)
(8)
G
ta(G)
(4)
tdis(G)
(6)
ten(G)
DQi
High Impedance
Output Data Valid
Output
t
PU (10)
ACTIVE
ICC
STANDBY
Symbol
Alt. #1 Alt. #2
Switching Characteristics
Write Cycle
No.
Min.
Max.
Unit
IEC
12 Write Cycle Time
tAVAV
tAVAV
tcW
tw(W)
tsu(W)
tsu(A)
25
20
20
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
13 Write Pulse Width
tWLWH
14 Write Pulse Width Setup Time
15 Address Setup Time
tWLEH
tAVEL
tAVEH
tAVWL
tAVWH
tELWH
tsu(A-WH)
16 Address Valid to End of Write
17 Chip Enable Setup Time
18 Chip Enable to End of Write
19 Data Setup Time to End of Write
20 Data Hold Time after End of Write
21 Address Hold after End of Write
22 W LOW to Output in High-Zh, i
23 W HIGH to Output in Low-Z
20
20
20
10
0
tsu(E)
tw(E)
tsu(D)
th(D)
tELEH
tDVEH
tEHDX
tEHAX
tDVWH
tWHDX
tWHAX
tWLQZ
tWHQX
th(A)
0
tdis(W)
ten(W)
10
5
5
April 13, 2004
U637H256
Write Cycle #1: W-controlledj
tcW
(12)
Address Valid
tsu(E)
Ai
th(A
(21)
(17)
)
E
tsu(A-WH)
(16)
(13)
W
tw(W)
tsu(A)
(15)
tsu(D)
th(D)
(19)
Input Data Valid
ten(W)
(20)
DQi
Input
tdis(W)
Previous Data Valid
(22)
(23)
DQi
High Impedance
Output
Write Cycle #2: E-controlledj
tcW
(12)
Ai
E
Address Valid
tw(E)
(18)
tsu(A)
(15)
th(A)
(21)
(20)
tsu(W)
(14)
W
th(D)
tsu(D)
(19)
DQi
Input
Input Data Valid
High Impedance
DQi
Output
undefined
L- to H-level
H- to L-level
i: If W is low and when E goes low, the outputs remain in the high impedance state.
j: E or W must be VIH during address transition.
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April 13, 2004
U637H256
Nonvolatile Memory Operations
Mode Selection
A13 - A0
E
W
Mode
I/O
Power
Notes
(hex)
H
L
L
L
X
H
L
X
X
X
Not Selected
Read SRAM
Write SRAM
Output High Z
Output Data
Input Data
Standby
Active
Active
Active
m
H
0E38
31C7
03E0
3C1F
303F
0FC0
Read SRAM
Read SRAM
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
k, l
k, l
k, l
k, l
k, l
k, l
Read SRAM
Read SRAM
Read SRAM
Nonvolatile STORE
L
H
0E38
31C7
03E0
3C1F
303F
0C63
Read SRAM
Read SRAM
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active
k, l
k, l
k, l
k, l
k, l
k, l
Read SRAM
Read SRAM
Read SRAM
Nonvolatile RECALL
k: The six consecutive addresses must be in order listed. W must be high during all six consecutive cycles. See STORE cycle and RECALL
cycle tables and diagrams for further details.
The following six-address sequence is used for testing purposes and should not be used: 0E38, 31C7, 03E0, 3C1F, 303F, 339C.
l: While there are 15 addresses on the U637H256, only the lower 14 are used to control software modes.
Activation of nonvolatile cycles does not depend on the state of G.
m: I/O state assumes that G ≤ VIL.
Symbol
PowerStore
No.
Conditions
Min. Max. Unit
Power Up RECALL
Alt.
IEC
24 Power Up RECALL Durationn
25 STORE Cycle Durationf, e
26 Time allowed to Complete SRAM Cyclef tDELAY
tRESTORE
tPDSTORE
650
10
µs
ms
µs
V
1
Low Voltage Trigger Level
VSWITCH
4.0 4.5
n: tRESTORE starts from the time VCC rises above VSWITCH
.
7
April 13, 2004
U637H256
PowerStore and automatic Power Up RECALL
VCC
5.0 V
VSWITCH
t
PowerStore
(25)
tPDSTORE
Power Up
(24)
(24)
RECALL
tRESTORE
tRESTORE
W
tDELAY
DQi
BROWN OUT
POWER UP
RECALL
BROWN OUT
PowerStore
NO STORE
(NO SRAM WRITES)
Symbol
Software Controlled STORE/RECALL
No.
Min.
Max.
Unit
Cyclek, o
Alt.
IEC
27 STORE/RECALL Initiation Time
28 Chip Enable to Output Inactivep
29 STORE Cycle Timeq
tAVAV
tELQZ
tcR
25
ns
ns
ms
µs
ns
ns
ns
tdis(E)SR
td(E)S
600
10
tELQXS
tELQXR
tAVELN
tELEHN
tEHAXN
30 RECALL Cycle Timer
td(E)R
20
31 Address Setup to Chip Enables
32 Chip Enable Pulse Widths, t
33 Chip Disable to Address Changes
tsu(A)SR
tw(E)SR
th(A)SR
0
20
0
o: The software sequence is clocked with E controlled READs.
p: Once the software controlled STORE or RECALL cycle is initiated, it completes automatically, ignoring all inputs.
q: Note that STORE cycles (but not RECALL) are inhibited by VCC < VSWITCH (STORE inhibit).
r: An automatic RECALL also takes place at power up, starting when VCC exceeds VSWITCH and takes tRESTORE. VCC must not drop below
VSWITCH once it has been exceeded for the RECALL to function properly.
s: Noise on the E pin may trigger multiple READ cycles from the same address and abort the address sequence.
t: If the Chip Enable Pulse Width is less than ta(E) (see Read Cycle) but greater than or equal tw(E)SR, than the data may not be valid at
the end of the low pulse, however the STORE or RECALL will still be initiated.
8
April 13, 2004
U637H256
Software Controlled STORE/RECALL Cycles, t, u, v (E = HIGH after STORE initiation)
tcR
(27)
tcR
(27)
ADDRESS 6
ADDRESS 1
Ai
E
th(A)SR
(33)
tw(E)SR
tw(E)SR
(32)
(32)
tdis(E)
(5)
td(E)R
tsu(A)SR
High Impedance
th(A)SR
(31)
(31)
tsu(A)SR
(33)
td(E)S (29)
(30)
DQi
Output
VALID
tdis(E)SR
VALID
(28)
Software Controlled STORE/RECALL Cycles, t, u, v (E = LOW after STORE initiation)
tcR
(27)
Ai
E
ADDRESS 1
ADDRESS 6
th(A)SR
(33)
(30)
tw(E)SR
(32)
tsu(A)SR
(33)
th(A)SR
VALID
(31)
(31)
td(E)R
t
d(E)S (29)
tsu(A)SR
DQi
High Impedance
Output
VALID
tdis(E)SR
(28)
u: W must be HIGH when E is LOW during the address sequence in order to initiate a nonvolatile cycle. G may be either HIGH or LOW
throughout. Addresses 1 through 6 are found in the mode selection table. Address 6 determines wheter the U637H256 performs a STORE
or RECALL.
v: E must be used to clock in the address sequence for the Software controlled STORE and RECALL cycles.
9
April 13, 2004
U637H256
Test Configuration for Functional Check
5 V
x
VCC
A0
A1
A2
A3
A4
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
A5
480
A6
VIH
VIL
A7
A8
A9
A10
A11
A12
VO
A13
A14
30 pF w
E
W
G
255
VSS
w: In measurement of tdis-times and ten-times the capacitance is 5 pF.
x: Between VCC and VSS must be connected a high frequency bypass capacitor 0.1 µF to avoid disturbances.
Capacitancee
Conditions
Symbol
Min.
Max.
Unit
VCC
= 5.0 V
= VSS
Input Capacitance
CI
8
pF
VI
f
= 1 MHz
= 25 °C
Output Capacitance
CO
7
pF
Ta
All Pins not under test must be connected with ground by capacitors.
IC Code Numbers
U637H256 D1
25
C
Type
Internal Code
Access Time
Package
D1 = PDIP28 (600 mil)
25 = 25 ns
Operating Temperature Range
C =
K =
0 to 70 °C
-40 to 85°C
The date of manufacture is given by the last 4 digits of the mark, the first 2 digits indicating the year, and the last 2
digits the calendar week.
10
April 13, 2004
U637H256
Device Operation
In order to prevent unneeded STORE operations, auto-
matic STORE will be ignored unless at least one
WRITE operation has taken place since the most
recent STORE or RECALL cycle. Software initiated
STORE cycles are performed regardless of whether or
not a WRITE operation has taken place.
The U637H256 has two separate modes of operation:
SRAM mode and nonvolatile mode. The memory ope-
rates in SRAM mode as a standard fast static RAM.
Data is transferred in nonvolatile mode from SRAM to
EEPROM (the STORE operation) or from EEPROM to
SRAM (the RECALL operation). In this mode SRAM
functions are disabled.
SRAM READ and WRITE operations that are in pro-
gress after an automatic STORE cycle on power down
is requested are given time to complete before the
STORE operation is initiated.
STORE cycles may be initiated under user control via a
software sequence and are also automatically initiated
when the power supply voltage level of the chip falls
below VSWITCH. RECALL operations are automatically
initiated upon power up and may also occur when the
VCC rises above VSWITCH, after a low power condition.
RECALL cycles may also be initiated by a software
sequence.
During tDELAY multiple SRAM READ operations may
take place. If a WRITE is in progress it will be allowed a
time, tDELAY, to complete. Any SRAM WRITE cycles
requested after the VCC pin drops below VSWITCH will be
inhibited.
Automatic RECALL
SRAM READ
During power up, an automatic RECALL takes place.
At a low power condition (power supply voltage <
The U637H256 performs a READ cycle whenever E
and G are LOW and W is HIGH. The address specified
on pins A0 - A14 determines which of the 32768 data
bytes will be accessed. When the READ is initiated by
an address transition, the outputs will be valid after a
delay of tcR. If the READ is initiated by E or G, the out-
puts will be valid at ta(E) or at ta(G), whichever is later.
The data outputs will repeatedly respond to address
changes within the tcR access time without the need for
transition on any control input pins, and will remain
valid until another address change or until E or G is
brought HIGH or W is brought LOW.
VSWITCH) an internal RECALL request may be latched.
As soon as power supply voltage exceeds the sense
voltage of VSWITCH, a requested RECALL cycle will
automatically be initiated and will take tRESTORE to com-
plete.
If the U637H256 is in a WRITE state at the end of
power up RECALL, the SRAM data will be corrupted.
To help avoid this situation, a 10 kΩ resistor should be
connected between W and power supply voltage.
Software Nonvolatile STORE
The U637H256 software controlled STORE cycle is
initiated by executing sequential READ cycles from six
specific address locations. By relying on READ cycles
only, the U637H256 implements nonvolatile operation
while remaining compatible with standard 32K x 8
SRAMs. During the STORE cycle, an erase of the pre-
vious nonvolatile data is performed first, followed by a
parallel programming of all the nonvolatile elements.
Once a STORE cycle is initiated, further inputs and out-
puts are disabled until the cycle is completed.
SRAM WRITE
A WRITE cycle is performed whenever E and W are
LOW. The address inputs must be stable prior to
entering the WRITE cycle and must remain stable until
either E or W goes HIGH at the end of the cycle. The
data on pins DQ0 - 7 will be written into the memory if it
is valid tsu(D) before the end of a W controlled WRITE or
tsu(D) before the end of an E controlled WRITE.
It is recommended that G is kept HIGH during the
entire WRITE cycle to avoid data bus contention on the
common I/O lines. If G is left LOW, internal circuitry will
turn off the output buffers tdis (W) after W goes LOW.
Because a sequence of addresses is used for STORE
initiation, it is important that no other READ or WRITE
accesses intervene in the sequence or the sequence
will be aborted.
To initiate the STORE cycle the following READ
sequence must be performed:
Automatic STORE
During normal operation, the U637H256 will draw cur-
rent from VCC to charge up an integrated capacitor.
This stored charge will be used by the chip to perform a
single STORE operation. If the voltage on the VCC pin
drops below VSWITCH, the part will automatically discon-
nect the internal components from the external power
supply with a typical delay of 150 ns and initiate a
STORE operation with tPDSTORE max. 10 ms.
1.
2.
3.
4.
5.
6.
Read addresses 0E38 (hex) Valid READ
Read addresses 31C7 (hex) Valid READ
Read addresses 03E0 (hex) Valid READ
Read addresses 3C1F (hex) Valid READ
Read addresses 303F (hex) Valid READ
Read addresses 0FC0 (hex) Initiate STORE
Cycle
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April 13, 2004
U637H256
Once the sixth address in the sequence has been
entered, the STORE cycle will commence and the chip
will be disabled. It is important that READ cycles and
not WRITE cycles be used in the sequence, although it
is not necessary that G be LOW for the sequence to be
valid. After the tSTORE cycle time has been fulfilled, the
SRAM will again be activated for READ and WRITE
operation. When VCC < VSWITCH all software STORE
operations will be inhibited.
Internally, RECALL is a two step procedure. First, the
SRAM data is cleared and second, the nonvolatile
information is transferred into the SRAM cells. After
td(E)R cycle time the SRAM will once again be ready for
READ and WRITE operations.The RECALL operation
in no way alters the data in the EEPROM cells. The
nonvolatile data can be recalled an unlimited number of
times.
Any SRAM WRITE cycles requested after the VCC pin
drops below VSWITCH will be inhibited.
Low Average Active Power
The U637H256 has been designed to draw significantly
less power when E is LOW (chip enabled) but the
access cycle time is longer than 55 ns.
When E is HIGH the chip consumes only standby cur-
rent.
Software Nonvolatile RECALL
A RECALL cycle of the EEPROM data into the SRAM
is initiated with a sequence of READ operations in a
manner similar to the STORE initiation. To initiate the
RECALL cycle the following sequence of READ opera-
tions must be performed:
The overall average current drawn by the part depends
on the following items:
1. CMOS or TTL input levels
2. the time during which the chip is disabled (E HIGH)
3. the cycle time for accesses (E LOW)
4. the ratio of READs to WRITEs
1.
2.
3.
4.
5.
6.
Read addresses 0E38 (hex) Valid READ
Read addresses 31C7 (hex) Valid READ
Read addresses 03E0 (hex) Valid READ
Read addresses 3C1F (hex) Valid READ
Read addresses 303F (hex) Valid READ
Read addresses 0C63 (hex) Initiate RECALL
Cycle
5. the operating temperature
6. the VCC level
The information describes the type of component and shall not be considered as assured characteristics.
Terms of delivery and rights to change design reserved.
12
April 13, 2004
Preliminary
U637H256
LIFE SUPPORT POLICY
ZMD products are not designed, intended, or authorized for use as components in systems intended for surgical
implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the ZMD product could create a situation where personal injury or death may occur.
Components used in life-support devices or systems must be expressly authorized by ZMD for such purpose.
LIMITED WARRANTY
The information in this document has been carefully checked and is believed to be reliable. However Zentrum Mikro-
elektronik Dresden AG (ZMD) makes no guarantee or warranty concerning the accuracy of said information and
shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon it. The
information in this document describes the type of component and shall not be considered as assured characteri-
stics.
ZMD does not guarantee that the use of any information contained herein will not infringe upon the patent, trade-
mark, copyright, mask work right or other rights of third parties, and no patent or licence is implied hereby. This
document does not in any way extent ZMD’s warranty on any product beyond that set forth in its standard terms and
conditions of sale.
ZMD reserves terms of delivery and reserves the right to make changes in the products or specifications, or both,
presented in this publication at any time and without notice.
Zentrum Mikroelektronik Dresden AG
November01, 2001
Grenzstraße 28 • D-01109 Dresden • P. O. B. 80 01 34 • D-01101 Dresden • Germany
Phone: +49 351 8822 306 • Fax: +49 351 8822 337 • Email: sales@zmd.de • http://www.zmd.de
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