UL631H256SC35 [SIMTEK]
SimtekLow Voltage SoftStore 32K x 8 nvSRAM; SimtekLow电压SoftStore 32K ×8的nvSRAM
| 型号： | UL631H256SC35 |
| 厂家： | 
SIMTEK CORPORATION |
| 描述： | SimtekLow Voltage SoftStore 32K x 8 nvSRAM |
| 文件： | 总13页 (文件大小：180K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Obsolete - Not Recommended for New Designs
UL631H256
SimtekLow Voltage SoftStore 32K x 8 nvSRAM
Features
Description
• High-performance CMOS non-
The UL631H256 has two separate of a fast SRAM with nonvolatile
volatile static RAM 32768 x 8 bits modes of operation: SRAM mode data integrity.
• 35 and 45 ns Access Times
• 15 and 20 ns Output Enable
Access Times
• Software STORE Initiation
• Automatic STORE Timing
• 106 STORE cycles to EEPROM
• 100 years data retention in
EEPROM
and nonvolatile mode. In SRAM Once a STORE cycle is initiated,
mode, the memory operates as an further input or output are disabled
ordinary static RAM. In nonvolatile until the cycle is completed.
operation, data is transferred in Because a sequence of addresses
parallel from SRAM to EEPROM or is used for STORE initiation, it is
from EEPROM to SRAM. In this important that no other read or
mode SRAM functions are disab- write accesses intervene in the
led.
sequence or the sequence will be
• Automatic RECALL on Power Up The UL631H256 is a fast static aborted.
• Software RECALL Initiation
• Unlimited RECALL cycles from
EEPROM
RAM (35 and 45 ns), with a nonvo- Internally, RECALL is a two step
latile electrically erasable PROM procedure. First, the SRAM data is
(EEPROM) element incorporated cleared and second, the nonvola-
in each static memory cell. The tile information is transferred into
SRAM can be read and written an the SRAM cells.
• Unlimited Read and Write to
SRAM
• Wide voltage range: 2.7 ... 3.6 V
(3.0 ... 3.6 V for 35 ns type)
• Operating temperature range:
0 to 70 °C
unlimited number of times, while The RECALL operation in no way
independent nonvolatile data resi- alters the data in the EEPROM
des in EEPROM. Data transfers cells. The nonvolatile data can be
from the SRAM to the EEPROM recalled an unlimited number of
(the STORE operation), or from the times.
-40 to 85 °C
• QS 9000 Quality Standard
• RoHS compliance and Pb- free
• ESD protection > 2000 V
(MIL STD 883C M3015.7-HBM)
• Package: SOP28 (330 mil)
EEPROM to the SRAM (the The UL631H256 is pin compatible
RECALL operation) are initiated with standard SRAMs.
through software sequences.
The UL631H256 combines the
high performance and ease of use
Pin Configuration
Pin Description
G
A11
A9
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
n.c.
A10
E
Signal Name Signal Description
VCC
W
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0 10
DQ0
DQ1
DQ2
VSS
1
2
3
4
5
6
7
8
9
28
27
26
25
24
23
22
21
20
19
18
17
16
15
2
3
A0 - A14
Address Inputs
Data In/Out
A8
4
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A13
W
n. c.
VCC
n. c.
A14
A12
A7 12
A6 13
A5
A4
A3
5
DQ0 - DQ7
6
7
Chip Enable
E
8
TSOP
SOP
9
Output Enable
Write Enable
Power Supply Voltage
Ground
G
10
11
W
11
12
13
14
VCC
VSS
14
15
16
A1
A2
n.c.
Top View
Top View
March 31, 2006
STK Control #ML0057
1
Rev 1.0
UL631H256
Block Diagram
EEPROM Array
512 x (64 x 8)
A5
A6
STORE
A7
A8
A9
RECALL
VCC
VSS
SRAM
Array
A11
A12
A13
A14
512 Rows x
64 x 8 Columns
Store/
Recall
Control
VCC
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
Column I/O
Software
Detect
Column Decoder
A0 - A13
G
A0 A1 A2 A3 A4A10
DQ7
E
W
Truth Table for SRAM Operations
Operating Mode
E
W
G
DQ0 - DQ7
Standby/not selected
Internal Read
Read
H
L
L
L
High-Z
High-Z
*
*
H
H
L
H
L
Data Outputs Low-Z
Data Inputs High-Z
Write
*
* H or L
Characteristics
All voltages are referenced to VSS = 0 V (ground).
All characteristics are valid in the power supply voltage range and in the operating temperature range specified.
Dynamic measurements are based on a rise and fall time of ≤ 5 ns, measured between 10 % and 90 % of VI, as well as
input levels of VIL = 0 V and VIH = 3 V. The timing reference level of all input and output signals is 1.5 V,
with the exception of the tdis-times and ten-times, in which cases transition is measured ± ±200 mV from steady-state voltage.
Absolute Maximum Ratingsa
Symbol
Min.
Max.
Unit
Power Supply Voltage
Input Voltage
VCC
VI
-0.5
-0.3
-0.3
4.6
VCC+0.5
VCC+0.5
1
V
V
Output Voltage
VO
PD
V
Power Dissipation
W
Operating Temperature
C-Type
K-Type
0
-40
70
85
°C
°C
Ta
Storage Temperature
Tstg
-65
150
°C
a: Stresses greater than those listed under „Absolute Maximum Ratings“ may cause permanent damage to the device. This is a stress
rating only, and functional operation of the device at condition above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Rev 1.0
March 31, 2006
STK Control #ML0057
2
UL631H256
Recommended
Operating Conditions
Symbol
Conditions
tc = 35 ns
Min.
Max.
Unit
Power Supply Voltage
VCC
3.0
2.7
3.6
3.6
V
V
tc = 45 ns
-2 V at Pulse Width
10 ns permitted
Input Low Voltage
Input High Voltage
VIL
-0.3
2.2
0.8
V
V
VIH
VCC+0.3
C-Type
K-Type
DC Characteristics
Symbol
Conditions
Unit
Min. Max. Min. Max.
Operating Supply Currentb
ICC1
VCC
VIL
VIH
= 3.6 V
= 0.8 V
= 2.2 V
tc
tc
= 35 ns
= 45 ns
45
35
47
37
mA
mA
Average Supply Current during
STOREc
ICC2
VCC
E
W
VIL
VIH
= 3.6 V
3
4
mA
≥ VCC-0.2 V
≥ VCC-0.2 V
≤ 0.2 V
≥ VCC-0.2 V
Average Supply Current
at tcR = 200 nsb
(Cycling CMOS Input Levels)
ICC3
VCC
W
VIL
VIH
= 3.6V
10
11
mA
≥ VCC-0.2 V
≤ 0.2 V
≥ VCC-0.2 V
Standby Supply Currentd
(Cycling TTL Input Levels)
ICC(SB)1
VCC
E
= 3.6 V
≥±VIH
tc
tc
= 35ns
= 45 ns
11
9
12
10
mA
mA
Standby Supply Curentd
(Stable CMOS Input Levels)
ICC(SB)
VCC
E
VIL
VIH
= 3.6 V
0.7
0.7
mA
≥ VCC-0.2 V
≤ 0.2 V
≥ VCC-0.2 V
b: ICC1 and ICC3 are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded
The current ICC1 is measured for WRITE/READ - ratio of 1/2.
c: ICC2 is the average current required for the duration of the STORE cycle (tSTORE).
d: Bringing E±≥±VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out.
The current ICC(SB)1 is measured for WRITE/READ - ratio of 1/2.
March 31, 2006
STK Control #ML0057
3
Rev 1.0
UL631H256
C-Type
K-Type
DC Characteristics
Symbol
Conditions
Unit
Min. Max. Min. Max.
VCC
IOH
IOL
= VCC
min
=-2 mA
= 2 mA
Output High Voltage
Output Low Voltage
VOH
VOL
2.4
2
2.4
2
V
V
0.4
-2
0.4
-2
VCC
VOH
VOL
= VCC
min
= 2.4 V
= 0.4 V
Output High Current
Output Low Current
IOH
IOL
mA
mA
Input Leakage Current
VCC
= 3.6 V
High
Low
IIH
IIL
VIH
VIL
= 3.6 V
1
1
μA
μA
=
0 V
-1
-1
-1
-1
Output Leakage Current
VCC
E or G ≥ VIH
VOH
VOL
= 3.6 V
High at Three-State- Output
Low at Three-State- Output
IOHZ
IOLZ
= 3.6 V
0 V
1
1
μA
μA
=
SRAM Memory Operations
Symbol
35
45
Switching Characteristics
No.
Unit
Read Cycle
Alt.
IEC
Min.
Max.
1
2
3
4
Read Cycle Timef
tAVAV
tAVQV
tELQV
tcR
35
45
ns
ns
ns
Address Access Time to Data Validg
Chip Enable Access Time to Data Valid
ta(A)
ta(E)
35
35
45
45
Output Enable Access Time to Data
Valid
tGLQV
ta(G)
15
20
ns
5
6
7
8
9
E HIGH to Output in High-Zh
G HIGH to Output in High-Zh
E LOW to Output in Low-Z
tEHQZ
tGHQZ
tELQX
tdis(E)
tdis(G)
ten(E)
ten(G)
tv(A)
13
13
15
15
ns
ns
ns
ns
ns
ns
ns
5
0
3
0
5
0
3
G LOW to Output in Low-Z
tGLQX
Output Hold Time after Addr. Changeg
tAXQX
10 Chip Enable to Power Activee
tELICCH
tEHICCL
tPU
11 Chip Disable to Power Standbyd, e
tPD
35
45
e: Parameter guaranteed but not tested.
f: Device is continuously selected with E and G both Low.
g: Address valid prior to or coincident with E transition LOW.
h: Measured ± ±200 mV from steady state output voltage.
Rev 1.0
March 31, 2006
STK Control #ML0057
4
UL631H256
f
=
=
Read Cycle 1: Ai-controlled (during Read cycle: E
G
VIL, W = VIH)
tcR
(1)
Ai
Address Valid
ta(A)
(2)
DQi
Previous Data Valid
Output
Output Data Valid
tv(A)
(9)
Read Cycle 2: G-, E-controlled (during Read cycle: W = VIH)g
tcR
(1)
Ai
E
Address Valid
ta(A) (2)
ta(E) (3)
tPD
(11)
tdis(E)
(5)
ten(E)
(7)
G
ta(G)
(4)
tdis(G) (6)
ten(G)
(8)
DQi
Output
High Impedance
Output Data Valid
tPU
(10)
ACTIVE
ICC
STANDBY
Symbol
Alt. #1 Alt. #2
35
45
Switching Characteristics
Write Cycle
No.
Unit
IEC
Min.
Max.
Min.
Max.
12 Write Cycle Time
tAVAV
tAVAV
tcW
35
25
25
0
45
30
30
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
13 Write Pulse Width
tWLWH
tw(W)
tsu(W)
tsu(A)
14 Write Pulse Width Setup Time
15 Address Setup Time
tWLEH
tAVEL
tAVEH
tAVWL
tAVWH
tELWH
tsu(A-WH)
tsu(E)
tw(E)
16 Address Valid to End of Write
17 Chip Enable Setup Time
18 Chip Enable to End of Write
19 Data Setup Time to End of Write
25
25
25
12
0
30
30
30
15
0
tELEH
tDVEH
tEHDX
tEHAX
tDVWH
tsu(D)
th(D)
20 Data Hold Time after End of Write tWHDX
21 Address Hold after End of Write
22 W LOW to Output in High-Zh, i
23 W HIGH to Output in Low-Z
tWHAX
tWLQZ
tWHQX
th(A)
0
0
tdis(W)
ten(W)
13
15
5
5
March 31, 2006
STK Control #ML0057
5
Rev 1.0
UL631H256
Write Cycle #1: W-controlledj
tcW
(12)
Ai
Address Valid
tsu(E)
th(A)
(17)
(21)
E
tsu(A-WH)
(16)
tw(W) (13)
W
tsu(A)
(15)
tsu(D)
th(D)
(20)
(19)
Input Data Valid
ten(W)
DQi
Input
tdis(W)
(12)
(23)
DQi
Output
High Impedance
Previous Data
Write Cycle #2: E-controlledj
tcW
(12)
Ai
E
Address Valid
tw(E)
tsu(A)
(15)
th(A)
(21)
(18)
tsu(W) (14)
W
tsu(D)
th(D) (20)
Input Data Valid
(19)
DQi
Input
High Impedance
DQi
Output
undefined
L- to H-level
H- to L-level
i: If W is low and when E goes low, the outputs remain in the high impedance state.
>
j: E or W must be VIH during address transitions.
Rev 1.0
March 31, 2006
STK Control #ML0057
6
UL631H256
Nonvolatile Memory Operations
Symbol
Alt. IEC
STORE Cycle Inhibit and
No.
Min.
Max.
Unit
Automatic Power Up RECALL
24 Power Up RECALL Durationk
Low Voltage Trigger Level
tRESTORE
VSWITCH
650
2.7
μs
2.4
V
k: tRESTORE starts from the time VCC rises above VSWITCH
.
STORE Cycle Inhibit and Automatic Power Up RECALL
VCC
3.0 V
VSWITCH
t
STORE inhibit
(24)
Power Up
RECALL
tRESTORE
Software Mode Selection
A13 - A0
E
W
Mode
I/O
Power
Notes
(hex)
L
H
0E38
31C7
03E0
3C1F
303F
0FC0
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active
l, m
l, m
l, m
l, m
l, m
l, m
Nonvolatile STORE
ICC2
L
H
0E38
31C7
03E0
3C1F
303F
0C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active
l, m
l, m
l, m
l, m
l, m
l, m
Nonvolatile RECALL
l: The six consecutive addresses must be in order listed. W must be high during all six consecutive cycles. See STORE cycle and RECALL
cycle tables and diagrams for further details.
The following six-address sequence is used for testing purposes and should not be used: 0E38, 31C7, 03E0, 3C1F, 303F, 339C.
m: While there are 15 addresses on the UL631H256, only the lower 14 are used to control software modes.
March 31, 2006
STK Control #ML0057
7
Rev 1.0
UL631H256
35
45
Symbol
Alt.
tAVAV
tELQZ
No. Software Controlled STORE/RECALL
Cyclel, n
Unit
Min.
Max.
IEC
tcR
Min.
Max.
25 STORE/RECALL Initiation Time
26 Chip Enable to Output Inactiveo
27 STORE Cycle Timep
35
45
ns
ns
ms
ms
ns
ns
ns
tdis(E)SR
td(E)S
600
10
600
10
tELQXS
tELQXR
tAVELN
tELEHN
tEHAXN
28 RECALL Cycle Timeq
td(E)R
20
20
29 Address Setup to Chip Enabler
30 Chip Enable Pulse Widthr, s
31 Chip Disable to Address Changer
tsu(A)SR
tw(E)SR
th(A)SR
0
25
0
0
30
0
n: The software sequence is clocked with E controlled READs
o: Once the software controlled STORE or RECALL cycle is initiated, it completes automatically, ignoring all inputs.
p: Note that STORE cycles (but not RECALL) are aborted by VCC < VSWITCH (STORE inhibit).
q: An automatic RECALL also takes place at power up, starting when VCC exceeds VSWITCH and takes tRESTORE. VCC must not drop below
VSWITCH once it has been exceeded for the RECALL to function properly.
r: Noise on the E pin may trigger multiple READ cycles from the same address and abort the address sequence.
s: If the Chip Enable Pulse Width is less than ta(E) (see Read Cycle) but greater than or equal tw(E)SR, than the data may not be valid at
the end of the low pulse, however the STORE or RECALL will still be initiated.
Software Controlled STORE/RECALL Cyclet, u (E = HIGH after STORE initiation)
tcR
tcR
(25)
(25)
Ai
E
ADDRESS 1
ADDRESS 6
tw(E)SR
(30)
th(A)SR
(31)
tsu(A)SR
(29)
td(E)S (27)
VALID
t
d(E)R (28)
DQi
Output
High Impedance
VALID
tdis(E)SR
(26)
Software Controlled STORE/RECALL Cycler, s, t, u (E = LOW after STORE initiation)
tcR
(25)
ADDRESS 1
Ai
E
ADDRESS 6
th(A)SR (31)
tw(E)SR
(30)
tsu(A)SR
(29)
(29)
tsu(A)SR
(31) th(A)SR
td(E)S
td(E)R
(28)
(27)
DQi
Output
High Impedance
VALID
VALID
tdis(E)SR
(26)
t: W must be HIGH when E is LOW during the address sequence in order to initiate a nonvolatile cycle. G may be either HIGH or LOW
throughout. Addresses 1 through 6 are found in the mode selection table. Address 6 determines wheter the UL631H256 performs a
STORE or RECALL.
u: E must be used to clock in the address sequence for the Software controlled STORE and RECALL cycles.
Rev 1.0
March 31, 2006
STK Control #ML0057
8
UL631H256
Test Configuration for Functional Check
3 V
w
A0
A1
VCC
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
1.1 k
VIH
VIL
VO
v
30 pF
E
W
G
950
VSS
v: In measurement of tdis-times and ten-times the capacitance is 5 pF.
w: Between VCC and VSS must be connected a high frequency bypass capacitor 0.1 μF to avoid disturbances.
Capacitancee
Conditions
Symbol
Min.
Max.
Unit
VCC
VI
f
= 3.0 V
= VSS
= 1MHz
= 25 °C
Input Capacitance
CI
8
pF
Output Capacitance
CO
7
pF
Ta
All pins not under test must be connected with ground by capacitors.
Ordering Code
Example
Type
UL631H256 S2
C
45 G1
Leadfree Option
blank= Standard Package
Package
G1 = Leadfree Green Package x
S = SOP28 (330mil) Type 1
S2 = SOP28 (330mil) Type 2
Access Time
35 = 35 ns (VCC = 3.0 ... 3.6 V)
45 = 45 ns (VCC = 2.7 ... 3.6 V)
Operating Temperature Range
C = 0 to 70 °C
K = -40 to 85 °C
x: on special request
Device Marking (example)
ZMD
Product specification
Date of manufacture
UL631H256S2C
(The first 2 digits indicating
the year, and the last 2
digits the calendar week.)
45
Z 0425
G1
Internal Code
Leadfree Green Package
March 31, 2006
STK Control #ML0057
9
Rev 1.0
UL631H256
Device Operation
vious nonvolatile data is first performed, followed by a
program of the nonvolatile elements. Once a STORE
cycle is initiated, further inputs and outputs are disabled
until the cycle is completed.
Because a sequence of addresses is used for STORE
initiation, it is important that no other READ or WRITE
accesses intervene in the sequence or the sequence
will be aborted and no STORE or RECALL will take
place.
The UL631H256 has two separate modes of operation:
SRAM mode and nonvolatile mode. The memory ope-
rates in SRAM mode as a standard fast static RAM.
Data is transferred In nonvolatile mode from SRAM to
EEPROM shadow (the STORE operation) or from
EEPROM to SRAM (the RECALL operation). In this
mode SRAM functions are disabled.
To initiate the STORE cycle the following READ
sequence must be performed:
SRAM READ
The UL631H256 performs a READ cycle whenever E
and G are LOW while W is HIGH. The address speci-
fied on pins A0 - A14 determines which of the 32768
data bytes will be accessed. When the READ is initia-
ted by an address transition, the outputs will be valid
after a delay of tcR. If the READ is initiated by E or G,
the outputs will be valid at ta(E) or at ta(G), whichever is
later. The data outputs will repeatedly respond to
address changes within the tcR access time without the
need for transition on any control input pins, and will
remain valid until another address change or until E or
G is brought HIGH or W is brought LOW.
1.
2.
3.
4.
5.
6.
Read addresses 0E38 (hex) Valid READ
Read addresses 31C7 (hex) Valid READ
Read addresses 03E0 (hex) Valid READ
Read addresses 3C1F (hex) Valid READ
Read addresses 303F (hex) Valid READ
Read addresses 0FC0 (hex) Initiate STORE
Cycle
Once the sixth address in the sequence has been
entered, the STORE cycle will commence and the chip
will be disabled. It is important that READ cycles and
not WRITE cycles be used in the sequence, although it
is not necessary that G be LOW for the sequence to be
valid. After the tSTORE cycle time has been fulfilled, the
SRAM will again be activated for READ and WRITE
operation.
SRAM WRITE
A WRITE cycle is performed whenever E and W are
LOW. The address inputs must be stable prior to
entering the WRITE cycle and must remain stable until
either E or W goes HIGH at the end of the cycle. The
data on pins DQ0 - 7 will be written into the memory if it
is valid tsu(D) before the end of a W controlled WRITE
or tsu(D) before the end of an E controlled WRITE.
It is recommended that G is kept HIGH during the
entire WRITE cycle to avoid data bus contention on the
common I/O lines. If G is left LOW, internal circuitry will
turn off the output buffers tdis(W) after W goes LOW.
Software Nonvolatile RECALL
A RECALL cycle of the EEPROM data into the SRAM
is initiated with a sequence of READ operations in a
manner similar to the STORE initiation. To initiate the
RECALL cycle the following sequence of READ opera-
tions must be performed:
1.
2.
3.
4.
5.
6.
Read addresses 0E38 (hex) Valid READ
Read addresses 31C7 (hex) Valid READ
Read addresses 03E0 (hex) Valid READ
Read addresses 3C1F (hex) Valid READ
Read addresses 303F (hex) Valid READ
Read addresses 0C63 (hex) Initiate RECALL
Cycle
Noise Consideration
The UL631H256 is a high speed memory and therefore
must have a high frequency bypass capacitor of appro-
ximately 0.1 μF connected between VCC and VSS using
leads and traces that are as short as possible. As with
all high speed CMOS ICs, normal carefull routing of
power, ground and signals will help prevent noise pro-
blems.
Internally, RECALL is a two step procedure. First, the
SRAM data is cleared and second, the nonvolatile
information is transferred into the SRAM cells. The
RECALL operation in no way alters the data in the
EEPROM cells. The nonvolatile data can be recalled an
unlimited number of times.
Software Nonvolatile STORE
The UL631H256 software controlled STORE cycle is
initiated by executing sequential READ cycles from six
specific address locations. By relying on READ cycles
only, the UL631H256 implements nonvolatile operation
while remaining compatible with standard 32K x 8
SRAMs. During the STORE cycle, an erase of the pre-
Automatic Power Up RECALL
On power up, once VCC exceeds the sense voltage of
V
SWITCH, a RECALL cycle is automatically initiated.
The voltage on the VCC pin must not drop below
VSWITCH once it has risen above it in order for the
Rev 1.0
March 31, 2006
STK Control #ML0057
10
UL631H256
RECALL,SRAM operation cannot commence until
RESTORE after VCC exceeds VSWITCH
Low Average Active Power
t
.
If the UL631H256 is in a WRITE state at the end of
power up RECALL, the SRAM data will be corrupted.
To help avoid this situation, a 10 kΩ resistor should be
connected between W and VCC.
The UL631H256 has been designed to draw signifi-
cantly less power when E is LOW (chip enabled) but
the cycle time is longer than 45 ns.
When E is HIGH the chip consumes only standby cur-
rent.
Hardware Protection
The overall average current drawn by the part depends
on the following items:
The UL631H256 offers hardware protection against
inadvertent STORE operation through VCC sense.
For VCC < VSWITCH the software initiated STORE ope-
ration will be inhibited.
1. CMOS or TTL input levels
2. the time during which the chip is disabled (E HIGH)
3. the cycle time for accesses (E LOW)
4. the ratio of READs to WRITEs
5. the operating temperature
6. the VCC level
The information describes the type of component and shall not be considered as assured characteristics. Terms of
delivery and rights to change design reserved.
March 31, 2006
STK Control #ML0057
11
Rev 1.0
UL631H256
LIFE SUPPORT POLICY
Simtek products are not designed, intended, or authorized for use as components in systems intended for surgical
implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the Simtek product could create a situation where personal injury or death may occur.
Components used in life-support devices or systems must be expressly authorized by Simtek for such purpose.
LIMITED WARRANTY
The information in this document has been carefully checked and is believed to be reliable. However, Simtek
makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any
loss or damage of whatever nature resulting from the use of, or reliance upon it. The information in this document
describes the type of component and shall not be considered as assured characteristics.
Simtek does not guarantee that the use of any information contained herein will not infringe upon the patent, trade-
mark, copyright, mask work right or other rights of third parties, and no patent or licence is implied hereby. This
document does not in any way extent Simtek’s warranty on any product beyond that set forth in its standard terms
and conditions of sale.
Simtek reserves terms of delivery and reserves the right to make changes in the products or specifications, or both,
presented in this publication at any time and without notice.
March 31, 2006
Change record
Date/Rev
Name
Change
01.11.2001 Ivonne Steffens
format revision and release for „Memory CD 2002“
adding 35 ns type with VCC = 3.0 ... 3.6 V
Adding „Type 1“ to SOP28 (330mil)
03.07.2002 Matthias Schniebel
25.09.2002 Matthias Schniebel
09.01.2003 Matthias Schniebel
20.10.2003 Matthias Schniebel
05.12.2003 Matthias Schniebel
21.04.2004 Matthias Schniebel
Removing 55 ns type
Low Voltage Trigger Level VSWITCH = 2.4 ... 2.7 V (old: 2.5 ... 2.7 V)
adding K-Type with 35 ns: ICC1 = 47 mA, ICC(SB)1 = 12mA
adding „Leadfree Green Package“ to ordering information
adding „Device Marking“
7.4.2005
Stefan Günther
adding RoHS compliance and Pb- free, 106 endurance cycles, 100a
data retention, S2 package for chippack
31.3.2006
1.0
Troy Meester
Simtek
changed to obsolete status
Assigned Simtek Document Control Number
相关型号：
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