SP502CF [SIPEX]
Multi-Mode Serial Transceiver; 多模式串行收发器型号: | SP502CF |
厂家: | SIPEX CORPORATION |
描述: | Multi-Mode Serial Transceiver |
文件: | 总32页 (文件大小:344K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
®
SP502
Multi–Mode SerialTransceiver
■ Single-Chip Serial Transceiver
Supports Industry-Standard
■ Software-Selectable Protocols:
— RS-232 (V.28)
— RS-422A (V.11, X.27)
— RS-449
— RS-485
— V.35
— EIA-530
■ Programmable Selection of Interface
■ +5V-Only Operation
■ Six (6) Drivers and Seven (7) Receivers
■ Surface Mount Packaging
DESCRIPTION…
The SP502 is a highly integrated serial transceiver that allows software control of its interface
modes. ItoffershardwareinterfacemodesforRS-232(V.28), RS-422A(V.11), RS-449, RS-485,
V.35, and EIA-530. TheSP502 is fabricated using low–power BiCMOS process technology, and
incorporates a Sipex patented (5,306,954) charge pump allowing +5V only operation.
Drivers
Receivers
SP502
Charge
Pump
Driver
Decode
Receiver
Decode
Rev. 7/21/03
SP502 Multi-Mode Serial Transceiver
© Copyright 2003 Sipex Corporation
SPECIFICATIONS
MIN.
2.0
TYP.
MAX.
UNITS
CONDITIONS
LOGIC INPUTS
VIL
VIH
0.8
Volts
Volts
LOGIC OUTPUTS
VOL
VOH
0.4
0.8
Volts
Volts
IOUT= 3.2mA
IOUT= 1.0mA
2.4
RS-485 DRIVER
TTL Input Levels
VIL
Volts
Volts
VIH
2.0
Outputs
HIGH Level Output
LOW level Output
Differential Output
Balance
+6.0
-0.3
±5.0
±0.2
±6.0
Volts
Volts
Volts
Volts
Volts
mA
mA
ns
Mbps
±1.5
28.0
5
RL=54Ω, CL=50pF
Open Circuit Voltage
Output Current
Short Circuit Current
Transition Time
Maximum Transmission Rate
RL=54Ω
Terminated in -7V to +12V
Rise/fall time, 10%-90%
±250
120
RS-485 RECEIVER
TTL Output Levels
VOL
0
2.4
0.4
Volts
Volts
VOH
Input
HIGH Threshold
LOW Threshold
Common Mode Range
HIGH Input Current
LOW Input Current
Receiver Sensitivity
+0.2
-7.0
-7.0
+12.0
-0.2
+12.0
Volts
Volts
Volts
(a)-(b)
(a)-(b)
Refer to graph
Refer to graph
Over -7V to +12V common
mode range
±0.2
Volts
Input Impedance
1
Unit Load
Refer to graph
V.35 DRIVER
TTL Input Levels
VIL
0
2.0
0.8
Volts
Volts
VIH
Outputs
Differential Output
±0.44
50
±0.66
Volts
With termination network;
RL=100Ω
With termination network
Output Impedance
Transition Time
150
40
Ω
ns
Maximum Transmission Rate
5
Mbps
V.35 RECEIVER
TTL Output Levels
VOL
0
2.4
0.4
±0.2
110
Volts
Volts
Volts
VOH
Receiver Sensitivity
Over -7V to +12V common
mode range
With termination network
Input Impedance
90
Ω
Rev. 7/21/03
SP502 Multi-Mode Serial Transceiver
© Copyright 2003 Sipex Corporation
2
SPECIFICATIONS (Continued)
MIN.
TYP.
MAX.
UNITS
CONDITIONS
RS-422 DRIVER
TTL Input Levels
VIL
0
2.0
0.8
Volts
Volts
VIH
Outputs
Differential Output
Open Circuit Voltage,VO
Balance
±2.0
±5.0
±6.0
±0.4
+3.0
±150
±100
60
Volts
Volts
Volts
Volts
mA
µA
ns
Mbps
RL=100Ω
|VT| – |VT|
Offset
Short Circuit Current
Power Off Current
Transition Time
Maximum Transmission Rate
Rise/fall time, 10%-90%
5
RS-422 RECEIVER
TTL Output Levels
VOL
0
2.4
0.4
Volts
Volts
VOH
Input
HIGH Threshold
LOW Threshold
Common Mode Range
HIGH Input Current
LOW Input Current
Receiver Sensitivity
Input Impedance
+0.2
-6.0
-10.0
+6.0
-0.2
+10.0
Volts
Volts
Volts
(a)-(b)
(a)-(b)
Refer to graph
Refer to graph
±0.2
Volts
kΩ
4
RS-232 DRIVER
TTL Input Level
VIL
0
2.0
0.8
Volts
Volts
VIH
Outputs
HIGH Level Output
LOW Level Output
Open Circuit Voltage
Short Circuit Current
Power Off Impedance
Slew Rate
+5.0
-15.0
-15
+15
-5.0
+15
Volts
Volts
Volts
mA
Ω
V/µs
µs
RL=3kΩ, VIN=0.8V
RL=3kΩ, VIN=2.0V
±100
300
30
1.56
RL=3kΩ, CL=15pF
Transition Time
Maximum Transmission Rate 120
Kbps
RS-232 RECEIVER
TTL Output Levels
VOL
VOH
Input
0
2.4
0.4
2.4
Volts
Volts
HIGH Threshold
LOW Threshold
Receiver Open Circuit Bias
Input Impedance
1.7
1.2
Volts
Volts
Volts
kΩ
0.8
0
3
+2.0
7
5
RS-423 DRIVER
TTL Input Levels
VIL
0
2.0
0.8
Volts
Volts
VIH
Output
HIGH Level Output
LOW Level Output
+3.6
–6.0
+6.0
–3.6
Volts
Volts
RL=450Ω
RL=450Ω
Rev. 7/21/03
SP502 Multi-Mode Serial Transceiver
© Copyright 2003 Sipex Corporation
3
SPECIFICATIONS (Continued)
MIN.
±4.0
TYP.
MAX.
UNITS
CONDITIONS
RS-423 DRIVER
Open Circuit Voltage
Short Circuit Current
Power Off Current
Transition Time
±9.0
±150
±100
40
Volts
mA
µA
µs
Rise/fall time, 10-90%
Maximum Transmission Rate 120
kbps
RS-423 RECEIVER
TTL Output Levels
VOL
VOH
0
2.4
0.4
Volts
Volts
Input
HIGH Threshold
LOW Threshold
+0.2
-7.0
-7.0
+12.0
-0.2
+12.0
Volts
Volts
Volts
Common Mode Range
HIGH Input Current
LOW Input Current
Receiver Sensitivity
Input Impedance
Refer to graph
Refer to graph
±0.2
Volts
kΩ
4
POWER REQUIREMENTS
VCC
ICC
4.75
5.25
30
Volts
mA
20
VCC =5V; no interface selected
ENVIRONMENTAL AND MECHANICAL
Operating Temperature Range
Storage Temperature Range
Package
0
-65
+70
+150
°C
°C
80–pin QFP
RS422 RECEIVER
RS423 RECEIVER
+3.25mA
+3.25mA
+10V
–10V
–3V
–10V
–3V
+3V
+10V
+3V
Maximum Input Current
versus Voltage
Maximum Input Current
versus Voltage
–3.25mA
–3.25mA
RS485 RECEIVER
+1.0mA
–7V –3V
+6V
+12V
1 Unit Load
Maximum Input Current
versus Voltage
–0.6mA
Rev. 7/21/03
SP502 Multi-Mode Serial Transceiver
© Copyright 2003 Sipex Corporation
4
AC CHARACTERISTICS
PARAMETER
MIN.
TYP.
MAX.
UNITS
CONDITIONS
SINGLE–ENDED MODE
RS-232
Driver Propagation Delay
Input = 0.8V to 2.0V; 60kHz
Unloaded
Unloaded
Loaded with 3kΩ and
2,500pF
Loaded with 3kΩ and
2,500pF
tPHL
tPLH
tPHL
1.7
1.1
2.0
µs
µs
µs
8.0
8.0
tPLH
2.0
µs
Receiver Propagation Delay
Input = 0V to 5.0V; 60kHz;
Note 1
tPHL
tPLH
1.0
1.0
µs
µs
RS-423
Driver Propagation Delay
Input = 0.8V to 2.0V; 60kHz
Loaded with 450Ω
Loaded with 450Ω
tPHL
tPLH
2.0
2.0
8.0
8.0
µs
µs
Receiver Propagation Delay
Input = -0.2V to 2.0V; ;
60kHz; Note 2
tPHL
tPLH
1.0
1.0
µs
µs
DIFFERENTIAL MODE
RS-485
Driver Propagation Delay
Input = 0V to 3.0V; 100kHz
Note 3
tPHL
tPLH
200
200
ns
ns
Loaded with 54Ω
Loaded with 54Ω
Input = a to GND;
B = -200mV to +200mV;
100kHz, Note 4
Receiver Propagation Delay
tPHL
tPLH
200
200
ns
ns
RS-422
Driver Propagation Delay
Input = 0V to 3.0V; 100kHz
Note 3
tPHL
tPLH
200
200
ns
ns
Loaded with 100Ω
Loaded with 100Ω
Input = a to GND;
B = -200mV to +200mV;
100kHz, Note 4
Receiver Propagation Delay
tPHL
tPLH
ns
ns
V.35
Driver Propagation Delay
Input = 0V to 3.0V; 100kHz
Note 3
tPHL
tPLH
200
200
ns
ns
Loaded with 100Ω
Loaded with 100Ω
Input = a to GND;
B = -200mV to +200mV;
100kHz, Note 4
Receiver Propagation Delay
tPHL
tPLH
200
200
ns
ns
Rev. 7/21/03
SP502 Multi-Mode Serial Transceiver
© Copyright 2003 Sipex Corporation
5
OTHER AC CHARACTERISTICS (continued)
PARAMETER
MIN.
TYP.
MAX.
UNITS
CONDITIONS
DELAY TIME FROM ENABLE MODE TO TRI–STATE MODE
RS-232 (SINGLE–ENDED MODE)
tPZL; Enable to Output LOW
tPZH; Enable to Output HIGH
tPLZ; Disable from Output LOW
tPHZ; Disable from Output HIGH
190
130
270
400
ns
ns
ns
ns
3kΩ pull–up to output
3kΩ pull–down to output
5V to input
GND to input
RS-422 (DIFFERENTIAL MODE)
tPZL; Enable to Output LOW
100
100
130
140
ns
ns
ns
ns
3kΩ pull–up to output
3kΩ pull–down to output
5V to input
tPZH; Enable to Output HIGH
tPLZ; Disable from Output LOW
tPHZ; Disable from Output HIGH
GND to input
Notes:
1.
2.
3.
4.
Measured from 2.5V of RIN to 2.5V of ROUT.
Measured from one–half of R to 2.5V of ROUT
.
.
Measured from 1.5V of TIN to IoNne–half of TOUT
Measured from 2.5V of RO to 0V of A and B.
POWER MATRIX
k;
or
Mode Open Input Input to 5V Input to GND AC Signal 5V to Input GND to Input AC Signal
Conditions
to Input with Load with Load
with Load
V.35
1110
20.71mA
21.5mA
20.74mA
28.32mA 58.19mA
55.64mA
73.08mA
With external driver output
termination network;
Input = 0.8V to 2V, 60kHz;
Load = 3kΩ, 2500pF for
RS-232; load = 100Ω for V.35
RS-232
0010
22.53mA
17.93mA
17.82mA
19.93mA
22.41mA
17.83mA
17.74mA
19.87mA
23.15mA
14.13mA
14.07mA
17.84mA
31.54mA 43.74mA
40.96mA
62.47mA
146.55mA
183.65mA
131.94mA
Input = 0.8V to 2V, 60kHz ;
Load = 3kΩ, 2500pF
RS-422
0100
32.92mA 143.47mA 140.65mA
32.85mA 182.93mA 180.71mA
23.57mA 134.90mA 131.35mA
Input = 0.8V to 2V, 2.5MHz;
Load = 100Ω
RS-485
0101
Input 0.8V to 2V, 2.5MHz;
Load = 54Ω
RS-449
1100
Input = 0.8V to 2V, 60kHz;
Load = 450Ω for RS-423;
Load = 100Ω for RS-422
EIA-530
1101
19.85mA
19.83mA
17.82mA
23.54mA 134.90mA 131.25mA
131.78mA
Input = 0.8V to 2V, 60kHz;
Load = 450Ω for RS-423;
Load = 100Ω for RS-422
*All Driver Input Common VCC=5V
Rev. 7/21/03
SP502 Multi-Mode Serial Transceiver
© Copyright 2003 Sipex Corporation
6
Pin 70 — RD(a) — Receive Data, analog input;
inverted; source for RxD.
PINOUT…
Pin 71 — RD(b) — Receive Data; analog input;
non-inverted; source for RxD.
RxD
1
2
3
4
5
6
7
8
9
60 GND
59 SD(b)
58 TR(a)
57 GND
56 TR(b)
RDEC
RDEC
0
1
2
CONTROL LINE GROUP
RDEC
RDEC
Pin 13 — DTR — Data Terminal Ready; TTL
input; source for TR(a) and TR(b) outputs.
Pin 16 — RTS — Ready To Send; TTL input;
source for RS(a) and RS(b) outputs.
Pin 17 — RL — Remote Loopback; TTL input;
source for RL(a) and RL(b) outputs.
Pin 19 — DCD— Data Carrier Detect; TTL
output; sourced from RR(a) and RR(b) inputs.
Pin 21 — RI — Ring In; TTL output; sourced
from IC(a) and IC(b) inputs.
3
ST/TT
GND
55 V
CC
54 RS(a)
53 GND
52 RS(b)
51 LL(a)
50 GND
49 LL(b)
V
CC
TDEC
3
TDEC 10
2
SP502
TDEC 11
1
TDEC 12
0
DTR 13
TxD 14
TxC 15
RTS 16
RL 17
48 V
CC
47 RL(a)
46 GND
45 RL(b)
44 ST(b)
43 GND
42 ST(a)
NC 18
DCD 19
RxC 20
41
V
CC
Pin 24 — LL — Local Loopback; TTL input;
source for LL(a) and LL(b) outputs.
Note: NC (No Connection) pins should be left floating.
Internal signals may be present.
Pin 35 — RR(a)— Receiver Ready; analog
input, inverted; source for DCD.
Pin 36 — RR(b)— Receiver Ready; analog
input, non-inverted; source for DCD.
Pin 39 — IC(a)— Incoming Call; analog input,
inverted; source for RI.
Pin 40 — IC(b)— Incoming Call; analog input,
non-inverted; source for RI.
Pin 45 — RL(b) — Remote Loopback; analog
output, non-inverted; sourced from RL.
Pin 47 — RL(a) — Remote Loopback; analog
output inverted; sourced from RL.
Pin 49— LL(b) — Local Loopback; analog
output, non-inverted; sourced from LL.
Pin 51 — LL(a) — Local Loopback; analog
output, inverted; sourced from LL.
Pin 52 — RS(b) — Ready To Send; analog
output, non-inverted; sourced from RTS.
Pin 54 — RS(a) — Ready To Send; analog
output, inverted; sourced from RTS.
Pin 56 — TR(b) — Terminal Ready; analog
output, non-inverted; sourced from DTR.
Pin 58 — TR(a) — Terminal Ready; analog
output, inverted; sourced from DTR.
Pin 66 — CS(a)— Clear To Send; analog input,
inverted; source for CTS.
PIN ASSIGNMENTS…
CLOCK AND DATA GROUP
Pin 1 — RxD — Receive Data; TTL output,
sourced from RD(a) and RD(b) inputs.
Pin 14 — TxD — TTL input ; transmit data
source for SD(a) and SD(b) outputs.
Pin 15 — TxC — Transmit Clock; common
TTL input for both ST and TT driver outputs.
Pin 20 — RxC — Receive Clock; TTL output
sourced from RT(a) and RT(b) inputs.
Pin 37 — RT(a) — Receive Timing; analog
input, inverted; source for RxC.
Pin 38 — RT(b) — Receive Timing; analog
input, non-inverted; source for RxC.
Pin 42 — ST(a) — Send Timing; analog output,
inverted; sourced from ST.
Pin 44 — ST(b) — Send Timing; analog output,
non-inverted; sourced from ST.
Pin 59 — SD(b) — Analog Out — Send data,
non-inverted; sourced from TxD.
Pin 61 — SD(a) — Analog Out — Send data,
inverted; sourced from TxD.
Pin 63 — TT(a) — Analog In or Out —
Terminal Timing, inverted; sourced to TxC or
RxT.
Pin 65 — TT(b) — Analog In or Out —
TerminalTiming,non–inverted;sourcedtoTxC
or RxT.
Pin 67 — CS(b)— Clear To Send; analog input,
non-inverted; source for CTS.
Pin 68 — DM(a)— Data Mode; analog input,
inverted; source for DSR.
Pin 69 — DM(b)— Data Mode; analog input,
non-inverted; source for DSR.
Rev. 7/21/03
SP502 Multi-Mode Serial Transceiver
© Copyright 2003 Sipex Corporation
7
device is packaged in an 80–pin Quad FlatPack
package.
Pin 78 — DSR— Data Set Ready; TTL output;
sourced from DM(a), DM(b) inputs.
Pin 80 — CTS— Clear To Send; TTL output;
sourced from CS(a) and CS(b) inputs.
The SP502 is ideally suited for wide area net-
work connectivity based on the interface modes
offered and the driver and receiver configura-
tions. The SP502 has five (5) independent driv-
ers and six (6) independent receivers and one
half–duplex transceiver channel, which allows
a maximum of six (6) drivers and seven (7)
receivers. The driver and receiver configuration
for the SP502 is ideal for DTE applications. The
SP502 is made up of four separate circuit blocks
– the charge pump, drivers, receivers, and
decoder. Each of these circuit blocks is de-
scribed in detail below.
CONTROL REGISTERS
Pins 2–5 — RDEC0 – RDEC3 — Receiver
decoderegister;configuresreceivermodes;TTL
inputs.
Pin 6 — ST/TT — Enables ST or TT drivers,
TTL input.
Pins 12–9 — TDEC0 – TDEC3 — Transmitter
decode register; configures transmitter modes;
TTL inputs.
POWER SUPPLIES
Pins 8, 25, 33, 41, 48, 55, 62, 73, 74 — VCC
+5V input.
—
Pins 7, 29, 34, 43, 46, 50, 53, 57, 60, 64, 72, 75
— GND — Ground.
THEORY OF OPERATION
Pin27—VDD +10VChargePumpCapacitor—
Connects from VDD to VCC. Suggested capaci-
tor size is 22µF, 16V.
Charge–Pump
The charge pump is a Sipex patented design
(5,306,954) and uses a unique approach com-
pared to older less efficient designs. The charge
pump still requires four external capacitors, but
uses a four–phase voltage shifting technique to
attain symmetrical 10V power supplies. Figure
3a shows the waveform found on the positive
side of capcitor C2, and Figure 3b shows the
negative side of capcitor C2. There is a free–
running oscillator that controls the four phases
of the voltage shifting. A description of each
phase follows.
Pin 32 — VSS –10V Charge Pump Capacitor —
Connects from ground to VSS. Suggested ca-
pacitor size is 22µF, 16V.
–
Pins 26 and 30 — C1+ and C1 — Charge Pump
–
Capacitor — Connects from C1+ to C1 . Sug-
gested capacitor size is 22µF, 16V.
–
Pins 28 and 31 — C2+ and C2 — Charge Pump
–
Capacitor — Connects from C2+ to C2 . Sug-
gested capacitor size is 22µF, 16V.
NOTE: NC pins should be left floating; internal
signals may be present.
Phase 1
— VSS charge storage —During this phase of
the clock cycle, the positive side of capacitors
C1 and C2 are initially charged to +5V. Cl+ is
–
FEATURES…
then switched to ground and the charge on C1
–
+
The SP502 is a highly integrated serial trans-
ceiver that allows software control of its inter-
face modes. The SP502 offers hardware inter-
facemodesforRS-232(V.28),RS-422A(V.11),
RS-449, RS-485, V.35, and EIA-530. The inter-
face mode selection is done via an 8–bit switch;
four (4) bits control the drivers and four (4) bits
control the receivers. The SP502 is fabricated
usinglow–powerBiCMOSprocesstechnology,
and incorporates a Sipex patented (5,306,954)
chargepumpallowing+5Vonlyoperation.Each
is transferred to C2 . Since C2 is connected
to +5V, the voltage potential across capacitor
C2 is now 10V.
Phase 2
— VSS transfer — Phase two of the clock con-
nects the negative terminal of C2 to the VSS
storage capacitor and the positive terminal of C2
to ground, and transfers the generated –l0V to
C3. Simultaneously, the positive side of capaci-
Rev. 7/21/03
SP502 Multi-Mode Serial Transceiver
© Copyright 2003 Sipex Corporation
8
V
= +5V
CC
V
= +5V
CC
C
+
4
C
+
+5V
4
–
+
V
V
Storage Capacitor
Storage Capacitor
–
+
DD
V
V
Storage Capacitor
Storage Capacitor
DD
+
–
+
–
+
–
+
–
C
C
2
1
C
C
2
1
–
–
SS
SS
C
–10V
3
C
–5V
–5V
3
Figure 1. Charge Pump Phase 1.
Figure 2. Charge Pump Phase 2.
tor C 1 is switched to +5V and the negative side
is connected to ground.
proaches that generate V– from V+ will show a
decrease in the magnitude of V– compared to
V+ due to the inherent inefficiencies in the design.
Phase 3
— VDD charge storage — The third phase of the
clock is identical to the first phase — the charge
transferred in C1 produces –5V in the negative
terminal of C1, which is applied to the negative
side of capacitor C2. Since C2 is at +5V, the
voltage potential across C2 is l0V.
The clock rate for the charge pump typically
operates at 15kHz. The external capacitors must
be 22µF with a 16V breakdown rating. Two
external Schottky diodes connected as inFigure
6 are required for high rate of rise power sup-
plies.
+
Phase 4
— VDD transfer — The fourth phase of the clock
connects the negative terminal of C2 to ground
and transfers the generated l0V across C2 to C4,
the VDD storage capacitor. Again, simultaneously
with this, the positive side of capacitor C1 is
switched to +5V and the negative side is con-
nected to ground, and the cycle begins again.
External Power Supplies
For applications that do not require +5V only,
external supplies can be applied at the V+ and
V– pins. The value of the external supply volt-
ages must be no greater than ±l0V. The current
drain for the ±10V supplies is used for RS-232,
and RS-423 drivers. For the RS-232 driver the
current requirement will be 3.5mA per driver,
and for the RS-423 driver the worst case current
drain will be 11mA per driver. The external
Since both V+ and V– are separately generated
from VCC in a no–load condition, V+ and V–
will be symmetrical. Older charge pump ap-
+10V
+
C2
a)
b)
GND
GND
–
C2
–10V
Figure 3. Charge Pump Waveforms
Rev. 7/21/03
SP502 Multi-Mode Serial Transceiver
© Copyright 2003 Sipex Corporation
9
V
= +5V
CC
V
= +5V
CC
C
+5V
4
+
–
+
V
V
Storage Capacitor
Storage Capacitor
DD
C
+
+10V
4
+
–
+
–
C
C
2
–
+
1
V
V
Storage Capacitor
Storage Capacitor
DD
–
+
–
+
–
SS
C
C
2
1
–
C
–5V
–5V
3
SS
C
3
Figure 5. Charge Pump Phase 4.
Figure 4. Charge Pump Phase 3.
power supplies should provide a power
supply sequence of: +l0V, then +5V, followed
by –l0V.
arranged such that for each mode of operation
the relative position and functionality of the
drivers are set up to accommodate the selected
interface mode. As the mode of the drivers is
changed,theelectricalcharacteristicswillchange
to support the requirements of clock, data, and
control line signal levels. Table 1 shows a sum-
mary of the electrical characteristics of the driv-
ers in the different interface modes. Unused
driver inputs can be left floating; however, to
ensure a desired state with no input signal, pull–
up resistors to +5V or pull–down resistors to
ground are suggested. Since the driver inputs
are both TTL or CMOS compatible, any value
resistor less than 100kΩ will suffice.
Drivers
The SP502 has six (6) drivers which can be
programmed in six different modes of opera-
tion. One of the drivers for the SP502 is inter-
nally connected to an internal receiver input to
make up a half-duplex configuration. As shown
in the Mode Diagrams, the driver input of the
half-duplex channel is shared with an adjacent
driver such that when one is active the other is
disabled.
Control for the mode selection is done via a
four–bit control word. The SP502 does not have
a latch; the control word must be externally
latched either high or low to write the appropri-
ate code into the SP502. The drivers are pre-
There are three basic types of driver circuits —
RS-232, RS-423, and RS-485. The RS-232 driv-
ers output a minimum of ±5V level single–ended
signals (with 3kΩ and 2500pF loading), and
Pin Label
TDEC3–TDEC0
SD(a)
Mode:
0000
RS-232
0010
V.35
1110
RS-422
0100
RS-485
0101
RS-449
1100
EIA-530
1101
tri–state
tri–state
tri–state
tri–state
tri–state
tri–state
tri–state
tri–state
tri–state
tri–state
tri–state
tri–state
tri–state
tri–state
RS-232
tri–state
RS-232
tri–state
RS-232
tri–state
RS-232
tri–state
RS-232
tri–state
RS-232
tri–state
RS-232
tri–state
V.35–
RS-422–
RS-422+
RS-422–
RS-422+
RS-422–
RS-422+
RS-422–
RS-422+
RS-422–
RS-422+
RS-422–
RS-422+
RS-422–
RS-422+
RS-485–
RS-485+
RS-485–
RS-485+
RS-485–
RS-485+
RS-485–
RS-485+
RS-485–
RS-485+
RS-485–
RS-485+
RS-485–
RS-485+
RS-422–
RS-422+
RS-422–
RS-422+
RS-422–
RS-422+
RS-423
tri–state
RS-423
tri–state
RS-422–
RS-422+
RS-422–
RS-422+
RS-422–
RS-422+
RS-422–
RS-422+
RS-422–
RS-422+
RS-423
tri–state
RS-423
tri–state
RS-422–
RS-422+
RS-422–
RS-422+
SD(b)
V.35+
TR(a)
RS-232
tri–state
RS-232
tri–state
RS-232
tri–state
RS-232
tri–state
V.35–
TR(b)
RS(a)
RS(b)
RL(a)
RL(b)
LL(a)
LL(b)
ST(a)
ST(b)
V.35+
TT(a)
V.35–
TT(b)
V.35+
*The ST and TT driver outputs cannot be enabled simultaneously.
Table 1. SP502 Drivers
Rev. 7/21/03
SP502 Multi-Mode Serial Transceiver
© Copyright 2003 Sipex Corporation
10
+5V, ±5%
1N5819
D
2
22µF (V decoupling)
CC
All VCC connections can be tied
+
+
'together. Charge pump capacitors must
be placed as close to the package as
possible.
D1 and D2 are Schottky diodes. They
are necessary to guard against VCC
rates of rise greater than 1V/µs, which
can cause start–up problems.
22µF, 16V
27
25
V
V
CC
DD
+
196Ω
26
422Ω
C
1
+
422Ω
196Ω
22µF
16V
422Ω
30
28
–
C
C
1
V.35 External
Driver Output
Termination Resistors
Charge
Pump
+
196Ω
422Ω
422Ω
2
+
22µF
16V
422Ω
196Ω
31
–
C
V
2
1N5819
D
1
+
GND
SS
32
22µF, 16V
SP502
1
1
1
0
47Ω
47Ω
120Ω
Driver
Decode
V.35 External
Receiver Input
Termination Resistors
47Ω
47Ω
120Ω
Ext.
Latch
1
1
1
0
Receiver
Decode
For NET2 certified circuits, please contact the factory.
Figure 6. Typical Operating Circuit
Rev. 7/21/03
SP502 Multi-Mode Serial Transceiver
© Copyright 2003 Sipex Corporation
11
can operate up to 120kbps. The RS-232 drivers
are used in RS-232 mode for all signals, and also
in V.35 mode where they are used as the control
line signals.
ance for V.35. For applications that require
V.11 signals for clock and data instead of V.35
levels, omit the external termination networks.
All of the differential drivers, RS-485, RS-422,
and V.35 can operate up to 5Mbps.
The RS-423 drivers output a minimum of ±3.6V
level single–ended signals (with 450Ω loading)
and can operate up to 120kbps. Open circuit
VOL and VOH measurements may exceed the
±6V limitation of RS-423. The RS-423 drivers
are used in RS-449 and EIA-530 modes as RL
and LL outputs.
Receivers
The SP502 is equipped with seven (7) receivers
which can be programmed in six (6) different
modes of operation. One of the seven (7) receiv-
ers(RxT)ispartofahalf-duplexchannel, which
means its inputs are shared with a driver
output, as shown in the Mode Diagrams. The
RxT receiver has its inputs internally connected
to the TT(a) and TT(b) pins. The select pin
labeled ST/TT enables either the TT-driver or
the ST-driver, but it does not disable the re-
ceiver. The RxT receiver is always connected to
the TT(a) and TT(b) pins. Any signal that is
received or transmitted on TT(a) and TT(b) will
trigger a TTL-output at the RxT pin.
The third type of driver supports RS-485, which
is a differential signal that can maintain ±1.5V
differential output levels with a worst case load
of 54Ω. The signal levels and drive capability of
the RS-485 drivers allow the drivers to also
support RS-422 requirements of ±2V differen-
tial output levels with 100Ω loads. The RS-422
drivers are used in RS-449 and EIA-530 modes
as clock, data, and some control line signals.
Control for the mode selection is done via a 4–
bit control word that is independent from the
driver control word. The coding for the drivers
andreceiversisidentical.Therefore,ifthemodes
for the drivers and receivers are supposed to be
identical in the application, the control lines can
be tied together.
The RS-485–type drivers are also used in the
V.35 mode. V.35 levels require ±0.55V signals
with a load of 100Ω. In order to meet the voltage
requirements of V.35, external series resistors
with source impedance termination resistors
mustbeimplementedtovoltagedividethedriver
outputs from 0 to +5V to 0 to +0.55V. Figure 6
shows the values of the resistor network and
how to connect them. The termination network
also achieves the 50Ω to 150Ω source imped-
Like the drivers, the receivers are pre-arranged
forthespecificrequirementsoftheinterface. As
the operating mode of the receivers is changed,
Pin Label
RDEC3–RDEC0
RD(a)
Mode:
RS-232
0010
V.35
1110
RS-422
0100
RS-485
0101
RS-449
1100
EIA-530
1101
0000
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
RS-232
V.35–
RS-422–
RS-422+
RS-422–
RS-422+
RS-422–
RS-422+
RS-422–
RS-422+
RS-422–
RS-422+
RS-422–
RS-422+
RS-422–
RS-422+
RS-485–
RS-485+
RS-485–
RS-485+
RS-485–
RS-485+
RS-485–
RS-485+
RS-485–
RS-485+
RS-485–
RS-485+
RS-485–
RS-485+
RS-422–
RS-422+
RS-422–
RS-422+
RS-422–
RS-422+
RS-422–
RS-422+
RS-422–
RS-422+
RS-423
RS-422–
RS-422+
RS-422–
RS-422+
RS-422–
RS-422+
RS-422–
RS-422+
RS-422–
RS-422+
RS-423
RD(b)
15kΩ to GND
RS-232
V.35+
RT(a)
V.35–
RT(b)
15kΩ to GND
RS-232
V.35+
CS(a)
RS-232
15kΩ to GND
RS-232
15kΩ to GND
RS-232
15kΩ to GND
RS-232
15kΩ to GND
V.35–
CS(b)
15kΩ to GND
RS-232
DM(a)
DM(b)
15kΩ to GND
RS-232
RR(a)
RR(b)
15kΩ to GND
RS-232
IC(a)
IC(b)
15kΩ to GND
RS-232
15kΩ to GND
RS-422–
RS-422+
15kΩ to GND
RS-422–
RS-422+
SCT(a)
SCT(b)
15kΩ to GND
V.35+
*TT(a) and TT(b) can be programmed as driver outputs or receiver inputs.
Table 2. SP502 Receivers
Rev. 7/21/03
SP502 Multi-Mode Serial Transceiver
© Copyright 2003 Sipex Corporation
12
the electrical characteristics will change to sup-
port the requirements of clock, data, and control
line receivers. Table 2 shows a summary of the
electrical characteristics of the receivers in the
different interface modes. Unused receiver in-
puts can be left floating without causing oscilla-
tion. To ensure a desired state of the receiver
output, a pull–up resistor of 100kΩ to +5V
should be connected to the inverting input for a
logic LOW, or the non–inverting input for a
logic high. For single-ended receivers, a pull–
down resistor to ground of 5kΩ is internally
connected, which will ensure a logic HIGH
output.
Since the characteristics of an RS-422 receiver
are actually subsets of RS-485, the receivers for
RS-422 requirements are identical to the
RS-485 receivers. RS-422 receivers are used in
RS-449 and EIA-530 for receiving clock, data,
and some control line signals. The RS-485
receivers are also used for the V.35 mode. V.35
levels require the ±0.55V signals with a load of
100Ω. In order to meet the V.35 input imped-
ance of 100Ω, the external termination network
ofFigure6mustbeapplied.Thethresholdofthe
V.35 receiver is ±200mV. The V.35 receivers
can operate up to 5Mbps. All of the differential
receivers can receive data up to 5Mbps.
There are three basic types of receivers —
RS-232, RS-423, and RS-485. The RS-232
receiver is a single–ended input with a threshold
of 0.8V to 2.4V. The RS-232 receiver has an
operating voltage range of ±15V and can re-
ceive signals up to 120kbps. RS-232 receivers
are used in RS-232 mode for all signal types,
and in V.35 mode for control line signals.
Decoder
The SP502 has the ability to change the inter-
facemodeofthedriversorreceiversviaan8–bit
switch. The decoder for the drivers and receiv-
ers is not latched; it is merely a combinational
logic switch. The codes shown in Tables 1 and
2 are the only specified, valid modes for the
SP502. Undefined codes may represent other
interface modes not specified or random out-
puts (consult the factory for more information).
The drivers are controlled with the data bits
labeled TDEC3–TDEC0. The drivers can be put
into tri-state mode by writing 0000 to the driver
decodeswitch.Thereceiversarecontrolledwith
databitsRDEC3–RDEC0;thecode0000written
to the receivers will place the outputs in an
undetermined state. All receivers, with the ex-
ception of SCT, do not have tri-state capability;
the outputs will either be HIGH or LOW de-
pending upon the state of the receiver input.
The RS-423 receivers are also single–ended but
have an input threshold as low as ±200mV. The
inputimpedanceisguaranteedtobegreaterthan
4kΩ, with an operating voltage range of ±7V.
TheRS-423receiverscanoperateupto120kbps.
RS-423 receivers are used for the IC signal in
RS-449andEIA-530modes, asshowninTable2.
The third type of receiver supports RS-485,
which is a differential interface mode. The
RS-485 receiver has an input impedance of
15kΩ and a differential threshold of ±200mV.
Rev. 7/21/03
SP502 Multi-Mode Serial Transceiver
© Copyright 2003 Sipex Corporation
13
MODE: RS-232
DRIVER
2
RECEIVER
TDEC TDEC TDEC TDEC RDEC RDEC RDEC RDEC
3
3
1
0
2
1
0
0
0
1
0
0
0
1
0
RD(a) 70
RxD 1
14 TxD
61 SD(a)
13 DTR
58 TR(a)
16 RTS
54 RS(a)
17 RL
RT(a) 37
RxC 20
CS(a) 66
CTS 80
DM(a) 68
DSR 78
RR(a) 35
DCD 19
IC(a) 39
RI 21
47 RL(a)
24 LL
51 LL(a)
15 TxC
42 ST(a)
6 ST/TT
63 TT(a)
RxT 79
ST/TT
ST
Enabled
Disabled
TT
Disabled
Enabled
RxT*
Active
Inactive
1
0
* TT driver must be disabled to allow TT(a) and TT(b)
to serve as receiver inputs.
* When the RxT receiver is active, TT(a) and TT(b) act
as receiver inputs. When the RxT receiver is inactive,
it cannot serve as a receiver since its inputs are internally
connected to the TT(a) and TT(b) driver outputs.
Figure 7. Mode Diagram — RS-232
Rev. 7/21/03
SP502 Multi-Mode Serial Transceiver
© Copyright 2003 Sipex Corporation
14
MODE: V.35
DRIVER
RECEIVER
TDEC TDEC TDEC TDEC RDEC RDEC RDEC RDEC
3
2
1
0
3
2
1
0
1
1
1
0
1
1
1
0
14 TxD
RD(a) 70
RxD 1
61 SD(a)
59 SD(b)
RD(b) 71
RT(a) 37
13 DTR
58 TR(a)
16 RTS
54 RS(a)
17 RL
RxC 20
RT(b) 38
CS(a) 66
CTS 80
DM(a) 68
DSR 78
RR(a) 35
DCD 19
IC(a) 39
RI 21
47 RL(a)
24 LL
51 LL(a)
15 TxC
42 ST(a)
44 ST(b)
6
ST/TT
63 TT(a)
65 TT(b)
RxT 79
ST/TT
ST
Enabled
Disabled
TT
Disabled
Enabled
RxT*
Active
Inactive
1
0
* TT driver must be disabled to allow TT(a) and TT(b)
to serve as receiver inputs.
* When the RxT receiver is active, TT(a) and TT(b) act
as receiver inputs. When the RxT receiver is inactive,
it cannot serve as a receiver since its inputs are internally
connected to the TT(a) and TT(b) driver outputs.
Figure 8. Mode Diagram — V.35
Rev. 7/21/03
SP502 Multi-Mode Serial Transceiver
© Copyright 2003 Sipex Corporation
15
MODE: RS-422
DRIVER
2
RECEIVER
TDEC TDEC TDEC TDEC RDEC RDEC RDEC RDEC
3
3
1
0
2
1
0
0
1
0
0
0
1
0
0
14 TxD
RD(a) 70
RxD 1
61 SD(a)
59 SD(b)
RD(b) 71
RT(a) 37
13 DTR
58 TR(a)
56 TR(b)
RxC 20
RT(b) 38
CS(a) 66
16 RTS
54 RS(a)
52 RS(b)
CTS 80
CS(b) 67
17 RL
DM(a) 68
47 RL(a)
45 RL(b)
DSR 78
DM (b) 69
RR(a) 35
24 LL
51 LL(a)
49 LL(b)
DCD 19
RR(b) 36
IC(a) 39
15 TxC
42 ST(a)
44 ST(b)
RI 21
IC(b) 40
6
ST/TT
63 TT(a)
65 TT(b)
RxT 79
ST/TT
ST
Enabled
Disabled
TT
Disabled
Enabled
RxT*
Active
Inactive
1
0
* TT driver must be disabled to allow TT(a) and TT(b)
to serve as receiver inputs.
* When the RxT receiver is active, TT(a) and TT(b) act
as receiver inputs. When the RxT receiver is inactive,
it cannot serve as a receiver since its inputs are internally
connected to the TT(a) and TT(b) driver outputs.
Figure 9. Mode Diagram — RS-422
Rev. 7/21/03
SP502 Multi-Mode Serial Transceiver
© Copyright 2003 Sipex Corporation
16
MODE: RS-449
DRIVER
2
RECEIVER
TDEC TDEC TDEC TDEC RDEC RDEC RDEC RDEC
3
3
1
0
2
1
0
1
1
0
0
1
1
0
0
14 TxD
RD(a) 70
RxD 1
61 SD(a)
59 SD(b)
RD(b) 71
RT(a) 37
13 DTR
58 TR(a)
56 TR(b)
RxC 20
RT(b) 38
CS(a) 66
16 RTS
54 RS(a)
52 RS(b)
CTS 80
CS(b) 67
17 RL
DM(a) 68
47 RL(a)
DSR 78
DM (b) 69
RR(a) 35
DCD 19
RR(b) 36
IC(a) 39
RI 21
24 LL
51 LL(a)
15 TxC
42 ST(a)
44 ST(b)
6 ST/TT
63 TT(a)
65 TT(b)
RxT 79
ST/TT
ST
Enabled
Disabled
TT
Disabled
Enabled
RxT*
Active
Inactive
1
0
* TT driver must be disabled to allow TT(a) and TT(b)
to serve as receiver inputs.
* When the RxT receiver is active, TT(a) and TT(b) act
as receiver inputs. When the RxT receiver is inactive,
it cannot serve as a receiver since its inputs are internally
connected to the TT(a) and TT(b) driver outputs.
Figure 10. Mode Diagram — RS-449
Rev. 7/21/03
SP502 Multi-Mode Serial Transceiver
© Copyright 2003 Sipex Corporation
17
MODE: RS-485
DRIVER
2
RECEIVER
TDEC TDEC TDEC TDEC RDEC RDEC RDEC RDEC
3
3
1
0
2
1
0
0
1
0
1
0
1
0
1
14 TxD
RD(a) 70
RxD 1
61 SD(a)
59 SD(b)
RD(b) 71
RT(a) 37
13 DTR
58 TR(a)
56 TR(b)
RxC 20
RT(b) 38
CS(a) 66
16 RTS
54 RS(a)
52 RS(b)
CTS 80
CS(b) 67
17 RL
DM(a) 68
47 RL(a)
45 RL(b)
DSR 78
DM (b) 69
RR(a) 35
24 LL
51 LL(a)
49 LL(b)
DCD 19
RR(b) 36
IC(a) 39
15 TxC
42 ST(a)
44 ST(b)
RI 21
IC(b) 40
6
ST/TT
63 TT(a)
65 TT(b)
RxT 79
ST/TT
ST
Enabled
Disabled
TT
Disabled
Enabled
RxT*
Active
Inactive
1
0
* TT driver must be disabled to allow TT(a) and TT(b)
to serve as receiver inputs.
* When the RxT receiver is active, TT(a) and TT(b) act
as receiver inputs. When the RxT receiver is inactive,
it cannot serve as a receiver since its inputs are internally
connected to the TT(a) and TT(b) driver outputs.
Figure 11. Mode Diagram — RS-485
Rev. 7/21/03
SP502 Multi-Mode Serial Transceiver
© Copyright 2003 Sipex Corporation
18
MODE: EIA-530
DRIVER
2
RECEIVER
TDEC TDEC TDEC TDEC RDEC RDEC RDEC RDEC
3
3
1
0
2
1
0
1
1
0
1
1
1
0
1
14 TxD
RD(a) 70
RxD 1
61 SD(a)
59 SD(b)
RD(b) 71
RT(a) 37
13 DTR
58 TR(a)
56 TR(b)
RxC 20
RT(b) 38
CS(a) 66
16 RTS
54 RS(a)
52 RS(b)
CTS 80
CS(b) 67
17 RL
DM(a) 68
47 RL(a)
DSR 78
DM (b) 69
RR(a) 35
DCD 19
RR(b) 36
IC(a) 39
RI 21
24 LL
51 LL(a)
15 TxC
42 ST(a)
44 ST(b)
6 ST/TT
63 TT(a)
65 TT(b)
RxT 79
ST/TT
ST
Enabled
Disabled
TT
Disabled
Enabled
RxT*
Active
Inactive
1
0
* TT driver must be disabled to allow TT(a) and TT(b)
to serve as receiver inputs.
* When the RxT receiver is active, TT(a) and TT(b) act
as receiver inputs. When the RxT receiver is inactive,
it cannot serve as a receiver since its inputs are internally
connected to the TT(a) and TT(b) driver outputs.
Figure 12. Mode Diagram — EIA-530
Rev. 7/21/03
SP502 Multi-Mode Serial Transceiver
© Copyright 2003 Sipex Corporation
19
APPLICATION EXAMPLE
The example application that follows is a fully
configured serial I/O channel in a DTE configu-
ration. The example is comprised of the follow-
ing functional elements:
• Processor
• SCC
• SP502
• Mode Select Register (R0[WR])
• RL & LL Control Bit Register (R1[WR])
• RI Status Bit Register (R1[RD])
• Address Decode Logic
• Baud Rate Clock Source
• I/O Connector Interface
support standards other than EIA-530, such as
V.35, RS-232, RS-449, etc. with an appropriate
cable adapter.
The SP502 driver and receiver modes are inde-
pendently configured by programming the
SP502’s RDEC and TDEC input pins. In the
example, the pins are driven by the Mode Select
Register with a programmed value stored by the
user’s software.
Since the SP502 is shown in a DTE configura-
tion, the example assumes that any synchronous
interface clocking will be provided by the at-
tached DCE device. Consequently, the ST/TT
pin is tied to +5V, thus causing the SP502 to
receive the transmit clock on the TT(a) and
TT(b)inputpinsandoutputthetransmitclockto
the SCC on the RxT output pin. The receive
clock is input to the SP502 on the RT(a) and
RT(b) pins and output to the SCC on the RxC
pin.
Each of the elements of the application example
are described below. Please refer to Figure13.
Processor
The example schematic shows a generic 8-bit
processor connected to a generic SCC. The
processor is also connected to three registers.
The registers are described in further detail
below.
Mode Select Register
The mode select register is an 8-bit latch at-
tached to the Processor data bus. The Processor,
under user-software control, can program the
Mode Select Register with the appropriate val-
ues to select the SP502’s driver and receiver
modes.
Address Decode Logic
The address decode logic is connected to the
Processor control and address busses and pro-
vides the logic necessary to decode the I/O read
and write operations for the SCC, Mode Select
Register, RL and LL Control Bit Register and
the RI Status Bit Register.
The table shown on the schematic below the
register lists the values for programming the
register to drive the RDEC and TDEC pins on
the SP502 for the desired physical level inter-
face. The receivers and drivers can be pro-
grammedindependently, butinthisexamplethe
ModeSelectRegistermustbeprogrammedwith
both the RDEC and TDEC values at the same
time. This is because the RDEC and TDEC pins
are driven from the same 8-bit latch.
SCC
The SCC provides the I/O functions for a single
serial channel. The SCC is connected to the
Processor I/O bus and is programmed by the
user software. The SCC’s TTL-level serial I/O
pins are connected to the corresponding
TTL-level serial I/O pins on the SP502.
SP502
The SP502 provides buffering and translation
from TTL levels to the selected physical level
interface standard, such as RS-232, V.35, etc.
The physical level interface pins are connected
to a standard 25 pin D-subminiature connector
wired in a DTE configuration with the pin as-
signments corresponding to the EIA-530 speci-
fication. This choice was purely arbitrary. How-
ever, it provides all the necessary signals to
Note that selecting modes for TDEC that are
shown in the table as undefined will result in the
drivers operating in an undefined mode and
should not be used. Likewise, selecting modes
for RDEC that are shown in the table as unde-
fined will result in indeterminate logic levels
present on the TTL outputs of the SP502. Unde-
fined RDEC or TDEC values should never be
programmed.
Rev. 7/21/03
SP502 Multi-Mode Serial Transceiver
© Copyright 2003 Sipex Corporation
20
7 3 , 7 4
4 8 , 5 5 , 6 2 ,
, 2 8 5 , 3 3 , 4 1 ,
C C
V
2 7
3 0
2 6
D D
+
V
-
1 C
S P 5 0 2
1
+ C
2 8
2
+ C
3 1
-
2 C
3 2
S S
V
L a t c h
L a t c h
S C C
D e c o d e L o g i c
A d d r e s s
P r o c e s s o r
Figure 13. DTE Serial Communications Channel
Rev. 7/21/03
SP502 Multi-Mode Serial Transceiver
© Copyright 2003 Sipex Corporation
21
Several other approaches for driving the RDEC
and TDEC signals are possible. One approach
would use two independent 4-bit latches, one
each to drive the RDEC and TDEC pins as
separate groups. Another approach would use
one 4-bit latch, each output of the latch would
drive a corresponding pair of RDEC/TDEC
signals. For instance, RDEC0 and TDEC0 could
be tied together and be driven by the low order
bit of the 4-bit latch.
Baud Rate Clock Source
Most SCCs require an external clock source for
operation in asynchronous and self-clocking
applications.
I/O Connector Interface
The I/O connector is wired to the SP502A such
that the interface represents a DTE device. As
shown, the connector is wired in an EIA-530
configuration with EIA-530 signal mnemonics.
A 25-pin connector wired to the EIA-530 speci-
fication provides pins for all interface signals
supported by the SP502. If the SP502 is pro-
grammed for other physical interfaces, such as
V.35, then an adapter cable will provide the
necessaryconversionfromtheEIA-530pin-outs
to those required by the V.35 standard together
with its ISO-2593 connector.
RL & LL Control Bit Registers
A 2-bit latch is used to allow the Processor to
program the states of the RL and LL interface
signals. This latch is necessary since most SCCs
do not support RL and LL control signals.
RI Status Bit Register
A 1-bit read register is implemented using a
tri-state buffer. This will allow the Processor to
read the state of the RI (Ring Indicator) inter-
face signal. This is necessary since most SCCs
do not support the RI interface signal.
Notes Regarding V.35 Operation
The user will have to provide additional resistor
networksifcorrectV.35signallevelsandtermi-
nation impedances are required. This is neces-
sary because the SP502 does not provide V.35
signal terminations when programmed for V.35
operation. Twoapproachesarepossible. First, if
the SP502 is permanently programmed to oper-
ate as V.35 only, with no other interface stan-
dard required, then the appropriate resistors can
bemountedonthePCBneartheSP502. Second,
if the SP502will be programmed for a variety of
standards, then a better approach might be to
provide the resistors as part of the cable adapter
assembly used to convert from the standard
EIA-530 connector pin-outs shown in the ex-
ample to the V.35/ISO-2593 connector and
pin-outs.
The example interface shows the SP502A’s
IC(a) input tied to the EIA-530 signal TM (Test
Mode). EIA530 does not specify an RI signal. If
EIA-530 operation is required, the RI Status Bit
Register could be used to monitor the condition
oftheTMsignaloritcouldbeignored. Forother
interface standards, the connector pin 25 on the
schematic could be tied to the RI signal through
a cable adapter arrangement. For instance, if
RS-232 operation is used, pin 25 of the connec-
tor could be tied to pin 22 of the RS-232 adapter
(circuit CE) and the RI Status Bit Register
then used to monitor the RS-232 signal for ring
indicator.
Rev. 7/21/03
SP502 Multi-Mode Serial Transceiver
© Copyright 2003 Sipex Corporation
22
If a logic one is asserted, the corresponding red
LED will be lit. If a zero is asserted, the corre-
sponding red LED will not be lit.
SP502/SP503 EVALUATION BOARD
The SP502/SP503 Evaluation Board (EB) Is
designedtoofferasmuchflexibilitytotheuseras
possible. Each board comes equipped with an
80-pin QFP Zero-Insertion Force socket to allow
for testing of multiple devices. The control lines
and inputs and outputs of the device can be
controlledeithermanuallyorviaadatabusunder
software control. There is a 50-pin connector to
allow for easy connection to an existing system
via ribbon cable. There are also open areas on the
PC board to add additional circuitry to support
application-specific requirements.
Software Control
A 50-pin connector brings all the analog and
digitalI/Olines, VCC, andGNDtotheedgeofthe
card. This can be wired to the user’s existing
design via ribbon cable. The pinout for the
connector is described in the following section.
When the evaluation board is operated under
software control, the DlP switch should be set
up so that all bits are LOW (all LEDs off). This
will tie pull-down resistors from the inputs to
ground and let the external system control the
state of the control inputs.
Manual Control
The SP502/SP503EB will support both the
SP502 or SP503 multi-mode serial transceivers.
When used for the SP502, disregard all notation
on the board that is in [brackets] . The SP502 has
a half-duplex connection between the RxT re-
ceiver and the TT driver. Due to this internal
connection, the RxT receiver inputs can be ac-
cessed via the TT(a) and TT(b) pins. If the user
needs separate receiver input test pins, jumpers
JP1 and JP2 can be inserted to allow for separate
receiver inputs located at SCT(a) and SCT(b).
The corresponding TTL output for this receiver
is labeled as SCT. This test point is tied to pin 79
of the SP502 or SP503. Pin 7 of the evaluation
board is connected to the DIP switch, and is
labeled as (SCTEN). When used with the SP502,
this pin should be switched to a low state. When
the evaluation board is used with the SP503, pin
7 is a tri-state control pin for the SCT receiver.
Power and Ground Requirements
The evaluation board layout has been optimized
for performance by using basic analog circuit
techniques, The four charge-pump capacitors
mustbe22µF(16V)andbeplacedasclosetothe
unit as possible; tantalum capacitors are sug-
gested. The decoupling capacitor must be a
minimumof1µF;dependingupontheoperating
environment, 10µF should be enough for worst
case situations. The ground plane for the part
must be solid, extending completely under the
package. The power supplies for the device
should be as accurate as possible; for rated
performance ±5% is necessary. The power sup-
ply current will vary depending upon the se-
lected mode, the amount of loading and the data
rate. As a maximum, the user should reserve
200mA for ICC. The worst-case operating mode
is RS-485 under full load of six (6) drivers
supplying 1.6V to 54Ω loads. The power and
ground inputs can be supplied through either the
banana jacks on the evaluation board (Red = VCC
= +5V±5%; Black = GND) or through the con-
nector.
The transceiver I/O lines are brought out to test
pinsarrangedinthesameconfigurationasshown
elsewhereinthisdatasheet.Atoplayersilk-screen
shows the drivers and receivers to allow direct
correlation to the data sheet. The transmitter and
receiver decode bits are tied together and are
brought out to a DIP switch for manual control of
both the driver and receiver interface modes.
Since the coding for the drivers and receivers is
identical, the bits have been tied together. The
DIP switch has 7 positions, four of which are
reserved for the TDEC/RDEC control. The other
three are used as tri-state control pins. The labels
that are in [brackets] apply only to the SP503.
For reference, the 80-pin QFP Socket is a
TESCO part number FPQ-80-65-09A. The
50-pin connector is an AMP part number
749075-5.
Rev. 7/21/03
SP502 Multi-Mode Serial Transceiver
© Copyright 2003 Sipex Corporation
23
Figure 13. SP502/503 Evaluation Board Schematic
Rev. 7/21/03
SP502 Multi-Mode Serial Transceiver
© Copyright 2003 Sipex Corporation
24
Figure 14a. Evaluation Board — Top Layers
Rev. 7/21/03
SP502 Multi-Mode Serial Transceiver
© Copyright 2003 Sipex Corporation
25
Figure 14b. Evaluation Board — Bottom Layers
Rev. 7/21/03
SP502 Multi-Mode Serial Transceiver
© Copyright 2003 Sipex Corporation
26
Figure 15. External Transient Suppressors
Rev. 7/21/03
SP502 Multi-Mode Serial Transceiver
© Copyright 2003 Sipex Corporation
27
7
1
2
3
4
5
6
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
32
26 27 28 29 30 31
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
EDGE
CONNECTOR
DUT PIN
DESCRIPTIONS
EDGE
CONNECTOR
DUT PIN
DESCRIPTIONS
13 RD(a) (pin 70) – Analog In – Receive
data, inverted: source for RxD.
01 TxD (pin 14) –TTL Input – Transmit
data; source for SD(a) and SD(b) out-
puts.
14 DM(b) (pin 69) – Analog In – Data
mode, non–inverted; source for DSR.
02 DTR (pin 13) – TTL Input – Data
terminal ready: source for TR(a) and
TR(b) outputs.
l5 DM(a) (pin 68) – Analog In – Data
mode, inverted; source for DSR.
03 ST/TT (pin 6) –TTL Input – ST/TT
select pin; enables ST drivers and dis-
ables TT drivers when high. Disables
STdriversandenablesTTdriverswhen
low.
16 CS(b) (pin 67) – Analog In – Clear to
send; non–inverted; source for CTS.
17 CS(a) (pin 66) – Analog In – Clear to
send, inverted; source for CTS.
04 DEC3/RDEC3 (pin 5) – TTL Input –
Transmitter/Receiver decode register.
18 TT(b) (pin 65) – Analog Out –
Terminal timing, non–inverted:
sourced from TxC input.
05 TDEC2/RDEC2 (pin 4) – TTL Input –
Transmitter/Receiver decode register.
19 TT(a) (pin 63) – Analog Out –
Terminal timing; inverted: sourced
from TxC input.
06 TDEC1/RDEC1 (pin 3) – TTL Input –
Transmitter/Receiver decode register.
20 TR(a) (pin 58) – Analog Out – Termi-
nalready,inverted;sourcedfromDTR.
07 TDEC0/RDEC0 (pin 2) – TTL Input –
Transmitter/Receiver decode register.
21 TR(b) (pin 56) – Analog Out – Termi-
nal ready; non–inverted; sourced from
DTR.
08 RxD (pin 1 ) – TTL Output – Receive
data; sourced from RD(a) and RD)b)
inputs.
22 SD(a) (pin 61) – Analog Out – Send
data, inverted; sourced from TxD.
09 CTS (pin 80) – TTL Output – Clear to
send; sourced from CS(a) and CS(b)
inputs.
23 SD(b) (pin 59) – Analog Out – Send
data;non–inverted;sourcedfromTxD.
10 RxT (pin 79) – TTL Output – RxT;
sourced from TT(a), TT(b) inputs.
24 RS(a)(pin54)–AnalogOut–Readyto
send; inverted; sourced from RTS.
11 DSR (pin 78) – TTL Output – Data set
ready;sourcedfromDM(a)andDM(b)
inputs.
25 RS(b) (pin 52) – Analog Out – Ready
to send, non–inverted; sourced from
RTS.
12 RD(b) (pin 71) – Analog In – Receive
data, non–inverted; source for RxD.
Rev. 7/21/03
SP502 Multi-Mode Serial Transceiver
© Copyright 2003 Sipex Corporation
28
7
1
2
3
4
5
6
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
32
26 27 28 29 30 31
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
EDGE
CONNECTOR
DUT PIN
DESCRIPTIONS
EDGE
CONNECTOR
DUT PIN
DESCRIPTIONS
26 ST (pin 22) – TTL Input – Send Tim-
ing; source for ST(a) and ST(b) out-
puts. SP503 only.
39 IC(a) (pin 39) – Analog In – Incoming
call; inverted; source for Rl.
40 RT(b) (pin 38) – Analog In – Receive
timing, non–inverted; source for RxC.
27 STEN (pin 23) – TTL Input — Driver
enable control pin; active low. SP503
only,
41 RT(a) (pin 37) – Analog In – Receive
timing; inverted; source from RxC.
28 SCT(a) (pin 76) – Analog Input – In-
verting; input for SCT receiver; SP503
only.
42 RR(b) (pin 36) – Analog In – Receiver
ready; non–inverted; source for DCD.
43 RR(a) (pin 35) – Analog In – Receiver
ready; inverted; source for DCD.
29 SCT(b)(pin77)–AnalogInput–Non–
inverting; input for SCT receiver.
SP503 only.
44 LL (pin 24) – TTL Input – Local
loopback; source for LL(a) and LL(b)
outputs.
30 VCC — +5V for all circuitry.
31 GND — signal and power ground.
45 Rl (pin 21) – TTL Output – Ring
indicator;sourcedfromIC(a)andIC(b)
inputs.
32 LL(a) (pin 51) – Analog Out – Local
loopback, inverted; sourced from LL.
33 LL(b) (pin 49) – Analog Out – Local
loopback, non–inverted sourced from
LL.
46 RxC (pin 20) – TTL Output – Receive
clock; sourced from RT(a) and RT(b)
inputs.
34 RL(a) (pin 47) – Analog Out – Remote
loopback; inverted; sourced from RL.
47 DCD (pin 19) – TTL Output – Data
carrier detect; sourced from RR(a) and
RR(b) inputs.
35 RL(b) (pin 45) – Analog Out – Remote
loopback; non–inverted; sourced from
RL.
48 RL (pin 17) – Analog Out – Remote
loopback; source for RL(a) and RL(b)
outputs.
36 ST(b) (pin 44) – Analog Out – Send
timing, non–inverted; sourced from
TxC.
49 RTS (pin 16) – TTL Input – Ready to
send; source for RS(a) and RS(b) out-
puts.
37 ST(a) (pin 42) – Analog Output –Send
timing, inverted; sourced from TxC.
50 TxC (pin 15) – TTL Input – Transmit
clock; source for TT(A) and TT(B)
outputs.
38 IC(b) (pin 40) – Analog In – Incoming
call; non–inverted; source for Rl.
Rev. 7/21/03
SP502 Multi-Mode Serial Transceiver
© Copyright 2003 Sipex Corporation
29
PACKAGE: 80 PIN MQFP
D
D1
D2
0.30" RAD. TYP.
PIN 1
c
0.20" RAD. TYP.
E1
C
L
5°-16°
E
E2
0° MIN.
0°–7°
5°-16°
C
L
L
L1
A2
A
Seating
Plane
A1
b
e
80–PIN MQFP
JEDEC MS-22
(BEC) Variation
DIMENSIONS
Minimum/Maximum
(mm)
COMMON DIMENTIONS
SYMBOL
MIN
NOM MAX
2.45
SYMBL MIN NOM MAX
A
A1
A2
b
c
L
0.11
23.00
0.00
1.80
0.22
0.25
0.73 0.88 1.03
1.60 BASIC
2.00
2.20
0.40
L1
D
17.20 BSC
14.00 BSC
12.35 REF
17.20 BSC
14.00 BSC
12.35 REF
0.65 BSC
80
D1
D2
E
E1
E2
e
N
80 PIN MQFP (MS-022 BC)
Rev. 7/21/03
SP502 Multi-Mode Serial Transceiver
© Copyright 2003 Sipex Corporation
30
PACKAGE: 80 PIN LQFP
D
0.2 RAD MAX.
c
D1
0.08 RAD MIN.
PIN 1
11° - 13°
0° Min
E1
C
L
E
0°–7°
11° - 13°
L
L1
C
L
A2
A
Seating
Plane
A1
b
e
80-PIN LQFP
JEDEC MS-026
(BEC) Variation
DIMENSIONS
Minimum/Maximum
(mm)
COMMON DIMENTIONS
SYMBOL
MIN
NOM MAX
1.60
SYMBL MIN NOM MAX
A
A1
A2
b
c
L
0.11
23.00
0.05
1.35
0.22
0.15
0.45 0.60 0.75
1.00 BASIC
1.40
0.32
1.45
0.38
L1
D
16.00 BSC
14.00 BSC
0.65 BSC
16.00 BSC
14.00 BSC
80
D1
e
E
E1
N
80 PIN LQFP
Rev. 7/21/03
SP502 Multi-Mode Serial Transceiver
© Copyright 2003 Sipex Corporation
31
ORDERING INFORMATION
Model
Temperature Range
Package Types
SP502CF ...............................................0°C to +70°C ............................80–pin JEDEC (MS-022 BC) MQFP
SP502CM ..............................................0°C to +70°C ........................... 80-pin JEDEC (MS-026 BEC) LQFP
Co rp o ra tio n
ANALOG EXCELLENCE
Sipex Corporation
Headquarters and
Sales Office
233 South Hillview Drive
Milpitas, CA 95035
TEL: (408) 934-7500
FAX: (408) 935-7600
Sales Office
22 Linnell Circle
Billerica, MA 01821
TEL: (978) 667-8700
FAX: (978) 670-9001
e-mail: sales@sipex.com
Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the
application or use of any product or circuit described hereing; neither does it convey any license under its patent rights nor the rights of others.
Rev. 7/21/03
SP502 Multi-Mode Serial Transceiver
© Copyright 2003 Sipex Corporation
32
相关型号:
SP503CF-L
Line Transceiver, 7 Func, 7 Driver, 7 Rcvr, BICMOS, PQFP80, LEAD FREE, MS-022BC, MQFP-80
SIPEX
©2020 ICPDF网 联系我们和版权申明