SP6120BEY-L/TR_技术文档

®

SP6120

Low Voltage, AnyFET^TM, Synchronous,Buck Controller

Ideal for 2A to 10A, High Performance, DC-DC Power Converters

FEATURES

■ Optimized for Single Supply, 3V - 5.5V Applications

■ High Efficiency: Greater Than 95% Possible

■ "AnyFET^TM"Technology: Capable Of Switching Either

PFET Or NFET High Side Switch

■ Selectable Discontinuous or Continuous Conduction

Mode For Use In Battery Or Bus Applications

■ Fast Transient Response

N/C

ENABLE

ISP

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

BST

GH

SWN

GND

PGND

GL

SP6120

ISN

16 Pin TSSOP

V_FB

COMP

SS

V_CC

PROG

R_OSC

■ 16-Pin TSSOP, Small Size

■ Accurate 1% Reference Over Line, Load and Temperature

■ Accurate 10% Frequency

Now Available in Lead Free Packaging

APPLICATIONS

■ DSP

■ Microprocessor Core

■ I/O & Logic

■ Industrial Control

■ Distributed Power

■ Low Voltage Power

■ Accurate, Rail to Rail, 43mV, Over-Current Sensing

■ Resistor Programmable Frequency

■ Resistor Programmable Output Voltage

■ Capacitor Programmable Soft Start

■ Low Quiescent Current: 950µA, 10µA in Shutdown

■ Hiccup Over-Current Protection

DESCRIPTION

The SP6120 is a fixed frequency, voltage mode, synchronous PWM controller designed to work

fromasingle5Vor3.3Vinputsupply. Sipex'sunique"AnyFET^TM"TechnologyallowstheSP6120

tobeusedforresolvingamultitudeofprice/performancetrade-offs. ItisseparatedfromthePWM

controller market by being the first controller to offer precision, speed, flexibility, protection and

efficiency over a wide range of operating conditions.

TYPICAL APPLICATIONS CIRCUIT

PMOS High Side Drive

NMOS High Side Drive

PROG = GND

3.3V

MBR0530

3.3V

PROG = V

V

CC

V

IN

C

IN

C

BST

1µF

NC

®®

BST

GH

NC

®®

330µF x 2

BST

GH

330µF x 2

ENABLE

QT1

ENABLE

ISP

ENABLE

QT

ENABLE

ISP

CS

RS

22.1k

L1

SWN

GND

22.1k

L1

SWN

GND

39nF

1.9V

1A to 8A

1.9V

39nF

SP6120

1A to 8A

ISN

V

ISN

V

OUT

2.5µH

V

PGND

GL

V

FB

PGND

GL

FB

QB

COMP

SS

DS

QB

C

OUT

470µF x 3

COMP

SS

DS

C

OUT

470µF x 3

RF

5.23k

RF

5.23k

RZ

15k

V

IN

V

RZ

15k

V

CC

IN

CC

C

SS

0.33µF

CP

R

CP

PROG

R

OSC

PROG

OSC

C

100pF

SS

0.33µF

100pF

CV

2.2µF

CV

CC

2.2µF

CC

R

OSC

RI

10k

RI

10k

R

OSC

CZ

4.7nF

CZ

4.7nF

18.7k

QT, QB = FAIRCHILD FDS6690A

QT1 = FAIRCHILD FDS6375 (PMOS only)

L1 = PANASONIC ETQP6F2R5SFA

DS = STMICROELECTRONICS STPS2L25U

C_IN= SANYO 6TPB330M

C_OUT= SANYO 4TPB470M

Date: 1/21/05

SP6120 Low Voltage, AnyFET^TM, Synchronous, Buck Controller

1

ABSOLUTE MAXIMUM RATINGS

These are stress ratings only and functional operation

of the device at these ratings or any other above those

indicated in the operation sections of the specifications

below is not implied. Exposure to absolute maximum

rating conditions for extended periods of time may

affect reliability.

Peak Output Current < 10µs

GH, GL ............................................................................. 2A

Operating Temperature Range

SP6120C ................................................ 0°C to +70°C

SP6120E .............................................. -40°C to +85°C

Junction Temperature, T_J.......................................... +125°C

Storage Temperature Range ....................... -65˚C to +150˚C

Power Dissipation

V_CC.................................................................................... 7V

BST ............................................................................. 13.2V

BST-SWN......................................................................... 7V

SWN ....................................................................... -1V to 7V

GH .......................................................... -0.3V to BST +0.3V

GH-SWN .......................................................................... 7V

All Other Pins ...........................................-0.3V to V_CC+0.3V

ESD Rating ............................................................ 2kV HBM

ELECTRICAL CHARACTERISTICS

Unless otherwise specified: 3.0V < V_CC<5.5V, 3.0V < BST < 13.2, R_OSC= 18.7kΩ, C_COMP= 0.1µF, C_SS= 0.1µF, ENABLE = 3V,

CGH = CGL = 3.3nF, V_FB= 1.25V, ISP = ISN = 1.25V, SWN = GND = PGND = 0V, -40°C < T_AMB<85°C (Note 1)

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

QUIESCENT CURRENT

V

_CCSupply Current

No Switching

ENABLE = 0V

No Switching

-

0.95

5

1.8

20

mA

µA

V_CCSupply Current (Disabled)

BST Supply Current

1

ERROR AMPLIFIER

Error Amplifier Transconductance

COMP Sink Current

600

35

µS

µA

V

_FB= 1.35V, COMP = 0.5V, No

15

65

Faults

COMP Source Current

V_FB= 1.15V, COMP = 1.6V

35

3

µA

MOhm

nA

COMP Output Impedence

V_FBInput Bias Current

-

60

100

REFERENCE

Error Amplifier Reference

Trimmed with Error Amp in Unity

Gain

1.238

1.250

1.262

V

_FB3% Low Comparator

_FB3% High Comparator

|-3|

3

%VREF

V

OSCILLATOR & DELAY PATH

Oscillator Frequency

Oscillator Frequency #2

Duty Ratio

270

450

300

500

330

550

kHz

R

_OSC= 10.2kOhm

Loop In Control -100% DC

possible

95

%

V

R_OSCVoltage

Information Only - Moves with

Oscillator Trim

0.65

Minimum GH Pulse Width

V_CC> 4.5V, Ramp up COMP

Voltage > 0.6V until GH starts

Switching

120

ns

Date: 1/21/05

SP6120 Low Voltage, AnyFET^TM, Synchronous, Buck Controller

2

ELECTRICAL CHARACTERISTICS

Unless otherwise specified: 3.0V < V_CC<5.5V, 3.0V < BST < 13.2, R_OSC= 18.7kΩ, C_COMP= 0.1µF, C_SS= 0.1µF, ENABLE = 3V,

CGH = CGL = 3.3nF, V_FB= 1.25V, ISP = ISN = 1.25V, SWN = GND = PGND = 0V, -40°C < T_AMB<85°C (Note 1)

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

SOFTSTART

µA

V

SS Charge Current

SS Discharge Current

COMP Discharge Current

COMP Clamp Voltage

SS Ok Threshold

SS Fault Reset

V

_SS= 1.5V

25

2

50

5

70

7

_SS= 1.5V

_COMP= 0.5V, Fault Initiated

_FB< 1.0V, V_SS= 2.5V

200

2.1

1.8

0.2

2.1

500

2.4

2.0

0.25

2.4

-

2.8

2.2

0.3

2.8

V

SS Clamp Voltage

V

OVER CURRENT & ZERO CURRENT COMPARATORS

Over Current Comparator Threshold

Voltage

Rail to Rail Common Mode Input

32

-

43

54

mV

ISN, ISP Input Bias Current

Zero Current Comparator Threshold

ENABLE/UVLO

60

2

250

nA

VISP - VISN

mV

V

_CCStart Threshold

_CCStop Threshold

_CCHysteresis

2.75

2.65

2.85

2.75

100

1.1

4

2.95

2.9

V

mV

V

Enable Threshold

Enable Pin Source Current

GATE DRIVER

0.65

0.6

1.45

9

µA

GH Rise Time

V_CC> 4.5V

-

40

60

110

ns

GH Fall Time

GL Rise Time

GL Fall Time

GH to GL Non-Overlap Time

GL to GH Non-Overlap Time

Note 1: Specifications to -40°C are guaranteed by design, characterization and correlation with statistical process control.

Date: 1/21/05

SP6120 Low Voltage, AnyFET^TM, Synchronous, Buck Controller

3

PIN DESCRIPTION

NUMBER

NAME

FUNCTION

SP6120

N/C

No Connection

1

TTL compatible input with internal 4uA pullup. Floating or Venable> 1.5V

will enable the part, Venable < 0.65V disables part.

ENABLE

2

3

4

Current Sense Positive Input: Rail to Rail Input for Over-Current Detection,

43mV threshold with 10µs (typ) response time.

ISP

ISN

Current Sense Negative Input: Rail to Rail input for Over-Current

Detection.

Feedback Voltage Pin: Inverting input of the error amplifier and serves as

the output voltage feedback point for the buck converter. The output

voltage is sensed and can be adjusted through an external resistor divider.

V_FB

5

6

Error Amplifier Compensation Pin: A lead lag network is typically

connected to this pin to compensate the feedback loop. This pin is

clamped by the SS voltage and is limited to 2.8V maximum.

COMP

Soft Start Programming Pin: This pin sources 50µA on start-up. A 0.01µF

to 1µF capacitor on this pin is typically enough capacitance to soft start a

power supply. In addition, hiccup mode timing is controlled by this pin

through the 5µA discharge current. The SS voltage is clamped to 2.7V

maximum.

SS

7

8

9

Frequency Programming Pin: A resistor to ground is used to program

frequency. Typical values - 18,700 Ohms, 300kHz; 10,200 Ohms, 500kHz.

R_OSC

Programming Pin:

PROG = GND; MODE = NFET/CONTINOUS

PROG = 68kΩ to GND; MODE = NFET/DISCONTINOUS

PROG = V_CC; MODE = PFET/CONTINOUS

PROG = 68kΩ to V_CC; MODE = PFET/DISCONTINOUS

PROG

I.C. Supply Pin: ESD structures also hooked to this pin. Properly bypass

this pin to PGND with a low ESL/ESR ceramic capacitor.

V_CC

GL

10

11

12

13

14

Synchronous FET Driver: 1nF/20ns typical drive capability.

Power Ground Pin: Used for Power Stage. Connect Directly to GND at

I.C. pins for optimal performance.

PGND

GND

SWN

Ground Pin: Main ground pin for I.C.

Switch Node Reference: High side MOSFET driver reference. Can also be

tied to GND for low voltage applications.

HIgh Side MOSFET Driver: Can be NFET or PFET depending on Program

Mode. 1nF/20ns typical drive capability. Maximum voltage rating is

referenced to SWN.

GH

15

16

BST

High Side Driver Supply Pin.

Date: 1/21/05

SP6120 Low Voltage, AnyFET^TM, Synchronous, Buck Controller

4

BLOCK DIAGRAM

SS

+

V

_FB3% Low ENABLE

2V

-

V_FB

Continuous/

Discontinuous

-

3%

ON 100%

Program

Logic

+

-

+

Window

Comparator

Logic

9

PROG

NFET/PFET

1.25V

3%

Reference

2

ENABLE

GND

OFF 100%

-

+

-

V_FB

+

BST

GH

16

15

13

GM

Error Amplifier

RESET

Dominant

SS

+

-

PWM Latch

Driver

Logic

-

Synchronous

Driver

14 SWN

11 GL

V_FB

5

R

+

QPWM

Q

S

12

8

PGND

R_OSC

COMP

V_CC

6

10

0.65V

I_CHARGE

1V RAMP

UVLO

-

F (kHz) = 5.7E6/R_OSC(Ω)

2.85 V_ON

2.75 V_OFF

Set Dominant

+

Fault Latch

S

Soft Start

& Hiccup Logic

ISP

ISN

3

4

+

OVC

FAULT

Q

x 10

+

T_OFF

10µs

-

R

-

430mV

-

7

SS

+

-

250mV

Zero crossing detect

+

APPLICATION SCHEMATIC

NMOS High Side Drive

PROG = GND

MBR0530

3.3V

V

IN

C

B

IN

C

BST

1µF

®®

330µF x 2

NC

BST

GH

ENABLE

QT

ENABLE

ISP

CS

RS

22.1k

SWN

GND

1.9V

1A to 8A

39nF

SP6120

L1

ISN

V

OUT

2.5µH

V

PGND

GL

FB

QB

COMP

SS

DS

C

OUT

470µF x 3

RF

5.23k

RZ

15k

V

IN

CC

C

SS

0.33µF

CP

100pF

R

PROG

OSC

CV

CC

2.2µF

RI

10k

R

18.7k

OSC

CZ

4.7nF

Figure 1. Schematic 3.3V to 1.9V Power Supply

C_IN= SANYO 6TPB330M

C_OUT= SANYO 4TPB470M

QT, QB = FAIRCHILD FDS6690A

L1 = PANASONIC ETQP6F2R5SFA

DS = STMICROELECTRONICS STPS2L25U

Date: 1/21/05

SP6120 Low Voltage, AnyFET^TM, Synchronous, Buck Controller

5

TYPICAL PERFORMANCE CHARACTERISTICS

Refer to circuit in Figure 1 with V_IN= 3.3V; V_OUT= 1.9V, R_OSC= 18.7kΩ, and T_AMB= +25°C unless otherwise noted.

100

90

80

70

60

50

1.925

1.920

1.915

1.910

1.905

1.900

1.895

1.890

1.885

1.880

1.875

0

2

4

6

8

10

0

1

2

3

4

5

Load Current (A)

Output Current (A)

Figure 2. Efficiency vs. Output Current

Figure 3. Load Regulation

V_OUT

Gate High

I_OUT(1A/div)

I_OUT(5A/div)

Figure 5. Load Step Response: 0.4A to 7A

Figure 4. Load Step Response: 0.4A to 2A

V

OUT

V

OUT

V

IN

V

IN

Soft Start

I

(1A/div)

IN

I

(5A/div)

OUT

Figure 6. Start-Up Response: 5A Load

Figure 7. Overcurrent: 9A Load

Date: 1/21/05

SP6120 Low Voltage, AnyFET^TM, Synchronous, Buck Controller

6

TYPICAL PERFORMANCE CHARACTERISTICS: Continued

Unless otherwise specified: V_CC= BST = ENABLE = 3.3V, R_OSC= 18.7kΩ, C_COMP= 0.1µF, C_SS= 0.1µF, CGH = CGL = 3.3nF, V_FB= 1.25V,

ISP = ISN = 1.25V, SWN = GND = PGND = 0V, T_AMB= 25°C.

0.30

48

46

0.20

0.10

0.00

44

42

40

-0.10

-0.20

38

-40

-15

10

35

60

85

-40

-15

10

35

60

85

Temperature (°C)

Figure 8. Error Amplifier Reference vs. Temperature

Figure 9. Overcurrent Comparator Threshold Voltage

vs. Temperature

-44

-45

-46

-47

5.25

5.20

5.15

5.10

5.05

5.00

-40

-15

10

35

60

85

-40

-15

10

35

60

85

Temperature (°C)

Figure 11. SS Discharge Current vs. Temperature with

V_SS= 1.5V

Figure 10. SS Charge Current vs. Temperature with

V_SS= 1.5V

3.6

3.4

3.2

3.0

2.8

2.6

-2.2

-2.4

-2.6

-2.8

-3.0

-3.2

-40

-15

10

35

60

85

-40

-15

10

35

60

85

Temperature (°C)

Figure 12. V_FB3% High Comparator vs. Temperature

Figure 13. V_FB3% Low Comparator vs. Temperature

Date: 1/21/05

SP6120 Low Voltage, AnyFET^TM, Synchronous, Buck Controller

7

TYPICAL PERFORMANCE CHARACTERISTICS: Continued

Unless otherwise specified: V_CC= BST = ENABLE = 3.3V, R_OSC= 18.7k, C_COMP= 0.1µF, C_SS= 0.1µF, CGH = CGL = 3.3nF, V_FB= 1.25V,

ISP = ISN = 1.25V, SWN = GND = PGND = 0V, T_AMB= 25°C.

2.900

2.875

2.850

2.825

2.850

2.825

2.800

2.775

2.750

2.800

-40

-15

10

35

60

85

-40

-15

10

35

60

85

Temperature (°C)

Figure 14. V_CCStart Threshold vs. Temperature

Figure 15. V_CCStop Threshold vs. Temperature

800

700

600

500

400

300

200

302

301

300

299

298

-40

-15

10

35

60

85

5

10

15

20

25

30

Temperature (°C)

R

(kΩ)

OSC

Figure 17. Oscillator Frequency vs. R_OSCwith V_CC= 5V

and CGH = CGL = Open.

Figure 16. Oscillator Frequency vs. Temperature

THEORY OF OPERATIONS

General Overview

The SP6120 is a constant frequency, voltage

mode PWM controller for low voltage, DC/DC

step down converters. It has a main loop where

an external resistor (R_OSC) sets the frequency

andthedriveriscontrolledbythecomparisonof

an error amp output (COMP) and a 1V ramp

signal. The error amp has a transconductance of

600µS, an output impedance of 3 MΩ, an inter-

nal pole at 2 MHz and a 1.25V reference input.

Although the main control loop is capable of 0%

and 100% duty cycle, its response time is lim-

itedbytheexternalcomponentselection.There-

fore, a secondary loop, including a window

comparator positioned 3% above and below the

reference, has been added to insure fast re-

sponse to line and load transients. A unique

“Ripple & Frequency Independent” algorithm,

added to the secondary loop, insures that the

window comparator does not interfere with the

main loop during normal operation. In addition

to receiving driver commands from the main

and secondary loops, the Driver Logic is also

controlled by the Programming Logic, Fault

Logic and Zero Crossing Comparator. The Pro-

gramming Logic tells the Driver Logic whether

thecontrollerisusingaPFETorNFEThighside

Date: 1/21/05

SP6120 Low Voltage, AnyFET^TM, Synchronous, Buck Controller

8

THEORY OF OPERATIONS: Continued

Soft Start

(see figures on next page)

driver as well as whether the controller is oper-

ating in continuous or discontinuous mode. The

Fault Logic holds the high and low side drivers

off if V_CCdips below 2.75V, if an over current

conditionexists,orifthepartisdisabledthrough

the ENABLE pin. The Zero Crossing Compara-

tor turns the lower driver off if the conduction

current reaches zero and the Driver Logic has

made an attempt to turn the lower driver on and

the Programming Logic is set for discontinuous

mode. Lastly, the 4Ω drivers have internal gate

non-overlap circuitry and are designed to drive

MOSFETs associated with converter designs in

the 5A to 10A range. Typically the high side

driver is referenced to the SWN pin; further

improving the efficiency and performance of

the converter.

Soft start is required on step-down controllers to

prevent excess inrush current through the power

train during start-up. Typically this is managed

by sourcing a controlled current into a program-

ming capacitor (on the SS pin) and then using

the voltage across this capacitor to slowly ramp

up either the error amp reference or the error

amp output (COMP). The control loop creates

narrow width driver pulses while the output

voltage is low and allows these pulses to in-

crease to their steady-state duty cycle as the

output voltage increases to its regulated value.

As a result of controlling the inductor

volt*second product during start-up, inrush cur-

rent is also controlled.

The presence of the output capacitor creates

extracurrentdrawduringstart-up. Simplystated,

dV_OUT/dt requires an average sustained current

in the output capacitor and this current must be

considered while calculating peak inrush cur-

rent and over current thresholds. Since the

SP6120

ENABLE

Low quiescent mode or “Sleep Mode” is initi-

ated by pulling the ENABLE pin below 650mV.

The ENABLE pin has an internal 4µA pull-up

current and does not require any external inter-

face for normal operation. If the ENABLE pin

isdrivenfromavoltagesource, thevoltagemust

be above 1.45V in order to guarantee proper

“awake” operation. Assuming that V_CCis above

2.85V, the SP6120 transitions from “Sleep

Mode” to “Awake Mode” in about 20µs to 30µs

and from “Awake Mode” to “Sleep Mode” in a

few microseconds. SP6120 quiescent current in

sleep mode is 20µA maximum. During Sleep

Mode, the high side and low side MOSFETs are

turned off and the COMP and SS pins are held

low.

Soft Start: (continued)

ramps up the error amp reference voltage, an

expression for the output capacitor current can

be written as:

IC_OUT= (C_OUT/C_SS) * (V_OUT/1.25) * 50µA

As the figure shows, the SS voltage controls a

variety of signals. First, provided all the exter-

nal fault conditions are removed, the fault latch

is reset and the SS cap begins to charge. When

the SS voltage reaches around 0.3V, the error

amp reference begins to track the SS voltage

while maintaining the 0.3V differential. As the

SS voltage reaches 0.7V, the driver begins to

switch the high side and low side MOSFETs

with narrow pulses in an effort to keep the

converter output regulated. As the error amp

referencerampsupward,thedriverpulseswiden

untilasteadystatevalueisreached. The“bump”

in the inductor current transfer curve is indica-

tive of excess charge current incurred due to the

UVLO

Assuming that the ENABLE pin is either pulled

high or floating, the voltage on the V_CCpin then

determines operation of the SP6120. As V_CC

rises, the UVLO block monitors V_CCand keeps

the high side and low side MOSFETs off and the

COMPandSSpinslowuntilV_CCreaches2.85V.

If no faults are present, the SP6120 will initiate

a soft start when V_CCexceeds 2.85V. Hysteresis

(about 100mV) in the UVLO comparator pro-

vides noise immunity at start-up.

Date: 1/21/05

SP6120 Low Voltage, AnyFET^TM, Synchronous, Buck Controller

9

THEORY OF OPERATIONS: Continued

finitepropagationdelayofthecontroller. When

the SS voltage reaches 2.0V, the secondary loop

including the 3% window comparator is en-

abled. Lastly, theSSvoltageisclampedat2.4V,

ending the soft start charge cycle.

Restart will occur just like a normal soft start

cycle.

However, if a fault occurs during the soft start

charge cycle, the FAULT latch is immediately

set, turning off the high side and low side

MOSFETs. The MOSFETs remain off during

the remainder of the charge cycle and subse-

quentdischargecycleoftheSScapacitor. Again,

provided there are no external fault conditions,

the FAULT latch will be reset when the SS

voltage reaches 250 mV.

Hiccup Mode

When the converter enters a fault mode, the

driverholdsthehighsideandlowsideMOSFETs

off for a finite period of time. Provided the part

is enabled, this time is set by the discharge of the

SS capacitor. The discharge time is roughly 10

times the charge interval thereby giving the

power supply plenty of time to cool during an

over current fault. The driver off-time is pre-

dominantly determined by the discharge time.

Over Current Protection

The SP6120 over current protection scheme is

designed to take advantage of three popular

detectionschemes:SenseResistor, TraceResis-

tor or Inductor Sense. Because the detection

threshold is only 43mV, both trace resistor and

inductor sense become attractive protection

schemes. The inductor sense scheme adds no

additional dc loss to the converter and is an

excellent alternative to Rdson based schemes;

providing continuous current sensing and flex-

ibleMOSFETselection. Aninternal, 10µsfilter

conditions the over current signal from tran-

sients generated during load steps. In addition,

because the over current inputs, ISP and ISN,

are capable of rail to rail operation, the SP6120

provides excellent over current protection dur-

2.4V

2.0V

SS Voltage

0.7V

0.25V

0V

dV_SS/dt = 50µA/C_SS

Error Amplifier

V_OUT= V(Eamp REF)* (1+RF/RI)

Reference

Voltage

1.25V

0V

I_LOAD

Inductor Current

ing conditions where V_INapproaches V_OUT

.

0V

V(V_CC

)

43mV

FAULT

Reset Voltage

V(ISP) - V(ISN)

0V

2.4V

2.0V

V(V_CC

)

SWN

Voltage

SS Voltage

250mV

0V

V(V_CC

)

V(V_CC

)

3% Low

Enable Voltage

FAULT Voltage

0V

TIME

0V

Date: 1/21/05

SP6120 Low Voltage, AnyFET^TM, Synchronous, Buck Controller

10

THEORY OF OPERATIONS: Continued

Zero Crossing Detection

Insomeapplications,itmaybeundesirabletohave

negative conduction current in the inductor. This

situation happens when the ripple current in the

inductorishigherthantheloadcurrent. Therefore,

the SP6120 provides an option for “discontinu-

ous” operation. If the Program Logic (see next

section) is set for discontinuous mode, then the

DriverLogiclooksattheZeroCrossingCompara-

tor and the state of the lower gate driver. If the low

side MOSFET was “on” and V(ISP)-V(ISN) < 0

then the low side MOSFET is immediately turned

off and held off until the high side MOSFET is

turned “on”. When the high side MOSFET turns

“on” , the Driver Logic is reset. The following

figuresshowcontinuousanddiscontinuousopera-

tion for a converter with an NFET high side

MOSFET.

Continuous

Load

Current

0A

GH, GL

Voltage

0V

Discontinuous

Load

Current

0A

Discontinuous vs. Continuous Mode

The discontinuous mode is used when better light

load efficiency is desired, for example in portable

applications. Additionally, for power supply se-

quencing in some applications the DC-DC con-

verter output is pre-charged to a voltage through a

switch at start-up, and discontinuous operation

would be required to prevent reverse inductor

current from discharging the pre-charge voltage.

Thecontinuousmodeispreferableforlowernoise

andEMIapplicationssincethediscontinuousmode

can cause ringing of the switch node voltage when

it turns both switches off. Another example where

continuous mode could be required is one where

theinductorhasanextrawindingusedforanover-

windingregulatorandthuscontinuousconduction

isnecessarytoproducethissecondoutputvoltage.

GH, GL

Voltage

0V

TIME

Program Logic: continued

the voltage drop across the resistor signals the

SP6120toputtheDriverLogicin“discontinuous”

mode. With one pin and a 68kΩ resistor, the

SP6120 can be configured for a variety of operat-

ing modes:

Program Logic

The Program pin (PROG) of the SP6120 adds a

new level of flexibility to the design of DC/DC

converters. A10µAcurrentflowseitherintoorout

of the Program pin depending on the initial poten-

tialpresentedtothepin.Ifnoresistorispresent,the

ProgramLogicsimplylooksatthepotentialonthe

pin, sets the mode to “continuous” and programs

NFETorPFEThighsidedriveaccordingly. Ifthe

68kΩ resistor is present,

PROGRAM LOGIC TRUTH TABLE

PROGRAM PIN

Short to GND

68 kΩ to GND

Short to V_CC

NFET OR PFET

NFET

MODE

Continuous

Discontinuous

Continuous

Discontinous

NFET

PFET

68 kΩ to V_CC

PFET

Date: 1/21/05

SP6120 Low Voltage, AnyFET^TM, Synchronous, Buck Controller

11

THEORY OF OPERATIONS: Continued

Secondary Loop (continued)

The NFET/PFET programmability is for the

high side MOSFET. When designing DC/DC

converters, it is not always obvious when to use

an NFET with a charge pump or a simple PFET

forthehighsideMOSFET. Often,thecontroller

has to be changed, making performance evalu-

ations difficult. This difficulty is worsened by

the limited availability of true low voltage con-

trollers. In addition, by also programming the

mode,continuousordiscontinuous,switchmode

powerdesignsthataresuccessfulinbusapplica-

tions can now find homes in portable applica-

tions.

any additional loops, the current peak and val-

ley are determined by the edges associated with

the on-time in the main loop. The set pulse

corresponding to the start of an on-time indi-

cates a current valley and the reset pulse corre-

sponding to the end of an on-time indicates a

current peak. In effect, the main loop deter-

mines the status of the secondary loop.

Notice that the output voltage appears to coast

towardtheregulatedvalueduringperiodswhere

the main loop would be telling the drivers to

Secondary Loop (3% Window Comparator)

DSP, microcontroller and microprocessor ap-

plications have very strict supply voltage re-

quirements. In addition, the current require-

ments to these devices can change drastically.

Linear regulators, typically the workhorse for

DC/DC step-down, do a great job managing

accuracy and transient response at the expense

of efficiency. On the other hand, PWM switch-

ing regulators typically do a great job managing

efficiency at the expense of output ripple and

line/load step response. The trick in PWM

controller design is to emulate the transient

response of the linear regulator.

MAX

DC Load

Current

MIN

0A

Output

Voltage

V_OUT

.

Of course improving transient response should

be transparent to the power supply designer.

Very often this is not the case. Usually the very

circuitry that improves the controllers transient

response adversely interferes with the main

PWM loop or complicates the board level de-

sign of the power converter.

Reset

Main Loop

Set

V(V_CC

)

TheSP6120handlesline/loadtransientresponse

in a new way. First, a window comparator

detects whether the output voltage is above or

below the regulated value by 3%. Then, a

proprietary “Ripple & Frequency Independent”

algorithm synchronizes the output of the win-

dow comparator with the peak and valley of the

inductor current waveform. 3% low detection is

synchronized with inductor current peak; 3%

high detection is synchronized with the inductor

current valley. However, in order to eliminate

3% High

Latch On

0V

V(V_CC

)

3% Low

Latch On

0V

TIME

Date: 1/21/05

SP6120 Low Voltage, AnyFET^TM, Synchronous, Buck Controller

12

THEORY OF OPERATIONS: Continued

driver waveforms for the 5V, high side NFET

design.

switch. It is during this interval that the 3%

windowcomparatorhastakencontrolawayfrom

the main loop. The main loop regains control

only if the output voltage crosses through its

regulated value. Also notice where the 3%

comparator takes over. The output voltage is

considered “high” only if the trough of the ripple

is above 3%. The output voltage is considered

“low” only if the peak of the ripple is below 3%.

By managing the secondary loop in this fashion,

the SP6120 can improve the transient response

of high performance power converters without

causing strange disturbances in low to moderate

performance systems.

As with all synchronous designs, care must be

taken to ensure that the MOSFETs are properly

chosen for non-overlap time, peak current capa-

bility and efficiency.

GATE DRIVER TEST CONDITONS

5V

90%

GH (GL)

FALL TIME

2V

10%

5V

90%

RISE TIME

2V

Driver Logic

GH (GL)

10%

Signals from the PWM latch (QPWM), Fault

latch (FAULT), Program Logic, Zero Crossing

Comparator, and 3% Window Comparators all

flow into the Driver Logic. The following is a

truth table for determining the state of the GH

and GL voltages for given inputs:

NON-OVERLAP

V(BST)

GH

Voltage

DRIVER LOGIC TRUTH TABLE

0V

FAULT

1

0

1

0

1

0

V(VCC

)

QPWM or

3% COMP

X

GL

NFET/PFET

CONT/DISC

ZERO CROSS

GH

N

X

0

P

X

1

N

X

1

P

X

0

N

C

X

0

P

C

X

1

N

D

0

P

D

0

N

D

1

P

D

1

Voltage

0V

V(VCC = VIN

)

0

1

0

1

GL

0

1

0

SWN

Voltage

The QPWM and 3% Comparators are grouped

together because 3% Low is the same as QPWM

= 1 and 3% High is the same as QPWM = 0.

~0V

~V(Diode) V

~2V(VIN

)

BST

Voltage

Output Drivers

The driver stage consists of one high side, 4Ω

driver, GH and one low side, 4Ω, NFET driver,

GL. As previously stated, the high side driver

can be configured to drive a PFET or an NFET

highsideswitch. Thehighsidedrivercanalsobe

configured as a switch node referenced driver.

Due to voltage constraints, this mode is manda-

tory for 5V, single supply, high side NFET

applications.Thefollowingfigureshowstypical

~V(VIN

)

TIME

Date: 1/21/05

SP6120 Low Voltage, AnyFET^TM, Synchronous, Buck Controller

13

APPLICATIONS INFORMATION

Inductor Selection

duce considerable ac core loss, especially when

the inductor value is relatively low and the

ripple current is high. Ferrite materials, on the

other hand, are more expensive and have an

abrupt saturation characteristic with the induc-

tance dropping sharply when the peak design

current is exceeded. Nevertheless, they are pre-

ferred at high switching frequencies because

they present very low core loss and the design

only needs to prevent saturation. In general,

ferrite or molypermalloy materials are better

choice for all but the most cost sensitive appli-

cations.

There are many factors to consider in selecting

the inductor including cost, efficiency, size and

EMI. In a typical SP6120 circuit, the inductor is

chosen primarily for value, saturation current

andDCresistance.Increasingtheinductorvalue

will decrease output voltage ripple, but degrade

transient response. Low inductor values pro-

vide the smallest size, but cause large ripple

currents, poor efficiency and more output ca-

pacitance to smooth out the larger ripple cur-

rent. The inductor must also be able to handle

the peak current at the switching frequency

without saturating, and the copper resistance in

the winding should be kept as low as possible to

minimize resistive power loss. A good compro-

mise between size, loss and cost is to set the

inductor ripple current to be within 20% to 40%

of the maximum output current.

The power dissipated in the inductor is equal to

the sum of the core and copper losses. To mini-

mizecopperlosses,thewindingresistanceneeds

to be minimized, but this usually comes at the

expense of a larger inductor. Core losses have a

more significant contribution at low output cur-

rent where the copper losses are at a minimum,

and can typically be neglected at higher output

currentswherethecopperlossesdominate.Core

loss information is usually available from the

magnetic vendor.

The switching frequency and the inductor oper-

ating point determine the inductor value as

follows:

V_OUT(V_{IN (max)}−V_OUT

)

L =

V_{IN (max)}F_SK_rI_{OUT (max)}

where:

Thecopperlossintheinductorcanbecalculated

using the following equation:

F_S= switching frequency

K_r= ratio of the ac inductor ripple current to

the maximum output current

P_L(Cu)= I_L²_(RMS)R_WINDING

where I_L(RMS)is the RMS inductor current that

can be calculated as follows:

The peak to peak inductor ripple current is:

V_OUT(V_{IN (max)}−V_OUT

)

2

1

3

I_PP

I_OUT(max)

I_PP

=

I_L(RMS)= I_OUT(max)1 +

V_IN(max)F_SL

(

)

Oncetherequiredinductorvalueisselected, the

proper selection of core material is based on

peak inductor current and efficiency require-

ments.

The core material must be large enough not to

saturate at the peak inductor current

Output Capacitor Selection

The required ESR (Equivalent Series Resis-

tance) and capacitance drive the selection of the

type and quantity of the output capacitors. The

ESR must be small enough that both the resis-

tive voltage deviation due to a step change in the

load current and the output ripple voltage do not

exceed the tolerance limits expected on the

output voltage. During an output load transient,

the output capacitor must supply all the addi-

tional current demanded by the load until the

I_PP

I_PEAK= I_{OUT (max)}

+

2

and provide low core loss at the high switching

frequency. Low cost powdered iron cores have

a gradual saturation characteristic but can intro-

Date: 1/21/05

SP6120 Low Voltage, AnyFET^TM, Synchronous, Buck Controller

14

APPLICATIONS INFORMATION: Continued

KemetT510surfacemountcapacitorsarepopu-

lartantalumcapacitorsthatworkwellinSP6120

applications. POSCAP from Sanyo is a solid

electrolytic chip capacitor that has low ESR and

high capacitance. For the same ESR value,

POSCAP has lower profile compared with tan-

talum capacitor.

SP6120 adjusts the inductor current to the new

value. Therefore the capacitance must be large

enough so that the output voltage is held up

while the inductor current ramps up or down to

the value corresponding to the new load current.

Additionally, the ESR in the output capacitor

causes a step in the output voltage equal to the

ESR value multiplied by the change in load

current. Because of the fast transient response

and inherent 100% and 0% duty cycle capabil-

ity provided by the SP6120 when exposed to

output load transient, the output capacitor is

typically chosen for ESR, not for capacitance

value.

Input Capacitor Selection

The input capacitor should be selected for ripple

current rating, capacitance and voltage rating.

The input capacitor must meet the ripple current

requirement imposed by the switching current.

In continuous conduction mode, the source cur-

rent of the high-side MOSFET is approximately

a square wave of duty cycle V_OUT/V_IN. Most of

this current is supplied by the input bypass

capacitors. The RMS value of input capacitor

current is determined at the maximum output

current and under the assumption that the peak

to peak inductor ripple current is low, it is given

by:

The output capacitor’s ESR, combined with the

inductor ripple current, is typically the main

contributor to output voltage ripple. The maxi-

mum allowable ESR required to maintain a

specifiedoutputvoltageripplecanbecalculated

by:

∆V_OUT

R_ESR

≤

I_CIN(rms)= I

_OUT(max)√D(1 - D)

I_PP

The worse case occurs when the duty cycle D is

50% and gives an RMS current value equal to

I_OUT/2. Select input capacitors with adequate

ripple current rating to ensure reliable opera-

tion.

where:

∆V_OUT= peak to peak output voltage ripple

I_PP= peak to peak inductor ripple current

The total output ripple is a combination of the

ESR and the output capacitance value and can

be calculated as follows:

The power dissipated in the input capacitor is:

P

= I_C²_{IN (rms)}R_ESR(CIN)

CIN

∆V_OUT

=

²+ (I_PPR_ESR

)

This can become a significant part of power

losses in a converter and hurt the overall energy

transfer efficiency.

I_PP(1 – D)

2

C_OUTF_S

(

)

where:

The input voltage ripple primarily depends on

the input capacitor ESR and capacitance. Ignor-

ing the inductor ripple current, the input voltage

ripple can be determined by:

F_S= switching frequency

D = duty cycle

C_OUT= output capacitance value

I

_{OUT (MAX )}V_OUT(V_IN−V_OUT)

Recommended capacitors that can be used ef-

fectively in SP6120 applications are: low-ESR

aluminum electrolytic capacitors, OS-CON ca-

pacitors that provide a very high performance/

size ratio for electrolytic capacitors and low-

ESR tantalum capacitors. AVX TPS series and

∆V_IN= I_out(max)R_{ESR(CIN )}

+

2

F_SC_INV_IN

The capacitor type suitable for the output ca-

pacitors can also be used for the input capaci-

tors.However,exerciseextracautionwhentanta-

Date: 1/21/05

SP6120 Low Voltage, AnyFET^TM, Synchronous, Buck Controller

15

APPLICATIONS INFORMATION: Continued

lum capacitors are considered. Tantalum capaci-

tors are known for catastrophic failure when ex-

posed to surge current, and input capacitors are

prone to such surge current when power supplies

are connected ‘live’ to low impedance power

sources.Certaintantalumcapacitors,suchasAVX

TPS series, are surge tested. For generic tantalum

capacitors, use 2:1 voltage derating to protect the

input capacitors from surge fall-out.

The total power losses of the top MOSFET are the

sum of switching and conduction losses. For syn-

chronous buck converters of efficiency over 90%,

allow no more than 4% power losses for high or

low side MOSFETs. For input voltages of 3.3V

and 5V, conduction losses often dominate switch-

ing losses. Therefore, lowering the R_DS(ON)of the

MOSFETs always improves efficiency even

though it gives rise to higher switching losses due

to increased C_rss.

MOSFET Selection

Top and bottom MOSFETs experience unequal

conduction losses if their on time is unequal. For

applicationsrunningatlargeorsmalldutycycle, it

makes sense to use different top and bottom

MOSFETs. Alternatively, parallel multiple

MOSFETs to conduct large duty factor.

The losses associated with MOSFETs can be

divided into conduction and switching losses.

Conduction losses are related to the on resistance

of MOSFETs, and increase with the load current.

Switching losses occur on each on/off transition

when the MOSFETs experience both high current

and voltage. Since the bottom MOSFET switches

current from/to a paralleled diode (either its own

bodydiodeoraSchottkydiode),thevoltageacross

theMOSFETisnomorethan1Vduringswitching

transition. As a result, its switching losses are

negligible. The switching losses are difficult to

quantify due to all the variables affecting turn on/

off time. However, the following equation pro-

vides an approximation on the switching losses

associatedwiththetopMOSFETdrivenbySP6120.

R_DS(ON)variesgreatlywiththegatedrivervoltage.

The MOSFET vendors often specify R_DS(ON)on

multiple gate to source voltages (V_GS), as well as

provide typical curve of R_DS(ON)versus V_GS. For

5Vinput,usetheR_DS(ON)specifiedat4.5VV_GS.At

the time of this publication, vendors, such as

Fairchild, Siliconix and International Rectifier,

havestartedtospecifyR_DS(ON)atV_GSlessthan3V.

This has provided necessary data for designs in

which these MOSFETs are driven with 3.3V and

made it possible to use SP6120 in 3.3V only

applications.

P_{SH (max)}=12C_rssV_{IN (max)}I_{OUT (max)}F_S

where

C_rss= reverse transfer capacitance of the top

Thermal calculation must be conducted to ensure

the MOSFET can handle the maximum load cur-

rent. The junction temperature of the MOSFET,

determined as follows, must stay below the maxi-

mum rating.

MOSFET

Switching losses need to be taken into account for

high switching frequency, since they are directly

proportional to switching frequency. The conduc-

tion losses associated with top and bottom

MOSFETs are determined by:

P_{MOSFET (max)}

T_J(max)=T_A(max)

+

R_θ

_{CH (max)}= R_{DS (ON )}I_{OUT (max)}²D

JA

P

where

P

= R_{DS(ON )}I_{OUT (max)}²(1− D)

CL(max)

T_A(max)= maximum ambient temperature

PMOSFET(max) = maximum power dissipa-

tion of the MOSFET

where

P_CH(max)= conduction losses of the high side

R

_ΘJA= junction to ambient thermal resistance.

MOSFET

P_CL(max)= conduction losses of the low side

R

_ΘJAof the device depends greatly on the board

MOSFET

layout, as well as device package. Significant

R_DS(ON)= drain to source on resistance.

Date: 1/21/05

SP6120 Low Voltage, AnyFET^TM, Synchronous, Buck Controller

16

APPLICATIONS INFORMATION: Continued

Loop Compensation Design

thermalimprovementcanbeachievedinthemaxi-

mum power dissipation through the proper design

of copper mounting pads on the circuit board. For

example, in a SO-8 package, placing two 0.04

square inches copper pad directly under the pack-

age, without occupying additional board space,

can increase the maximum power from approxi-

mately 1 to 1.2W. For DPAK package, enlarging

the tap mounting pad to 1 square inches reduces

the R_ΘJA from 96°C/W to 40°C/W.

The goal of loop compensation is to manipulate

loopfrequencyresponsesuchthatitsgaincrosses

over 0db at a slope of –20db/dec. The SP6120

has a transconductance error amplifier and re-

quires the compensation network to be con-

nected between the COMP pin and ground, as

shown in Figure 18.

The first step of compensation design is to pick

the loop crossover frequency. High crossover

frequencyisdesirableforfasttransientresponse,

but often jeopardize the system stability. Since

the SP6120 is equipped with 3% window com-

parator that takes over the control loop on tran-

sient, the crossover frequency can be selected

primarily to the satisfaction of system stability.

Crossover frequency should be higher than the

ESR zero but less than 1/5 of the switching

frequency. The ESR zero is contributed by the

ESR associated with the output capacitors and

can be determined by:

Schottky Diode Selection

When paralleled with the bottom MOSFET, an

optional Schottky diode can improve efficiency

and reduce noises. Without this Schottky diode,

the body diode of the bottom MOSFET conducts

thecurrentduringthenon-overlaptimewhenboth

MOSFETsareturnedoff. Unfortunately,thebody

diode has high forward voltage and reverse recov-

ery problem. The reverse recovery of the body

diodecausesadditionalswitchingnoiseswhenthe

diode turns off. The Schottky diode alleviates

these noises and additionally improves efficiency

thanks to its low forward voltage. The reverse

voltage across the diode is equal to input voltage,

and the diode must be able to handle the peak

current equal to the maximum load current.

1

f_Z(ESR)

=

2πC_OUTR_ESR

Crossover frequency of 20kHz is a sound first

try if low ESR tantalum capacitors or poscaps

are used at the output. The next step is to calcu-

late the complex conjugate poles contributed by

the LC output filter,

The power dissipation of the Schottky diode is

determined by

1

f_P(LC)

=

P

_DIODE= 2V_FI_OUTT_NOLF_S

2π√ LC_OUT

where

The open loop gain of the whole system can be

divided into the gain of the error amplifier,

PWM modulator, buck converter, and feedback

resistor divider. In order to crossover at the

selected frequency fco, the gain of the error

amplifier has to compensate for the attenuation

caused by the rest of the loop at this frequency.

In the RC network shown in Figure 18, the

product of R1 and the error amplifier

transconductance determines this gain. There-

fore, R1 can be determined from the following

equation that takes into account the typical error

amplifier transconductance, reference voltage

and PWM ramp built into the SP6120.

T_NOL= non-overlap time between GH and GL.

V_F= forward voltage of the Schottky diode.

®®

COMP

R1

C2

SP6120

C1

1300V_OUTf_COf_Z(ESR)

R₁=

Figure 18. The RC network connected to the COMP pin

provides a pole and a zero to control loop.

2

V_INf_P(LC)

Date: 1/21/05

SP6120 Low Voltage, AnyFET^TM, Synchronous, Buck Controller

17

APPLICATIONS INFORMATION: Continued

Current Sense

In Figure 18, R1 and C1 provides a zero f_Z1

whichneedstobeplacedatorbelowf_P(LC). If f_Z1

is made equal to f_P(LC)for convenience, the

value of C1 can be calculated as

The SP6120 allows sensing current using the

inductor, PCB trace or current-sense resistor.

Inductor-sense utilizes the voltage drop across

the ESR of the inductor, while PCB trace and

current-sense resistor introduce additional re-

sistance in series with the inductor. The resis-

tance of the sense element determines the

overcurrent protection threshold as follows,

1

C₁=

2πf_P(LC)R₁

The optional C2 generates a pole f_P1with R1 to

cut down high frequency noise for reliable op-

eration. This pole should be placed one decade

higher than the crossover frequency to avoid

erosion of phase margin. Therefore, the value of

the C2 can be derived from

43mV

R_SEN

I_LIM

=

R_SEN= current-sense resistance which can be

implemented as ESR of the inductor, trace or

discrete resistor.

1

C₂=

Themaximumpowerdissipationonthecurrent-

20πf_COR₁

sense element is:

Figure 19 illustrates the overall loop frequency

response and frequency of each pole and zero.

Tofine-tunethecompensation, itisnecessaryto

physically measure the frequency response us-

ing a network analyzer.

2

P

= I_OUT(max)R_SEN

SEN

For the inductor-sense scheme shown in the

application circuit, R_Sand C_Sare used to repli-

catethesignalacrosstheESRoftheinductor.R_S

and C_Scan be looked at as a low pass filter

whose output represents the DC differential

voltage between the switch node and the output.

At steady state, this voltage happens to be the

output current times the ESR of the inductor. In

addition, if the following relationship is satisfied,

Gain

-20db/dec

L

ESR

= R_SC_S

-40db/dec

Loop

the output of the RsCs filter represents the exact

voltage across the ESR, including the ripple.

Since the SP6120’s hiccup overcurrent protec-

tion scheme is intended to safeguard sustained

overload conditions, the DC portion of the cur-

rent signal is more of interest. Therefore, design-

ing the R_SC_Stime constant higher than L/ESR

provides reliable current sense against any pre-

mature triggering due to noise or any transient

conditions. Pick Rs between 10k and 100k, and

Cs can be determined by:

-20db/dec

f

-20db/dec

Error Amplifier

f

L

1

f

CO

f

P1

C_S= 2

Z1 P(LC)

Z(ESR)

ESR R_S

HerethetimeconstantofR_SC_Sistwicethevalue

of L/ESR.

Figure 19. Frequency response of a stable system and its

error amplifier.

Date: 1/21/05

SP6120 Low Voltage, AnyFET^TM, Synchronous, Buck Controller

18

APPLICATIONS INFORMATION: Continued

Output Voltage Programming

In some applications, it may be desirable to

extend the current sense capability of a given

R_SENelement (usually the inductor ESR) be-

yond the limit set by the 43mV threshold.

As shown in Figure 21(A), the voltage divider

connecting to the V_FBpin programs the output

voltage according to

A straight forward way to do this would be to

add a resistor R_S2in parallel with C_S, creating a

voltage divider with R_S. This changes the rela-

tionship with R_Sand C_Sto be

R₁

R₂

V_OUT= 1.25( 1 +

)

where 1.25V is the internal reference voltage.

SelectR2intherangeof10kto100k, andR1can

be calculated using

L

1

C_S= 2

ESR R_S//R_S2

Using a voltage divider across the inductor, the

new relationship becomes:

R₂(V_OUT– 1.25)

R₁=

1.25

43mV R_S+ R_S2

I_LIM

=

ESR

R_S2

For output voltage less than 1.25V, a simple

circuit shown in Figure 21(B) can be used in

which V_REFis an external voltage reference

greater than 1.25V. For simplicity, use the same

resistor value for R1 and R2, then R3 is deter-

mined as follows,

To calculate R_S2, the formula becomes

I_LIMESR

43mV

R_S2= R_S

– 1

(

/

)

ISP

ISN

R

S2

(V_REF– 1.25)R₁

R₃=

R

S

2.5 – V_OUT

C

S

L

SWN

V

OUT

ESR

Figure 20: Current Sensing

V_OUT> 1.25V

V_OUT< 1.25V

V_REF

R3

®®

R1

V_FB

SP6120

R2

A

B

Figures 21(A), a voltage divider connected to the V_FBpin programs the output voltageand 21(B), a simple circuit using

one external voltage reference programs the output voltages to less than 1.25V.

Date: 1/21/05

SP6120 Low Voltage, AnyFET^TM, Synchronous, Buck Controller

19

APPLICATIONS INFORMATION: Continued

Layout Guideline

5. Connect the PGND pin close to the source of

the bottom MOSFET, and the SWN pin to the

source of the top MOSFET. Minimize the

trace between GH/GL and the gates of the

MOSFETs. All of these requirements reduce

the impedance driving the MOSFETs. This is

especiallyimportantforthebottomMOSFET

that tends to turn on through its miller capaci-

tor when the switch node swings high.

PCB layout plays a critical role in proper func-

tionoftheconvertersandEMIcontrol. Inswitch

mode power supplies, loops carrying high di/dt

give rise to EMI and ground bounces. The goal

of layout optimization is to identify these loops

and minimize them. It is also crucial on how to

connect the controller ground such that its op-

eration is not affected by noise. The following

guideline should be followed to ensure proper

operation.

6. Minimize the loop composed of input capaci-

tors, top/bottom MOSFETs and Schottky di-

ode, This loop carries high di/dt current. Also

increase the trace width to reduce copper

losses.

1. A ground plane is recommended for mini-

mizing noises, copper losses and maximizing

heat dissipation.

7. Maximize the trace width of the loop con-

necting the inductor, output capacitors,

Schottky diode and bottom MOSFET.

2. Connectthegroundoffeedbackdivider,com-

pensationcomponents, oscillatorresistorand

soft-start capacitor to the GND pin of the IC.

Then connect this pin as close as possible to

the ground of the output capacitor.

3. The V_CCbypass capacitor should be right

next to the Vcc and GND pin.

4. The traces connecting to feedback resistor

andcurrentsensecomponentsshouldbeshort

andfarawayfromtheswitchnode,andswitch-

ing components.

Date: 1/21/05

SP6120 Low Voltage, AnyFET^TM, Synchronous, Buck Controller

20

PACKAGE: PLASTIC THIN SMALL

OUTLINE

(TSSOP)

E2

E1

D

A

Ø

A1

L

e

B

DIMENSIONS

in inches (mm)

16–PIN

Minimum/Maximum

- /0.043

(- /1.10)

A

0.002/0.006

(0.05/0.15)

A1

B

0.007/0.012

(0.19/0.30)

0.193/0.201

(4.90/5.10)

D

0.169/0.177

(4.30/4.50)

E1

e

0.026 BSC

(0.65 BSC)

0.126 BSC

(3.20 BSC)

E2

L

0.020/0.030

(0.50/0.75)

0°/8°

Ø

Date: 1/21/05

SP6120 Low Voltage, AnyFET^TM, Synchronous, Buck Controller

21

ORDERING INFORMATION

Operating Temperature Range Package Type

Model

SP6120CY ............................................... 0˚C to +70˚C ........................................ 16-Pin TSSOP

SP6120CY/TR ......................................... 0˚C to +70˚C ....................................... 16-Pin TSSOP

SP6120EY .............................................. -40˚C to +85˚C ...................................... 16-Pin TSSOP

SP6120EY/TR......................................... -40˚C to +85˚C ..................................... 16-Pin TSSOP

Available in lead free packaging. To order add "-L" suffix to part number.

Example: SP6120EY/TR = standard; SP6120EY-L/TR = lead free

/TR = Tape and Reel

Pack quantity is 2,500 for 16-pin TSSOP.

Corporation

ANALOGEXCELLENCE

Sipex Corporation

Headquarters and

Sales Office

233 South Hillview Drive

Milpitas, CA 95035

TEL: (408) 934-7500

FAX: (408) 935-7600

Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the

application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.

Date: 1/21/05

SP6120 Low Voltage, AnyFET^TM, Synchronous, Buck Controller

22


型号：	SP6120BEY-L/TR
厂家：	SIPEX CORPORATION
描述：	Switching Controller, Voltage-mode, 2A, 550kHz Switching Freq-Max, PDSO16, ROHS COMPLIANT, MO-153AB, TSSOP-16 开关光电二极管
文件：	总22页 (文件大小：212K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SP6120BEY-L/TR [SIPEX]

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