SP6123ACN-L/TR_技术文档

®

SP6123/SP6123A

Low Voltage, Synchronous Step-Down PWM Controller

Ideal for 2A to 10A, Small Footprint, DC-DC Power Converters

■ Optimized for Single Supply, 3V - 5.5V Applications

1

2

3

4

8

7

6

5

BST

GH

GL

■ High Efficiency: Greater Than 95% Possible

SP6123

V_CC

■ Accurate Fixed 300kHz (SP6123) or 500kHz

SWN

V_FB

GND

8 Pin NSOIC

(SP6123A) Frequency Operation

COMP

■ Fast Transient Response

■ Internal Soft Start Circuit

Now Available in Lead Free Packaging

■ Accurate 0.8V Reference Allows Low Output

Voltages

APPLICATIONS

■ Resistor Programmable Output Voltage

■ DSP

■ Loss-less Current Limit with High Side R_DS(ON)

■ Microprocessor Core

■ I/O & Logic

Sensing

■ Hiccup Mode Current Limit Protection

■ Dual N-Channel MOSFET Synchronous Driver

■ Quiescent Current: 500µA, 30µA in Shutdown

■ 8-Pin Surface Mount Package

■ Industrial Control

■ Distributed Power

■ Low Voltage Power

DESCRIPTION

The SP6123 is a fixed frequency, voltage mode, synchronous PWM controller designed to

work from a single 5V or 3.3V input supply, providing excellent AC and DC regulation for high

efficiency power conversion. Requiring only few external components, the SP6123 pack-

aged in an 8-pin NSOIC, is especially suited for low voltage applications where cost, small

size and high efficiency are critical. The operating frequency is internally set to 300kHz

(SP6123) or 500kHz (SP6123A), allowing small inductor values and minimizing PC board

space. TheSP6123drivesanallN-channelsynchronouspowerMOSFETstageforimproved

efficiency and includes an accurate 0.8V reference for low output voltage applications.

TYPICAL APPLICATION CIRCUIT

3V to 5.5V

IN

MBR0530

C

IN

680µF

V

CBST

1µF

IN

BST

GH

GL

0.8V to 5.0V

2A to 10A

CB

2.2µF

V

FDS6890A

L1

CC

(1.6V, 4A shown)

SP6123A

SWN

GND

V

OUT

1.5µH

V

COMP

FB

R1

10k

RZ

15k

C

OUT3

1µF

OUT1

470µF

OUT2

470µF

CP

56pF

CC

4.7nF

R2

10k

FDS6890A

STPS2L25U

Date: 5/25/04

SP6123 Low Voltage, Synchronous Step Down PWM Controller

1

ABSOLUTE MAXIMUM RATINGS

These are stress ratings only and functional operation

of the device at these ratings or any other above those

indicated in the operation sections of the specifications

below is not implied. Exposure to absolute maximum

rating conditions for extended periods of time may

affect reliability.

All other pins ................................ -0.3V to V_CC+ 0.3V

Peak Output Current < 10µs

GH,GL .................................................................. 2A

Storage Temperature ........................ -65°C to 150°C

Power Dissipation

Lead Temperature (Soldering, 10 sec) ............ 300°C

ESD Rating. ................................................ 2kV HBM

V_CC^{.......................................................................................................}7V

BST .................................................................. 13.2V

BST-SWN .............................................................. 7V

ELECTRICAL CHARACTERISTICS

Unless otherwise specified: 0°C < T_A< 70°C, 3.0V < V_CC< 5.5V, C_COMP= 22nF, CGH = CGL = 3.3nF, V_FB= 0.8V,

SWN = GND=0V, typical value for design guideline only.

PARAMETER

MIN TYP MAX UNITS

CONDITIONS

QUIESCENT CURRENT

V_CCSupply Current

0.5

30

1.0

60

mA

No Switching

V_CCSupply Current (Disabled)

ERROR AMPLIFIER

µA

COMP = 0V

Error Amplifier Transconductance

COMP Sink Current

0.6

35

3

mS

µA

MΩ

nA

V

15

60

V_FB= 0.9V, COMP = 0.9V, No Faults

V_FB= 0.7V, COMP = 2V

COMP Source Current

COMP Output Impedance

V_FBInput Bias Current

100

Error Amplifier Reference

OSCILLATOR & DELAY PATH

Internal Oscillator Frequency

Max. Controlled Duty Cycle

Minimum Duty Cycle

0.788 0.8 0.812

Trimmed with Error Amp in Unity Gain

270 300 330

450 500 550

kHz

%

SP6123

SP6123A

90

93

0

%

Comp=0.7V

Minimum GH Pulse Width

100 250

ns

V_CC> 4.5V, Ramp up COMP voltage until

GH starts switching

CURRENT LIMIT

Internal Current Limit Threshold

160 200 240

mV

%/C

us

V_CC- V_SWN; Temp = 25 °C;

V_BST- V_CC> 2.5V

Current Limit Threshold

Temperature Coefficient

0.34

15

Current Limit Time Constant

SOFT START, SHUTDOWN, UVLO

Internal Soft Start Slew Rate

SP6123A

SP6123

0.35 0.60 0.95 V/ms

V_FB= 0.7V and 0V, measure hiccup cycle

period

0.1 0.3

0.6

V/ms

µA

V

COMP Discharge Current

COMP Clamp Voltage

COMP Clamp Current

Shutdown Threshold Voltage

Shutdown Input Pull-up Current

V_CCStart Threshold

185

COMP = 0.5V, Fault Initiated

V_FB= 0.9V

0.55 0.65 0.75

10 30 65

0.29 0.34 0.39

10

2.63 2.8 2.95

2.47 2.7 2.9

µA

V

COMP = 0.5V, V_FB= 0.9V

Measured at COMP Pin

COMP = 0.2V, Measured at COMP pin

2

5

µA

V

V_CCStop Threshold

V

Date: 5/25/04

SP6123 Low Voltage, Synchronous Step Down PWM Controller

2

ELECTRICAL CHARACTERISTICS

Unless otherwise specified: 0°C < T_A< 70°C, 3.0V < V_CC< 5.5V, C_COMP= 22nF, CGH = CGL = 3.3nF, V_FB= 0.8V,

SWN = GND=0V, typical value for design guideline only.

PARAMETER

MIN TYP MAX UNITS

CONDITIONS

GATE DRIVERS

GH Rise Time

110

ns

V_CC> 4.5V

GH Fall Time

GL Rise Time

GL Fall Time

GH to GL Non-Overlap Time

GL to GH Non-Overlap Time

100

PIN DESCRIPTION

PIN N0. PIN NAME DESCRIPTION

1

GL

High current driver output for the low side MOSFET switch. It is always low if GH is high.

GL swings from GND to V_CC

.

2

V_CC

Positive input supply for the control circuitry and the low side gate driver. Properly bypass

this pin to GND with a low ESL/ESR ceramic capacitor.

3

4

GND

Ground pin. Both power and control circuitry of the IC is referenced to this pin.

COMP

Output of the Error Amplifier. It is internally connected to the non-inverting input of the

PWM comparator. A lead-lag network is typically connected to the COMP pinto compen-

sate the feedback loop in order to optimize the dynamic performance of the voltage mode

control loop. Sleep mode can be invoked by pulling the COMP pin below 0.3V with an

external open-drain or open-collector transistor. Supply current is reduced to 30µA (typical)

in shutdown. An internal 5µA pull-up ensures start-up.

5

6

V_FB

Feedback Voltage Pin. It is the inverting input of the Error Amplifier and serves as the

output voltage feedback point for the Buck converter. The output voltage is sensed and

can be adjusted through an external resistor divider.

SWN

Lower supply rail for the GH high-side gate driver. It also connects to the Current Limit

comparator. Connect this pin to the switching node at the junction between the two

external power MOSFET transistors. This pin monitors the voltage drop across the R_DS(ON)

of the high side N-channel MOSFET while it is conducting. When this drop exceeds the

internal 200mV threshold, the overcurrent comparator sets the fault latch and terminates

the output pulses. The controller stops switching and goes through a hiccup sequence. This

prevents excessive power dissipation in the external power MOSFETS during an overload

condition. An internal delay circuit prevents that very short and mild overload conditions,

that could occur during a load transient, from activating the current limit circuit.

7

8

GH

High current driver output for the high side MOSFET switch. It is always low if GL is high or

during a fault. GH swings from SWN to BST.

BST

High side driver supply pin. Connect BST to the external boost diode and capacitor as

shown in the application schematic of page #1. Voltage between BST and SWN should

not exceed 5.5V.

Date: 5/25/04

SP6123 Low Voltage, Synchronous Step Down PWM Controller

3

BLOCK DIAGRAM

1V

-

DRIVER ENABLE

SHUTDOWN

0.8V

Reference

+

-

8

7

BST

GH

350mV

+

FAULT

GM

ERROR

AMP

5µA

PWM COMP

RESET

+

-

SOFTSTART

PWM

Logic

Dominant

-

Synchronous

Driver

R

+

1

GL

Q

V_FB

COMP

V_CC

5

4

S

6

SWN

2

UVLO

3

GND

750mV RAMP

F = 300kHz; SP6123

F = 500kHz; SP6123A

-

2.8V ON

2.7V OFF

+

Reset

Dominant

GH

COMP

S

FAULT

Q

Over Current

(Gated S&H)

SHUTDOWN

R

+

X 2.5

+

SWN

-

500mV

(4000 ppm/°C)

-

OPERATION

General Overview

MOSFET switch allowing for significant effi-

ciencyimprovements.TheSP6123includestwo

fast MOSFET drivers with internal non-overlap

circuitry and drives a pair of N-channel power

transistors. The SP6123 includes an internal

soft-start circuit that provides controlled ramp

up of the output voltage, preventing overshoot

and inrush current at power up.

TheSP6123isaconstantfrequency,voltagemode,

synchronous PWM controller designed for low

voltage, DC/DC step down converters. It is in-

tended to provide complete control for a high

power, high efficiency, precisely regulated output

voltage from a highly integrated 8-pin solution.

Theinternalfree-runningoscillatoraccuratelysets

thePWMfrequencyat300kHzor500kHzwithout

requiringanyexternalelementsandallowstheuse

of physically small, low value external compo-

nents without compromising performance. A

transconductance amplifier is used for the error

amplifier, which compares an attenuated sample

of the output voltage with a precision, 0.8V refer-

ence voltage. The output of the error amplifier

(COMP), is compared to a 0.75V peak-to-peak

ramp waveform to provide PWM control. The

COMP pin provides access to the output of the

error amplifier and allows the use of external

components to stabilize the voltage loop.

Current limiting is implemented by monitoring

the voltage drop across the R_DS(ON)of the high

sideN-channelMOSFETwhileitisconducting,

thereby eliminating the need for an external

sense resistor. The overcurrent comparator has

a built-in threshold of 200mV .

Whentheovercurrentthresholdisexceeded, the

overcurrent comparator sets the fault latch and

terminates the output pulses. The controller

stops switching and goes through a hiccup se-

quence. This prevents excessive power dissipa-

tion in the external power MOSFETs during an

overload condition. An internal delay circuit

prevents that very short and mild overload con-

ditions, that could occur during a load transient,

activate the current limit circuit.

High efficiency is obtained through the use of

synchronous rectification. Synchronous regula-

tors replace the catch diode in the standard buck

converter with a low R_DS(ON)N-channel

Date: 5/25/04

SP6123 Low Voltage, Synchronous Step Down PWM Controller

4

OPERATION

OPERATION: continued

Soft Start

A low power sleep mode can be invoked in the

SP6123 by externally forcing the COMP pin

below 0.3V. Quiescent supply current in sleep

mode is typically less than 30µA. An internal

5µA pull-up current at the COMP pin brings the

SP6123 out of shutdown mode.

Soft start is required on step-down controllers to

prevent excess inrush current through the power

train during start-up. Typically this is managed

by sourcing a controlled current into a timing

capacitor and then using the voltage across this

capacitor to slowly ramp up either the error amp

reference or the error amp output (COMP). The

control loop creates narrow width driver pulses

while the output voltage is low and allows these

pulses to increase to their steady-state duty

cycle as the output voltage increases to its regu-

lated value. As a result of controlling the induc-

tor volt*second product during startup, inrush

current is also controlled.

An internal 0.8V 1.5% reference allows output

voltage adjustment for low voltage applications.

The SP6123 also includes an accurate under-

voltage lockout that shuts down the controller

when the input voltage falls below 2.7V. Output

overvoltage protection is achieved by turning

off the high side switch and turning on the low

side N-channel MOSFET 100% of the time.

Enable

In the SP6123 the duration of the soft-start is

controlled by an internal timing circuit that

provides a 0.27V/ms slew-rate, which is used

during startup and overcurrent to set the hiccup

time.TheSP6123implementssoft-startbyramp-

ing up the error amplifier reference voltage

providing a controlled slew-rate of the output

voltage, thereby preventing overshoot and in-

rush current at power up.

Low quiescent mode or “Sleep Mode” is initi-

ated by pulling the COMP pin below 0.3V with

an external open-drain or open-collector tran-

sistor. Supply current is reduced to 30µA (typi-

cal) in shutdown. On power-up, assuming that

VCC has exceeded the UVLO start threshold

(2.8V), an internal 5µA pull-up current at the

COMP pin brings the SP6123 out of shutdown

mode and ensures start-up. During normal oper-

ating conditions and in absence of a fault, an

internal clamp prevents the COMP pin from

swinging below 0.6V. This guarantees that dur-

ing mild transient conditions, due either to line

or load variations, the SP6123 does not enter

shutdown unless it is externally activated.

The presence of the output capacitor creates

extracurrentdrawduringstartup. Simplystated,

dV_OUT/dt requires an average sustained current

in the output capacitor and this current must be

considered while calculating peak inrush cur-

rent and over current thresholds. An approxi-

mate expression to determine the excess inrush

current due to the dV_OUT/dt of the output capaci-

tor C_OUTis:

During Sleep Mode, the high side and low side

MOSFETS are turned off and the internal soft

start voltage is held low.

V_OUT

x

0.8V

Iinrush = C_OUTx S_SS

UVLO

Where,

Assuming that there is not shutdown condition

present, then the voltage on the V_CCpin deter-

mines operation of the SP6123. As V_CCrises,

the UVLO block monitors V_CCand keeps the

high side and low side MOSFETS off and the

internal SS voltage low until V_CCreaches 2.8V.

If no faults are present, the SP6123 will initiate

a soft start when V_CCexceeds 2.8 V.

S_SS= Softstart slew rate, 0.6V/ms for SP6123A

and 0.3V/ms for SP6123.

As the figure shows, the SS voltage controls a

variety of signals. First, provided all the exter-

nal fault conditions are removed, an internal

5µApull-upattheCOMPpinbringstheSP6123

out of shutdown mode. The internal timing

circuit is then activated and controls the ramp-

up of the error amp reference voltage. The

COMP pin is pulled to 0.7V by the internal

Hysteresis (about 100mV) in the UVLO com-

parator provides noise immunity at start-up.

Date: 5/25/04

SP6123 Low Voltage, Synchronous Step Down PWM Controller

5

OPERATION

clamp and then gradually charges preventing

the error amplifier from forcing the loop to

maximum duty cycle. As the COMP voltage

crosses about 1V (valley voltage of the PWM

ramp), the driver begins to switch the high side

MOSFET with narrow pulses in an effort to

keeptheconverteroutputregulated.TheSP6123

operates at low duty cycle as the COMP voltage

increases above 1V. As the error amp reference

ramps upward, the driver pulses widen until a

steady state value is reached and the output

voltage is regulated to the final value ending the

soft start charge cycle.

Hiccup Mode

When the converter enters a fault mode, the

SP6123 holds the high side and low side

MOSFETs off for a finite period of time. Pro-

vided that the SP6123 is enabled, this time is set

by the internal charge of the soft-start capacitor.

In the event of an overcurrent condition, the

current sense comparator sets the fault latch,

which in turn discharge the internal SS capaci-

tor, the COMP pin and holds the output drivers

off. During this condition, the SP6123 stays off

for the time it takes to discharge the COMP pin

down to the 0.27V shutdown threshold. At this

point, the fault latch is reset, but before the

SP6123 is allowed to attempt restart, the COMP

pin has to charge back to 1V before any output

switching can be initiated. Then, the regulator

attempts to restart normally by delivering short

gate pulses and if the overcurrent condition is

still present, the cycle will repeat itself. How-

ever, if upon restart, the overcurrent condition is

still present, the SP6123 will detect the fault and

remaininafaultstateuntilCOMPreachesabout

V_CC-1V thereby increasing the MOSFET off-

time. This protection scheme minimizes ther-

mal stress to the regulator components as the

overcurrent condition persists.

COMP

1 V

0.7 V

0.3 V

0 V

Internal SS

Voltage

Error Amp

Reference

Voltage

V_OUT= V_REF* (1+R1/R2)

0.8 V

The simplified waveforms that describe the hic-

cup mode operation are shown below.

0 V

I(L)

V_CC-V_SWN

200 mV

Inductor

Current

0 V

0 A

V_COMP

3 V

V(V_CC

)

FAULT

1.0 V

0.3 V

0 V

V(V_CC

)

V_BST

GH

Voltage

SWN

Voltage

0 V

V_SWN

TIME

Date: 5/25/04

SP6123 Low Voltage, Synchronous Step Down PWM Controller

6

OPERATION

A more detailed description of the waveform is shown below.

SP6123 OVER CURRENT (HICCUP MODE)

Test Conditions

V_FB= 0.7V

V

_CC= 5.0V

BST = 5.0V

SWN - tied to GND through 1k Resistor

COMP – released from GND

Overcurrent Detected

Internal SSTART rises until

G Turns Off

H

~ V -1V, then gives command

CC

(Fault Mode Enabled)

to attempt RESTART

G

H

COMP Clamps

~ 3V

COMP

After pop, COMP

retains internal

SSTART slope

ENABLE

Part

5µA PULLUP slope to 0.3V;

35µA PULLUP to 0.7V

Internal SSTART

Attempt

RESTART

passes V(V ), COMP

FB

pops to ~ internal

SSTART voltage +0.7V

Date: 5/25/04

SP6123 Low Voltage, Synchronous Step Down PWM Controller

7

OPERATION

Over Current Protection

lems in the external MOSFETs.

Over current protection on the SP6123 is imple-

mented through detection of an excess voltage

condition across the high side NMOS switch dur-

ingconduction.Thisistypicallyreferredtoashigh

side R_DS(ON)detection and eliminates the need of

an external sense resistor. The over current com-

parator charges an internal sampling capacitor

each time V(V_CC)-V(SWN) exceeds the 200mV

(typ)internalthresholdandtheGHvoltageishigh.

The discharge/charge current ratio on the sam-

pling capacitor is about 2%. Therefore, provided

that the over current condition persists, the capaci-

torvoltagewillbepumpedupduringeachtimeGH

switches high. This voltage will trigger an over

current condition upon reaching a CMOS inverter

threshold. There are many advantages to this

approach. First, the filtering action of the gated

schemeprotectsagainstfalseandundesirabletrig-

gering that could occur during a minor transient

overload condition or supply line noise. Further-

more, the total amount of time to trigger the fault

depends on the on-time of the high side NMOS

switch. Fifteen, 1µspulsesareequivalenttothirty,

500nspulsesorone,15µspulse,however,depend-

ing on the period, each scenario takes a different

amount of total time to trigger a fault. Therefore,

thefaultbecomesanindicatorofaveragepowerin

the high side switch. The 200mV overcurrent

threshold has a 3400 ppm/°C temperature coeffi-

cients in an effort to first order match the thermal

characteristics of the R_DS(ON)of the high side

NMOS switch. It assumed that the SP6123 will be

used in compact designs where there is a high

amount of thermal coupling between the high side

switch and the controller.

The following figure shows typical waveforms

for the output drivers.

As with all synchronous designs, care must be

taken to ensure that the MOSFETs are properly

chosen for non-overlap time, enhancement gate

drive voltage, “on” resistance R_DS(ON), reverse

transfer capacitance Crss, input voltage and

maximum output current.

GATE DRIVER TEST CONDITIONS

5 V

90 %

FALL TIME

GH(GL)

2 V

10 %

5 V

90 %

RISE TIME

2 V

GL(GH)

10 %

NON-OVERLAP

V(BST)

GH

Voltage

0 V

V(VCC)

GL

Voltage

0 V

V(VCC=VIN)

SWN

Voltage

~ 0 V

Output Drivers

- V(Diode) V

The SP6123, unlike some other bipolar control-

ler IC’s, incorporates gate drivers with rail-to-

rail swing that help prevent spurious turn on due

to capacitive coupling. The driver stage consists

of one high side NMOS, 4Ω driver, GH, and one

low side, 4 Ω, NMOS driver, GL, optimized for

driving external power MOSFET’s in a syn-

chronous buck topology. The output drivers

also provide gate drive non-overlap mechanism

that provides a dead time between GH and GL

transitionstoavoidpotentialshoot-throughprob-

~ 2*V(VIN)

BST

Voltage

~ V(VIN)

TIME

Date: 5/25/04

SP6123 Low Voltage, Synchronous Step Down PWM Controller

8

APPLICATIONS INFORMATION

a gradual saturation characteristic but can intro-

duce considerable ac core loss, especially when

the inductor value is relatively low and the

ripple current is high. Ferrite materials, on the

other hand, are more expensive and have an

abrupt saturation characteristic with the induc-

tance dropping sharply when the peak design

current is exceeded. Nevertheless, they are pre-

ferred at high switching frequencies because

they present very low core loss and the design

only needs to prevent saturation.

Inductor Selection

There are many factors to consider in selecting

the inductor including cost, efficiency, size and

EMI. In a typical SP6123 circuit, the inductor is

chosen primarily for value, saturation current

andDCresistance.Increasingtheinductorvalue

will decrease output voltage ripple, but degrade

transientresponse. Lowinductorvaluesprovide

the smallest size, but cause large ripple currents,

poor efficiency and more output capacitance to

smooth out the larger ripple current. The induc-

tor must also be able to handle the peak current

at the switching frequency without saturating,

and the copper resistance in the winding should

be kept as low as possible to minimize resistive

power loss. A good compromise between size,

loss and cost is to set the inductor ripple current

tobewithin20%to40%ofthemaximumoutput

current.

The power dissipated in the inductor is equal to

the sum of the core and copper losses. To mini-

mizecopperlosses,thewindingresistanceneeds

to be minimized, but this usually comes at the

expense of a larger inductor. Core losses have a

more significant contribution at low output cur-

rent where the copper losses are at a minimum,

and can typically be neglected at higher output

currentswherethecopperlossesdominate.Core

loss information is usually available from the

magnetic vendor.

The switching frequency and the inductor oper-

ating point determine the inductor value as fol-

lows:

Thecopperlossintheinductorcanbecalculated

using the following equation:

V_OUT(V_{IN (max)}−V_OUT

)

L =

P_L(Cu)= I_L²_(RMS)R_WINDING

V_{IN (max)}F_SK_rI_{OUT (max)}

where:

where I_L(RMS)is the RMS inductor current that

can be calculated as follows:

F_S= switching frequency

K_r= ratio of the peak to peak inductor ripple

current to the maximum output current

2

1

I_PP

I_OUT(max)

I_L(RMS)= I_OUT(max)1 +

(

)

3

The peak to peak inductor ripple current is:

Output Capacitor Selection

V_OUT(V_{IN (max)}−V_OUT

)

The required ESR (Equivalent Series Resis-

tance) and capacitance drive the selection of the

type and quantity of the output capacitors. The

ESR must be small enough that both the resis-

tive voltage deviation due to a step change in the

load current and the output ripple voltage do not

exceed the tolerance limits expected on the

output voltage. During an output load transient,

the output capacitor must supply all the addi-

tional current demanded by the load until the

SP6123 adjusts the inductor current to the new

value. Therefore the capacitance must be large

enough so that the output voltage is held up

while the inductor current ramps up or down to

I_PP

=

V_IN(max)F_SL

Once the required inductor value is selected, the

proper selection of core material is based on

peak inductor current and efficiency require-

ments. The core material must be large enough

not to saturate at the peak inductor current

I_PP

I_PEAK= I_{OUT (max)}

+

2

and provide low core loss at the high switching

frequency. Low cost powdered iron cores have

Date: 5/25/04

SP6123 Low Voltage, Synchronous Step Down PWM Controller

9

APPLICATIONS INFORMATION

the value corresponding to the new load current.

Additionally, the ESR in the output capacitor

causes a step in the output voltage equal to the

ESR value multiplied by the change in load

current. Because of the fast transient response

providedbytheSP6123whenexposedtooutput

load transient, the output capacitor is typically

chosen for ESR , not for capacitance value.

pacitors. These capacitors have a lower ESR

thantantalumcapacitors,reducingthetotalnum-

ber of capacitance required for a given transient

response.

Input Capacitor Selection

The input capacitor should be selected for ripple

current rating, capacitance and voltage rating.

The input capacitor must meet the ripple current

requirement imposed by the switching current.

In continuous conduction mode, the source cur-

rent of the high-side MOSFET is approximately

a square wave of duty cycle V_OUT/ V_IN. Most of

this current is supplied by the input bypass

capacitors. The RMS value of input capacitor

current is determined at the maximum output

current and under the assumption that the peak

to peak inductor ripple current is low, it is given

by:

The output capacitor’s ESR, combined with the

inductor ripple current, is typically the main con-

tributor to output voltage ripple. The maximum

allowable ESR required to maintain a specified

output voltage ripple can be calculated by:

∆V_OUT

R_ESR

≤

I_PP

where:

∆V_OUT= peak to peak output voltage ripple

I_PP= peak to peak inductor ripple current

I_CIN(rms)= I_OUT(max)

√D(1 - D)

The worse case occurs when the duty cycle, D,

is 50% and gives an RMS current value equal to

I_OUT/2. Select input capacitors with adequate

ripple current rating to ensure reliable opera-

tion.

The total output ripple is a combination of the

ESR and the output capacitance value and can

be calculated as follows:

∆V_OUT

=

²+ (I_PPR_ESR

)

I_PP(1 – D)

2

The power dissipated in the input capacitor is:

(

)

C_OUTF_S

P

= I_C²_{IN (rms)}R_ESR(CIN)

CIN

where:

This can become a significant part of power

losses in a converter and hurt the overall energy

transfer efficiency.

D = duty cycle equal to V_OUT/V_IN

C_OUT= output capacitance value

The input voltage ripple primarily depends on

the input capacitor ESR and capacitance. Ignor-

ing the inductor ripple current, the input voltage

ripple can be determined by:

Recommended capacitors that can be used ef-

fectively in SP6123 applications are: low-ESR

aluminum electrolytic capacitors, OS-CON ca-

pacitors that provide a very high performance/

size ratio for electrolytic capacitors and low-

ESR tantalum capacitors. AVX TPS series and

KemetT510surfacemountcapacitorsarepopu-

lartantalumcapacitorsthatworkwellinSP6123

applications. POSCAP from Sanyo is a solid

electrolytic chip capacitor that has low ESR and

high capacitance. For the same ESR value,

POSCAP has lower profile compared with tan-

talum capacitor.

I

_{OUT (MAX )}V_OUT(V_IN−V_OUT)

∆V_IN= I_out(max)R_{ESR(CIN )}

+

2

F_SC_INV_IN

The capacitor type suitable for the output ca-

pacitors can also be used for the input capaci-

tors. However, exercise extra caution when tan-

talum capacitors are considered. Tantalum ca-

pacitorsareknownforcatastrophicfailurewhen

exposed to surge current, and input capacitors

are prone to such surge current when power

supplies are connected ‘live’ to low impedance

Panasonic offers the SP series of specialty poly-

mer aluminum electrolytic surface mount ca-

Date: 5/25/04

SP6123 Low Voltage, Synchronous Step Down PWM Controller

10

APPLICATIONS INFORMATION

_CL(max)= R_{DS(ON) OUT(max)}

²(1 - D),

P

I

powersources.Certaintantalumcapacitors,such

as AVX TPS series, are surge tested. For generic

tantalum capacitors, use 2:1 voltage derating to

protect the input capacitors from surge fallout.

where:

P_CH(max)= conduction losses of the high side

MOSFET

MOSFET Selection

P_CL(max)= conduction losses of the low side

MOSFET

The losses associated with MOSFETs can be

divided into conduction and switching losses.

Conduction losses are related to the on resis-

tance of MOSFETs, and increase with the load

current. Switching losses occur on each on/off

transition when the MOSFETs experience both

high current and voltage. Since the bottom

MOSFET switches current from/to a paralleled

diode (either its own body diode or an external

Schottkydiode),thevoltageacrosstheMOSFET

is no more than 1V during switching transition.

As a result, its switching losses are negligible.

The switching losses are difficult to quantify

due to all the variables affecting turn on/off

time. However, making the assumption that the

turn on and turn off transition times are equal,

the transition time can be approximated by:

R_DS(ON)= drain to source on resistance.

The total power losses of the top MOSFET are

the sum of switching and conduction losses. For

synchronous buck converters of efficiency over

90%, allow no more than 4% power losses for

high or low side MOSFETs. For input voltages

of 3.3V and 5V, conduction losses often domi-

nate switching losses. Therefore, lowering the

R

_DS(ON)of the MOSFETs always improves effi-

ciencyeventhoughitgivesrisetohigherswitch-

ing losses due to increased C_ISS

.

Total gate charge is the charge required to turn

the MOSFETs on and off under the specified

operating conditions (V_GSand V_DS). The gate

charge is provided by the SP6123 gate drive

circuitry. (At 500kHz switching frequency, the

gate charge is the dominant source of power

dissipationintheSP6123). Atlowoutputlevels,

this power dissipation is noticeable as a reduc-

tion in efficiency. The average current required

to drive the high side and low side MOSFETs is:

C_ISSV_IN

t_T=

,

I_G

where C_ISSis the MOSFET’s input capacitance,

or the sum of the gate-to-source capacitance,

C_GS, and the drain-to-gate capacitance, C_GD

This parameter can be directly obtained from

the MOSFET’s data sheet.

.

I

_G(av)= Q_GHF_S+ Q_GLF_S, where

Q_GHand Q_GLare the total charge for the high

side and the low side MOSFETs respectively.

I_Gis the gate drive current provided by the

SP6123 (approximately 1A at V_IN=5V) and V_IN

is the input supply voltage.

Considering that the gate charge current comes

from the input supply voltage V_IN, the power

dissipated in the SP6123 due to the gate drive is:

Therefore an approximate expression for the

switching losses associated with the high side

MOSFET can be given as:

P_{GATE DRIVE}= V_INI_G(av)

P_SH(max)= (V_IN(max)+ V_F)I_OUT(max)t_TF_S,

Top and bottom MOSFETs experience unequal

conductionlossesiftheirontimeisunequal. For

applicationsrunningatlargeorsmalldutycycle,

it makes sense to use different top and bottom

MOSFETs. Alternatively, parallel multiple

MOSFETs to conduct large duty factor.

where t_Tis the switching transition time and V_F

is the free wheeling diode drop.

Switching losses need to be taken into account

for high switching frequency, since they are

directly proportional to switching frequency.

The conduction losses associated with top and

bottom MOSFETs are determined by

R_DS(ON)varies greatly with the gate driver volt-

age.TheMOSFETvendorsoftenspecifyR_DS(ON)

on multiple gate to source voltages (V_GS), as

well as provide typical curve of R_DS(ON)versus

P_CH(max)= R_{DS(ON) OUT(max)}

²D

I

Date: 5/25/04

SP6123 Low Voltage, Synchronous Step Down PWM Controller

11

APPLICATIONS INFORMATION

V_GS. For 5V input, use the R_DS(ON)specified at

4.5V V_GS. At the time of this publication, ven-

dors, such as Fairchild, Siliconix and Interna-

tional Rectifier, have started to specify R_DS(ON)

at V_GSless than 3V. This data is necessary for

designs where the MOSFETs are driven with

3.3V.

forward voltage. The reverse voltage across the

diode is equal to input voltage, and the diode

must be able to handle the peak current equal to

the maximum load current.

The power dissipation of the Schottky diode is

determined by

P_DIODE= 2V_FI_OUTT_NOLF_S

Thermal calculation must be conducted to en-

sure the MOSFET can handle the maximum

load current. The junction temperature of the

MOSFET, determined as follows, must stay

below the maximum rating.

where

T

_NOL= non-overlap time between G_Land G_H.

V_F= forward voltage of the Schottky diode.

®®

COMP

P_{MOSFET (max)}

T_J(max)=T_A(max)

+

,

R1

R_θ

C2

JA

SP6123

C1

where

T_A(max)= maximum ambient temperature

P_MOSFET(max)= maximum power dissipation of

the MOSFET

Figure 1. The RC network connected to the COMP pin

provides a pole and a zero to control loop.

R_θJA= junction to ambient thermal resistance.

Loop Compensation Design

R_θJAof the device depends greatly on the board

layout, as well as device package. Significant

thermalimprovementcanbeachievedinthemaxi-

mum power dissipation through the proper design

of copper mounting pads on the circuit board. For

example, in a SO-8 package, placing two 0.04

square inches copper pad directly under the pack-

age, without occupying additional board space,

canincreasethemaximumpowerdissipationfrom

approximately 1 to 1.2W. For DPAK package,

enlarging the tap mounting pad to 1 square inches

reduces the R_θJAfrom 96°C/W to 40°C/W.

The goal of loop compensation is to manipulate

loopfrequencyresponsesuchthatitsgaincrosses

over 0db at a slope of -20db/dec. The SP6123

has a transconductance error amplifier and re-

quires the compensation network to be con-

nected between the COMP pin and ground, as

shown in Figure 1.

The first step of compensation design is to pick

the loop crossover frequency. High crossover

frequencyisdesirableforfasttransientresponse,

but often jeopardize the system stability. Cross-

over frequency should be higher than the ESR

zero but less than 1/5 of the switching fre-

quency. TheESRzeroiscontributedbytheESR

associated with the output capacitors and can be

determined by

Schottky Diode Selection

When paralleled with the bottom MOSFET, an

optional Schottky diode can improve efficiency

and reduce noise. Without this Schottky diode,

the body diode of the bottom MOSFET con-

ducts the current during the non-overlap time

when both MOSFETs are turned off. Unfortu-

nately, the body diode has high forward voltage

and reverse recovery problem. The reverse re-

covery of the body diode causes additional

switching noises when the diode turns off. The

Schottky diode alleviates this noise and addi-

tionally improves efficiency thanks to its low

1

f_Z(ESR)

=

2πC_OUTR_ESR

Crossover frequency of 20kHz is a sound first

try if low ESR tantalum capacitors or POSCAPs

are used at the output. The next step is to calcu-

late the complex conjugate poles contributed by

the LC output filter,

Date: 5/25/04

SP6123 Low Voltage, Synchronous Step Down PWM Controller

12

APPLICATIONS INFORMATION

1

erosion of phase margin. Therefore, the value of

the C₂can be derived from

f_P(LC)

=

2π√ LC_OUT

1

C₂=

The open loop gain of the whole system can be

divided into the gain of the error amplifier,

PWM modulator, buck converter, and feedback

resistor divider. In order to crossover at the

selected frequency f_co, the gain of the error

amplifier has to compensate for the attenuation

caused by the rest of the loop at this frequency.

In the RC network shown in Figure 1, the product

of R1 and the error amplifier transconductance

determines this gain. Therefore, R1 can be de-

termined from the following equation that takes

into account the typical error amplifier

transconductance, reference voltage and PWM

ramp built into the SP6123.

20πf_COR₁

Figure 2 illustrates the overall loop frequency

response and frequency of each pole and zero.

Tofine-tunethecompensation, itisnecessaryto

physically measure the frequency response us-

ing a network analyzer.

Gain

-20db/dec

-40db/dec

Loop

-20db/dec

2083V_OUTf_COf_Z(ESR)

R₁=

f

2

V_INf_P(LC)

In Figure 1, R1 and C1 provides a zero f_Z1which

needs to be placed at or below f_P(LC). If f_Z1is

made equal to f_P(LC)for convenience, the value

of C₁can be calculated as

-20db/dec

Error Amplifier

1

f

C₁=

2πf_P(LC)R₁

f

CO

f

P1

Z1 P(LC)

Z(ESR)

The optional C₂generates a pole f_P1with R₁to

cut down high frequency noise for reliable op-

eration. This pole should be placed one decade

higher than the crossover frequency to avoid

Figure 2. Frequency response of a stable system and its

error amplifier.

3V to 5.5V

D1

MBR0530

R1

5.0

C

IN

47µF Ceramic

CBST

1µF

1

2

3

4

BST

GH

8

7

6

5

GL

Q1

FDS6890A

V

CC

L1

1µH

SP6123A

U1

SWN

GND

1.6V/4A

CB

2.2µF

COMP

V

FB

D2

C1

330pF

R2

80k

C

OUT

4x47µF Ceramic

STPS2L25U

Q1

FDS6890A

CZ

RZ

CP

47pF

680pF

R3

80k

20k

Figure 3. SP6123 Buck converter design with ceramic output capacitors.

Date: 5/25/04

SP6123 Low Voltage, Synchronous Step Down PWM Controller

13

APPLICATIONS INFORMATION

Most electrolytic and tantalum capacitors come

with adequate ESR value to generate a zero below

power supplies’ crossover frequency. This is cru-

cial to a stable close loop system. However, this

same system can become unstable if ceramic out-

put capacitors are used. The low ESR associated

with ceramic capacitors can push the ESR zero

above the crossover frequency and often higher

than 1MHz. In this case, type III compensation is

required to provide additional low frequency zero for

adequate phase margin and thus stable operation.

InSP6123, G_M(erroramplifiertransconductance)

and R_OUT(error amplifier output impedance) are

specified at 0.6ms and 3MΩ, respectively.

For frequencies above the second zero f_Z2, the

feedback gain rises at 20dB/dec and is equal to

A_FB= 2πfR_ZC₁

However, the error amplifier gain A_EAdeclines

at -20dB/dec due to C_P.

G_M

2πfC_P

A_EA

=

The design of type III compensation using

SP6123transconductanceerroramplifierisquite

straightforward. First, theresonantfrequencyof

the LC output filter could be derived from

When A_FBis less than A_EA, the compensated

error amplifier gain is dominated by A_FB. As a

result, it shows up as a positive 20dB/dec slope.

However, when the rising A_FBcrosses the fall-

ing A_EAat one particular frequency, the com-

pensated error amplifier gain is now solely de-

terminedbyA_EA. Therefore, the20dB/decslope

is converted to a -20dB/dec slope, and the bode

plot demonstrates a double pole at this fre-

quency which is equal to

1

f_r=

= 11.6kHz

2π√ L₁C_OUT

The values and references used in all the calcula-

tions agree with the schematic shown in Figure 3.

Select values of R2, C1, R_Zand C_Zto place two

zeros below or equal to the LC resonant fre-

quency. Those two zeros are located at:

1

2π

GM

C_PC₁R_Z

f_P2

=

= 221kHz

1

f_Z1

f_Z2

=

= 6kHz

2πR₂C₁

SelectC_Psuchthatf_P2islocatedatleastadecade

higher than the crossover frequency.

1

= 11.7kHz

2πR_ZC_Z

As shown in Figure 4, this type III compensation

generatesacloseloopsystemwith50degreephase

margin and crossover frequency at 20kHz. This

ensures a stable regulated power supply with tight

DC regulation and fast transient response.

There is low frequency pole determined by both

the error amplifier gain and feedback gain. It

occurs at

1

f_P1

=

= 3.25Hz

2π(R₂// R₃)C_ZG_MR_OUT

200

Phase

100

0

Gain

-100

-200

10Hz

100Hz

1.0kHz

10kHz

1.0MHz

10MHz

Frequency

Figure 4. Bode Plot for schematic shown in Figure 3. V_IN= 3.3V and V_OUT= 1.6V, no load.

Date: 5/25/04

SP6123 Low Voltage, Synchronous Step Down PWM Controller

14

APPLICATIONS INFORMATION

Overcurrent Protection

Output Voltage Program

Over current protection on the SP6123 is imple-

mented through detection of an excess voltage

condition across the high side switch during

conduction. This is typically referred to as high

side R_DS(ON)detection. By using the R_DS(ON)of

Q1 to measure the output current, the current

limit circuit eliminates the sense resistor that

would otherwise be required and the corre-

sponding loss associated with it. This improves

the overall efficiency and reduces the number of

components in the power path benefiting size

and cost. R_DS(ON)sensing is by default inaccu-

rate and is primarily meant to protect the power

supply during a fault condition. The overcurrent

trip point will vary from unit to unit as the

R_DS(ON)of MOSFET varies. The SP6123 pro-

vides a built-in 200mV threshold between the

As shown in Figure 5, the voltage divider con-

necting to the V_FBpin programs the output

voltage according to

R₁

R₂

V_OUT= 0.8(1 +

)

where 0.8V is the internal reference voltage.

SelectR2intherangeof10kto100k, andR1can

be calculated using

R₂(V_OUT– 0.8)

R₁=

0.8

V_OUT

V

_CCand SWN pins.

The overcurrent threshold can be calculated as

®

R1

R2

V_FB

200mV

R_DS(ON)

SP6123

I_MAX

=

To ensure accurate current sensing, the V_CCpin

should be connected directly to the drain of the

high side MOSFET. A RC filter on the V_CCpin

is not recommended because it would artifi-

cially alter the current signal and reduce the

overcurrent threshold from the value given by

the equation.

Figure 5. A voltage divider connected to the V_FBpin

programs the output voltage.

Date: 5/25/04

SP6123 Low Voltage, Synchronous Step Down PWM Controller

15

LAYOUT GUIDELINE

PCB layout plays a critical role in proper func-

tionoftheconvertersandEMIcontrol. Inswitch

mode power supplies, loops carrying high di/dt

give rise to EMI and ground bounces. The goal

of layout optimization is to identify these loops

and minimize them. It is also crucial on how to

connect the controller ground such that its op-

eration is not affected by noise. The following

guideline should be followed to ensure proper

operation.

4. TheV_CCbypasscapacitorshouldberightnext

to the V_CCand GND pins.

5. The trace connecting the feedback resistors to

the output should be short, direct and far away

from the switch node, and switching compo-

nents.

6. Minimize the trace between G_H/G_Land the

gates of the MOSFETs to reduce the impedance

drivingtheMOSFETs. Thisisespeciallyimpor-

tant for the bottom MOSFET that tends to turn

on through its Miller capacitor when the switch

node swings high.

1. A ground plane is recommended for minimiz-

ing noises, copper losses and maximizing heat

dissipation.

7. Minimize the loop composed of input capaci-

tors, top/bottomMOSFETsandSchottkydiode.

This loop carries high di/dt current. Also in-

crease the trace width to reduce copper losses.

2. Beginthelayoutbyplacingthepowercompo-

nents first. Orient the power circuitry to achieve

a clean power flow path. If possible make all the

connections on one side of the PCB with wide,

copper filled areas.

8. Maximizethetracewidthoftheloopconnect-

ing the inductor, output capacitors, Schottky

diode and bottom MOSFET.

3. Connect the ground of feedback divider and

compensation components directly to the GND

pin of the IC using a dedicated ground trace.

Then connect this pin as close as possible to the

ground of the output capacitor.

Date: 5/25/04

SP6123 Low Voltage, Synchronous Step Down PWM Controller

16

PACKAGE: 8 PIN NSOIC

D

e

E/2

E1

E

E1/2

SEE VIEW C

1

b

INDEX AREA

(D/2 X E1/2)

Ø1

TOP VIEW

Gauge Plane

L2

Ø

Ø1

Seating Plane

L

L1

VIEW C

A2

A

SEATING PLANE

A1

SIDE VIEW

b

WITH PLATING

8 Pin NSOIC

(JEDEC MS-012,

AA - VARIATION)

DIMENSIONS

Minimum/Maximum

(mm)

COMMON HEIGHT DIMENSION

SYMBOL

MIN NOM MAX

c

1.75

0.25

1.65

0.51

0.25

-

A

1.35

A1

A2

b

c

D

E

0.10

1.25

0.31

0.17

BASE METAL

4.90 BSC

6.00 BSC

3.90 BSC

1.27 BSC

CONTACT AREA

E1

e

L

-

0.40

1.27

L1

L2

1.04 REF

0.25 BSC

PACKAGE:

8 PIN NSOIC

-

0º

5º

8º

Ø

Ø1

(Narrow refers to symbol E1)

15º

Date: 5/25/04

SP6123 Low Voltage, Synchronous Step Down PWM Controller

17

ORDERING INFORMATION

Operating Temperature Range

Part Number

500kHz

Package Type

SP6123ACN............................................. 0˚C to +70˚C ........................................... 8-Pin NSOIC

SP6123ACN/TR ....................................... 0˚C to +70˚C ........................................... 8-Pin NSOIC

300kHz

SP6123CN ............................................... 0˚C to +70˚C ........................................... 8-Pin NSOIC

SP6123CN/TR ......................................... 0˚C to +70˚C .......................................... 8-Pin NSOIC

Available in lead free packaging. To order add "-L" suffix to part number.

Example: SP6123CN/TR = standard; SP6123CN-L/TR = lead free

/TR = Tape and Reel

Pack quantity is 2500 for NSOIC.

Corporation

ANALOG EXCELLENCE

Sipex Corporation

Headquarters and

Sales Office

233 South Hillview Drive

Milpitas, CA 95035

TEL: (408) 934-7500

FAX: (408) 935-7600

Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the

application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.

Date: 5/25/04

SP6123 Low Voltage, Synchronous Step Down PWM Controller

18


型号：	SP6123ACN-L/TR
厂家：	SIPEX CORPORATION
描述：	Switching Controller, Voltage-mode, 2A, 550kHz Switching Freq-Max, PDSO8, LEAD FREE, MS-012AA, SOIC-8 转换器二极管控制器局域网
文件：	总18页 (文件大小：154K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SP6123ACN-L/TR [SIPEX]

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SP6123CN

SP6123CN-L

SP6123CN/TR

SP6123EN

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SP6124

SP6124A

SP6124AE3

SP6124E3