SP6139EU-L_技术文档

®

Advanced

SP6139

Wide Input, 1.3MHz Synchronous PWM Controller

FEATURES

■ 2.5V to 20V Step Down Achieved Using Dual Input

V_CC

GL

10

9

1

2

3

4

5

BST

GH

SP6139

■ Small 10-Pin MSOP Package

GND

V_FB

8

SWN

SS

■ Up to 15A Ouput Capability

10 Pin MSOP

7

■ Highly Integrated Design, Minimal Components

■ UVLO Detects Both V_CCand V_IN

6

COMP

UVIN

■ Short Circuit Protection with Auto-Restart

■ On-Board 1.5Ω sink (2Ω source) NFET Drivers

■ Programmable Soft Start

Now Available in Lead Free Packaging

APPLICATIONS

■ DSL Modems

■ Fast Transient Response

■ High Efficiency: Greater than 94% Possible

■ A Synchronous Start-Up into a Pre-Charged Output

■ Set-Top Boxes

■ 12V V_INPoint of Load Apps.

DESCRIPTION

The SP6139 is a synchronous step-down switching regulator controller optimized for high efficiency. The part is

designed to be especially attractive for dual supply, 12V step down with 5V used to power the controller. This lower V_CC

voltage minimizes power dissipation in the part. The SP6139 is designed to drive a pair of external NFETs using a fixed

1.3MHz frequency, PWM voltage mode architecture. Protection features include UVLO, thermal shutdown and output

short circuit protection. The SP6139 is available in the cost and space saving 10-pin MSOP.

TYPICAL APPLICATION CIRCUIT

V

IN

12V

C1

22µF

16V

8

7

V

= 5V @ 30mA

CC

Si4922DY

8.3A, 18mΩ

QT

2

GND

C1, C2

RLF

3.0,5%

1

Ceramic

1210

X5R

CBST

L1 SD25-2R2

2.2µH @ 2.8A

DCR=31mΩ

0.1µF

U1

DBST

V

IN

OUT

≤

MBR0530

R5

5

6

3.3V @ 2A

RZ3

1

2

3

4

5

10

9

Bead

VCC

SP6139

BST

2.26k, 1%

C_VCC

10µF

C3

47µF

6.3V

C4

47µF

6.3V

GND 3

GL

GH

SWN

SS

Si4922DY

8.3A, 18mΩ

R1

QB

4

8

GND

VFB

68.1k, 1%

CZ3

220pF

R3

150k, 1%

6.3V

7

SS

0.8V

3

6

COMP

UVIN

C_VCC

Ceramic

8050

UV

IN

CSS

47nF

GND2

CZ2

RZ2

R2

21.5k, 1%

1.2nF 12.7k, 1%

CP1

R4

100k, 1%

X5R

C3, C4

Ceramic

1210

CF1

100pF

39pF

X5R

Date: 12/20/04

SP6139 Wide Input, 1.3MHz Synchronous PWM Controller

1

ABSOLUTE MAXIMUM RATINGS

These are stress ratings only and functional operation of the device at

these ratings or any other above those indicated in the operation sections

of the specifications below is not implied. Exposure to absolute maximum

rating conditions for extended periods of time may affect reliability.

Peak Output Current < 10us

GH,GL ............................................................................................. 2A

Storage Temperature .................................................. -65°C to 150°C

Power Dissipation .......................................................................... 1W

Lead Temperature (Soldering, 10 sec) ...................................... 300°C

ESD Rating .......................................................................... 2kV HBM

Thermal Resistance ............................................................. 41.9°C/W

V_CC.................................................................................................. 7V

BST ............................................................................................... 27V

BST-SWN ......................................................................... -0.3V to 7V

SWN ................................................................................... -1V to 20V

GH ......................................................................... -0.3V to BST+0.3V

GH-SWN ......................................................................................... 7V

All other pins .......................................................... -0.3V to V_CC+0.3V

ELECTRICAL CHARACTERISTICS

Unless otherwise specified: -40°C < T_AMB< 85°C, 4.5V < V_CC< 5.5V, BST=V_CC,SWN = GND = 0V, UVIN = 3.0V, CV_CC

=

10µF, C_COMP= 0.1µF, CGH = CGL = 3.3nF, C_SS= 50nF, Typical measured at V_CC=5V. The ♦ denotes the specifications

which apply over the full operating temperature range, unless otherwise specified.

PARAMETER

MIN

TYP

MAX UNITS

♦

CONDITIONS

QUIESCENT CURRENT

V_CCSupply Current

1.5

0.2

mA

V_FB=0.9V (No switching)

BST Supply Current

0.4

mA

PROTECTION: UVLO

V_CCUVLO Start Threshold

V_CCUVLO Stop Threshold

V_CCUVLO Hysteresis

UVIN Start Threshold

UVIN Stop Threshold

UVIN Hysteresis

4.00

3.80

4.25

4.05

200

2.5

4.5

4.4

V

♦

mV

V

2.3

2.0

2.65

2.35

♦

2.2

V

300

mV

ERROR AMPLIFIER REFERENCE

Error Amplifier Reference

0.792 0.800

0.788 0.800

0.808

0.812

V

2X Gain Config., Measure COMP/2

Error Amplifier Reference

Over Line and Temperature

♦

Error Amplifier Transconductance

Error Amplifier Gain

6

60

150

50

4

ms

dB

No Load

COMP Sink Current

µA

V_FB= 0.9V, COMP = 0.9V

V_FB= 0.7V, COMP = 2.2V

V_FB= 0.8V

COMP Source Current

V_FBInput Bias Current

Internal Pole

µA

200

nA

MHz

V

COMP Clamp

2.5

-2

V_FB=0.7V, T_A= 25°C

COMP Clamp Temp. Coefficient

mV/°C

CONTROL LOOP: PWM COMPARATOR, RAMP & LOOP DELAY PATH

Ramp Amplitude

RAMP Offset

0.92

1.1

1.28

180

1.5

V

T_A= 25°C, RAMP COMP

until GH starts switching

RAMP Offset Temp. Coefficient

GH Minimum Pulse Width

-2

90

97

mV/°C

ns

♦

Maximum Controllable Duty Ratio

92

%

Maximum Duty Ratio Measured just

before pulse skipping begins

Maximum Duty Ratio

100

1.1

%

Valid for 20 Cycles

Internal Oscillator Frequency

1.3

MHz

♦

Date: 12/20/04

SP6139 Wide Input, 1.3MHz Synchronous PWM Controller

2

ELECTRICAL CHARACTERISTICS

Unless otherwise specified: 0°C < T_AMB< 70°C, 4.5V < V_CC< 5.5V, BST=V_CC,SWN = GND = 0V, UVIN = 3.0V, CV_CC= 10µF,

C

_COMP= 0.1µF, CGH = CGL = 3.3nF, C_SS= 50nF, Typical measured at V_CC=5V. The ♦ denotes the specifications which

apply over the full operating temperature range, unless otherwise specified.

PARAMETER

MIN

TYP

MAX UNITS

♦

CONDITIONS

TIMERS: SOFTSTART

SS Charge Current:

SS Discharge Current:

10

µA

1

mA

♦

Fault Present, SS = 0.2V

PROTECTION: SHORT CIRCUIT & THERMAL

Short Circuit Threshold Voltage

Hiccup Timeout

0.2

0.25

50

0.3

V

Measured V_REF(0.8V) - V_FB

V_FB= 0V

ms

Number of Allowable Clock Cycles

at 100% Duty Cycle

20

Cycles

V_FB= 0.7V

Minimum GL Pulse After 20 Cycles

Thermal Shutdown Temperature

Thermal Recovery Temperature

Thermal Hysteresis

0.5

145

135

10

Cycles

°C

V_FB= 0.7V

°C

OUTPUT: NFET GATE DRIVERS

GH & GL Rise Times

35

30

45

20

50

40

70

30

ns

♦

Measured 10% to 90%

GH & GL Fall Times

Measured 90% to 10%

GL to GH Non Overlap Time

SWN to GL Non Overlap Time

GH & GL Pull Down Resistance

ns

GH & GL Measured at 2.0V

Measured SWN = 100mV to GL = 2.0V

ns

KΩ

PIN DESCRIPTION

PIN # PIN NAME DESCRIPTION

1

2

3

4

V_CC

Bias Supply Input. Connect to external 5V supply. Used to power internal circuits and

low side gate driver.

GL

High current driver output for the low side NFET switch. It is always low if GH is high or

during a fault. Resistor pull down ensure low state at low voltage.

GND

V_FB

Ground Pin. The control circuitry of the IC and lower power driver are referenced to this

pin. Return separately from other ground traces to the (-) terminal of C_OUT

.

Feedback Voltage and Short Circuit Detection pin. It is the inverting input of the Error

Amplifier and serves as the output voltage feedback point for the Buck Converter. The

output voltage is sensed and can be adjusted through an external resistor divider.

Whenever V_FBdrops 0.25V below the positive reference, a short circuit fault is detected

and the IC enters hiccup mode.

5

COMP

Output of the Error Amplifier. It is internally connected to the non-inverting input of the

PWM comparator. An optimal filter combination is chosen and connected to this pin and

either ground or V_FBto stabilize the voltage mode loop.

6

7

UVIN

SS

UVLO input for V_INvoltage. Connect a resistor divider between V_INand UVIN to set

minimum operating voltage.

Soft Start. Connect an external capacitor between SS and GND to set the soft start rate

based on the 10µA source current. The SS pin is held low via a 1mA (min) current during

all fault conditions.

8

9

SWN

GH

Lower supply rail for the GH high-side gate driver. Connect this pin to the switching node

at the junction between the two external power MOSFET transistors.

High current driver output for the high side NFET switch. It is always low if GL is high or

during a fault. Resistor pull down ensure low state at low voltage.

10

BST

High side driver supply pin. Connect BST to the external boost diode and capacitor as

shown in the Typical Application Circuit on page 1. High side driver is connected between

BST pin and SWN pin.

Date: 12/20/04

SP6139 Wide Input, 1.3MHz Synchronous PWM Controller

3

FUNCTIONAL DIAGRAM

5

COMP

100% Protection Logic

CLR

FAULT

PULSES

COUNT 20

V

10

9

BST

CC

CLOCK

CLK

RESET

PWM LOOP

Gm ERROR AMPLIFIER

VFBINT

V

DOMINANT

GH

Gm

FAULT

R

VPOS

SYNCHRONOUS

DRIVER

QPWM

V

FB

8

2

SWN

GL

CC

Q

V

CC

FAULT

S

10 µA

7

1.2 MHZ

CLK

SOFTSTART INPUT

POS REF

SS

RAMP = 1.1V

CLOCK PULSE GENERATOR

FAULT

0.4 V

GL HOLD OFF

SS

0.8V

1.7 V

REFERENCE

CORE

1.7 V

V

1

CC

REF OK

3

GND

ASYNC. STARTUP

COMPARATOR

THERMAL

SHUTDOWN

SET

DOMINANT

145 ˚C ON

135 ˚C OFF

S

HICCUP FAULT

REF OK

Q

SHORT CIRCUIT

DETECTION

+

FAULT

0.25 V

+ -

VPOS

-

R

VFBINT

+

VCC

POWER FAULT

4.25 V ON

4.05 V OFF

VCC UVLO

-

+

-

2.50 VON

2.20 V OFF

VIN UVLO

CLK

6

UVIN

COUNTER

CLR

200ms Delay

REF OK

THERMAL AND SHORT CIRCUIT PROTECTION

UVLO COMPARATORS

THEORY OF OPERATION

General Overview

The SP6139 is a fixed frequency, voltage mode,

synchronousPWMcontrolleroptimizedforhigh

efficiency. The part has been designed to be

especially attractive for split plane applications

utilizing 5V to power the controller and 2.5V to

20V for step down conversion.

The SP6139 contains two unique control fea-

tures that are very powerful in distributed appli-

cations. First, asynchronous driver control is

enabled during start up to prohibit the low side

NFET from pulling down the output until the

high side NFET has attempted to turn on. Sec-

ond, a 100% duty cycle timeout ensures that the

low side NFET is periodically enhanced during

extended periods at 100% duty cycle. This guar-

antees the synchronized refreshing of the BST

capacitor during very large duty ratios.

The heart of the SP6139 is a wide bandwidth

transconductance amplifier designed to accom-

modate Type II and Type III compensation

schemes. A precision 0.8V reference present on

the positive terminal of the error amplifier per-

mits the programming of the output voltage

down to 0.8V via the V_FBpin. The output of the

error amplifier, COMP, compared to a 1.1V

peak-to-peak ramp is responsible for trailing

edgePWMcontrol.ThisvoltagerampandPWM

control logic are governed by the internal oscil-

lator that accurately sets the PWM frequency to

1.3MHz.

The SP6139 also contains a number of valuable

protectionfeatures.Aprogrammableinput(V_IN)

UVLO allows a user to set the exact value at

which the conversion voltage is at a safe point to

begin down conversion, and an internal V_CC

UVLO ensures that the controller itself has

enough voltage to properly operate. Other pro-

Date: 12/20/04

SP6139 Wide Input, 1.3MHz Synchronous PWM Controller

4

THEORY OF OPERATION

Hiccup

tection features include thermal shutdown and

short-circuit detection. In the event that either a

thermal, short-circuit, or UVLO fault is de-

tected, the SP6139 is forced into an idle state

where the output drivers are held off for a finite

period before a re-start is attempted.

Uponthedetectionofapower,thermal,orshort-

circuit fault, the SP6139 is forced into an idle

state for 100mS (typical). The SS and COMP

pins are immediately pulled low, and the gate

drivers are held off for the duration of the

timeout period. Power and thermal faults have

toberemovedbeforearestartmaybeattempted,

whereas,ashort-circuitfaultisinternallycleared

shortly after the fault latch is set. Therefore, a

restartattemptisguaranteedevery100mS(typi-

cal) as long as the short-circuit condition per-

sists.

Under Voltage Lock Out (UVLO)

The SP6139 contains two separate UVLO com-

parators to monitor the bias (V_CC) and conver-

sion (V_IN) voltages independently. The V_CC

UVLO threshold is internally set to 4.25V,

whereas the V_INUVLO threshold is program-

mable through the UVIN pin. When the UVIN

pinisgreaterthan2.5V, theSP6139ispermitted

to start up pending the removal of all other

faults. Both the V_CCand V_INUVLO compara-

tors have been designed with hysteresis to pre-

vent noise from resetting a fault.

Thermal and Short-Circuit

Protection

Because the SP6139 is designed to drive large

NFETs running at high current, there is a chance

that either the controller or power converter will

become too hot. Therefore, an internal thermal

shutdown (145°C) has been included to prevent

the IC from malfunctioning at extreme tempera-

tures.

Soft Start

“Soft Start” is achieved when a power converter

ramps up the output voltage while controlling

the magnitude of the input supply source cur-

rent. In a modern step down converter, ramping

up the positive terminal of the error amplifier

controls soft start. As a result, excess source

current can be defined as the current required to

charge the output capacitor.

A short-circuit detection comparator has also

been included in the SP6139 to protect against

the accidental short or sever build up of current

at the output of the power converter. This com-

parator constantly monitors the positive and

negative terminals of the error amplifier, and if

the V_FBpin ever falls more than 250mV (typi-

cal) below the positive reference, a short-circuit

fault is set. Because the SS pin overrides the

internal 0.8V reference during soft start, the

SP6139 is capable of detecting short-circuit

faults throughout the duration of soft start as

well as in regular operation.

IV_IN= C_OUT* DV_OUT/ DTSoft-start

The SP6139 provides the user with the option to

program the soft start rate by tying a capacitor

from the SS pin to GND. The selection of this

capacitor is based on the 10uA pull up current

present at the SS pin and the 0.8V reference

voltage. Therefore, the excess source can be

redefined as:

Error Amplifier and Voltage Loop

Asstatedbefore, theheartoftheSP6139voltage

error loop is a high performance, wide band-

width transconductance amplifier. Because of

the amplifier’s current limited (+/-150µA)

transconductance, there are many ways to com-

pensate the voltage loop or to control the COMP

pin externally. If a simple, single pole, single

IV_IN= C_OUT* DV_OUT*10µA / (C_SS* 0.8V)

Date: 12/20/04

SP6139 Wide Input, 1.3MHz Synchronous PWM Controller

5

THEORY OF OPERATION

zero response is required, then compensation

can be a simple as an RC to ground. If a more

complex compensation is required, then the

amplifier has enough bandwidth (45° at 4 MHz)

andenoughgain(60dB)torunTypeIIIcompen-

sation schemes with adequate gain and phase

margins at cross over frequencies greater than

50kHz.

GATE DRIVER TEST CONDITIONS

90%

GH(GL)

10%

FALL TIME

2V

90%

RISE TIME

2V

GL(GH)

10%

NON-OVERLAP

The common mode output of the error amplifier

is 0.9V to 2.2V. Therefore, the PWM voltage

ramp has been set between 1.1V and 2.2V to

ensureproper0%to100%dutycyclecapability.

The voltage loop also includes two other very

importantfeatures. Oneisanasynchronousstart

up mode. Basically, the GL driver can not turn

on unless the GH driver has attempted to turn on

or the SS pin has exceeded 1.7V. This feature

prevents the controller from “dragging down”

the output voltage during startup or in fault

modes. The second feature is a 100% duty cycle

timeout that ensures synchronized refreshing of

the BST capacitor at very high duty ratios. In the

event that the GH driver is on for 20 continuous

clock cycles, a reset is given to the PWM flip

flop half way through the 21st cycle. This forces

GL to rise for the remainder of the cycle, in turn

refreshing the BST capacitor.

V(BST)

GH

Voltage

V(SWN)

V(VCC)

GL

Voltage

0V

V(VIN)

SWN

Voltage

-0V

-V(Diode) V

V(VIN)+V(VCC)

BST

Voltage

V(VCC)

TIME

Gate Drivers

The SP6139 contains a pair of powerful 2Ω

SOURCE and 1.5Ω SINK drivers. These state

of the art drivers are designed to drive external

NFETs capable of handling up to 30A. Rise,

fall,andnon-overlaptimeshaveallbeenminized

to achieve maximum efficiency. All drive pins

GH, GL & SWN are monitored continuously to

ensure that only one external NFET is ever on at

any given time.

Date: 12/20/04

SP6139 Wide Input, 1.3MHz Synchronous PWM Controller

6

APPLICATIONS INFORMATION

Inductor Selection

I_PP

I_PEAK= I_{OUT (max)}

+

2

There are many factors to consider in selecting

the inductor including cost, efficiency, size and

EMI. In a typical SP6139 circuit, the inductor is

chosen primarily for value, saturation current

andDCresistance.Increasingtheinductorvalue

will decrease output voltage ripple, but degrade

transientresponse. Lowinductorvaluesprovide

the smallest size, but cause large ripple currents,

poor efficiency and more output capacitance to

smooth out the larger ripple current. The induc-

tor must also be able to handle the peak current

at the switching frequency without saturating,

and the copper resistance in the winding should

be kept as low as possible to minimize resistive

power loss. A good compromise between size,

loss and cost is to set the inductor ripple current

tobewithin20%to40%ofthemaximumoutput

current.

and provide low core loss at the high switching

frequency. Low cost powdered iron cores have

a gradual saturation characteristic but can intro-

duce considerable ac core loss, especially when

the inductor value is relatively low and the

ripple current is high. Ferrite materials, on the

other hand, are more expensive and have an

abrupt saturation characteristic with the induc-

tance dropping sharply when the peak design

current is exceeded. Nevertheless, they are pre-

ferred at high switching frequencies because

they present very low core loss and the design

only needs to prevent saturation. In general,

ferrite or molypermalloy materials are better

choice for all but the most cost sensitive appli-

cations.

The switching frequency and the inductor oper-

ating point determine the inductor value as fol-

lows:

The power dissipated in the inductor is equal to

the sum of the core and copper losses. To mini-

mizecopperlosses,thewindingresistanceneeds

to be minimized, but this usually comes at the

expense of a larger inductor. Core losses have a

more significant contribution at low output cur-

rent where the copper losses are at a minimum,

and can typically be neglected at higher output

currentswherethecopperlossesdominate.Core

loss information is usually available from the

magnetic vendor.

V_OUT(V_{IN (max)}−V_OUT

)

L =

V_{IN (max)}F_SK_rI_{OUT (max)}

where:

Fs = switching frequency

Kr = ratio of the ac inductor ripple current to the

maximum output current

The peak to peak inductor ripple current is:

Thecopperlossintheinductorcanbecalculated

using the following equation:

P_L(Cu)= I_L²_(RMS)R_WINDING

V_OUT(V_{IN (max)}−V_OUT

)

I_PP

=

V_IN(max)F_SL

where I_L(RMS)is the RMS inductor current that

can be calculated as follows:

2

1

3

I_PP

I_OUT(max)

I_L(RMS)= I_OUT(max)1 +

Once the required inductor value is selected, the

proper selection of core material is based on

peak inductor current and efficiency require-

ments. The core must be large enough not to

saturate at the peak inductor current

(

)

Date: 12/20/04

SP6139 Wide Input, 1.3MHz Synchronous PWM Controller

7

APPLICATIONS INFORMATION

F_S= Switching Frequency

D = Duty Cycle

_OUT= Output Capacitance Value

Output Capacitor Selection

The required ESR (Equivalent Series Resis-

tance) and capacitance drive the selection of the

type and quantity of the output capacitors. The

ESR must be small enough that both the resis-

tive voltage deviation due to a step change in the

load current and the output ripple voltage do not

exceed the tolerance limits expected on the

output voltage. During an output load transient,

the output capacitor must supply all the addi-

tional current demanded by the load until the

SP6139CU adjusts the inductor current to the

new value.

C

Input Capacitor Selection

The input capacitor should be selected for ripple

current rating, capacitance and voltage rating.

The input capacitor must meet the ripple current

requirement imposed by the switching current.

In continuous conduction mode, the source cur-

rent of the high-side MOSFET is approximately

a square wave of duty cycle V_OUT/V_IN. Most of

this current is supplied by the input bypass

capacitors. The RMS value of input capacitor

current is determined at the maximum output

current and under the assumption that the peak

Therefore the capacitance must be large enough

so that the output voltage is help up while the

inductor current ramps up or down to the value

corresponding to the new load current. Addi-

tionally, the ESR in the output capacitor causes

a step in the output voltage equal to the current.

Because of the fast transient response and inher-

ent100%and0%dutycyclecapabilityprovided

by the SP6139CU when exposed to output load

transient, the output capacitor is typically cho-

sen for ESR, not for capacitance value.

to peak inductor ripple current is low, it is given

by:

I_CIN(rms)= I

_OUT(max)√D(1 - D)

The worse case occurs when the duty cycle D is

50% and gives an RMS current value equal to

I

_OUT/2.

Select input capacitors with adequate ripple

current rating to ensure reliable operation.

The output capacitor’s ESR, combined with the

inductor ripple current, is typically the main

contributor to output voltage ripple. The maxi-

mum allowable ESR required to maintain a

specifiedoutputvoltageripplecanbecalculated

by:

The power dissipated in the input capacitor is:

P

= I_C²_{IN (rms)}R_ESR(CIN)

CIN

RESR ≤ ∆V_OUT

I_PK-PK

This can become a significant part of power

losses in a converter and hurt the overall energy

transfer efficiency. The input voltage ripple

primarily depends on the input capacitor ESR

and capacitance. Ignoring the inductor ripple

current, the input voltage ripple can be deter-

mined by:

where:

∆V_OUT= Peak to Peak Output Voltage Ripple

I_PK-PK= Peak to Peak Inductor Ripple Current

The total output ripple is a combination of the

ESR and the output capacitance value and can

be calculated as follows:

I

_{OUT (MAX )}V_OUT(V_IN−V_OUT)

∆V_IN= I_out(max)R_{ESR(CIN )}

+

2

F_SC_INV_IN

²+ (I_PPR_ESR

)

I_PP(1 – D)

2

∆V_OUT

=

C_OUTF_S

(

)

Date: 12/20/04

where:

SP6139 Wide Input, 1.3MHz Synchronous PWM Controller

8

APPLICATIONS INFORMATION

The capacitor type suitable for the output capac-

itors can also be used for the input capacitors.

The total power losses of the top MOSFET are the

sum of switching and conduction losses. For syn-

chronous buck converters of efficiency over 90%,

allow no more than 4% power losses for high or

low side MOSFETs. For input voltages of 3.3V

and 5V, conduction losses often dominate switch-

ing losses. Therefore, lowering the R_DS(ON)of the

MOSFETs always improves efficiency even

though it gives rise to higher switching losses due

to increased C_rss.

However, exercise extra caution when tantalum

capacitorsareconsidered.Tantalumcapacitorsare

known for catastrophic failure when exposed to

surge current, and input capacitors are prone to

such surge current when power supplies are con-

nected “live” to low impedance power sources.

MOSFET Selection

The losses associated with MOSFETs can be

divided into conduction and switching losses.

Conduction losses are related to the on resistance

of MOSFETs, and increase with the load current.

Switching losses occur on each on/off transition

when the MOSFETs experience both high current

and voltage. Since the bottom MOSFET switches

current from/to a paralleled diode (either its own

bodydiodeoraSchottkydiode),thevoltageacross

theMOSFETisnomorethan1Vduringswitching

transition. As a result, its switching losses are

negligible. The switching losses are difficult to

quantify due to all the variables affecting turn on/

off time. However, the following equation pro-

vides an approximation on the switching losses

associatedwiththetopMOSFETdrivenbySP6139.

Top and bottom MOSFETs experience unequal

conduction losses if their on time is unequal. For

applicationsrunningatlargeorsmalldutycycle, it

makes sense to use different top and bottom

MOSFETs. Alternatively, parallel multiple

MOSFETs to conduct large duty factor.

R_DS(ON)variesgreatlywiththegatedrivervoltage.

The MOSFET vendors often specify R_DS(ON)on

multiple gate to source voltages (V_GS), as well as

provide typical curve of R_DS(ON)versus V_GS. For

5Vinput,usetheR_DS(ON)specifiedat4.5VV_GS.At

the time of this publication, vendors, such as

Fairchild, Siliconix and International Rectifier,

havestartedtospecifyR_DS(ON)atV_GSlessthan3V.

This has provided necessary data for designs in

which these MOSFETs are driven with 3.3V and

made it possible to use SP6139 in 3.3V only

applications.

P_{SH (max)}=12C_rssV_{IN (max)}I_{OUT (max)}F_S

where

C_rss= reverse transfer capacitance of the top

MOSFET

Thermal calculation must be conducted to ensure

the MOSFET can handle the maximum load cur-

rent. The junction temperature of the MOSFET,

determined as follows, must stay below the maxi-

mum rating.

Switching losses need to be taken into account for

high switching frequency, since they are directly

proportional to switching frequency. The conduc-

tion losses associated with top and bottom

MOSFETs are determined by:

P_{MOSFET (max)}

T_J(max)=T_A(max)

+

_{CH (max)}= R_{DS (ON )}I_{OUT (max)}²D

R_θ

P

JA

where

P

= R_{DS(ON )}I_{OUT (max)}²(1− D)

CL(max)

T_A(max)= maximum ambient temperature

PMOSFET(max) = maximum power dissipa-

tion of the MOSFET

where

P_CH(max)= conduction losses of the high side

MOSFET

R

_ΘJA= junction to ambient thermal resistance.

P_CL(max)= conduction losses of the low side

R

_ΘJAof the device depends greatly on the board

MOSFET

layout, as well as device package. Significant

R_DS(ON)= drain to source on resistance.

Date: 12/20/04

SP6139 Wide Input, 1.3MHz Synchronous PWM Controller

9

APPLICATIONS INFORMATION

diode is equal to input voltage, and the diode

must be able to handle the peak current equal to

the maximum load current.

thermalimprovementcanbeachievedinthemaxi-

mum power dissipation through the proper design

of copper mounting pads on the circuit board. For

example, in a SO-8 package, placing two 0.04

square inches copper pad directly under the pack-

age, without occupying additional board space,

can increase the maximum power from approxi-

mately 1 to 1.2W. For DPAK package, enlarging

thetapmountingpadto1squareinchesreducesthe

R_ΘJA from 96°C/W to 40°C/W.

The power dissipation of the Schottky diode is

determined by

P

_DIODE= 2V_FI_OUTT_NOLF_S

where

Schottky Diode Selection

T_NOL= non-overlap time between GH and GL.

V_F= forward voltage of the Schottky diode.

When paralleled with the bottom MOSFET, an

optional Schottky diode can improve efficiency

and reduce noises. Without this Schottky diode,

the body diode of the bottom MOSFET con-

ducts the current during the non-overlap time

when both MOSFETs are turned off. Unfortu-

nately, the body diode has high forward voltage

and reverse recovery problem. The reverse re-

covery of the body diode causes additional

switching noises when the diode turns off. The

Schottky diode alleviates these noises and addi-

tionally improves efficiency thanks to its low

forward voltage. The reverse voltage across the

Loop Compensation Design

The open loop gain of the whole system can be

divided into the gain of the error amplifier,

PWM modulator, buck converter output stage,

and feedback resistor divider. In order to cross-

over at the selected frequency FCO, the gain of

the error amplifier has to compensate for the

attenuation caused by the rest of the loop at this

frequency.

Type III Voltage Loop

Compensation

G_AMP(s) Gain Block

PWM Stage

G_PWMGain

Block

Output Stage

G_OUT(s) Gain

Block

V_IN

(SRz2Cz2+1)(SR1Cz3+1)

(SR_ESRC_OUT+ 1)

+

_

V_REF

(Volts)

V_OUT

(Volts)

V_{RAMP_PP}

SR1Cz2(SRz3Cz3+1)(SRz2Cp1+1)

[S^2LC_OUT+S(R_ESR+R_DC) C_OUT+1]

Notes: R_ESR= Output Capacitor Equivalent Series Resistance.

R_DC= Output Inductor DC Resistance.

V_{RAMP_PP}= SP6132 Internal RAMP Amplitude Peak to Peak Voltage.

Condition: Cz2 >> Cp1 & R1 >> Rz3

Output Load Resistance >> R_ESR& R_DC

Voltage Feedback

G_FBKGain Block

R₂

(R₁R₂)

V_REF

V_OUT

or

+

V_FBK

(Volts)

SP6134 Voltage Mode Control Loop with Loop Dynamic

Date: 12/20/04

SP6139 Wide Input, 1.3MHz Synchronous PWM Controller

10

APPLICATIONS INFORMATION

The goal of loop compensation is to manipulate

loopfrequencyresponsesuchthatitsgaincrosses

When the output capacitors are of a Ceramic

Type,theSP6139CUEvaluationBoardrequires

a Type III compensation circuit to give a phase

boostof180°inordertocounteracttheeffectsof

an under damped resonance of the output filter

at the double pole frequency.

over 0db at a slope of -20db/dec. The first step

of compensation design is to pick the loop

crossover frequency. High crossover frequency

is desirable for fast transient response, but often

jeopardizes the system stability. Crossover fre-

quency should be higher than the ESR zero but

less than 1/5 of the switching frequency. The

ESR zero is contributed by the ESR associated

with the output capacitors and can be deter-

mined by:

Gain

(dB)

Error Amplify Gain

Bandwidth Product

Condition:

C22 >> CP1, R1 >> RZ3

1

20 Log (RZ2/R1)

ƒ_Z(ESR)

=

2π C_OUTR_ESR

Frequency

(Hz)

The next step is to calculated the complex con-

jugate poles contributed by the LC output filter,

Bode Plot of Type III Error Amplify Compensation.

1

ƒ_P(LC)

=

2π L C_OUT

INDUCTORS - SURFACE MOUNT

Inductor Specification

Inductance

(uH)

Manufacturer/Part No.

Series R

mΩ

I_SAT

(a)

Size

LxW(mm)

Inductor Type

Manufaturer

Website

Ht.(mm)

2.7

3.3

Easy Magnet SC5018-2R7M

TDK RLF 12560T-2R7N110

Coilcraft DO5010P-332HC

4.30

4.50

8.60

12.0

12.2

17.0

12.6x12.6

12.5x12.8

14.7x15.2

4.5

6.0

8.0

Shielded Ferrite Core

Unshielded Ferrite Core

inter-technical.com

tdk.com

coilcraft.com

1.2

1.5

1.9

Easy Magnet SC5018-1R2M

Inter-Technical SC4015-1R2M

Coilcraft DO5010P-152HC

TDK RLF 12560T-1R9N120

1.96

4.37

4.00

3.60

20.0

17.0

25.0

13.2

12.6x12.6

10.0x10.0

14.7x15.2

12.5x12.8

4.5

3.8

8.0

6.0

Shielded Ferrite Core

Unshielded Ferrite Core

Shielded Ferrite Core

inter-technical.com

coilcraft.com

tdk.com

CAPACITORS -SURFACE MOUNT

Capacitance

(uF)

Manufacturer/Part No.

ESR

Ω (max)

Ripple Current

(A)@45°C

Size

Voltage

(V)

Capacitor

Type

Manufaturer

Website

LxW(mm) Ht.(mm)

22

47

TDK C3225X5R1C226M

TDK C3225X5ROJ476M

0.002

4.00

3.2x2.5

2.0

2.5

16.0

6.3

X5R Ceramic

tdk.com

0.002

MOSFET - Surface Mount

MOSFET

Manufacturer/Part No.

RDS (on)

Ω (max)

ID Current

(A)

Qg

nC(Typ)

Qg

nC(Max)

Voltage Foot Print

(V)

Manufaturer

Website

N-Channel

Fairchild Semi FDS6676S

Fairchild Semi FD7088N3

Vishay Si4336DY

0.006

0.005

0.004

14.50

21.10

25.0

43

37

32

60.0

30.0

SO-8

fairchildsemi.com

vishay.com

48.0

50.0

Note: Components highlighted in Bold are those used on the SP6134 Evaluation Board.

Table 1. Input and Output Stage Components Selection Charts.

Date: 12/20/04

SP6139 Wide Input, 1.3MHz Synchronous PWM Controller

11

PACKAGE: 10 PIN MSOP

D

e1

Ø1

R1

R

E/2

Gauge Plane

L2

E

E1

Ø

Ø1

Seating Plane

L

L1

1

2

e

Pin #1 indentifier must be indicated within this shaded area (D/2 * E1/2)

B

10 Pin MSOP JEDEC MO-187 (BA) Variation

MIN

NOM

MAX

SYMBOL

A

A1

A2

b

-

0

0.75

0.17

0.08

-

1.1

0.15

0.95

0.27

0.23

0.85

-

c

D

3.00 BSC

A2

A

E

4.90 BSC

E1

e

3.00 BSC

0.50 BSC

b

A1

e1

L

2.00 BSC

0.4

0.6

0.8

L1

L2

N

R

R1

ø

0.95 REF

0.25 BSC

b

-

10

-

8º

15º

WITH PLATING

0.07

0º

ø1

0º

c

Note: Dimensions in (mm)

BASE METAL

Section B-B

1

Date: 12/20/04

SP6139 Wide Input, 1.3MHz Synchronous PWM Controller

12

ORDERING INFORMATION

Package

Part Number

Temperature

Topmark

SP6139EU........................-40°C to +85°C...................SP6139EU ........................... 10 Pin MSOP

SP6139EU/TR..................-40°C to +85°C...................SP6139EU ........................... 10 Pin MSOP

Available in lead free packaging. To order add "-L" suffix to part number.

Example: SP6139EU/TR = standard; SP6139EU-L/TR = lead free

/TR = Tape and Reel

Pack quantity is 2,500 for MSOP.

CLICK HERE TO ORDER SAMPLES

Corporation

ANALOGEXCELLENCE

Sipex Corporation

Headquarters and

Sales Office

233 South Hillview Drive

Milpitas, CA 95035

TEL: (408) 934-7500

FAX: (408) 935-7600

Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the

application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.

Date: 12/20/04

SP6139 Wide Input, 1.3MHz Synchronous PWM Controller

13


型号：	SP6139EU-L
厂家：	SIPEX CORPORATION
描述：	Wide Input, 1.3MHz Synchronous PWM Controller 宽输入， 1.3MHz同步PWM控制器稳压器开关式稳压器或控制器电源电路开关式控制器光电二极管
文件：	总13页 (文件大小：147K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SP6139EU-L [SIPEX]

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SP6139EU-L/TR

SP6139EU-L/TR

SP6139EU/TR

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SP6140E3

SP6141

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