SP6205ER-2-8-L [SIPEX]
Regulator,;型号: | SP6205ER-2-8-L |
厂家: | SIPEX CORPORATION |
描述: | Regulator, 稳压器 调节器 光电二极管 输出元件 |
文件: | 总16页 (文件大小:711K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Solved by
SP6203/6205
TM
Low Noise, 300mA and 500mA CMOS LDO Regulators
FEATURES
FꢀXED
ADJUSTABLE
■ Very Low Dropout Voltage: 0.61 PMOS Pass
ꢃ
VOUT
ꢃ
ꢀ
ꢀ
2
VOUT
V
OUT
Device
ADJ
NC
SP6203
SP6205
SP6203
SP6205
■ Accurate Output Voltage: 2% over Temperature
■ Guaranteed 500mA Output Current: SP6205
■ Ultra Low Noise Output: ꢀ2µVRMS with ꢀ0nF
Bypass
BYP
7
6
5
2
3
ꢂ
NC
NC
NC
NC
7
6
5
GND
GND
EN
3
ꢂ
8 Pin DFN
8 Pin DFN
VIN
EN
V
IN
■ Unconditionally Stable with 2.2µF Ceramic
■ Low Quiescent Current: ꢂ5µA
■ Very Low Ground Current: 350µA at 500 mA
■ Power-Saving Shutdown Mode: < ꢀµA
■ Fast Turn-On and Turn-Off: 60µS
■ Fast Transient Response
NowAvailableinLeadFreePackaging
APPLꢀCATꢀONS
■ Current Limit and Thermal Shutdown Protection
■ Very Good Load/Line Regulation: 0.07/0.0ꢂ%
■ Excellent PSRR: 67dB < ꢀkHz
■ Industry Standard SOT-23-5 and Small ꢃ pin
2X3 DFN Package
■ Fixed Output Voltages: 2.5V, 2.7V, 2.ꢃV,
■ Cellular / GSM Phones
■ Laptop / Palmtop Computers
■ Battery-Powered Systems
■ Pagers
■ Medical Devices
■ MP3/CD Players
2.ꢃ5V, 3.0V and 3.3V
■ Adjustable Output Available
■ Digital Still Cameras
DESCRꢀPTꢀON
The SP6203/6205 are ultra low noise CMOS LDOs with very low dropout and ground current. The noise
performance is achieved by means of an external bypass capacitor without sacrificing turn-on and turn-off
speedcriticaltoportableapplications.Extremelystableandeasytouse,thesedevicesofferexcellentPSRR
and Line/Load regulation. Target applications include battery-powered equipment such as portable and
wirelessproducts.Regulators'groundcurrentincreasesonlyslightlyindropout.Fastturn-on/turn-offenable
control and an internal 301 pull down on output allows quick discharge of output even under no load
conditions. Both LDOs are protected with current limit and thermal shutdown.
Both LDOs are available in fixed & adjustable output voltage versions and come in an industry standard
SOT-23 5-pin and small 2X3 ꢃpin DFN packages. For SC-70 ꢀ00mA CMOS LDO, SP62ꢀ3 is available.
TYPꢀCAL APPLꢀCATꢀON CꢀRCUꢀT
V
V
IN
IN
V
V
OUT
OUT
1
2
3
5
4
1
2
3
5
4
C
C
2.2µF
IN
IN
C
OUT
2.2µF Ceramic
C
OUT
2.2µF Ceramic
2.2µF
SP6203
SP6205
SP6203
SP6205
5-Pin
ADJUSTABLE
5-Pin
FIXED
ADJ
EN
EN
BYP
Date: Apr2-07
SP6203/SP6205 Low Noise, 300 and 500mA CMOS LDO Regulators
© 2007 Sipex Corporation
ꢀ
OPERATꢀNG RATꢀNGS
ABSOLUTE MAXꢀMUM RATꢀNGS
Input Voltage (VIN)...........................................+2.7V to +5.5V
Enable Input Voltage (VEN)...........................................0 to 5.5V
Junction Temperature (TJ)...........................................-ꢂ0°C to +ꢀ25°C
Thermal Resistance, SOT-23-5 (eJA)...........................................Note ꢀ
Thermal Resistance, SOT-23-6 (eJA)...........................................Note ꢀ
Supply Input Voltage (VIN)..........................................................-2V to 6V
Output Voltage (VOUT).....................................................-0.6V to VIN +ꢀV
Enable Input Voltage (VEN)........................................................-2V to 6V
Power Dissipation (PD)......................................Internally Limited, Note ꢀ
Lead Temperature (soldering 5s)...........................................+260°C
Storage Temperature.....................................................-65°C to +ꢀ50°C
Junction Temperature..........................................................+ꢀ50°C
Remark: The device is not guaranteed to function outside its operating rating.
Thesearestressratingsonlyandfunctionaloperationofthedeviceatthese
ratings or any other above those indicated in the operation sections of the
specifications below is not implied. Exposure to absolute maximum rating
conditions for extended periods of time may affect reliability.
ELECTRꢀCAL SPECꢀFꢀCATꢀONS
Unless otherwise specified: VIN=VOUT + 0.5V to 6V, COUT = 2.2µF ceramic, CIN = 2.2µF, IOUT =ꢀ00µA,
-ꢂ0°C < T < ꢀ25°C. The z denotes the specifications which apply over full operating temperature range -ꢂ0°C to
+ꢀ25°C, unless otherwise specified.
PARAMETER
MꢀN
TYP
MAX
6
UNꢀTS
V
z
z
CONDꢀTꢀONS
Input Voltage
Output Voltage Accuracy
-2
+2
%
z
Variation from specified VOUT
Output Voltage
50
ppm/°C
6VOUT/6T
Temperature Coefficient, Note2
Reference Voltage
Line Regulation
ꢀ.225
ꢀ.25
0.0ꢂ
ꢀ.275
0.3
V
%/V
%
z
Adjustable version only
6VOUT (VIN below 6V)
Load Regulation, Note 3
0.07
0.ꢀ3
0.3
0.5
IOUT = 0.ꢀmA to 300mA (SP6203)
IOUT = 0.ꢀmA to 500mA (SP6205)
Dropout Voltage for VOUT > 3.0V,
Note ꢂ
0.06
60
IOUT = 0.ꢀmA
IOUT = ꢀ00mA
ꢀ20
ꢀꢃ0
300
mV
IOUT = 200mA
IOUT = 300mA (SP6203)
IOUT = 500mA (SP6205)
300
500
z
z
Ground Pin Current, Note 5
ꢂ5
ꢀ00
z
IOUT = 0.ꢀmA (IQUIESCENT
)
ꢀꢀ0
ꢀ75
235
350
IOUT = ꢀ00mA
IOUT = 200mA
IOUT = 300mA (SP6203)
IOUT = 500mA (SP6205)
µA
330
ꢂꢁ0
z
z
Shutdown Supply Current
Current Limit
0.0ꢀ
ꢀ
µA
z
VEN < 0.ꢂV (shutdown)
0.33
0.55
0.50
0.ꢃ5
0.ꢃ
ꢀ.ꢂ
A
VOUT = ZeroV (SP6203)
VOUT = ZeroV (SP6205)
Thermal Shutdown Junction
Temperature
ꢀ70
°C
Regulator Turns off
Thermal Shutdown Hysteresis
Power Supply Rejection Ratio
Output Noise Voltage, Note 6
ꢀ2
67
°C
Regulator turns on again at ꢀ5ꢃ°C
f ) ꢀkHz
dB
ꢀ50
630
ꢀ2
CBYP = 0nF, IOUT = 0.ꢀmA
CBYP = 0nF, IOUT =300mA
CBYP = ꢀ0nF, IOUT = 0.ꢀmA
CBYP = ꢀ0nF, IOUT = 300mA
µVRMS
50
75
Thermal Regulation, Note 7
0.05
25
%/W
6VOUT/6PD
Wake-Up Time (TWU), Note ꢃ
(from shutdown mode)
50
µs
V
IN * ꢂV, Note ꢀ0
IOUT = 30mA
VIN * ꢂV, Note ꢀ0
Turn-On Time (TON), Note ꢁ
(from shutdown mode)
60
ꢀ20
µs
µs
IOUT = 30mA
Turn-Off Time (TOFF),
ꢀ00
ꢀ5
250
25
IOUT = 0.ꢀmA, VIN * ꢂV, Note ꢀ0
IOUT = 300mA, VIN * ꢂV, Note ꢀ0
Output Discharge Resistance
Enable Input Logic Low Voltage
Enable Input Logic High Voltage
30
1
V
No Load
0.ꢂ
z
z
Regulator Shutdown
Regulator Enabled
ꢀ.6
V
Date: Apr2-07
SP6203/SP6205 Low Noise, 300 and 500mA CMOS LDO Regulators
© 2007 Sipex Corporation
2
ELECTRꢀCAL SPECꢀFꢀCATꢀONS NOTES
Note 1: Maximum power dissipation can be calculated using the formula: PD = (TJ(max) - TA) / eJA, where TJ(max) is
the junction temperature, TA is the ambient temperature and eJA is the junction-to-ambient thermal resistance. eJC
is 6°C/W for this package. Exceeding the maximum allowable power dissipation will result in excessive die
temperature and the regulator will go into thermal shutdown mode. eJA is 191°C/W for SOT-23-5, and is 59°C/W
for the ꢃ-pin DFN. A part mounted on a PC board will deliver improved thermal performance based upon copper
surface area.
Note 2: Output voltage temperature coefficient is defined as the worst case voltage change divided by the total
temperature range.
Note 3: Regulation is measured at constant junction temperature using low duty cycle pulse testing. Changes in
output voltage due to heating effects are covered by the thermal regulation specification.
Note 4: Dropout-voltage is defined as the input to output differential at which the output voltage drops 2% below its
nominal value measured at ꢀV differential.
Note 5: Ground pin current is the regulator quiescent current. The total current drawn from the supply is the sum of
the load current plus the ground pin current.
Note 6: Output noise voltage is defined within a certain bandwidth, namely ꢀ0Hz < BW < ꢀ00kHz. An external
bypass cap (ꢀ0nF) from reference output (BYP pin) to ground significantly reduces noise at output.
Note 7: Thermal regulation is defined as the change in output voltage at a time “t” after a change in power
dissipation is applied, excluding load and line regulation effects. Specifications are for a 300mA load pulse at VIN
6V for t = ꢀms.
=
Note 8: The wake-up time (TWU) is defined as the time it takes for the output to start rising after enable is brought
high.
Note 9: The total turn-on time is called the settling time (TS), which is defined as the condition when both the
output and the bypass node are within 2% of their fully enabled values when released from shutdown.
Note 10: For output voltage versions requiring VIN to be lower than ꢂV, timing (TON & TOFF) increases slightly.
FUNCTIONAL DIAGRAM
VOUT
V
IN
VIN
EN
VOUT
EN
1.25V
bandgap
reference
1.25V
bandgap
reference
R1
BYP
ADJ
R2
current limit
current limit
Cbyp
(optional)
&
&
thermal shutdown
thermal shutdown
GND
GND
Low Noise Fixed Regulator - 5 Pin
Low Noise Adjustable Regulator - 5 Pin
Date: Apr2-07
SP6203/SP6205 Low Noise, 300 and 500mA CMOS LDO Regulators
© 2007 Sipex Corporation
3
PꢀN DESCRꢀPTꢀON
5 PꢀN OPTꢀON
PIN NUMBER
NAME
VIN
FUNCTION
ꢀ
2
3
Power Supply Input
Ground Terminal
GND
EN
Enable/Shutdown (Logic high = enable, logic
low = shutdown)
ꢂ (Fixed)
ꢂ (adj.)
5
BYP
ADJ
VOUT
Reference bypass input for ultra-quiet operation.
Connecting a ꢀ0nF cap on this pin reduces
output noise.
Adjustable (Input): Adjustable regulator feed-
back input. Connect to a resistive voltage-
divider network.
Regulator Output Voltage
PꢀNOUT 5 PꢀN SOT-23
V
EN GND
IN
V
GND
2
EN
IN
3
2
1
1
3
SIPEX
SIPEX
4
4
5
5
V
OUT
V
ADJ
BYP
OUT
Fixed Voltage Regulator
Adjustable Voltage Regulator
Date: Apr2-07
SP6203/SP6205 Low Noise, 300 and 500mA CMOS LDO Regulators
© 2007 Sipex Corporation
ꢂ
PꢀN DESCRꢀPTꢀON
8 PꢀN OPTꢀON
ꢃ PIN DFN
PIN CONFIGURATION
PIN NUMBER
ꢀ(fixed)
NAME
FUNCTION
VOUT
Regulator Output Voltage. Connect to Pin ꢃ
VOUT.
ꢀ(Adj)
ADJ
Adjustable (Input): Adjustable regulator feed-
back input. Connect to a resistive voltage-
divider network.
2(fixed)
BYP
Reference bypass input for ultra-quiet operation.
Connecting a ꢀ0nF cap on this pin reduces
output noise.
2(Adj)
NC
GND
EN
No Connect
Ground
3
ꢂ
Enable/Shutdown (Logic high = enable, logic
low = shutdown)
5
6
7
ꢃ
VIN
NC
Power Supply Input
No Connect
NC
No Connect
VOUT
Regulator Output VoltageA
PꢀNOUT 8 PꢀN DFN
FꢀXED
ADJUSTABLE
VOUT
ꢃ
ꢃ
ꢀ
ꢀ
2
VOUT
V
ADJ
NC
OUT
SP6203
SP6205
SP6203
SP6205
BYP
7
6
5
2
3
ꢂ
NC
NC
7
6
5
NC
NC
GND
3
ꢂ
GND
EN
8 Pin DFN
8 Pin DFN
VIN
EN
V
IN
Date: Apr2-07
SP6203/SP6205 Low Noise, 300 and 500mA CMOS LDO Regulators
© 2007 Sipex Corporation
5
TYPꢀCAL PERFORMANCE CHARACTERꢀSTꢀCS
V
OUT
V
OUT
I
(200mA/DIV)
O
V
EN
Current Limit
Turn on Time, RLOAD = 501 (60mA)
V
OUT
V
OUT
V
EN
V
EN
Turn off Time, RLOAD = 30K (0.1mA)
Turn off Time, RLOAD = 61 (500mA)
VOUT (AC)
VOUT (AC)
VꢀN
ꢀOUT
Load Regulation, IO = 100µA ~ 500mA
Line Regulation, Line Step from 4V to 6V, IO = 1mA
Date: Apr2-07
SP6203/SP6205 Low Noise, 300 and 500mA CMOS LDO Regulators
© 2007 Sipex Corporation
6
TYPꢀCAL PERFORMANCE CHARACTERꢀSTꢀCS: Continued
V
IN
V
EN
V
OUT
V
OUT
V
= 3.5V, I = 500mA
O
IN
BYP
Start Up Waveform, VIN = 3.5V, IO = 500mA
Start Up Waveform, Slow VIN , No Load
V
IN
V
IN
V
OUT
V
OUT
BYP
BYP
Start Up Waveform, Slow VIN , 500mA Output Load
Start Up Waveform, Slow VIN , COUT=1000µF, IO=0mA
V
IN
V
IN
V
OUT
V
OUT
BYP
BYP
Start Up Waveform, Slow VIN, COUT=1000µF, IO=500mA
Fast VIN , No Load
Date: Apr2-07
SP6203/SP6205 Low Noise, 300 and 500mA CMOS LDO Regulators
© 2007 Sipex Corporation
7
TYPꢀCAL PERFORMANCE CHARACTERꢀSTꢀCS: Continued
V
IN
V
OUT
BYP
Fast VIN , 500mA Output Load
Fast VIN = 1000µF Output Load
V
IN
V
OUT
BYP
Fast VIN , COUT=1000µF, IO=500mA
Output Noise (uVrms), Cbyp = 10nF
Output Noise (uVrms), Cbyp = open
ꢀ000
ꢃ00
600
ꢂ00
200
0
50
ꢂ0
30
20
ꢀ0
0
0.ꢀ
ꢀ
ꢀ0
ꢀ00
ꢀ000
0.ꢀ
ꢀ
ꢀ0
ꢀ00
ꢀ000
Output current (mA)
Output current (mA)
Date: Apr2-07
SP6203/SP6205 Low Noise, 300 and 500mA CMOS LDO Regulators
© 2007 Sipex Corporation
ꢃ
THEORY OF OPERATꢀON
General Overview
Output Capacitor
The SP6203/6205 is intended for applications
where very low dropout voltage, low supply
current and low output noise are critical, even
with high load conditions (500mA maximum).
An output capacitor is required between VOUT
and GND to prevent oscillation. A 2.2µF output
capacitor is recommended.
Larger values make the chip more stable which
means an improvement of the regulator’s tran-
sient response. Also, when operating from other
sources than batteries, supply-noise rejection
can be improved by increasing the value of the
input and output capacitors and using passive
filtering techniques.
Unlike bipolar regulators, the SP6203/6205
(CMOS LDO) supply current increases only
slightly with load current.
The SP6203/6205 contains an internal bandgap
reference which is fed into the inverting input of
the LDO-amplifier. The output voltage is then
set by means of a resistor divider and compared
to the bandgap reference voltage. The error
LDO-amplifier drives the gate of a P-channel
MOSFET pass device that has a RDS(ON) of 0.61
at 500mA producing a 300mV drop at the out-
put.
For a lower output current, a smaller output
capacitance can be chosen.
Finally, the output capacitor should have an
effectiveseriesresistance(ESR)of0.51orless.
Therefore, the use of good quality ceramic or
tantalum capacitors is advised.
Furthermore, the SP6203/6205 has its own cur-
rent limit circuitry (500mA/850mA) to ensure
that the output current will not damage the
device during output short, overload or start-up.
Bypass Capacitor
A bypass pin (BYP) is provided to decouple the
bandgap reference. A 10nF external capacitor
connected from BYP to GND reduces noise
present on the internal reference, which in turn
significantly reduces output noise and also im-
proves power supply rejection. Note that the
minimum value of COUT must be increased to
maintain stability when the bypass capacitor is
used because CBYP reduces the regulator phase
margin. If output noise is not a concern, this
input may be left unconnected. Larger capacitor
values may be used to further improve power
supply rejection, but result in a longer time
period (slower turn on) to settle output voltage
when power is initially applied.
Also, the SP6203/6205 includes thermal shut-
down circuitry to turn off the device when the
junction temperature exceeds 170°C and it re-
mains off until the temperature drops by 12°C.
Enable/Shutdown Operation
The SP6203/6205 is turned off by pulling the
VEN pin below 0.4V and turned on by pulling it
above 1.6V.
If this enable/shutdown feature is not required,
it should be tied directly to the input supply
voltage to keep the regulator output on at all
time.
While in shutdown, VOUT quickly falls to zero
(turn-off time is dependent on load conditions
and output capacitance on VOUT) and power
consumption drops nearly to zero.
No Load Stability
The SP6203/6205 will remain stable and in
regulation with no external load (other than the
internal voltage driver) unlike many other volt-
age regulators. This is especially important in
CMOS RAM battery back-up applications.
ꢀnput Capacitor
A small capacitor of 2.2µF is required from VIN
to GND if a battery is used as the power
source. Any good quality electrolytic, ceramic
or tantalum capacitor may be used at the input.
Date: Apr2-07
SP6203/SP6205 Low Noise, 300 and 500mA CMOS LDO Regulators
© 2007 Sipex Corporation
ꢁ
THEORY OF OPERATꢀON: Continued
Turn On Time
TJ(max) is the maximum junction temperature of
the die and is 125°C. TA is the ambient tempera-
ture. eJA is the junction-to-ambient thermal re-
sistance for the regulator and is layout depen-
dent. The SOT-23-5 package has a eJA of
approximately 256°C/W for minimum PCB
copper footprint area.
The turn on response is split up in two separate
response categories: the wake up time (TWU
)
and the settlling time (TS). The wake up time is
defined as the time it takes for the output to rise
to 2% of its total value after being released from
shutdown (EN > 0.4V). The settling time is
definedastheconditionwheretheoutputreaches
98% of its total value after being released from
shutdown. The latter is also called the turn on
time and is dependent on the output capacitor, a
little bit on load and, if present, on a bypass
capacitor.
This results in a maximum power dissipation of:
PD(max) = [(125°C - 25°C)/(191°C/W)] = 523mW
The actual power dissipation of the regulator
circuit can be determined using one simple
equation:
PD = (VIN - VOUT) * IOUT + VIN * IGND
t(s) = T(on)
V
ENABLE
To prevent the device from entering thermal
shutdown. maximum power dissipation can not
be exceeded.
ꢁꢃ%
2%
t(wu)
V
OUT
Substituting PD(max) for PD and solving for the
operating conditions that are critical to the ap-
plication will give the maximum operating con-
ditions for the regulator circuit. For example, if
we are operating the SP6203 3.0V at room
temperature, with a minimum footprint layout
and and output current of 300mA, the maximum
input voltage can be determined, based on the
equationbelow.Groundpincurrentcanbetaken
from the electrical specifications table (0.23mA
at 300mA).
Turn Off Time
The turn off time is defined as the condition
where the output voltage drops about 66% (e) of
its total value. 5e to 7e is the constant where the
output voltage drops nearly to zero. There will
always be a small voltage drop in shutdown
because of the switch unless we short-circuit it.
The turn off time of the output voltage is depen-
dent on load conditions, output capacitance on
VOUT (time constant o = RLCL) and also on the
difference in voltage between input and output.
390mW = (VIN-3.0V) * 300mA + VIN *0.23mA
After calculations, we find that the maximum
input voltage of a 3.0V application at 300mA of
output current in a SOT-23-5 package is 4.7V.
Thermal Considerations
The SP6203/6205 is designed to provide 300/
500 mA of continuous current in a tiny package.
Maximum power dissipation can be calculated
based on the output current and the voltage drop
across the part. To determine the maximum
power dissipation of the package, use the junc-
tion-to-ambient thermal resistance of the device
and the following basic equation:
So if the intend is to operate a 5V output version
from a 6V supply at 300mA load and at a 25°C
ambienttemperature,thentheactualtotalpower
dissipation will be:
PD=([6V-5V]*[300mA])+(6V*0.23mA)=301.4mW
This is well below the 523mW package maxi-
mum. Therefore, the regulator can be used.
PD = (TJ(max) - TA) / eJA
Date: Apr2-07
SP6203/SP6205 Low Noise, 300 and 500mA CMOS LDO Regulators
© 2007 Sipex Corporation
ꢀ0
THEORY OF OPERATꢀON: Continued
Layout Considerations
Note that the regulator cannot always be used at
its maximum current rating. For example, in a
5V input to 3.0V output application at an ambi-
ent temperature of 25°C and operating at the full
500mA (IGND = 0.355mA) load, the regulator is
limited to a much lower load current, deter-
mined by the following equation:
The primary path of heat conduction out of the
package is via the package leads. Therefore,
careful considerations have to be taken into
account:
1) Attaching the part to a larger copper footprint
will enable better heat transfer from the device,
especially on PCB’s where there are internal
ground and power planes.
523mW = ( [5V-3V]*[ Iload(max)]) +(5V*0.350mA)
After calculation, we find that in such an appli-
cation (SP6205) the regulator is limited to
260.6mA. Doing the same calculations for the
300mALDO(SP6203)willlimittheregulator’s
output current to 260.9mA.
2) Place the input, output and bypass capacitors
close to the device for optimal transient re-
sponse and device behavior.
3) Connect all ground connections directly to
the ground plane. In case there’s no ground
plane, connect to a common local ground point
before connecting to board ground.
Also, taking advantage of the very low dropout
voltage characteristics of the SP6203/6205,
power dissipation can be reduced by using the
lowest possible input voltage to minimize the
input-to-output drop.
Such layouts will provide a much better thermal
conductivity (lower eJA) for, a higher maximum
allowable power dissipation limit.
Adjustable Regulator Applications
The SP6203/6205 can be adjusted to a specific
output voltage by using two external resistors
(see functional diagram). The resistors set the
output voltage based on the following equation:
VOUT = VREF *(R1/R2 + 1)
Resistor values are not critical because ADJ
(adjust) has a high input impedance, but for best
performance use resistors of 470K1 or less. A
bypass capacitor from ADJ to VOUT provides
improved noise performance.
Dual-Supply Operation
When used in dual supply systems where the
regulator load is returned to a negative supply,
the output voltage must be diode clamped to
ground.
Date: Apr2-07
SP6203/SP6205 Low Noise, 300 and 500mA CMOS LDO Regulators
© 2007 Sipex Corporation
ꢀꢀ
PACKAGE: 5Pin SOT-23
Date: Apr2-07
SP6203/SP6205 Low Noise, 300 and 500mA CMOS LDO Regulators
© 2007 Sipex Corporation
ꢀ2
PACKAGE: 8Pin DFN
Date: Apr2-07
SP6203/SP6205 Low Noise, 300 and 500mA CMOS LDO Regulators
© 2007 Sipex Corporation
ꢀ3
ORDERꢀNG ꢀNFORMATꢀON
Top
Marking
N2WW
N2WW
L2WW
L2WW
G2WW
G2WW
Q3WW
Q3WW
H2WW
H2WW
M2WW
M2WW
J2WW
Temperature Voltage Package
Part Number
Range
Option
ꢀ.ꢃV
ꢀ.ꢃV
2.5V
2.5V
2.7V
2.7V
2.ꢃV
2.ꢃV
Type
SP6203EM5-ꢀ-ꢃ
SP6203EM5-ꢀ-ꢃ/TR
SP6203EM5-2-5
SP6203EM5-2-5/TR
SP6203EM5-2-7
SP6203EM5-2-7/TR
SP6203EM5-2-ꢃ
SP6203EM5-2-ꢃ/TR
SP6203EM5-2-ꢃ5
SP6203EM5-2-ꢃ5/TR
SP6203EM5-3-0
SP6203EM5-3-0/TR
SP6203EM5-3-3
SP6203EM5-3-3/TR
SP6203EM5
-40˚C to +125˚C
-40˚C to +125˚C
-40˚C to +125˚C
-40˚C to +125˚C
-40˚C to +125˚C
-40˚C to +125˚C
-40˚C to +125˚C
-40˚C to +125˚C
5 Pin SOT-23
5 Pin SOT-23
5 Pin SOT-23
5 Pin SOT-23
5 Pin SOT-23
5 Pin SOT-23
5 Pin SOT-23
5 Pin SOT-23
-40˚C to +125˚C 2.ꢃ5V 5 Pin SOT-23
-40˚C to +125˚C 2.ꢃ5V 5 Pin SOT-23
-40˚C to +125˚C
-40˚C to +125˚C
-40˚C to +125˚C
-40˚C to +125˚C
-40˚C to +125˚C
-40˚C to +125˚C
3.0V
3.0V
3.3V
3.3V
ADJ
ADJ
5 Pin SOT-23
5 Pin SOT-23
5 Pin SOT-23
5 Pin SOT-23
5 Pin SOT-23
5 Pin SOT-23
J2WW
Q2WW
Q2WW
SP6203EM5/TR
SP6203ER-ꢀ-ꢃ
SP6203ER-ꢀ-ꢃ/TR
SP6203ER-2-5
SP6203ER-2-5/TR
SP6203ER-2-7
SP6203ER-2-7/TR
SP6203ER-2-ꢃ
SP6203ER-2-ꢃ/TR
SP6203ER-2-ꢃ5
SP6203ER-2-ꢃ5/TR
SP6203ER-3-0
SP6203ER-3-0/TR
SP6203ER-3-3
SP6203ER-3-3/TR
SP6203ER
6203ꢀꢃYWW -40˚C to +125˚C
6203ꢀꢃYWW -40˚C to +125˚C
620325YWW -40˚C to +125˚C
620325YWW -40˚C to +125˚C
620327YWW -40˚C to +125˚C
620327YWW -40˚C to +125˚C
62032ꢃYWW -40˚C to +125˚C
62032ꢃYWW -40˚C to +125˚C
ꢀ.ꢃV
ꢀ.ꢃV
2.5V
2.5V
2.7V
2.7V
2.ꢃV
2.ꢃV
ꢃ Pin DFN
ꢃ Pin DFN
ꢃ Pin DFN
ꢃ Pin DFN
ꢃ Pin DFN
ꢃ Pin DFN
ꢃ Pin DFN
ꢃ Pin DFN
ꢃ Pin DFN
ꢃ Pin DFN
ꢃ Pin DFN
ꢃ Pin DFN
ꢃ Pin DFN
ꢃ Pin DFN
ꢃ Pin DFN
ꢃ Pin DFN
6203ꢃ5YWW -40˚C to +125˚C 2.ꢃ5V
6203ꢃ5YWW -40˚C to +125˚C 2.ꢃ5V
620330YWW -40˚C to +125˚C
620330YWW -40˚C to +125˚C
620333YWW -40˚C to +125˚C
620333YWW -40˚C to +125˚C
6203ERYWW -40˚C to +125˚C
6203ERYWW -40˚C to +125˚C
3.0V
3.0V
3.3V
3.3V
ADJ
ADJ
SP6203ER/TR
Solved by
TM
Date: Apr2-07
SP6203/SP6205 Low Noise, 300 and 500mA CMOS LDO Regulators
© 2007 Sipex Corporation
ꢀꢂ
ORDERꢀNG ꢀNFORMATꢀON
Top
Marking
X2WW
X2WW
V2WW
V2WW
R2WW
R2WW
E3WW
E3WW
S2WW
S2WW
W2WW
W2WW
T2WW
T2WW
A3WW
A3WW
Temperature Voltage Package
Part Number
Range
Option
ꢀ.ꢃV
ꢀ.ꢃV
2.5V
2.5V
2.7V
2.7V
2.ꢃV
2.ꢃV
Type
SP6205EM5-ꢀ-ꢃ
SP6205EM5-ꢀ-ꢃ/TR
SP6205EM5-2-5
SP6205EM5-2-5/TR
SP6205EM5-2-7
SP6205EM5-2-7/TR
SP6205EM5-2-ꢃ
SP6205EM5-2-ꢃ/TR
SP6205EM5-2-ꢃ5
SP6205EM5-2-ꢃ5/TR
SP6205EM5-3-0
SP6205EM5-3-0/TR
SP6205EM5-3-3
SP6205EM5-3-3/TR
SP6205EM5
-40˚C to +125˚C
-40˚C to +125˚C
-40˚C to +125˚C
-40˚C to +125˚C
-40˚C to +125˚C
-40˚C to +125˚C
-40˚C to +125˚C
-40˚C to +125˚C
-40˚C to +125˚C
-40˚C to +125˚C
-40˚C to +125˚C
-40˚C to +125˚C
-40˚C to +125˚C
-40˚C to +125˚C
-40˚C to +125˚C
-40˚C to +125˚C
5 Pin SOT-23
5 Pin SOT-23
5 Pin SOT-23
5 Pin SOT-23
5 Pin SOT-23
5 Pin SOT-23
5 Pin SOT-23
5 Pin SOT-23
2.ꢃ5V 5 Pin SOT-23
2.ꢃ5V 5 Pin SOT-23
3.0V
3.0V
3.3V
3.3V
ADJ
ADJ
5 Pin SOT-23
5 Pin SOT-23
5 Pin SOT-23
5 Pin SOT-23
5 Pin SOT-23
5 Pin SOT-23
SP6205EM5 /TR
SP6205ER-ꢀ-ꢃ
SP6205ER-ꢀ-ꢃ/TR
SP6205ER-2-5
SP6205ER-2-5/TR
SP6205ER-2-7
SP6205ER-2-7/TR
SP6205ER-2-ꢃ
SP6205ER-2-ꢃ/TR
SP6205ER-2-ꢃ5
SP6205ER-2-ꢃ5/TR
SP6205ER-3-0
SP6205ER-3-0/TR
SP6205ER-3-3
SP6205ER-3-3/TR
SP6205ER
6205ꢀꢃYWW -40˚C to +125˚C
6205ꢀꢃYWW -40˚C to +125˚C
620525YWW -40˚C to +125˚C
620525YWW -40˚C to +125˚C
620527YWW -40˚C to +125˚C
620527YWW -40˚C to +125˚C
62052ꢃYWW -40˚C to +125˚C
62052ꢃYWW -40˚C to +125˚C
6205ꢃ5YWW -40˚C to +125˚C
6205ꢃ5YWW -40˚C to +125˚C
620530YWW -40˚C to +125˚C
620530YWW -40˚C to +125˚C
620533YWW -40˚C to +125˚C
620533YWW -40˚C to +125˚C
6205ERYWW -40˚C to +125˚C
6205ERYWW -40˚C to +125˚C
ꢀ.ꢃV
ꢀ.ꢃV
2.5V
2.5V
2.7V
2.7V
2.ꢃV
2.ꢃV
2.ꢃ5V
2.ꢃ5V
3.0V
3.0V
3.3V
3.3V
ADJ
ꢃ Pin DFN
ꢃ Pin DFN
ꢃ Pin DFN
ꢃ Pin DFN
ꢃ Pin DFN
ꢃ Pin DFN
ꢃ Pin DFN
ꢃ Pin DFN
ꢃ Pin DFN
ꢃ Pin DFN
ꢃ Pin DFN
ꢃ Pin DFN
ꢃ Pin DFN
ꢃ Pin DFN
ꢃ Pin DFN
ꢃ Pin DFN
SP6205ER /TR
Solved by
ADJ
TM
Date: Apr2-07
SP6203/SP6205 Low Noise, 300 and 500mA CMOS LDO Regulators
© 2007 Sipex Corporation
ꢀ5
For further assistance:
Application note and calculator file for Thermal considerations with Linear
Regulators:
ANP 2
ANP 3
Email:
LDO Thermal Considerations for Linear Regulators
LDO Linear Regulator Heat Calculator
Sipexsupport@sipex.com
[PDF]
[Excel]
WWW Support page:
http://www.sipex.com/content.aspx?p=support
Sipex Application Notes: http://www.sipex.com/applicationNotes.aspx
Solved by
Sipex Corporation
Headquarters and
TM
Sales Office
233 South Hillview Drive
Milpitas, CA ꢁ5035
TEL: (ꢂ0ꢃ) ꢁ3ꢂ-7500
FAX: (ꢂ0ꢃ) ꢁ35-7600
Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume
any liability arising out of the application or use of any product or circuit described herein; neither does it convey
any license under its patent rights nor the rights of others.
Date: Apr2-07
SP6203/SP6205 Low Noise, 300 and 500mA CMOS LDO Regulators
© 2007 Sipex Corporation
ꢀ6
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