SP6330EK1-L-R-A-B/TR [SIPEX]
Power Supply Management Circuit, Adjustable, 4 Channel, PDSO8, LEAD FREE, MO-193BA, TSOT-8;
| 型号： | SP6330EK1-L-R-A-B/TR |
| 厂家： | 
SIPEX CORPORATION |
| 描述： | Power Supply Management Circuit, Adjustable, 4 Channel, PDSO8, LEAD FREE, MO-193BA, TSOT-8 光电二极管 |
| 文件： | 总33页 (文件大小：1631K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SP6330, SP6332
and SP6334
Quad µPower Supervisory Circuits
with Manual Reset & Watchdog
FEATURES
1
8
7
6
5
RSTB
WDI
V1
■ Low operating voltage of 1.6V
■ Low operating current of 20µA typical
■ Monitors up to four supplies simultaneously
■ Adjustable inputs monitor down to 0.5V
■ Reset asserted down to 0.9V
SP6330
2
3
4
V2
MRIB
V3
8 Pin TSOT
GND
V4
■ 2% accuracy over temperature range
■ Open Drain (OD) or CMOS RSTB output or
CMOS RST output
Open Drain RESET
■ 4 Reset Timeout Periods:
SEE PAGE 2 FOR OTHER
AVAILABLE PINOUTS
50ms, 100ms, 200ms and 400ms
■ Watch Dog Input Functionality -- WDI
■ Manual Reset Input (Active Low) -- MRIB
■ 8 Pin TSOT package
Available in Lead Free Packaging
DESCRIPTION
SP6330-SP6332- SP6334 Quad Power Supervisory Circuit Family is a family of
microprocessor reset supervisory circuits with multiple reset voltages. The family provides
low voltage monitoring ability for up-to four supplies with two precision factory-set thresholds
and two user defined custom thresholds. These circuits perform a single function: if any of
the input supply voltages drops below its associated threshold, reset outputs are asserted.
The SP6330, SP6332, and SP6334 are packaged in an 8-pin TSOT package. All devices are
fully specified over -40oC to +85oC temperature range.
TYPICAL APPLICATION CIRCUIT
Nov20-06 Rev M
SP6330/32/34 Quad Power Supervisory Circuit Family
© Copyright 2006 Sipex Corporation
1
PINOUT DIAGRAMS
1
2
3
4
8
7
6
5
RSTB
WDI
1
2
3
4
8
7
6
5
RST
WDI
1
2
3
4
8
7
6
5
RSTB
WDI
V1
V2
V1
V2
V1
V2
SP6332
8 Pin TSOT
SP6334
8 Pin TSOT
SP6330
8 Pin TSOT
MRIB
V3
GND
V4
MRIB
V3
GND
V4
MRIB
V3
GND
V4
CMOS RESET
Reset
CMOS RESET
WDI
Open Drain RESET
PART
V1 V2 V3 V4
MRIB
NUMBER
SP6330
SP6332
SP6334
√
√
√
√
√
√
√
√
√
√
√
√
OD Active Low
√
√
√
√
√
√
CMOS Active Low
CMOS Active High
Feature and Pinout Diagram
Representative Samples Available
Sipex
Product
Product
V1
V2
V3
V4
Reset
Package
Ordering #
(Volts)
(Volts)
(Volts)
(Volts)
(ms)
Description
Quad Supervisor
Open Drain low
Quad Supervisor
Open Drain low
Quad Supervisor
Open Drain low
Quad Supervisor
CMOS low
SP6330
SP6330
SP6330
SP6332
8 Pin TSOT
8 Pin TSOT
8 Pin TSOT
8 Pin TSOT
2.925
3.075
4.625
2.625
1.575
2.313
2.313
1.575
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
200
200
200
200
SP6330EK1-L-W-G-C
SP6330EK1-L-X-J-C
SP6330EK1-L-Z-J-C
SP6330EK1-L-V-G-C
ABSOLUTE MAXIMUM RATINGS
These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections
of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability
and cause permanent damage to the device.
Terminal Voltage (with respect to GND)
Operating Temperature
V1, V2..................................................... -0.3 to +6V
Open-DrainRSTB.......................................-0.3to+6V
CMOS RST, RSTB, ..................... -0.3 to (V1+0.3V)
Input Current/Output
Range...............................................-40°Cto +85 °C
Storage Temperature
Range...............................................-65°C to 150°C
Current..................................,,........................20mA
Thermal Resistance OJA.............................134°C/W
V3, V4, MRIB, WDI........................-0.3 to (V1+0.3V)
Nov20-06 Rev M
SP6330/32/34 Quad Power Supervisory Circuit Family
© Copyright 2006 Sipex Corporation
2
ELECTRICAL CHARACTERISTICS
PARAMETER MIN
TYP MAX UNITS
CONDITIONS
V1 =1.6V to 5.5V; TA = -40ºC to +85ºC; unless otherwise noted. Typical values are at TA =+25ºC
Operating Voltage
Range
0.9
5.5
30
25
V
T = -40ºC to +85ºC
A
V1 < 5.5V, V2 < 3.60V, all I/O
pins open
V1 < 3.6V, V2 < 2.75V, all I/O
pins open
20
15
uA
Supply Current
4.532
4.287
3.013
2.866
2.572
2.273
2.146
1.636
1.548
2.266
2.144
1.631
1.543
1.360
1.286
1.087
1.029
0.816
0.772
4.625
4.375
3.075
2.925
2.625
2.320
2.190
1.670
1.580
2.313
2.188
1.665
1.575
1.388
1.313
1.110
1.050
0.833
0.788
4.718
4.463
3.137
2.984
2.678
2.367
2.234
1.704
1.612
2.360
2.232
1.698
1.607
1.416
1.340
1.133
1.071
0.850
0.804
Z (valid for V1 falling)
Y (valid for V1 falling)
X (valid for V1 falling)
W (valid for V1 falling)
V (valid for V1 falling)
U (valid for V1 falling)
T (valid for V1 falling)
S (valid for V1 falling)
R (valid for V1 falling)
J (valid for V2 falling)
I (valid for V2 falling)
H (valid for V2 falling)
G (valid for V2 falling)
F (valid for V2 falling)
E (valid for V2 falling)
D (valid for V2 falling)
C (valid for V2 falling)
B (valid for V2 falling)
A (valid for V2 falling)
V1 Reset
Threshold
V
V2 Reset
Threshold
V
Threshold 1
Tempco
Threshold 2
Tempco
Threshold 1
Hysteresis
Threshold 2
Hysteresis
0.06
0.04
0.65
0.5
mV/ºC
mV/ºC
%
reference to Vth1 typical
reference to Vth2 typical
%
V1 to RST/RSTB
Delay
V1 = Vth1 to (Vth1-0.1V), Vth1
= 3.075
50
us
V2 to RST/RSTB
Delay
V2 = Vth2 to (Vth2-0.1V), Vth2
= 1.575
50
us
Reset Timeout
Period (T1)
Reset Timeout
Period (T2)
Reset Timeout
Period (T3)
Reset Timeout
Period (T4)
37
74
50
63
ms
TOPT-1
TOPT-2
TOPT-3
TOPT-4
100
200
400
126
252
504
ms
148
296
ms
ms
Nov20-06 Rev M
SP6330/32/34 Quad Power Supervisory Circuit Family
© Copyright 2006 Sipex Corporation
3
ELECTRICAL CHARACTERISTICS
PARAMETER MIN
TYP MAX UNITS
CONDITIONS
V1 =1.6V to 5.5V; TA = -40ºC to +85ºC; unless otherwise noted. Typical values are at TA =+25ºC
V3 RESET COMPARATOR INPUT
V3 Input Threshold
V3 Input Current
V3 Threshold
Hysteresis
V4 RESET COMPARATOR INPUT
V4 Input Threshold
V4 Input Current
V4 Threshold
490
-50
500
1.5
500
1.5
510
50
mV
nA
T
A
= +25ºC
= +25ºC
mV
490
-50
510
50
mV
nA
TA
mV
Hysteresis
MRIB - MANUAL RESET INPUT
MRIB Input
Threshold
0.2*V1
V
V
Vil
Vih
MRIB Input
Threshold
0.8*V1
MRIB Minimum
Input Pulse Width
MRIB Glitch
Rejection
MRIB to RST/RSTB
Delay
MRIB Pull-Up
Resistance
WDI - WATCHDOG INPUT
Watchdog Timeout
1
us
ns
ns
kΩ
150
100
55
30
85
1.9
1.3
1.6
sec
us
V
Period
WDI Pulse Width
WDI Input
0.1
0.2*V1
Vil
Threshold
WDI Input
Threshold
WDI Input Current
0.8*V1
-500
V
Vih
500
nA
WDI = 0.0V or V1
RESET OUTPUTS RST / RSTB
RSTB
(CMOS or OD)
V1 = Vth1 - 0.1V, Isink = 1mA,
output asserted
0.2*V1
V
V1 = Vth1 + 0.1V, Isource =
1mA, output not asserted
V1 = Vth1 - 0.1V, Isource =
1mA, output asserted
RSTB (CMOS)
RST (CMOS)
0.8*V1
0.8*V1
V
V
V1 = Vth1 + 0.1V, V2 > Vth2,
V3 > 0.5, V4 > 0.5, Isource =
1mA, output not asserted
RST (CMOS)
0.2*V1
V
RSTB Output OD
Leakage Current
2
nA
TA = +25ºC
Nov20-06 Rev M
SP6330/32/34 Quad Power Supervisory Circuit Family
© Copyright 2006 Sipex Corporation
4
PIN DESCRIPTION
Pin #
Name
V1
Description
First supply voltage input. Also powers internal circuitry. Trip threshold
voltage internally set.
1
2
V2
Second supply voltage input. Trip threshold voltage internally set.
Manual Reset Input pin. Active low. It has an internal pull-up resistor.
Reset asserted when MRIB is pulled low and is kept asserted for
200ms after MRIB is released or pulled high. Leave open if not used.
3
MRIB
4
5
V3
V4
Input for the third supply voltage. Trip threshold is 0.5V.
Input for the fourth supply voltage. Trip threshold is 0.5V.
6
GND
Common ground reference pin.
Watch-Dog Input pin. When no transition is detected at the WDI pin for
the duration of WDI timeout period, reset is asserted. Leave open if
not used. RST/RSTB output is used to signal watchdog timeout
overflow. RST/RSTB output pulses high/low (depending on the active
reset polarity) for the reset timeout period after each watchdog timeout
overflow. The watchdog timer clears whenever the reset is asserted
or manual reset is asserted or a transition is observed at WDI pin.
Watchdog timer functionality can be disabled in parts by leaving this
input floating.
7
WDI
Reset output. Open-Drain or CMOS, active high or low. Reset is
asserted when any of the four supply inputs is below its trip threshold.
It stays asserted for 200 ms (typical / default) after the last supply input
traverses its trip threshold. Reset is guaranteed to be in the correct
state for V1>0.9V. RST/RSTB asserts when V1 or V2 or V3 or V4 drop
below their corresponding reset thresholds, or MRIB is pulled
“LOW” or the watchdog timer triggers a reset (devices without
WDOB). RST/RSTB remains asserted for the reset timeout period
after V1 and V2 and V3 and V4 exceed their corresponding reset
thresholds or MRIB goes “LOW” to “HIGH”. Open-drain outputs
require an external pull-up resistor. CMOS outputs are referenced to
V1.
8
RST/RSTB
Nov20-06 Rev M
SP6330/32/34 Quad Power Supervisory Circuit Family
© Copyright 2006 Sipex Corporation
5
THEORY OF OPERATION
V1
V2
V3
WDI
V4
WDI
OSC
LOGIC
Bandgap
Ref
1.25V
CONTROL
LOGIC
RSTB (RST)
0.5V
MRIB
GND
Block Diagram
The SP6330, SP6332, and SP6334 include
a low-voltage precision bandgap reference,
four precision comparators, an oscillator, a
digital counter chain, a logic control block,
trimmed resistor divider chains and
additionalsupportingcircuitry. Thefamilyis
designed to supervise up to 4 independent
supply voltages. V1 and V2 supply inputs
have their resistor dividers on the chip.
Their trip thresholds are factory trimmed.
V3 and V4 inputs allow user to customize
two additional supply thresholds to be
monitored by means of external resistor
dividers. The devices also feature manual
reset and watchdog functionalities.
As these devices do not have watchdog
outputs, the watchdog timer is serviced
internally during the watchdog timeout
period when WDI is left unconnected. The
watchdog functionality can be disabled by
leaving the WDI input floating.
Nov20-06 Rev M
SP6330/32/34 Quad Power Supervisory Circuit Family
© Copyright 2006 Sipex Corporation
6
THEORY OF OPERATION
Vth1
V1
V2
Vth2
Vth3=0.5V
Vth4=0.5V
V3
V4
T<Twd
T<Twd
T<Twd
T<Twd
T<Twd
MRIB
WDI
Trp
Trp
Trp
Twd
RSTB
Figure 1: Functionality of a SP63XX family member with manual reset and watchdog
capabilities but without WDOB output.
• V1 > Vth1, V2 > Vth2 , V3 > Vth3 and V4 > Vth4 (all supplies over their corresponding
thresholds)---> RSTB is de-asserted after reset timeout period (Trp).
• MRIB goes to “LOW” to force “Reset” ----> RSTB is asserted immediately.
• WDI does not make any transition during watchdog timeout period (Twd) ---->RSTB is
asserted for a duration of reset timeout period (Trp).
• One of the supplies drops below its corresponding threshold (in this case V3)---->RSTB
is asserted immediately.
Nov20-06 Rev M
SP6330/32/34 Quad Power Supervisory Circuit Family
© Copyright 2006 Sipex Corporation
7
APPLICATION INFORMATION
V1
RSTB
ResetB Timeout Delay
WDI = GND, V1=V2=V3=V4=5V,
MRIB = open.
Watchdog Timeout Period = 1.52S
Watchdog Timeout Period
Nov20-06 Rev M
SP6330/32/34 Quad Power Supervisory Circuit Family
© Copyright 2006 Sipex Corporation
8
APPLICATION INFORMATION
Reset Timeout vs. Temperature
(400ms Reset)
500
400
300
200
100
0
85 80 70 60 50 40 30 20 10 0 -10 -20 -30 -40
Deg C
ResetTimeout Delay Vs. Temperature
R S T B vs. V 1 (V 2 = G N D )
5
4.5
4
3
3
. 2.5
5
2
1.5
1
0.5
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
V1 (Vdc)
Reset Good
Nov20-06 Rev M
SP6330/32/34 Quad Power Supervisory Circuit Family
© Copyright 2006 Sipex Corporation
9
APPLICATION INFORMATION
V 1 an d V 2 G litc h rejectio n
250
200
150
100
50
RSTB asserted
above line
0
0
20
40
60
80
100
120
Overdrive (mV)
V1 and V2 Glitch Rejection
V 3 an d V 4 g litch rejectio n
120
100
80
RSTB asserted
above line
60
40
20
0
0
20
40
60
80
100
120
O verdrive (mV)
V3 and V4 Glitch Rejection
Nov20-06 Rev M
SP6330/32/34 Quad Power Supervisory Circuit Family
© Copyright 2006 Sipex Corporation
10
PACKAGE: 8 PIN TSOT
D
D/2
e1
7
8
6
5
E/2
SIDE VIEW
A2
E1/2
E
E1
A
Seating
Plane
3
4
2
A1
1
(L1)
Pin1 Designator
to be within this
INDEX AREA
(D/2 x E1/2)
e
b
TOP VIEW
ø1
FRONT VIEW
R1
Gauge Plane
R
L2
ø1
c
Seating
Plane
ø
L
8 Pin TSOT
JEDEC MO-193
Variation BA
Dimensions in Inches
Conversion Factor:
1 Inch = 25.40 mm
Dimensions in Millimeters:
Controlling Dimension
SYMBOL
MIN
-
0.00
0.70
0.08
NOM
-
-
0.90
-
MAX
1.10
0.10
1.00
0.20
MIN NOM
MAX
0.043
0.004
0.039
0.008
A
-
-
-
A1
A2
c
0.000
0.028 0.036
0.003
-
D
E
E1
L
2.90 BSC
2.80 BSC
1.60 BSC
0.45
0.114 BSC
0.110 BSC
0.063 BSC
0.30
0.60
0.012 0.018
0.024
L1
L2
Ø
Ø1
R
0.60 REF
0.25 BSC
4º
10º
-
0.024 REF
0.010 BSC
4º
10º
0˚
4˚
0.10
0.10
0.22
8º
12º
-
0.25
0.38
0º
4º
0.004
0.004
0.009
8º
12º
-
-
R1
-
-
-
-
0.010
0.015
b
e
e1
0.65 BSC
1.95 BSC
0.026 BSC
0.077 BSC
SIPEX Pkg Signoff Date/Rev:
JL Oct3-05 / Rev A
Nov20-06 Rev M
SP6330/32/34 Quad Power Supervisory Circuit Family
© Copyright 2006 Sipex Corporation
11
Part Naming Nomenclature
SP63NN - Th1 - Th2 - TOPT
T1 -- 50 ms
A
-- 100 ms
B
-- 200 ms
{
C
-- 400 ms
D
A -- 0.788 V
B -- 0.833 V
C -- 1.050 V
D -- 1.110 V
E -- 1.313 V
F -- 1.388 V
G -- 1.575 V
Example:
{
H -- 1.665 V
I -- 2.188 V
J -- 2.313 V
AZJD means:
SP6330 in TSOT-8 lead package
V1 Threshold is 4.625V
V2 Threshold is 2.313V
Reset Timeout is 400ms
Z -- 4.625 V
Y -- 4.375 V
X -- 3.075 V
W -- 2.925 V
V -- 2.625 V
U -- 2.320 V
T -- 2.190 V
S -- 1.670 V
R -- 1.580 V
AZJD
Pin 1
{
30 -- Quad Sp, MR, WDI, OD RSTB
31 -- Quad Sp, OD RSTB
32 -- Quad Sp, MR, WDI, CMOS RSTB
33 -- Quad Sp, CMOS RSTB
34 -- Quad Sp, MR, WDI, CMOS RST
35 -- Quad Sp, CMOS RST
36 -- Triple Sp, WDI, PF, OD RSTB
37 -- Triple Sp, WDI, PF, CMOS RSTB
A
B
C
D
E
F
G
H
38 -- Triple Sp, WDI, PF, CMOS RST
I
39 -- Triple Sp, MR, WDI, OD RSTB - WDOB
40 -- Dual Sp, WDI, OD RSTB - WDOB
41 -- Triple Sp, WDI, PF, CMOS RSTB - WDOB
42 -- Dual Sp, WDI, CMOS RSTB - WDOB
J
K
L
M
Nov20-06 Rev M
SP6330/32/34 Quad Power Supervisory Circuit Family
© Copyright 2006 Sipex Corporation
12
ORDERING INFORMATION
Model
Temperature Range
Package Types
SP6330EK1-L-X-X-X...........................................-40°C to +85°C.................................Lead Free 8-Pin TSOT
SP6330EK1-L-X-X-X/TR......................................-40°Cto+85°C.................................LeadFree8-PinTSOT
SP6332EK1-L-X-X-X............................................-40°Cto+85°C.................................LeadFree8-PinTSOT
SP6332EK1-L-X-X-X/TR......................................-40°Cto+85°C.................................LeadFree8-PinTSOT
SP6334EK1-L-X-X-X............................................-40°Cto+85°C.................................LeadFree8-PinTSOT
SP6334EK1-L-X-X-X/TR......................................-40°Cto+85°C.................................LeadFree8-PinTSOT
Available in lead free packaging only. /TR = Tape and Reel
Pack quantity 2,500 forTSOT-8
Contact Factory for availability of particular voltage threshold and reset timeout options. Note that the
Ordering Information denoting those options corresponds to the Part Naming Nomenclature shown on the
previous page.
Ordering example: SP6330EK1-L-W-G-C/TR == W -- 2.925V for Voltage Threshold 1; G -- 1.575V for
Voltage Threshold 2; and C -- 200ms reset timeout.
Sipex Corporation
Headquarters and
Sales Office
233 South Hillview Drive
Milpitas, CA 95035
TEL: (408) 934-7500
FAX: (408) 935-7600
Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the
application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.
Nov20-06 Rev M
SP6330/32/34 Quad Power Supervisory Circuit Family
© Copyright 2006 Sipex Corporation
13
Solved by
TM
Appendix and Web Link Information
For further assistance:
Email:
Sipexsupport@sipex.com
WWW Support page:
Sipex Application Notes:
Product Change Notices:
http://www.sipex.com/content.aspx?p=support
http://www.sipex.com/applicationNotes.aspx
http://www.sipex.com/content.aspx?p=pcn
Sipex Corporation
Solved by
Headquarters and
Sales Office
233 South Hillview Drive
Milpitas, CA95035
tel: (408) 934-7500
faX: (408) 935-7600
TM
Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the application or use of
any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.
The following sections contain information which is more
changeable in nature and is therefore generated as appendices.
1) Package Outline Drawings
2) Ordering Information
If Available:
3) Frequently Asked Questions
4) Evaluation Board Manuals
5) Reliability Reports
6) Product Characterization Reports
7) Application Notes for this product
8) Design Solutions for this product
Datasheet Appendix & Web Link Information
© 2007 Sipex Corporation
Sipex Corporation - Sipex Product Details
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Quad microPower Supervisory Circuits with Manual
Reset and Watchdog
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2%ꢀaccuracyꢀoverꢀtemperatureꢀrangeꢀꢀ
CMOSꢀRSTBꢀoutputꢀꢀ
4ꢀResetꢀTimeoutꢀPeriods:ꢀ50ms,ꢀ100ms,ꢀ200msꢀandꢀ
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Seeꢀdatasheetꢀforꢀsamplesꢀrepresentativeꢀtable.ꢀContactꢀ
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Part Number
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Status Buy Samples
Code
Temp.
(°C)
SP6332EK1ꢁLꢀ
QUADꢀ
ꢀ
ꢀ
ꢀ
ꢀ
SUPERVISORS
SP6332EK1ꢁLꢁVꢁ TSOT8
▪
ꢁ40
85
Active
Order Sa
New!
GꢁC
Part Status Legend
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NRND (Not Recommended for New Designs)ꢀꢁꢀtheꢀpartꢀisꢀnotꢀrecommendedꢀforꢀnewꢀdesigns.ꢀ
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7/23/2007
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APPLICATION NOTE ANP14
TM
Understanding and Selecting a Multi-Voltage
Introduction
The primary function of a microprocessor (µP) supervisor circuit is to ensure that
the input supply voltage of a microprocessor is at proper levels during power up,
power down and brownout conditions. If the input supply voltage to a
microprocessor is below its required operating range, it could cause code-
execution errors, memory corruption and latch up. The supervisor will constantly
monitor the input supply to the microprocessor, and in the event this supply
voltage falls below a certain threshold, the RESET output will be asserted. Many
of today’s power products require several different voltage rails for powering
various components. The microprocessor itself can have a separate core voltage
and logic voltage. Other components such as DSPs, ASICs and microcontrollers
can have their own unique voltage requirements. To service this demand of
monitoring multi-voltage systems, Sipex has developed the SP6330 family. The
SP6330 family is a series of multi-voltage supervisors that offer monitoring of up
to 4 separate supplies and are equipped with specialized features. A complete
listing of products and features are listed in Figure 4 at the end of this note.
MR
Supplies
to be
monitored
uP
C1
0.1uF
SP6332
1
2
3
4
8
7
6
5
V1
V2
V3
V4
V1
RSTB
WDI
GND
V4
RSTB
I/O
V2
C2
0.1uF
MRIB
V3
R2
R3
R4
C3
0.1uF
C4
0.1uF
R5
SP6332 typical applications circuit for monitoring 4 supplies with Master
Reset, Watchdog input and CMOS Reset output
Jun 27-06
SP6330 Family: Selecting a Multi-Voltage Supervisor
Page 1 of 6
© 2006 Sipex Corporation
Inputs to the SP6330 Family
The SP6330 family has the ability to monitor up to 4 different voltages. Two of
these inputs (V1 and V2) have precision factory-set thresholds while the
remaining two inputs (V3 and V4) are adjustable. V3 and V4 inputs allow the user
to customize two additional supply thresholds by means of an external divider.
The threshold for V3 and V4 inputs is 0.5Volts. The V1 input supplies power to
the device and will have the highest threshold for a given application; its
minimum operating voltage for is 1.8V. The factory set threshold range for V1
and V2 inputs are shown in Figure 1.
V1 V2
Typical Typical
Threshold Threshold
4.625
4.375
3.075
2.925
2.625
2.320
2.190
1.670
1.580
2.313
2.188
1.665
1.575
1.388
1.313
1.110
1.050
0.833
0.788
Figure 1
Reset Output – RST or RSTB
The reset output can be either active low or active high depending on each
device. The reset output can also be either open-drain or push-pull outputs. The
open drain output requires an external pull-up resistor to V1 for normal operation.
The output high voltage (VOH) of the reset output will be approximately equal to
the V1 input voltage.
Reset Timeout Period
The reset timeout period is a built-in time delay for the reset output. This timeout
period is activated at power up or when all monitored voltages have risen above
their respective thresholds. Reset timeout period for the SP6330 family is offered
in four different time intervals: 50ms, 100ms, 200ms and 400ms. The actual
selection of timeout period depends on the applications requirements of the
system voltage settle time. The reset timeout period is used to ensure that all
voltage rails and system clocks have stabilized prior to executing code to prevent
errors or data corruption.
Jun 27-06
SP6330 Family: Selecting a Multi-Voltage Supervisor
Page 2 of 6
© 2006 Sipex Corporation
Manual Reset Input (Active Low) – MRIB
The manual reset input allows the user to manually trigger a reset when
monitored voltages are within tolerance. This is useful for resetting the
microprocessor when it locks up due to software issues. A push-button type
switch can be used to allow the user to trigger a reset externally. However, since
a push button switch will bounce several times, a debounce element is needed.
The manual reset input signal may also be a logic signal from an I/O line,
watchdog timer or a power fail output.
Watchdog Input – WDI
The watchdog checks for proper software execution. If the software locks up or
enters into an unwanted, loop the watchdog timer can either assert a reset output
or a watchdog output. Some members of the SP6330 family offer a watchdog
output while others do not. The watchdog has an internal timer that has a typical
watchdog timeout period of 1.6 seconds. If the watchdog input (WDI) does not
detect a transition within 1.6 seconds, a reset or watchdog output (WDO) will be
generated. The watchdog input is usually connected to an I/O line for monitoring
software activity. The watchdog circuit is useful for generating a reset or Non-
Maskable Interrupt (NMI) signal during software lock up conditions without
human intervention. Floating the WDI will disable the watchdog feature.
Watchdog Output (Active Low) – WDOB
The Watchdog output is active low and can be either an open drain or push-pull
output. If WDI remains at “HIGH” or “LOW” logic level for longer than the
watchdog timeout period, the internal watchdog timer overflows and the WDOB
will be asserted. Additionally, if the reset output is asserted due to an under-
voltage condition, at any voltage input the WDOB would also be asserted.
Floating WDI will not disable the watchdog timer in devices with dedicated
WDOB output.
Power Fail Input (PFI)
The power fail input is used to monitor the unregulated DC voltage or other
upstream voltage and to alert the system that a brownout or power failure is
imminent. When the PFI input is tripped, it can inform the system to start a
power-down routine in order to save important data before a reset output is
asserted. The power fail input has a threshold of 0.5V. By using a voltage divider
the user can monitor any upstream voltage. Connect PFI to V1 or GND if not used.
Jun 27-06
SP6330 Family: Selecting a Multi-Voltage Supervisor
Page 3 of 6
© 2006 Sipex Corporation
Power Fail Output (Active Low) - PFOB
The PFOB pin is an open drain, active low output. When the input voltage at PFI
is <0.5V, PFOB will be asserted.
RI
Supplies
to be
monitored
uP
C1
0.1uF
1
2
3
4
8
7
6
5
V1
V2
V3
V1 RSTB
V2 WDI
PFI GND
RSTB
I/O
C2
0.1uF
NMI
V3 PFOB
SP6336
R6
Unregulated DC
R2
R3
R4
C3
0.1uF
R5
SP6336 Typical Applications circuit for monitoring 3 supplies with Power
Fail Input / Output function and open drain RESET output
Glitch Immunity at Voltage Inputs
The V1, V2, V3 and V4 inputs have a built-in glitch immunity feature that
prevents nuisance resets during normal operation. Noise and normal voltage
transients can cause these unwanted resets without some type of glitch
immunity. Figure 2 shows the combination of voltage overdrive and duration that
will not cause a reset for V1 and V2 inputs. Figure 3 shows the same data as
applied to the V3 and V4 inputs. Adding a small bypass capacitor to voltage
inputs can improve glitch rejection for very harsh environments.
Jun 27-06
SP6330 Family: Selecting a Multi-Voltage Supervisor
Page 4 of 6
© 2006 Sipex Corporation
V1 and V2 Glitch rejection
250
200
150
100
50
RSTB asserted
above line
0
0
20
40
60
80
100
120
Overdrive (mV)
Figure 2
V3 and V4 glitch rejection
120
100
80
60
40
20
0
RSTB asserted
above line
0
20
40
60
80
100
120
Overdrive (mV)
Figure 3
Jun 27-06
SP6330 Family: Selecting a Multi-Voltage Supervisor
Page 5 of 6
© 2006 Sipex Corporation
SP633X Features
• Quad, triple or dual supply monitoring
• Very low operating voltage down to 1.6V
• Low 20µA typical operating current
• Adjustable inputs monitor down to 0.5V
• Open drain or CMOS reset outputs
• 4 reset timeout periods: 50ms, 100ms, 200ms and 400ms
• Glitch immunity inputs
• Tiny 6 pin or 8 pin TSOT package
P/N
V1 V2 V3 V4 Reset Reset MRIB WDI WDOB WDOB PFI PFOB Package
Output Active
OD
CMOS
SP6330
SP6332
SP6334
SP6331
SP6333
SP6335
SP6336
SP6337
SP6338
SP6339
SP6341
SP6340
SP6342
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
OD
LOW X
X
X
X
8-TSOT
8-TSOT
8-TSOT
6-TSOT
6-TSOT
6-TSOT
8-TSOT
8-TSOT
8-TSOT
8-TSOT
8-TSOT
6-TSOT
6-TSOT
CMOS LOW X
CMOS HIGH X
OD
LOW
CMOS LOW
CMOS HIGH
OD
LOW
X
X
X
X
X
X
X
X
X
X
X
X
X
CMOS LOW
CMOS HIGH
OD
LOW X
X
X
CMOS LOW X
X
X
OD
LOW
CMOS LOW
Figure 4: Product Selection Guide
Jun 27-06
SP6330 Family: Selecting a Multi-Voltage Supervisor
Page 6 of 6
© 2006 Sipex Corporation
FAQ
SP6330 - SP6342
Dual/Triple/Quad µPower Supervisory Circuit
Family
FEATURES
■ Low operating voltage of 1.8V
1
2
3
4
8
7
6
5
RSTB
WDI
V1
V2
■ Low operating current of 20µA typical
■ Monitors up to four supplies simultaneously
■ Adjustable inputs monitor down to 0.5V
■ Reset asserted down to 0.9V
■ 2% accuracy over temperature range
■ Power Fail function
SP6330
8 Pin SOT-23
MRIB
V3
GND
V4
■ Open Drain (OD) or CMOS RSTB output or
CMOS RST output
Open Drain RESET
■ 200ms Reset Timeout Period
■ Watch Dog Timer Function
SEE PAGE 3 FOR OTHER
AVAILABLE PINOUTS
■ Independent Open Drain Watchdog Output
■ Manual Reset Input
■ SOT23-6/8 packages
Available in Lead Free Packaging
DESCRIPTION
SP6330-SP6342 Dual/Triple/Quad Power Supervisory Circuit Family is a family of
microprocessor reset supervisory circuits with multiple reset voltages. The SP6330 family
provides low voltage monitoring ability for up-to four supplies with two precision factory-set
thresholds and two user defined custom thresholds. These circuits perform a single function:
if any of the input supply voltages drops below its associated threshold, reset outputs are
asserted. Some of the products in the family offer manual reset,power fail and watchdog
functionalities. TheSP63XXfamilyincludesalow-voltageprecisionbandgapreference, four
precision comparators, an oscillator, a digital counter chain, a logic control block, trimmed
resistor divider chains and additional supporting circuitry. V1 and V2 supply inputs have their
resistor dividers on the chip. Their trip thresholds are factory trimmed. V3 and V4 inputs allow
user to customize two additional supply thresholds to be monitored by means of external
resistor dividers. Some members of the family are furnished with manual reset, power fail
indication, watchdog functionalities.SP6330 thru SP6342 are housed in a 6-pin or 8-pin
SOT23 package. All devices are fully specified over -40oC to +85oC temperature range.
Date: 5/3/06
SP6330-SP6342 Dual/Triple/Quad Power Supervisory Circuit Family
© Copyright 2006 Sipex Corporation
1
Date: 5/3/06
SP6330-SP6342 Dual/Triple/Quad Power Supervisory Circuit Family
© Copyright 2006 Sipex Corporation
2
PINOUT MASTER DIAGRAM
Date: 5/3/06
SP6330-SP6342 Dual/Triple/Quad Power Supervisory Circuit Family
© Copyright 2006 Sipex Corporation
3
FAQ
SP6330 - SP6342
Dual/Triple/Quad µPower Supervisory Circuit
Family
FEATURES
■ Low operating voltage of 1.8V
1
2
3
4
8
7
6
5
RSTB
WDI
V1
V2
■ Low operating current of 20µA typical
■ Monitors up to four supplies simultaneously
■ Adjustable inputs monitor down to 0.5V
■ Reset asserted down to 0.9V
■ 2% accuracy over temperature range
■ Power Fail function
SP6330
8 Pin SOT-23
MRIB
V3
GND
V4
■ Open Drain (OD) or CMOS RSTB output or
CMOS RST output
Open Drain RESET
■ 200ms Reset Timeout Period
■ Watch Dog Timer Function
SEE PAGE 3 FOR OTHER
AVAILABLE PINOUTS
■ Independent Open Drain Watchdog Output
■ Manual Reset Input
■ SOT23-6/8 packages
Available in Lead Free Packaging
DESCRIPTION
SP6330-SP6342 Dual/Triple/Quad Power Supervisory Circuit Family is a family of
microprocessor reset supervisory circuits with multiple reset voltages. The SP6330 family
provides low voltage monitoring ability for up-to four supplies with two precision factory-set
thresholds and two user defined custom thresholds. These circuits perform a single function:
if any of the input supply voltages drops below its associated threshold, reset outputs are
asserted. Some of the products in the family offer manual reset,power fail and watchdog
functionalities. TheSP63XXfamilyincludesalow-voltageprecisionbandgapreference, four
precision comparators, an oscillator, a digital counter chain, a logic control block, trimmed
resistor divider chains and additional supporting circuitry. V1 and V2 supply inputs have their
resistor dividers on the chip. Their trip thresholds are factory trimmed. V3 and V4 inputs allow
user to customize two additional supply thresholds to be monitored by means of external
resistor dividers. Some members of the family are furnished with manual reset, power fail
indication, watchdog functionalities.SP6330 thru SP6342 are housed in a 6-pin or 8-pin
SOT23 package. All devices are fully specified over -40oC to +85oC temperature range.
Date: 5/3/06
SP6330-SP6342 Dual/Triple/Quad Power Supervisory Circuit Family
© Copyright 2006 Sipex Corporation
1
Date: 5/3/06
SP6330-SP6342 Dual/Triple/Quad Power Supervisory Circuit Family
© Copyright 2006 Sipex Corporation
2
PINOUT MASTER DIAGRAM
Date: 5/3/06
SP6330-SP6342 Dual/Triple/Quad Power Supervisory Circuit Family
© Copyright 2006 Sipex Corporation
3
Reliability and Qualification Report
SP6330
Prepared by: G. West
Manager, Quality Assurance
Date: April 7, 2006
Reviewed by: Fred Claussen
VP Quality & Reliability
Date: April 7, 2006
Reliability Report: SP6330
April 7, 2006
Page 1 of 5
Table Of Contents
Title Page…………………………………………………………..………I
Table of Contents………………………………………………….………II
Device Description …………………………………………..………..…..II
Block Diagram……………………………………………………………..II
Manufacturing Information……………………….……………………….III
Package Information………………………………….……………………III
Reliability Test Summary.………………..……………….…………….…IV
Life Test Data……………………………………………………………...IV
FIT Data Calculations……………………………………………….……..V
MTBF Data Calculations……………………………………...…………...V
Device Description:
SP6330-SP6332- SP6334 Quad Power Supervisory Circuit Family is a family of
microprocessor reset supervisory circuits with multiple reset voltages. The family provides
low voltage monitoring ability for up-to four supplies with two precision factory-set thresholds
and two user defined custom thresholds. These circuits perform a single function: if any of
the input supply voltages drops below its associated threshold, reset outputs are asserted.
The SP6330, SP6332, and SP6334 are packaged in an 8-pin TSOT package. All devices are
fully specified over -40oC to +85oC temperature range.
SP6330 Pin Out
Manufacturing Information:
Products:
SP6330
Description:
Mask Set(s):
Quad Power Supervisory Circuit
MS1512AZ
Process:
CMOS
Process Name:
Wafer Manufacturer:
Assembly Location:
Qualification Lot #’s:
PBC4
Polar Semiconductor, Inc.
Carsem– Malaysia
3522A001A.11, 3638A001.8, 3638A001.6
Reliability Report: SP6330
April 7, 2006
Page 2 of 5
Package Information:
Package Type:
Die Size:
8 pin TSOT
45 x 67 mil
Reliability Qualification Test Summary:
Stress Level
Device
Burn-In Temp Sample Size
No. Fail
168Hrs
500Hrs
1000Hrs
SP6330
SP6330
SP6330
240
240
240
0
0
0
125 °C
125 °C
125 °C
Life Test
Life testing is conducted to determine if there are any fundamental reliability related
failure mechanism(s) present in the device.
These failure mechanisms can be divided roughly into four groups:
1. Process or die related failures, such as oxide-related defects, metalization-related
defects and diffusion-related defects.
2. Assembly-related defects such as chip mount wire bond or package-related
failures.
3. Design related defects.
4. Miscellaneous, undetermined or application-induced failures.
Life Test Results
As part of the Sipex design qualification program, the Engineering group had subjected
80 parts from each of 3 lots of SP6330 for a 1000 hour reliability life test at 125° C.
168 hour Life test
240 parts of SP6330 parts were subjected to the life test profile and completed
168hr the test without any part failures.
500 hour Life test
Reliability Report: SP6330
April 7, 2006
Page 3 of 5
The 240 parts of SP6330 we reintroduced to the second phase of the test, where
the parts again showed successfully completing the 500-hour life test without any
failures.
1000 hour Life test
The 240 parts of the SP6330 were reintroduced to the final phase of the test,
where the parts again successfully completed 1000-hour life test without any shift
on the process parameters.
FIT Rate Calculations
The FIT (failures in time) rate is the predicted number of failures per billion device-
hours. This predicted value is based upon the:
1. Life Test conditions (time and temperature, device quantity and number of failures)
are summarized under HTOL test table.
2. Activation Energy (Ea) of the potential failure modes.
The weighted Activation Energy, E, of observed failure mechanisms of Sipex products
a
has been determined to be 0.8 eV.
Based on the above criteria, the FIT rates at 25°, 55° and 70°C operation at both 60% and
90% confidence levels for the SP6330 product lines have been calculated and are listed
below.
FIT Failure Rates SP6330 Product
Confidence Level
+25°C
1.6
4.1
+55°C
26.6
68.4
+70°C
90.8
233.1
60%
90%
1 FIT = 1 Failure per Billion Device-Hours
MTBF Calculation for SP6330 Product
Confidence Level
+25°C
+55°C
+70°C
60%
90%
6.30E+08
2.46E+08
3.75E+07
1.46E+07
1.10E+07
4.29E+06
Reliability Report: SP6330
April 7, 2006
Page 4 of 5
ESD Testing
HBM ESD Testing - 5 units from each of three lots were subjected to 4000 V Human
Body Model (HBM) ESD stress. Eachpin was subjected to three positive and three
negative pulses with respect to ground. All units passed testing after ESD stress.
Latch-up Testing - 5 units from each of three lots were subjected to latch-up testing at +/-
100mA. All units passed.
Reliability Report: SP6330
April 7, 2006
Page 5 of 5
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