SP6655_技术文档

®

SP6655

High Efficiency 400mA Synchronous Buck Regulator

Ideal for portable designs powered with Li Ion battery

FEATURES

P_VIN

VIN

10

9

1

2

3

4

5

LX

P

■ 98% Efficiency Possible

■ Small 10-Pin DFN Package

■ Ultra-low 20µA Quiescent Current

■ 625mA Inductor Peak Current Limit

■ Guaranteed Minimum 400mA Output

Current

SP6655

GND

BLON

D1

8

GND

10 Pin DFN

7

V

OUT

6

D0

FB

■ 2.7V to 5.5V Input Voltage Range

■ Output Adjustable Down to 1.0V

■ 100% Duty Ratio Low Dropout

Operation

■ 80µA Light Load Quiescent Current in

Dropout

Now Available in Lead Free Packaging

APPLICATIONS

■ Cell Phones

■ PDA's

■ DSC's

■ MP3 Players

■ USB Devices

■ Point of Use Power

DESCRIPTION

The SP6655 is a 400mA synchronous buck regulator which is ideal for portable applications that

useaLi-Ionor3cellalkaline/NiCD/NiMHinput. TheSP6655’sproprietarycontrolloop, 20µAlight

loadquiescentcurrent,and0.3Ωpowerswitchesprovideexcellentefficiencyacrossawiderange

of output currents. As the input battery supply decreases towards the output voltage the SP6655

seamlessly transitions into 100% duty ratio operation further extending useful battery life. The

SP6655 is protected against overload and short circuit conditions with a precise inductor peak

current limit. Other features include programmable under voltage lockout and low battery

detection, externally programmed output voltage down to 1.0V, logic level shutdown control, and

140°C over temperature shutdown.

TYPICAL APPLICATION SCHEMATIC

2.7V to 5.5V Input

L1

V_OUT

10µH

400mA

VI

10Ω

VO

C_IN

R_VIN

SP6655

C_OUT

LX

P_VIN

10µF

CV_IN

10µF

P_GND

V_IN

1M

1µF

CF

22pF

GND

V_OUT

BLON

D1

R_F

BLON

D1

D0

FB

R_I

200K

Date: 7/12/04

SP6655 High Efficiency 400mA Synchronous Buck Regulator

1

ABSOLUTE MAXIMUM RATINGS

These are stress ratings only and functional operation of the device at

these ratings or any other above those indicated in the operation

sections of the specifications below is not implied. Exposure to

absolute maximum rating conditions for extended periods of time may

affect reliability.

PV_IN,V_IN.............................................................................................. 6V

All other pins .............................................................. -0.3V to V_IN+0.3V

PV_IN, P_GND, LX current ........................................................................ 2A

Storage Temperature .................................................. -65 °C to 150 °C

Operating Temperature ................................................. -40°C to +85°C

Lead Temperature (Soldering, 10 sec) ....................................... 300 °C

ELECTRICAL CHARACTERISTICS

V_IN=UV_IN=V_SDN=3.6V, V_OUT=V_FB, I_O= 0mA, T_AMB= -40°C to +85°C, typical values at 27°C unless otherwise noted.

PARAMETER

MIN

TYP

MAX UNITS CONDITIONS

Input Voltage Operating

Range

UVLO

5.5

V

Result of I_Qmeasurement at V_IN=PV_IN=5.5V

Minimum Output Voltage

FB Set Voltage, Vr

1.0

0.784

V

0.800

0.816

25°C, I_O=200mA Close Loop. L_I= 10µH,

C_OUT= 22µF

Overall Accuracy

(-40°C to 85°C)

(0°C to 70°C)

Measured at V_IN=5.5V, no load and

V_IN=3.6V, 200mA load, Close Loop

±5

±4

%

On-Time Constant - K_ON

1.5

1.6

2.25

2.4

3.0

V*µs

Close Loop, L_I= 10µH,C_OUT= 22µF

Min, T_ON=K_ON/(V_IN-V_OUT

)

Off-Time Constant - K_OFF

Min, T_OFF=K_OFF/V_OUT

3.2

Inductor current limit tripped, VFB=0.5V

Measured at V_OUT=1V

Off-Time Blanking

Turn On Time

PMOS Switch Resistance

NMOS Switch Resistance

Inductor Current Limit

Power Efficiency

100

200

0.3

625

96

92

500

ns

µs

Ω

mA

%

400

0.6

400mA Load

I_PMOS= 200mA

I_NMOS= 200mA

VFB=0.5V

V_OUT=2.5V, I_O=200mA

V_OUT=3.3V, I_O=400mA

500

400

750

Minimum Guaranteed Load

Current

mA

V_INQuiescent Current

V_INShutdown Current

V_OUTQuiescent Current

V_OUTShutdown Current

20

1

2

30

500

5

µA

nA

µA

nA

V_OUT=3.3V, V_IN=3.6V and V_IN= 5.5V

D1=D0=0V

V_OUT= 3.3V

1

500

D1=D0=0V

UVLO

Undervoltage Lockout

Threshold, V_INfalling

2.55

2.70

2.85

2.70

2.85

3.00

2.85

3.00

3.15

D1=0V, D0=V_IN

D1=V_IN, D0=0V

D1=V_IN, D0=V_IN

V

UVLO hysteresis

40

300

9

mV

V

µA

°C

Battlo Trip Voltage, V_INfalling

Battlo Trip Voltage Hysteresis

BLON Low Output Voltage

BLON Leakage Current

Over-Temperature

Rising Trip Point

265

335

Measured as V_IN-V_OUT

0.4

1

V_IN=3.3V, I_SINK=1mA

V_BLON=3.6V

140

Over-Temperature Hysteresis

D1,D0 Leakage Current

14

1

°C

nA

500

D1,D0 Input Threshold Voltage

0.60

0.90

1.25

1

3

V

nA

High to Low Transition

Low to High Transition

FB=1V

D1,D0=0V, V_IN=3.6V

LX=0V,LX=V_IN+0.2V

1.8

100

5

FB Leakage Current

LX Leakage

µA

Date: 7/12/04

SP6655 High Efficiency 400mA Synchronous Buck Regulator

2

PIN DESCRIPTION

PIN NUMBER

PIN NAME

P_VIN

DESCRIPTION

1

2

3

Input voltage power pin. Inductor charging current passes through this pin.

Internal supply voltage. Control circuitry powered from this pin.

V_IN

BLON

Open drain battery low output. (V_IN-V_O) less than 300mV pulls this

node to ground. (V_IN-V_O) above threshold, this node is open.

4

5

6

D1

D0

FB

Digital mode control input. See table I for definition.

External feedback network input connection. Connect a resistor from

FB to ground and FB to V_OUTto set the output voltage. This pin

regulates to the internal bandgap reference voltage of 0.8V.

7

V_OUT

Output voltage sense pin. Used by the timing circuit to set minimum on

and off times.

8

9

GND

P_GND

LX

Internal ground pin. Control circuitry returns current to this pin.

Power ground pin. Synchronous rectifier current returns through this pin.

10

Inductor switching node. Inductor tied between this pin and the output

capacitor to create regulated output voltage.

D1

0

D0

0

Shutdown. All internal circuitry is disabled and the power switches are opened.

Device enabled, falling UVLO threshold =2.70V

0

1

0

Device enabled, falling UVLO threshold =2.85V

1

Device enabled, falling UVLO threshold =3.00V

Table 1. Operating Mode Definition

FUNCTIONAL DIAGRAM

P_VIN

V_OUT

V_IN

DRVON

VOLOW

MIN Ton

T_ONOVER

Internal Supply

T_ONOVER

Min T_ON

=

K_ON/(V_IN

-

V_OUT

)

Min Ton

OVR_I

M

1

Vos

VOLOW

REF'

DRVON

+

-

REF

+

-

+

C

ILIM/M

R

Q

_

Q

C

DRIVER

-

V_RAMP

S

FB'

+

-

FB

OVR_I

RST

DRVON

LX

+

REF

UVLO

Zero_X

D0

D1

C

One-Shot

=100ns

Ref

-

TSD

ILIM/M

Block

P_GND

BLANK

T_OFF

=

300mV

K_OFF/V_OUT

OVR_I

BLON

-

+

V_OUT

V_IN

+

-

GND

C

DRVON

BLANK

BLANK = T_BLANK(=100ns) or T_OFF= K_OFF/V_OUT

UVLO

Date: 7/12/04

SP6655 High Efficiency 400mA Synchronous Buck Regulator

3

TYPICAL PERFORMANCE CHARACTERISTICS

Refer to the typical application schematic, T_AMB= +27°C

100

95

90

85

80

100

95

90

85

75

70

65

60

80

75

Vi=3.6V

Vi=3.9V

Vi=4.2V

Vi=5.0V

0.1

1.0

10.0

ILoad (mA)

100.0

1000.0

0.1

1.0

10.0

100.0

1000.0

ILoad (mA)

Efficiency vs. Load, V_OUT=3.3V, V_IN=3.6V

Efficiency vs Load, V_OUT= 1.5V

3.45

1.55

1.53

Vi=3.6V

Vi=3.9V

Vi=4.2V

Vi=5.0V

Vi=3.9V

Vi=4.2V

Vi=5.0V

3.40

3.35

3.30

1.51

1.49

3.25

3.20

1.47

1.45

3.15

0

100

200

300

400

500

0

100

200

300

400

500

ILoad (mA)

Line/Load Rejection, V_OUT= 3.3V

Line/Load Rejection, V_OUT= 1.5V

500

400

300

50

40

30

Tamb = 85°C

Tamb = 25°C

Tamb = -40°C

Tamb = 85°C

Tamb = 25°C

Tamb = -40°C

200

100

0

20

10

0

3.0

3.3

3.6

3.9

4.2

3.0

3.3

3.6

3.9

4.2

Vin (V)

No Load Battery Current, V_OUT=3.3V

No Load Battery Current, V_OUT=1.5V

Date: 7/12/04

SP6655 High Efficiency 400mA Synchronous Buck Regulator

4

TYPICAL PERFORMANCE CHARACTERISTICS

Refer to the typical application schematic, T_AMB= +27°C

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

3.6

3.9

4.2

4.5

4.8

5.1

5.4

3.0 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4

Vin (V)

K_ONvs V_IN, V_OUT=3.3V

K_ONvs V_IN, V_OUT=1.5V

3.5

3.0

2.5

2.0

3.5

3.0

2.5

2.0

1.5

1.0

1.5

1.0

0.5

0.0

0.5

0.0

3.6

3.9

4.2

4.5

4.8

5.1

5.4

3.0

3.3

3.6

3.9

4.2

4.5

4.8

5.1

5.4

Vin (V)

K_OFFvs V_IN, V_OUT=3.3V

K

_OFFvs V_IN, V_OUT=1.5V

700.0

600.0

500.0

700.0

600.0

500.0

400.0

300.0

400.0

300.0

200.0

100.0

0.0

200.0

100.0

Vout = 3.3V

Measured

Vout = 1.5V

Measured

Vout = 1.5V

Calculated

Vout = 3.3V

Calculated

0.0

3.5

3.4

3.8

4.2

4.6

5.0

4.0

4.5

5.0

Vin (V)

Ripple Frequency vs. V_IN, I_OUT=0.4A, V_OUT=3.3V

Ripple Frequency vs. V_IN, I_OUT=0.4A, V_OUT=1.5V

Date: 7/12/04

SP6655 High Efficiency 400mA Synchronous Buck Regulator

5

TYPICAL PERFORMANCE CHARACTERISTICS

Refer to the typical application schematic, T_AMB= +27°C

Plot Overlay

1: Startupawg (APU #16)

2: S1 Fbx data (APU #10)

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

0.25

0.50

0.75

1.00

1.25

1.50

Time in Milliseconds

Turn on Time, 400mA Load

Date: 7/12/04

SP6655 High Efficiency 400mA Synchronous Buck Regulator

6

TYPICAL PERFORMANCE CHARACTERISTICS

Refer to the typical application schematic, T_AMB= +27°C

CH.1=V_IN

5.0V/DIV.

CH.1=V_SHDN

5.0V/DIV.

CH.2=V_OUT

0.5V/DIV.

CH.2=V_OUT

2.0V/DIV.

CH.4=I_LX

0.5A/DIV.

CH.4=I_IN

0.5A/DIV.

V

_INStart up,V_IN=4.2V, I_OUT=0.4A, V_OUT=1.5V

V_INStart up, V_IN=4.2V, I_OUT=0.4A, V_OUT=3.3V

Load Step, V_IN=4.2V, I_OUT=0.1A to 0.4A, V_OUT=3.3V

Load Step, V_IN=4.2V, I_OUT=0.1A to 0.4A, V_OUT=1.5V

CH.1=V_SHDN

5.0V/DIV.

CH.1=V_SHDN

5.0V/DIV.

CH.2=V_OUT

2.0V/DIV.

CH.2=V_OUT

0.5V/DIV.

CH.4=I_LX

0.5A/DIV.

CH.4=I_LX

0.5A/DIV.

Start up from SHDN, V_IN=5V ,I_OUT=0.4A, V_OUT=3.3V

Start up from SHDN, V_IN=5V, I_OUT=0.4A, V_OUT=1.5V

Date: 7/12/04

SP6655 High Efficiency 400mA Synchronous Buck Regulator

7

THEORY OF OPERATION

RAMP: CCM OPERATION

The SP6655 is a high efficiency synchronous

buck regulator with an input voltage range of

+2.7V to +5.5Vand an output that is adjustable

between +1.0V and V_IN. The SP6655 features a

unique on-time control loop that runs in discon-

tinuous conduction mode (DCM) or continuous

conduction mode (CCM) using synchronous

rectification. Other features include over-tem-

peratureshutdown,over-currentprotection,digi-

tally controlled enable and under-voltage lock-

out, a battery low indicator, and an external

feedback pin.

DRVON

I(L1)

FB’

REF, FB

V

OS

REF’

The SP6655 operates with a light load quiescent

current of 20µA using a 0.3Ω PMOS main

switch and a 0.3Ω NMOS synchronous switch.

It operates with excellent efficiency across the

entire load range, making it an ideal solution for

battery powered applications and low current

step-down conversions. The part smoothly tran-

sitionsintoa 100%dutycycle underheavyload/

low input voltage conditions.

RAMP: DCM OPERATION

DRVON

I(L1)

FB’

On-Time Control - Charge Phase

REF, FB

V

OS

The SP6655 uses a precision comparator and a

minimum on-time to regulate the output voltage

and control the inductor current under normal

load conditions. As the feedback pin drops be-

low the regulation point, the loop comparator

output goes high and closes the main switch.

The minimum on-timer is triggered, setting a

logic high for the duration defined by:

REF’

ramp voltage (V_RAMPin the functional diagram)

is added to FB and this creates the FB's signal.

This FB signal is applied to the negative termi-

nal of the loop comparator. To the positive

terminal of the loop comparator is applied the

REF voltage of 0.8V plus an offset voltage Vos

to compensate for the DC level of V_RAMPap-

plied to the negative terminal. The result is an

internal ramp with enough negative going offset

(approximately 50mV) to trip the loop com-

parator whenever FB falls below regulation.

K_ON

T_ON

=

V_IN- V_OUT

where:

K_ON= 2.25V*µsec constant

V_IN= V_INpin voltage

V_OUT= V_OUTpin voltage

To accommodate the use of ceramic and other

low ESR capacitors, an open loop ramp is added

to the feedback signal to mimic the inductor

current ripple. The following waveforms de-

scribetheidealrampoperationinbothCCMand

DCM operation.

The output of the loop comparator, a rising

VOLOW, causes a SET if BLANK = 0 and

OVR_I = 0. This starts inductor charging

(DRVON = 1) and starts the minimum on-timer.

The minimum on-timer times out and indicates

DRVON can be reset if the voltage loop is

satisfied. If V_OUTis still below the regulation

In either CCM or DCM, the negative going

Date: 7/12/04

SP6655 High Efficiency 400mA Synchronous Buck Regulator

8

THEORY OF OPERATION

point RESET is held low until V_OUTis above

regulation. Once RESET occurs T_ONminimum

is reset, and the T_OFFone-shot is triggered to

blank the loop comparator from starting a new

charge cycle for a minimum period. This blank-

ing period occurs during the noisy LX transition

to discharge, where spurious comparator states

may occur. For T_OFF> T_BLANKthe loop is in a

discharge or wait state until the loop comparator

starts the next charge cycle by DRVON going

high.

where:

L = Inductor value

I_OUT= Load current

R_CH= PMOS on resistance, 0.3Ω typ.

If the I_OUT* R_CHterm is negligible compared

with(V_IN-V_OUT), theaboveequationsimplifies

to:

K_ON

I_LR

≈

L

Formostapplications,theinductorcurrentripple

controlled by the SP6655 is constant regardless

of input and output voltage. Because the output

voltage ripple is equal to:

If an over current occurs during charge the loop

is interrupted and DRVON is RESET. The off-

time one-shot pulse width is widened to T_OFF

=

K_OFF/ V_OUT, which holds the loop in discharge

for that time. At the end of the off-time the loop

is released and controlled by VOLOW. In this

mannermaximuminductorcurrentiscontrolled

onacycle-by-cyclebasis.AnassertionofUVLO

(undervoltage lockout) or TSD (thermal shut-

down) holds the loop in no-charge until the fault

has ended.

V

_OUT(ripple) = I_LR* R_ESR

where:

R_ESR= ESR of the output capacitor

the output ripple of the SP6655 regulator is

independent of the input and output voltages.

For battery powered applications, where the

batteryvoltagechangessignificantly,theSP6655

providesconstantoutputvoltageripplethrough-

out the battery lifetime. This greatly simplifies

the LC filter design.

On-Time Control - Discharge Phase

The discharge phase follows with the high side

PMOS switch opening and the low side NMOS

switch closing to provide a discharge path for

the inductor current. The decreasing inductor

current and the load current cause the output

voltage to drop. Under normal load conditions

when the inductor current is below the pro-

grammed limit, the off-time will continue until

the output voltage falls below the regulation

threshold, whichinitiatesanewchargecyclevia

the loop comparator.

The maximum loop frequency in CCM is de-

fined by the equation:

(V_IN- V_OUT

)

(V_OUT+ I_OUTR_DC)

*

F_LP

≈

K_ON[V_IN+ I_OUT(R_DC- R_CH)]

*

where:

F_LP= CCM loop frequency

R_DC= NMOS on resistance, 0.3Ω typ.

The inductor current “floats” in continuous con-

duction mode. During this mode the inductor

peak current is below the programmed limit and

thevalleycurrentisabovezero. Thisistosatisfy

load currents that are greater than half the mini-

mum current ripple. The current ripple, I_LR, is

defined by the equation:

Ignoring conduction losses simplifies the loop

frequency to:

1

V_OUT

V_IN

F_LP

≈

*

* (V_IN- V_OUT)

K_ON

AND’ing the loop comparator and the on-timer

reduces the switching frequency for load cur-

rentsbelowhalftheinductorripplecurrent. This

increases light load efficiency. The minimum

on-time insures that the inductor current ripple

K_ON

L

V_IN- V_OUT- I_OUTR_CH

*

I_LR

≈

*

V_IN- V_OUT

Date: 7/12/04

SP6655 High Efficiency 400mA Synchronous Buck Regulator

9

THEORY OF OPERATION

age drop of the PMOS passing the inductor

current with a second voltage drop representing

the maximum allowable inductor current. As

the two voltages become equal, the over-current

comparator triggers a minimum off-time one

shot. The off-time one shot forces the loop into

the discharge phase for a minimum T_OFFtime

causing the inductor current to decrease. At the

end of the off-time, loop control is handed back

to the AND’d on-time signal. If the output

voltage is still low, charging begins until the

output is in regulation or the current limit has

been reached again. During startup and over-

load conditions, the converter behaves like a

current source at the programmed limit minus

half the current ripple. The minimum T_OFFis

controlled by the equation:

is a minimum of K_ON/L, more than the load

current demands. The converter goes in to a

standard pulse frequency modulation (PFM)

mode where the switching frequency is propor-

tional to the load current.

Low Dropout and Load Transient Operation

AND’ingtheloopcomparatoralsoincreasesthe

duty ratio past the ideal D= V_OUT/V_INup to and

including 100%. Under a light to heavy load

transient, the loop comparator will hold the

main switch on longer than the minimum on

timer until the output is brought back into regu-

lation.

Also, as the input voltage supply drops down

close to the output voltage, the main MOSFET

resistance loss will dictate a much higher duty

ratio to regulate the output. Eventually as the

input voltage drops low enough, the output

voltage will follow, causing the loop compara-

tor to hold the converter at 100% duty cycle.

K_OFF

T_{OFF (MIN)}

=

V_OUT

Under-Voltage Lockout

This mode is critical in extending battery life

when the output voltage is at or above the

minimum usable input voltage. The dropout

voltage is the minimum (V_IN-V_OUT) below

which the output regulation cannot be main-

tained. The dropout voltage of SP6655 is equal

to I_L* (0.3Ω+ R_L1) where 0.3Ω is the typical

R_DS(ON)of the P-Channel MOSFET and R_Lis

the DC resistance of the inductor.

The SP6655 is equipped with a programmable

under-voltage lockout to protect the input bat-

tery source from excessive currents when sub-

stantially discharged. When the input supply is

belowtheUVLOthresholdbothpowerswitches

are open to prevent inductor current from flow-

ing. The three levels of falling input voltage

UVLO threshold are shown in Table 1, with a

typical hysteresis of 120mV to prevent chatter-

ing due to the impedance of the input source.

During UVLO, BLON is forced low.

The SP6655 has been designed to operate in

dropout with a light load Iq of only 80µA. The

on-time control circuit seamlessly operates the

converter between CCM, DCM, and low drop-

out modes without the need for compensation.

Theconverter’stransientresponseisquicksince

thereisnocompensatederroramplifierintheloop.

Under-Current Detection

The synchronous rectifier is comprised of an

inductor discharge switch, a voltage compara-

tor, and a driver latch. During the off-time,

positive inductor current flows into the PGND

pin 9 through the low side NMOS switch to LX

pin 10, through the inductor and the output

capacitor, and back to pin 9. The comparator

monitors the voltage drop across the discharge

NMOS.Astheinductorcurrentapproacheszero,

the channel voltage sign goes from negative to

positive, causing the comparator to trigger the

Inductor Over-Current Protection

To reduce the light load dropout Iq, the SP6655

over-current system is only enabled when I_L1

>

400mA. The inductor over-current protection

circuitry is programmed to limit the peak induc-

tor current to 0.625A. This is done during the

on-time by comparing the source to drain volt-

Date: 7/12/04

SP6655 High Efficiency 400mA Synchronous Buck Regulator

10

THEORY OF OPERATION

driver latch and open the switch to prevent

inductor current reversal. This circuit along

with the on-timer puts the converter into PFM

mode and improves light load efficiency when

the load current is less than half the inductor

ripple current defined by K_ON/L.

circuitrytore-establishitself. Powerconversion

begins with the assertion of the internal refer-

ence ready signal which occurs approximately

150µs after the enable signal is received.

Battery Low Indicator

The BLON function is a differential measure-

ment of (V_IN-V_OUT) which causes the open

drain NMOS on pin 3 to sink current to ground

when (V_IN-V_OUT) < 300mV. Tying a resistor

from pin 3 to V_INor V_OUTcreates a logic level

battery low indicator. A low bandwidth com-

paratorand3%hysteresisfiltertheinputvoltage

ripple to prevent noisy transitions at the thresh

old. BLON is forced Low when in UVLO.

Thermal Shutdown

The converter will open both power switches if

the die junction temperature rises above 140°C.

The die must cool down below 126°C before the

regulator is re-enabled. This feature protects the

SP6655 and surrounding circuitry from exces-

sive power dissipation due to fault conditions.

Shutdown/Enable Control

External Feedback Pin

The D0, D1 pins 4,5 of the device are logic level

control pins that according to Table 1 shut down

the converter when both are a logic low, or

enables the converter when either are a logic

high. When the converter is shut down, the

power switches are opened and all circuit bias-

ing is extinguished leaving only junction leak-

age currents on supply pins 1 and 2. After pins

4 or 5 are brought high to enable the converter,

there is a turn on delay to allow the regulator

The FB pin 6 is compared to an internal refer-

ence voltage of 0.8V to regulate the SP6655

output. The output voltage can be externally

programmed within the range +1.0V to +5.0V

by tying a resistor from FB to ground and FB to

V_OUT(pin7). See the applications section for

resistor selection information.

APPLICATION INFORMATION

Inductor Selection

would be fairly constant for different input and

output voltages, simplifying the selection of com-

ponents for the SP6655 power circuit. Other

inductor values could be selected, as shown in

Table 2 Components Selection. Using a larger

value than 10µH in an attempt to reduce output

voltageripplewouldreduceinductorcurrentripple

and may not produce as stable an output ripple.

For larger inductors with the SP6655, which has

a peak inductor current of 0.625A, most 15µH

or 22µH inductors would have to be larger

physical sizes, limiting their use in small por-

table applications. Smaller values like 10µH

would more easily meet the 0.625A limit and

come in small case sizes, and the increased

The SP6655 uses a specially adapted minimum

on-time control of regulation utilizing a preci-

sion comparator and bandgap reference. This

adaptive minimum on-time control has the ad-

vantage of setting a constant current ripple for a

giveninductorsize. Fromtheoperationssection

it has been shown:

K_ON

Inductor Current Ripple, I_LR

≈

L

For the typical SP6655 application circuit with

inductor size of 10µH, and K_ONof 2V*µsec, the

SP6655currentripplewouldbeabout200mA,and

Date: 7/12/04

SP6655 High Efficiency 400mA Synchronous Buck Regulator

11

APPLICATION INFORMATION

inductor current ripple of almost 200mA would

produce very stable regulation and fast load

transient response at the expense of slightly

reduced efficiency.

For the 10µF Ceramic Output Capacitor with

0.003ΩESR,anda10µHinductoryielding200mA

inductor current ripple I_LR, the V_OUTripple would

be 0.6mVpp. Since 0.6mV is a very small signal

level, the actual value would probably be as large

as 10mV due to noise and layout issues, but this

illustrates that the SP6655 output ripple can be

very low indeed. To improve stability, a small

ceramic capacitor, C_F= 22pF should be paralleled

withthefeedbackvoltagedividerRF, asshownon

the typical application schematic on page 1. An-

other function of the output capacitance is to hold

uptheoutputvoltageduringtheloadtransientsand

prevent excessive overshoot and undershoot. The

typical performance characteristics curves show

very good load step transient response for the

SP6655 with the recommended output capaci-

tance of 10µF ceramic.

Other inductor parameters are important: the in-

ductorcurrentratingandtheDCresistance. When

the current through the inductor reaches the level

of I_SAT, the inductance drops to 70% of the

nominal value. This non-linear change can cause

stability problems or excessive fluctuation in in-

ductor current ripple. To avoid this, the inductor

should be selected with saturation current at least

equal to the maximum output current of the con-

verter plus half the inductor current ripple. To

provide the best performance in dynamic condi-

tionssuchasstart-upandloadtransients,inductors

should be chosen with saturation current close to

the SP6655 inductor current limit of 0.625A.

The input capacitor will reduce the peak current

drawn from the battery, improve efficiency and

significantly reduce high frequency noises in-

duced by a switching power supply. The typical

input capacitor for the SP6655 is 10µF ceramic.

Thesecapacitorswillprovidegoodhighfrequency

bypassing and their low ESR will reduce resistive

lossesforhigherefficiency. AnRCfilterisrecom-

mended for the V_INpin 2 to effectively reduce the

noise for the ICs analog supply rail which powers

sensitive circuits. This time constant needs to be at

least 5 times greater than the switching period,

which is calculated as 1/FLP during the CCM

mode. The typical application schematic uses the

valuesofR_VIN=10ΩandC_VIN=1µFtomeetthese

requirements.

DC resistance, another important inductor charac-

teristic, directly affects the efficiency of the con-

verter, so inductors with minimum DC resistance

should be chosen for high efficiency designs.

Recommended inductors with low DC resistance

are listed in Table 2. Preferred inductors for on

board power supplies with the SP6655 are mag-

neticallyshieldedtypestominimizeradiatedmag-

netic field emissions.

Capacitor Selection

The SP6655 has been designed to work uith very

low ESR output capacitors (listed in Table 2

ComponentSelection)whichforthetypicalappli-

cation circuit are 10µF ceramic capacitors. These

capacitors combine small size, low ESR and good

value.ToregulatetheoutputwithlowESRcapaci-

tors of 0.01Ω or less, an internal ramp voltage

V_RAMPhas been added to the FB signal to reliably

trip the loop comparator (as described in the Op-

erations section).

Output ripple for a buck regulator is determined

mostly by output capacitor ESR, which for the

SP6655withaconstantinductorcurrentripplecan

be expressed as:

V_OUT(ripple) = I_LRR_ESR

*

Date: 7/12/04

SP6655 High Efficiency 400mA Synchronous Buck Regulator

12

APPLICATION INFORMATION

INDUCTORS SURFACE MOUNT

Inductor Specification

Inductance

(µH)

Manufacturer/Part No.

Series R Ω

I_SAT(A)

Size

Inductor Type

Manufacturer

Website

LxW(mm)

3.2 x 1.6

5.6 x 5.2

6.0 x 5.4

3.2 x 1.6

5.6 x 5.2

6.0 x 5.4

Ht. (mm)

1.8

10

22

Murata LQH32CN100K11

TDK RLF5018T-100MR94

Coilcraft LPO6013-103K

Murata LQH32CN220K21

TDK RLF5018T- 220MR63

Coilcraft LPO6013-103

0.300

0.056

0.300

0.710

0.130

0.520

0.45

0.94

0.70

0.25

0.63

0.45

Unshielded Ferrite Core murata.com

Shielded Ferrite Core tdk.com

Unshielded Ferrite Core coilcraft.com

2.0

1.3

1.8

Unshielded Ferrite Core

Shielded Ferrite Core

murata.com

tdk.com

2.0

1.3

Unshielded Ferrite Core coilcraft.com

CAPACITORS - SURFACE MOUNT

Capacitor Specification

Capacitance

Manufacturer/Part No.

ESR

RippleCurrent

Size

Voltage

(V)

Capacitor Type

Manufacturer

Website

(µF)

Ω (max) (A) @ 45°C LxW(mm) Ht. (mm)

10

TDK C2012X5R0J106M

0.003

1.00

2.0 x 1.2

1.25

6.3

X5R Ceramic

POSCAP

tdk.com

Murata GRM21BR60J106KE01 0.003

TDK C2012X5R0J475M 0.005

Murata GRM21BR60J475KE01 0.005

murata.com

tdk.com

4.7

X5R Ceramic

POSCAP

murata.com

Note: Components highlighted in bold are those used on the SP6655 Evaluation Board.

Table 2 Component Selection

Output Voltage Program

is half the 200mA inductor current ripple), the

output ripple frequency will be fairly constant.

Fromtheoperationssection,thismaximumloop

frequency in continuous conduction mode is:

The output voltage is programmed by the external

divider, as shown in the typical application circuit

on page 1. First pick a value for R_Ithat is no larger

than 300K. Too large a value of R_Iwill reduce the

AC voltage seen by the loop comparator since the

internal FB pin capacitance can form a low pass

filter with R_Fin parallel with R_I. The formula for

R_Fwith a given R_Iand output voltage is:

1

V_OUT

V_IN

_*(V_IN- V_OUT

)

F_LP

≈

*

K_ON

Data for loop frequency, as measured from

output voltage ripple frequency, can be found in

the typical performance curves.

V_OUT

R_F= (

- 1 ) • R_I

0.8V

Layout Considerations

Output Voltage Ripple Frequency

Proper layout of the power and control circuits is

necessary in a switching power supply to obtain

good output regulation with stability and a mini-

mum of output noise. The SP6655 application

circuit can be made very small and reside close to

the IC for best performance and solution size, as

long as some layout techniques are taken into

consideration. To avoid excessive interference

betweentheSP6655highfrequencyconverterand

the other active components on the board, some

An important consideration in a power supply

application is the frequency value of the output

ripple.GiventhecontroltechniqueoftheSP6655

(as described in the operations section), the

frequency of the output ripple will vary when in

light to moderate load in the discontinuous or

PFM mode. For moderate to heavy loads greater

than about 100mA inductor current ripple, (for

thetypical10µHinductorapplicationon100mA

Date: 7/12/04

SP6655 High Efficiency 400mA Synchronous Buck Regulator

13

APPLICATION INFORMATION

rules should be followed. Refer to the typical

application schematic on page 1 and the sample

PCB layout shown in the following figures to

illustrate how to layout a SP6655 power supply.

Power loops on the input and output of the con-

verter should be laid out with the shortest and

widest traces possible. The longer and narrower

the trace, the higher the resistance and inductance

it will have. The length of traces in series with the

capacitors increases its ESR and ESL and reduces

their effectiveness at high frequencies. Therefore,

putthe1µFbypasscapacitorasclosetotheV_INand

GND pins of the converter as possible, the 10µF

Avoid injecting noise into the sensitive part of

circuit via the ground plane. Input and output

capacitorsconducthighfrequencycurrentthrough

the ground plane. Separate the control and power

grounds and connect them together at a single

point. Power ground plane is shown in the figure

titled PCB top sample layout and connects the

ground of the C_OUTcapacitor to the ground of the

C_INclose to the P_VINpin and the 10µF output

capacitor as close to the inductor as possible. The

external voltage feedback network R_F, R_Iand

feedforward capacitor C_Fshould be placed very

close to the FB pin. Any noise traces like the LX

pinshouldbekeptawayfromthevoltagefeedback

network and separated from it by using power

ground copper to minimize EMI.

C_INcapacitor and then to the PGND pin 10. The

control ground plane connects from pin 9 GND to

ground of the C_VINcapacitor and the R_Iground

returnofthefeedbackresistor. Thesetwoseparate

control and power ground planes come together in

the figure titled PCB top sample layout where

SP6655 pin 9 GND is connected to pin 10 PGND.

SP6655 Component Sample Layout

SP6655 PC Layout Top Side

SP6655 PC Layout Bottom Side

Date: 7/12/04

SP6655 High Efficiency 400mA Synchronous Buck Regulator

14

PACKAGE: 10 PIN DFN

Bottom View

Top View

D

b

e

D/2

1

2

E/2

E2

E

K

L

Pin 1 identifier to be located within this shaded area.

Terminal #1 Index Area (D/2 * E/2)

D2

A

A1

A3

Side View

DIMENSIONS

Minimum/Maximum

(mm)

10 Pin DFN

(JEDEC MO-229,

VEED-5 VARIATION)

COMMON HEIGHT DIMENSION

SYMBOL

MIN NOM MAX

0.80 0.90 1.00

A

A1

A3

b

D

D2

e

0.02 0.05

0.20 REF

0

0.18

0.25 0.30

3.00 BSC

2.20 2.70

0.50

-

PITCH

3.00 BSC

E

E2

K

1.40

0.20

-

1.75

-

L

0.30 0.40 0.50

10 PIN DFN

Date: 7/12/04

SP6655 High Efficiency 400mA Synchronous Buck Regulator

15

ORDERING INFORMATION

Top Mark Package Type

Part Number

Operating Temperature Range

SP6655ER ............................-40°C to +85°C ............................ SP6655ERYWW ...................... 10 Pin DFN

SP6655ER/TR ......................-40°C to +85°C ............................ SP6655ER/TRYWW ................ 10 Pin DFN

Available in lead free packaging. To order add "-L" suffix to part number.

Example: SP6655ER/TR = standard; SP6655ER-L/TR = lead free

/TR = Tape and Reel

Pack quantity is 3,500 for DFN.

Corporation

ANALOGEXCELLENCE

Sipex Corporation

Headquarters and

Sales Office

233 South Hillview Drive

Milpitas, CA 95035

TEL: (408) 934-7500

FAX: (408) 935-7600

Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the

application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.

Date: 7/12/04

SP6655 High Efficiency 400mA Synchronous Buck Regulator

16


型号：	SP6655
厂家：	SIPEX CORPORATION
描述：	High Efficiency 400mA Synchronous Buck Regulator Ideal for portable designs powered with Li Ion battery 高效率400毫安同步降压稳压器非常适用于便携式的设计与动力锂离子电池稳压器电池射频微波便携式
文件：	总16页 (文件大小：180K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SP6655 [SIPEX]

相关型号：

SP6655EB

SP6655ER

SP6655ER-L

SP6655ER/TR

SP6655ER2

SP6655ER2

SP6655ER2-L

SP6655ER2-L

SP6655ER2-L/TR

SP6655ER2/TR

SP6655EU

SP6655EU-L