SP674AB/LCC [SIPEX]
ADC, Successive Approximation, 12-Bit, 1 Func, Parallel, Word Access, CQCC28, LCC-28;
| 型号： | SP674AB/LCC |
| 厂家： | 
SIPEX CORPORATION |
| 描述： | ADC, Successive Approximation, 12-Bit, 1 Func, Parallel, Word Access, CQCC28, LCC-28 转换器 |
| 文件： | 总14页 (文件大小：157K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HS574A/SP674A
12–Bit Sampling A/D Converters
■ Complete12–bitA/DConverterswithSample–
Hold, Reference, Clock and Tri–state Outputs
■ Low Power Dissipation — 110mW Maximum
■ 12–Bit Linearity Over Temperature
■ Fast Conversion time:
25µs Max (HS574A)
15µs Max (SP674A)
■ Monolithic Construction
DESCRIPTION…
The HS574A/SP674A Series are complete 12–bit successive–approximation A/D converters
integrated on a single die with tri-state output latches, an internal reference, clock and a sample–
hold. They feature 12–bit linearity over temperature, low power dissipation and fast conversion
time. They are available in commercial and military temperature ranges.
STS
28
DB11 DB10
27
DB9
25
DB8
24
DB7
23
DB6
22
DB5
21
DB4
20
DB3
19
DB2
18
DB1
17
DB0 DGND
16 15
26
NIBBLE A
NIBBLE B
NIBBLE C
THREE–STATE BUFFERS AND CONTROL
12–BIT SAR
12–BIT
CAPACITANCE
DAC
COMP
OSC
OFFSET/GAIN
TRIM
REF
CONTROL LOGIC
7.5K
15K
12
7.5K
7.5K
15K
N/C
1
2
4
5
6
7
8
9
10
11
V
13
14
3
V
12/8
CS
A
R/C
CE
V
REF AGND REF
OUT IN
BIP
OFF
10V
IN
20V
IN
LOGIC
0
CC
EE
3
ABSOLUTE MAXIMUM RATINGS
VCC to Digital Common .................................................. 0 to +16.5V
VLOGIC to Digital Common ................................................... 0 to +7V
Analog Common to Digital Common ......................................... ±1V
Control Inputs to Digital Common ................. –0.5V to VLOGIC +0.5V
(CE, CS, A0, 12/8, R/C)
Analog Inputs to Analog Common ...................................... ±16.5V
(REF IN, BIP OFF, 10VIN)
20VIN to Analog Common ........................................................ ±24V
REF OUT ............................................... Indefinite short to common
Momentary short to VCC
Power Dissipation ............................................................. 1000mW
Lead Temperature, Soldering ................................... 300˚C, 10Sec
ΘJ/C ................................................................................... 45˚C/W
MTBF–25˚C Ground Base ................................ 2.915 million hours
MTBF–125˚C Missile Launch ...................... 10.16 thousand hours
CAUTION:
ESD (ElectroStatic Discharge) sensitive
device. Permanent damage may occur on
unconnected devices subject to high energy
electrostatic fields. Unused devices must be
stored in conductive foam or shunts.
Personnel should be properly grounded prior
to handling this device. The protective foam
should be discharged to the destination
socket before devices are removed.
• Inputs exceeding +30% or –30% of FS will cause erratic performance.
SPECIFICATIONS
(Typical @ 25°C with VCC = +15V, VEE = 0V, VLOGIC = +5V unless otherwise noted)
PARAMETER
MIN.
TYP.
MAX.
UNIT
CONDITIONS
RESOLUTION
All models
12
Bits
ANALOG INPUTS
Input Ranges
Bipolar
±5, ±10
0 to +10, 0 to +20
V
V
Unipolar
Input Impedance
10 Volt Input
20 Volt Input
3.75
15
6.25
25
KΩ
KΩ
DIGITAL INPUTS
Logic Inputs CE, CS R/C, AO, 12/8
Logic 1
Logic 0
+2.4
–0.3
+5.5
+0.8
±50
V
V
µA
pF
Current
±0.1
5
0V to +5.5V Input
Capacitance
12/8 Control Input
Hardwire to VLOGIC or DIGITAL COMMON (SP574A only)
DIGITAL OUTPUTS
Logic Outputs DB11–DB0, STS
Logic 1
+2.4
V
V
I
I
SOURCE ≤ 500µA
SINK ≤ 1.6mA
Logic 0
+0.4
Leakage (High Z State)
Capacitance
±40
µA
pF
Data bits only
5
Parallel Data Output Codes
Unipolar
Positive true binary
Bipolar
Positive true offset binary
REFERENCE
Internal
10.00 ±0.1
V
Output Current
2
mA
Note 1
CONVERSION TIME
HS574A
12–Bit Conversion
8–Bit Conversion
SP674A
13
10
25
19
µs
µs
12–Bit Conversion
8–Bit Conversion
9
6
15
11.25
µs
µs
4
SPECIFICATIONS (continued)
(Typical @ 25°C with VCC = +15V, VEE = 0V, VLOGIC = +5V unless otherwise noted)
PARAMETER
MIN.
TYP.
MAX.
UNIT
CONDITIONS
ACCURACY
Linearity Error @ 25°C
–J, –S
–K, –L, –T, –U
Differential Linearity Error
–J, –S
±1.0
±0.5
LSB
LSB
@ 25°C and TMIN to TMAX
@ 25°C and TMIN to TMAX
Note 2
@ 25°C
TMIN to TMAX
@ 25°C
TMIN to TMAX
Note3
11
11
12
12
Bits
Bits
Bits
Bits
–K, –L, –T, –U
Offset
Unipolar
±2
LSB
Bipolar
–J, –S
–K, –L, –T, –U
Full Scale (Gain) Error
±10
±4
LSB
LSB
% of full scale; TMIN to TMAX
Note 4
±0.3
±0.5
±0.22
±0.4
±0.12
±0.35
±0.05
±0.8
±0.5
±0.6
±0.25
±0.4
±0.12
%FS
%FS
%FS
%FS
%FS
%FS
%FS
%FS
%FS
%FS
%FS
%FS
%FS
–J
No adjustment @ 25°C
With adjustment @ 25°C
No adjustment @ 25°C
With adjustment @ 25°C
No adjustment @ 25°C
With adjustment @ 25°C
No adjustment @ 25°C
With adjustment @ 25°C
No adjustment @ 25°C
With adjustment @ 25°C
No adjustment @ 25°C
With adjustment @ 25°C
–K
–L
–S
–T
–U
STABILITY
Unipolar Offset
–J
±10
±5
±2.5
ppm/°C
ppm/°C
ppm/°C
TMIN to TMAX
TMIN to TMAX
TMIN to TMAX
–K, –L, –S
–T, –U
Bipolar Offset
–J, –S
±10
±5
±2.5
ppm/°C
ppm/°C
ppm/°C
TMIN to TMAX
TMIN to TMAX
TMIN to TMAX
–K, –L, –T
–U
Gain (Scale Factor)
–J, –S
±50
±25
±10
ppm/°C
ppm/°C
ppm/°C
TMIN to TMAX
TMIN to TMAX
TMIN to TMAX
–K, –T
–L, –U
PSRR
VLOGIC
VCC
±0.5
LSB
+4.5V ≤ VLOGIC ≤ +5.5V
Note 5
–J, –S
–K, –L, –T, –U
±2
±1
LSB
LSB
POWER REQUIREMENTS
VLOGIC
ILOGIC
+4.5
+5.5
V
HS574A
SP674A
VCC
1
1
3
3
mA
mA
V
+11.4
+16.5
ICC
HS574A
SP674A
7
7
9
9
mA
mA
5
SPECIFICATIONS (continued)
(Typical @ 25°C with VCC = +15V, VEE = 0V, VLOGIC = +5V unless otherwise noted)
PARAMETER
Power Dissipation
HS574A
MIN.
TYP.
MAX.
UNIT
CONDITIONS
110
110
150
150
mW
mW
SP674A
ENVIRONMENTAL
Operating Temperature Range
–J, –K, –L
0
–55
+70
+125
°C
°C
–S, –T, –U
Storage Temperature Range
–J, –K, –L
–40
–65
+85
+150
°C
°C
–A, –S, –T, –U
Notes:
1.
Available for external loads. External load should not change during conversion. When supplying an
external load and operating on a +12V supply, a buffer amplifier must be provided for the reference
output.
2.
3.
4.
5.
6.
Minimum resolution for which no missing codes are guaranteed.
Externally adjustable to zero. See Calibration information.
Fixed 50Ω resistor between REF OUT and REF IN.
+13.5V ≤ VCC ≤ +16.5V or +11.4V ≤ VCC ≤ +12.6V.
Specifications are identical for all models unless otherwise noted.
PIN ASSIGNMENTS…
PIN FUNCTION
PIN FUNCTION
1
2
VLOGIC
12/8
28
27
26
25
24
23
22
21
20
19
18
17
16
15
STS
DB11(MSB)
DB10
3
CS
4
A0
DB9
5
R/C
DB8
6
CE
DB7
7
VCC
DB6
8
REF OUT
ANA GND(AC)
REF IN
N/C*
DB5
9
DB4
10
11
12
13
14
DB3
DB2
BIP OFF
10VIN
20VIN
DB1
DB0(LSB)
DIG. GND
*HS574A – This pin is not connected to the device; it
can be tied to –15V, ground, or left floating.
*SP674A – This pin is not connected to the device; VEE
is generated internally.
6
the LSB at the beginning of the conversion cycle
toprovideanoutputvoltagefromtheCDACthat
is equal to the input signal voltage (which is
divided by the input voltage divider network).
Thecomparatordetermineswhethertheaddition
ofeachsuccessively–weightedbitvoltagecauses
theCDACoutputvoltagesummationtobegreater
or less than the input voltage; if the sum is less,
the bit is left on; if more, the bit is turned off.
After testing all the bits, the SAR contains a 12–
bit binary code which accurately represents the
input signal to within ±1⁄2 LSB.
FEATURES…
The HS574A/SP674A feature standard bipolar
and unipolar input ranges of 10V and 20V. Input
ranges are controlled by a bipolar offset pin and
laser-trimmed for specified linearity, gain and
offset accuracy. Power requirements are +5V
and +12V to +15V with a maximum dissipation
of 150mW at the specified voltages. Conversion
times of 8µs, 10µs, 15µs and 25µs are available,
asareunitswith10,25or50ppm/°Ctemperature
coefficients for flexible matching to specific
application requirements.
Theinternalreferenceprovidesthevoltagerefer-
ence to the CDAC with excellent stability over
temperature and time. The reference is trimmed
to 10.00 Volts ±1% and can supply up to 2mA to
an external load in addition to that required to
drive the reference input resistor (1mA) and
offset resistor (1mA) when operating with ±15V
supplies. If the HS574A/SP674A is used with
±12V supplies, or if external current must be
supplied over the full temperature range, an
external buffer amplifier is recommended. Any
externalloadonthe HS574A/SP674Areference
must remain constant during conversion.
The HS574A/SP674A are available in six prod-
uct grades for each conversion time. The –J, –K
and –L models are specified over 0˚C to + 70˚C
commercial temperature range; the –S, –T and –
Umodelsarespecifiedoverthe–55˚Cto+125˚C
military temperature range. Processing in accor-
dance with MIL–STD–883C is also available.
The HS574A/SP674A are packaged in a 28–pin
CerDIP. Please consult the factory for other
packaging options.
CIRCUIT OPERATION…
The HS574A/SP674A are complete 12–bit ana-
log-to-digital converters with integral voltage
reference, comparator, successive–approxima-
tion register (SAR), sample–and–hold, clock,
output buffers and control circuitry. The high
level of integration of the HS574A/SP674A
means they require few external components.
The sample and hold is a default function by
virtue of the CDAC architecture. Therefore the
majority of the S/H specifications are included
within the A/D specifications.
Sample–and–Hold Function
Although there is no sample-and-hold circuit in
the classical sense, the sampling nature of the
capacitive DAC makes the HS574A/SP674A
appear to have a built in sample and hold. This
sample and hold action substantially increases
the usefulness of the HS574A/SP674Aover that
of similar competing devices.
WhenthecontrolsectionoftheHS574A/SP674A
initiates a conversion command, the clock is
enabled and the successive–approximation reg-
ister is reset to all zeros. Once the conversion
cycle begins, it can not be stopped or re–started
and data is not available from the output buffers.
Note that even though the user may use an
external sample and hold for very high fre-
quency inputs, the internal sample and hold still
provides a very useful isolation function. Once
theinternalsampleistakenbytheCDACcapaci-
tance, the input of the HS574A/SP674A is dis-
connected from the input. This prevents tran-
sients occurring during conversion from being
inflicted upon the attached buffer. All other 574/
674circuitswillcauseatransientloadcurrenton
TheSAR, timedbytheclock, sequencesthrough
the conversion cycle and returns an end–of–
convert flag to the control section of the ADC.
The clock is then disabled by the control section,
the output status goes low, and the control sec-
tion is enabled to allow the data to be read by
external command.
The internal HS574A/SP674A 12–bit CDAC is
sequenced by the SAR starting from the MSB to
7
CE
dv
dt
∆V
ERROR = ∆t
R/C
t
(ACQ)
SAMPLE
POINT
ACQUISITION
TIME
∆VERROR
WAIT FOR
CONVERT SIGNAL
WAIT FOR
BUS READ
CONVERSION
∆t
V
IN
ACQUISITION TIME =
APERTURE DELAY TIME =
CDAC VOLTAGE
0 VOLTS
0.12 x t
CONVERT
Figure 1. Aperture Uncertainty
Figure 3. Sample–and–Hold Function
acquisition of the input by the CDAC (this time
is defined as tACQ). Following these two cycles,
the input sample is taken and held. The A/D
conversion follows this cycle with the duration
controlled by the internal clock cycle, which is
determined by the specific product model. Note
that because the sample is taken relative to the
R/C transition, tACQ is also the traditional “aper-
ture delay” of this internal sample and hold.
the input which will upset the buffer output and
may add error to the conversion itself.
Furthermore, the isolation of the input after the
acquisition time in the HS574A/SP674A allows
the user an opportunity to release the hold on an
external sample-and-hold and start it tracking
the next sample. This will increase system
throughput with the user's existing components.
Since
t
is measured in clock cycles, its
durationACwQill vary with the internal clock
When using an external S/H, the HS574A/
SP674A acts as any other 574–type device be-
causetheinternalS/Histransparent.Thesample/
hold function in the HS574A/SP674A is inher-
enttothecapacitorDACstructure, anditstiming
characteristics are determined by the internally
generated clock. However, for multiplexer op-
eration, the internal S/H may eliminate the need
for an external S/H. The operation of the S/H
function is internal to the HS574A/SP674A and
iscontrolledthroughthenormalR/Ccontrolline
(refer to Figure 3). When the R/C line makes a
negative transition, the HS574A/SP674A starts
the timing of the sampling and conversion. The
first two clock cycles are allocated to signal
frequency. This results in T
= 2.9µ sec
±1.1µsecsbetweenunitsandovAeCrQtemperatures.
Offset, gain and linearity errors of the S/H cir-
cuit, as well as the effects of its droop rate, are
included in the overall specs for the HS574A/
SP674A.
USING THE SPX74A SERIES
Typical Interface Circuit
The HS574A/SP674A is a complete A/D con-
verter that is fully operational when powered up
and issued a Start Convert Signal. Only a few
external components are necessary. Figure 4
depicts a typical interface circuit for operating
the HS574A/SP674A in a unipolar input mode.
Figure 5 depicts a typical interface circuit for
operating the HS574A/SP674A in a bipolar in-
put mode. Further information is given in the
followingsectionsontheseconnections,butfirst
a few considerations concerning board layout to
achieve the best operation.
25pF
REQ = 4KΩ at any range.
T = REQ x CEQ = 100ns.
For each application of this device, strict atten-
tion must be given to power supply decoupling,
board layout (to reduce pickup between analog
Figure 2. Equivalent SP574A Input Circuit
8
OUTPUT BITS
MSB
LSB
27 26 25 24 23 22 21 20 19 18 17 16
2
12/8
CS
NIBBLE A
NIBBLE B
NIBBLE C
3
4
5
6
CONTROL
LOGIC
A
THREE–STATE BUFFERS AND CONTROL
0
R/C
CE
12–BITS
28
1
OSCILLATOR
12–BIT SAR
STS
R1
100K
+5V
V
LOGIC
-15V
+15V
STROBE
12–BITS
1µF
DGND
10V
IN
0 TO 10V
13
15
SAMPLE/HOLD
MSB
CDAC
COMP
ANALOG
INPUTS
20V
IN 14
100K
100
LSB
BIP
OFF
0 TO 20V
12
V
OUT
REF
OFFSET/GAIN
TRIM NETWORK
REF
8
REF
AMP
R2
100
10
V
REF
IN
7
11
V
CC
1µF
+15V
9
AGND
NO CONNNECTION
PERMITTED
Figure 4. Unipolar Input Connections
and digital sections), and grounding. Digital
timing, calibration and the analog signal source
must be considered for correct operation.
on the component side is recommended. Keep
analog signal traces away from digital lines. It is
best to lay the PC board out such that there is an
analog section and a digital section with a single
pointgroundconnectionbetweenthetwothrough
an RF bead. If this is not possible, run analog
To achieve specified accuracy, a double–sided
printed circuit board with a copper ground plane
OUTPUT BITS
MSB
LSB
27 26 25 24 23 22 21 20 19 18 17 16
2
12/8
CS
NIBBLE A
NIBBLE B
NIBBLE C
3
4
5
6
CONTROL
LOGIC
A
THREE–STATE BUFFERS AND CONTROL
0
R/C
CE
12–BITS
28
1
OSCILLATOR
12–BIT SAR
STS
+5V
V
LOGIC
1µF
DGND
STROBE
12–BITS
10V
IN
±5V
13
15
SAMPLE/HOLD
CDAC
COMP
ANALOG
INPUTS
20V
IN 14
±10V
LSB
MSB
BIP
OFF
12
100
R1
V
OUT
REF
OFFSET/GAIN
TRIM NETWORK
REF
8
REF
AMP
100
R2
10
V
REF
IN
7
11
V
CC
1µF
+15V
9
NO CONNECTION
PERMITTED
AGND
Figure 5. Bipolar Input Connections
9
signals between ground traces and cross digital
lines at right angles only.
7) and analog common (pin 9) is sufficient. VEE
isgeneratedinternallysopin11maybegrounded
or connected to a negative supply if the SPx74A
is being used to upgrade an already existing
design.
Grounding Considerations
Any ground path from the analog and digital
ground should be as low resistance as possible to
accommodate the ground currents present with
this device.
CALIBRATION AND CONNECTION
PROCEDURES
Unipolar
Theanaloggroundcurrentisapproximately6mA
DC while the digital ground is 3mA DC. The
analog and digital common pins should be tied
together as close to the package as possible to
guarantee best performance. The code–depen-
dent currents flow through the VLOGIC and V
terminals and not through the analog and digitCaCl
common pins.
The calibration procedure consists of adjusting
the converter’s most negative output to its ideal
value for offset adjustment, and then adjusting
themostpositiveoutputtoitsidealvalueforgain
adjustment.
Starting with offset adjustment and referring to
Figure4,themidpointofthefirstLSBincrement
shouldbepositionedattheorigintogetanoutput
code of all 0s. To do this, an input of +1⁄2 LSB or
+1.22mVforthe10Vrangeand+2.44mVforthe
20V range should be applied to the SPx74A.
Adjust the offset potentiometer R1 for code tran-
sition flickers between 0000 0000 0000 and
0000 0000 0001.
Power Supplies
The supply voltages for the SPx74A must be
kept as quiet as possible from noise pickup and
also regulated from transients or drops. Because
the part has 12–bit accuracy, voltage spikes on
the supply lines can cause several LSB devia-
tions on the output. Switching power supply
noise can be a problem. Careful filtering and
shielding should be employed to prevent the
noise from being picked up by the converter.
The gain adjustment should be done at positive
full scale. The ideal input corresponding to the
last code change is applied. This is 11⁄2LSB
below the nominal full scale which is +9.9963V
for the 10V range and +19.9927V for the 20V
range.AdjustthegainpotentiometerR2 forflicker
between codes 1111 1111 1110 and 1111 1111
1111. If calibration is not necessary for the
intended application, replace R with a 50Ω, 1%
metal film resistor and remove 2the network ana-
Capacitor bypass pairs are needed from each
supply pin to its respective ground to filter noise
and counter the problems caused by the varia-
tions in supply current. A 10µF tantalum and a
0.1µF ceramic type in parallel between VLOGIC
(pin1)anddigitalcommon(pin15), andVCC (pin
NIBBLE B ZERO
OVERRIDE
NIBBLE A, B
INPUT BUFFERS
12/8
NIBBLE C
READ CONTROL
CS
A
0
R/C
CE
Q
D
H
CK
R
EOC8
CK
Q
DELAY
STS
D
Q
A
LATCH
0
EOC12
Figure 6. SPx74A Control Logic
10
log input to pin 13 for the 0V to 10V range or to
pin 14 for the 0V to 20V range.
of these inputs in controlling the converter’s
operation is shown in Table 1, and the internal
control logic is shown in a simplified schematic
in Figure 6.
Bipolar
The gain and offset errors listed in the specifica-
tions may be adjusted to zero using the potenti-
ometers R and R (See Figure 5). If adjustment
isnotneed1ed,eith2erorbothpotsmaybereplaced
by a 50Ω, 1% metal film resistor.
Conversion Start
A conversion may be initiated by a logic transi-
tion on any of the three inputs: CE, CS R/C, as
shown in Table 1. The last of the three to reach
the correct state starts the conversion, so one,
two or all three may be dynamically controlled.
The nominal delay from each is the same and all
three may change state simultaneously. In order
to assure that a particular input controls the start
of conversion, the other two should be setup at
least 50ns earlier. Refer to the convert mode
timing specifications. The Convert Mode timing
diagram is shown in Figure 8.
To calibrate, connect the analog input signal to
pin 13 for a ±5V range or to pin 14 for a ±10V
1
range. First apply a DC input voltage ⁄2 LSB
above negative full scale which is –4.9988V for
the ±5V range or –9.9976V for the ±10V range.
Adjust the offset potentiometer R for flicker
between output codes 0000 0000 00100 and 0000
0000 0001. Next, apply a DC input voltage 11⁄2
LSBbelowpositivefullscalewhichis+4.9963V
forthe±5rangeor+9.9927Vforthe±10Vrange.
Adjust the gain potentiometer R for flicker
between codes 1111 1111 1110 an2d 1111 1111
1111.
The output signal STS is the status flag and goes
high only when a conversion is in progress.
While STS is high, the output buffers remain in
a high impedance state so that data can not be
read. Also, when STS is high, an additional Start
Convert will not reset the converter or reinitiate
a conversion. Note, if A0 changes state after a
conversion begins, an additional Start Convert
command will latch the new state of A0 and
possibly cause a wrong cycle length for that
conversion (8–versus 12–bits).
Alternative
The 100Ω potentiometer R2 provides gain adjust
for 10V and 20V ranges. In some applications, a
full scale of 10.24V (for and LSB of 2.5mV) or
20.48(foranLSBof5.0mV)ismoreconvenient.
For these, replace R2 by a 50Ω, 1% metal film
resistor.Thentoprovidegainadjustforthe10.24
range, add a 200Ω potentiometer and a 95Ω
fixed resistor, all in series with pin 13. For the
20.48V range, add a 500Ω potentiometer and a
200Ω fixed resistor in series with pin 14.
CE CS R/C 12/8 A0
OPERATION
0
x
x
1
0
0
x
x
0
0
0
0
x
x
x
x
x
x
x
x
1
0
0
x
x
0
1
0
1
0
1
x
0
1
None
None
Initiate 12–Bit Conversion
Initiate 8–Bit Conversion
Initiate 12–Bit Conversion
Initiate 8–Bit Conversion
Initiate 12–Bit Conversion
Initiate 8–Bit Conversion
Enable 12–Bit Output
CONTROLLING THE SPx74A
1
1
1
1
1
1
1
The SPx74A can be operated by most micropro-
cessor systems due to the control input pins and
on–chip logic. It may also be operated in the
“stand–alone” mode and enabled by the R/C
input pin. Full microprocessor control consists
of selecting an 8– or 12–bit conversion cycle,
initiating the conversion, and reading the output
data when ready. The output read has the options
of choosing either 12–bits at once or 8–bits
followed by 4–bits in a left–justified format. All
five control inputs are TTL/CMOS compatible
and include 12/8, CS, A0, R/C and CE. The use
0
0
0
0
0
1
1
1
Enable 8 MSB's Only
Enable 4 LSB's plus 4
Trailing Zeroes
Table 1. SPx74A Control Input Truth Table
11
Conversion Length
4 through 7 are forced to a zero and the four
LSB’s are enabled. The two byte format is “left
justified data” as shown above and can be con-
sidered to have a decimal point or binary to the
left of byte 1.
A conversion start transition latches the state of
A0 asshowninFigure8andTable1. Thelatched
state determines if the conversion stops with 8–
bits (A0 high) or continues for 12–bits (A0 low).
If all 12–bits are read following an 8–bit conver-
sion, the three LSB’s will be a logic “0” and DB3
will be a logic “1”. A0 is latched because it is also
involved in enabling the output buffers as ex-
plained elsewhere. No other control inputs are
latched.
A0 may be toggled without damage to the con-
verter at any time. Break–before–make action is
guaranteed between the two data bytes. This
assures that the outputs which are strapped to-
gether in Figure 11 will never be enabled at the
same time.
Stand–Alone Operation
Thesimplestinterfaceisacontrollineconnected
to R/C. The other controls must be tied to known
states as follows: CE and 12/8 are wired high, A0
and CS are wired low. The output data arrives in
words of 12–bits each. The limits on R/C duty
cycle are shown in Figures 9 and 10. The duty
cycle may be within and including the extremes
shown in the specifications. In general, data may
bereadwhenR/CishighunlessSTSisalsohigh,
indicating a conversion is in progress.
In Figure 11, it can be seen that a read operation
usually begins after the conversion is complete
and STS is low. If earlier access is needed, the
read can begin no later than the addition of times
tDD and tHS before STS goes low.
Reading Output Data
The output data buffers remain in a high imped-
ance state until the following four conditions are
met: R/C is high, STS is low, CE is high and CS
is low. The data lines become active in response
to these four conditions, and output data accord-
ing to the conditions of the control lines 12/8 and
A . The timing diagram for this process is shown
in0 Figure 11. When 12/8 is high, all 12 data
outputs become active simultaneously and the
A input is ignored. The 12/8 input is usually tied
hi0gh or low; it is TTL/CMOS compatible. When
12/8islow, theoutputisseparatedintotwo8–bit
bytes as shown below:
ADDRESS BUS
A
0
28
STS
27
26
25
24
23
22
21
20
19
2
4
12/8
DB11 (MSB)
A
0
DATA
BUS
BYTE 1
xxxx xxxx
BYTE2
xxxx 0000
SPx74A
MSB
LSB
18
17
16
15
Thisconfigurationmakesiteasytoconnecttoan
8–bit address bus as shown in Figure 7. The A
control can be connected to the least significan0t
bitofthedatabusinordertostoretheoutputdata
into two consecutive memory locations. When
A0 is pulled low, the 8 MSB’s are enabled only.
When A0 is high, the 8 MSB’s are disabled, bits
DB0 (LSB)
DIG
COM
Figure 7. Interfacing SPx74A to 8–Bit Interface Bus
12
CONVERT MODE TIMING
t
CE
CS
HEC
t
t
SSC
SRC
R/C
t
HRC
A
0
t
SAC
t
HAC
STS
t
t
C
DSC
HIGH IMPEDANCE
DB
–
11
DB
0
CHARACTERISTICS
Typical @ 25˚C, VCC = +15V or +10V, VLOGIC = +5V, VEE = 0V, unless otherwise specified.
PARAMETER
MIN.
TYP.
MAX.
UNITS
ns
CONDITIONS
t
STS Delay from CE
CE Pulse Width
200
DSC
t
50
50
50
50
50
0
ns
HEC
t
CS to CE Setup
ns
SSC
t
CS Low during CE High
R/C to CE Setup
ns
HSC
t
ns
SRC
t
R/C Low during CE High
ns
HRC
t
A to CE Setup
0
ns
SAC
t
A Valid during CE High
0
50
ns
HAC
1, 3, 4
t
C
Conversion Time
See specifications
NOTES:
1.
2.
3.
4.
Parameters guaranteed by design and sample tested.
Parameters 100% tested @ 25˚C on special orders.
100% tested.
T
MIN
to T
.
MAX
Figure 8. Convert Mode Timing
13
STAND–ALONE MODE TIMING CHARACTERISTICS
Typical @ 25˚C, VCC= +15V or +12V, VLOGIC = +5V, VEE =0V, unless otherwise specified.
PARAMETER
MIN.
TYP.
MAX.
200
UNITS
ns
CONDITIONS
2
t
Low R/C Pulse Width
50
HRL
2
t
STS Delay from R/C
Data Valid After R/C Low
ns
DS
2
t
25
ns
HDR
2
t
STS Delay After Data Valid
High R/C Pulse Width
Data Access Time
300
150
1000
150
ns
HS
t
ns
HRH
t
ns
DDR
NOTES:
1. Parameters guaranteed by design and sample tested.
2. Parameters 100% tested @ 25˚C on special orders.
t
t
HRL
R/C
DS
t
C
STS
t
HDR
t
HS
DATA VALID
DATA VALID
DB11–DB0
Figure 9. Low Pulse for R/C — Outputs Enabled After Conversion
R/C
t
t
DS
HRH
t
C
STS
t
t
HDR
DDR
HIGH–Z
HIGH–Z
DATA VALID
DB11–DB0
Figure 10. High Pulse For R/C — Outputs Enabled While R/C is High, Otherwise High Impedance
14
READ MODE TIMING
CE
CS
t
t
t
t
SSR
HSR
HRR
R/C
SRR
A
0
t
t
HAR
SAR
STS
t
HD
HIGH
DATA
VALID
DB11–
DB0
IMPEDANCE
t
t
HL
DD
CHARACTERISTICS
Typical @ 25˚C, VCC = +15V or +12V, VLOGIC = +5V, VEE = 0V, unless otherwise specified.
PARAMETER
Access Time From CE
MIN.
TYP.
MAX.
UNITS
ns
CONDITIONS
2
t
150
DD
2
t
Data Valid After CE Low
25
ns
HD
2
t
HL
Output Float Delay
150
ns
t
CS to CE Setup
R/C to CE Setup
50
0
0
0
ns
SSR
t
ns
SRR
t
A to CE Setup
0
50
0
ns
SAR
t
CS Valid After CE Low
R/C High After CE Low
0
ns
HSR
t
0
50
ns
HRR
t
A Valid After CE Low
0
50
300
ns
HAR
t
STS Delay After Data Valid
1000
ns
HS
NOTES:
1.
2.
Parameters guaranteed by design and sample tested.
Parameters 100% tested @ 25˚C on special orders.
Figure 11. Read Mode Timing
15
ORDERING INFORMATION
Model .................... No Missing Codes to; ... Linearity ...................... Gain TC ......................... Temperature Range ............ Package Type
25µs Conversion Time
HS574AA .............. 11 Bits .............................. ±1.0 LSB ...................... 50ppm/°C .............. –40°C to +85°C ............ 28–pin, 0.6" Ceramic DIP
HS574AB .............. 12 Bits .............................. ±0.5 LSB ...................... 27ppm/°C .............. –40°C to +85°C ............ 28–pin, 0.6" Ceramic DIP
HS574AC .............. 12 Bits .............................. ±0.5 LSB ...................... 10ppm/°C .............. –40°C to +85°C ............ 28–pin, 0.6" Ceramic DIP
HS574AJ ............... 11 Bits .............................. ±1.0 LSB ...................... 50ppm/°C .............. 0°C to +70°C ................ 28–pin, 0.6" Ceramic DIP
HS574AK .............. 12 Bits .............................. ±0.5 LSB ...................... 27ppm/°C .............. 0°C to +70°C ................ 28–pin, 0.6" Ceramic DIP
HS574AL .............. 12 Bits .............................. ±0.5 LSB ...................... 10ppm/°C .............. 0°C to +70°C ................ 28–pin, 0.6" Ceramic DIP
HS574AS .............. 11 Bits .............................. ±1.0 LSB ...................... 50ppm/°C .............. –55°C to +125°C .......... 28–pin, 0.6" Ceramic DIP
HS574AT .............. 12 Bits .............................. ±0.5 LSB ...................... 25ppm/°C .............. –55°C to +125°C .......... 28–pin, 0.6" Ceramic DIP
HS574AU .............. 12 Bits .............................. ±0.5 LSB ...................... 12.5ppm/°C ........... –55°C to +125°C .......... 28–pin, 0.6" Ceramic DIP
HS574AS/883* ...... 11 Bits .............................. ±1.0 LSB ...................... 50ppm/°C .............. –55°C to +125°C .......... 28–pin, 0.6" Ceramic DIP
HS574AT/883* ...... 12 Bits .............................. ±0.5 LSB ...................... 25ppm/°C .............. –55°C to +125°C .......... 28–pin, 0.6" Ceramic DIP
HS574AU/883* ..... 12 Bits .............................. ±0.5 LSB ...................... 12.5ppm/°C ........... –55°C to +125°C .......... 28–pin, 0.6" Ceramic DIP
15µs Conversion Time
SP674AA .............. 11 Bits .............................. ±1.0 LSB ...................... 50ppm/°C .............. –40°C to +85°C ............ 28–pin, 0.6" Ceramic DIP
SP674AB .............. 12 Bits .............................. ±0.5 LSB ...................... 27ppm/°C .............. –40°C to +85°C ............ 28–pin, 0.6" Ceramic DIP
SP674AC .............. 12 Bits .............................. ±0.5 LSB ...................... 10ppm/°C .............. –40°C to +85°C ............ 28–pin, 0.6" Ceramic DIP
SP674AJ ............... 11 Bits .............................. ±1.0 LSB ...................... 50ppm/°C .............. 0°C to +70°C ................ 28–pin, 0.6" Ceramic DIP
SP674AK .............. 12 Bits .............................. ±0.5 LSB ...................... 27ppm/°C .............. 0°C to +70°C ................ 28–pin, 0.6" Ceramic DIP
SP674AL ............... 12 Bits .............................. ±0.5 LSB ...................... 10ppm/°C .............. 0°C to +70°C ................ 28–pin, 0.6" Ceramic DIP
SP674AS .............. 11 Bits .............................. ±1.0 LSB ...................... 50ppm/°C .............. –55°C to +125°C .......... 28–pin, 0.6" Ceramic DIP
SP674AT ............... 12 Bits .............................. ±0.5 LSB ...................... 25ppm/°C .............. –55°C to +125°C .......... 28–pin, 0.6" Ceramic DIP
SP674AU .............. 12 Bits .............................. ±0.5 LSB ...................... 12.5ppm/°C ........... –55°C to +125°C .......... 28–pin, 0.6" Ceramic DIP
SP674AS/883* ...... 11 Bits .............................. ±1.0 LSB ...................... 50ppm/°C .............. –55°C to +125°C .......... 28–pin, 0.6" Ceramic DIP
SP674AT/883* ...... 12 Bits .............................. ±0.5 LSB ...................... 25ppm/°C .............. –55°C to +125°C .......... 28–pin, 0.6" Ceramic DIP
SP674AU/883* ...... 12 Bits .............................. ±0.5 LSB ...................... 12.5ppm/°C ........... –55°C to +125°C .......... 28–pin, 0.6" Ceramic DIP
* MIL–STD–883C processing.
NOTE: Electrical specifications for –AA, –AB and –AC grades are the same as –AJ, –AK, and –AL models respectively, with the exception of
extended operating temperature range performance from –40°C to +85°C.
Please consult the factory for other packaging options.
16
相关型号：
SP674AC/LCC
ADC, Successive Approximation, 12-Bit, 1 Func, Parallel, Word Access, CQCC28, LCC-28
SIPEX
SP674AJ/LCC
ADC, Successive Approximation, 12-Bit, 1 Func, Parallel, Word Access, CQCC28, LCC-28
SIPEX
SP674AK
ADC, Successive Approximation, 12-Bit, 1 Func, 1 Channel, Parallel, Word Access, CDIP28, 0.600 INCH, CERDIP-28
SPECTRUM
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