SP7516BN [SIPEX]
16-Bit Multiplying DACs; 16位乘法DAC
| 型号： | SP7516BN |
| 厂家： | 
SIPEX CORPORATION |
| 描述： | 16-Bit Multiplying DACs |
| 文件： | 总8页 (文件大小：124K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Corporation
SP7516 and HS3160
SIGNAL PROCESSING EXCELLENCE
16-Bit Multiplying DACs
■ Monolithic Construction
■ 16–Bit Resolution
■ 0.003% Non-Linearity
■ Four-Quadrant Multiplication
■ Latch-up Protected
■ Low Power - 30mW
■ Single +15V Power Supply
DESCRIPTION…
The SP7516 and HS3160 are precision 16-bit multiplying DACs, that provide four-quadrant
multiplication. Both parts accept both AC and DC reference voltages. The SP7516 is available
for use in commercial and industrial temperature ranges, packaged in a 24-pin SOIC. The
HS3160 is available in commercial and military temperature ranges, packaged in a 22-pin
side-brazed DIP.
23
V
REF
Force
22
V
Sense
REF
2
I
I
2 Sense
OUT
OUT
3
1
4
2 Force
1
GND
I
OUT
21
V
DD
SP7516
5
6
7
8
20
24
BIT1 BIT2 BIT3 BIT4
(MSB)
BIT16
(LSB)
R
FEEDBACK
Switches shown in high state.
21
V
REF
2
1
I
I
2
1
OUT
OUT
3
GND
20
V
DD
HS3160
4
5
6
7
19
22
BIT1 BIT2 BIT3 BIT4
(MSB)
BIT16
(LSB)
R
FEEDBACK
Switches shown in high state.
127
Corporation
SIGNAL PROCESSING EXCELLENCE
SPECIFICATIONS
(Typical @ 25°C, nominal power supply, VREF = +10V, unipolar unless otherwise noted)
PARAMETER
MIN.
TYP.
MAX.
UNITS
CONDITIONS
DIGITAL INPUT
Resolution
16
Bits
2–Quad, Unipolar Coding
4–Quad, Bipolar Coding
Logic Compatibility
Input Current
Binary
Offset Binary
CMOS, TTL
Note 1
±1
µA
REFERENCE INPUT
Voltage Range
±25
V
Note 2
Input Impedance
3.25
75
9.75
KOhms
ANALOG OUTPUT
Scale Factor
Scale Factor Accuracy
Output Leakage
225
±1
10
µA/VREF
%
Note 3
Note 4
nA
Output Capacitance
COUT 1, all inputs high
COUT 1, all inputs low
COUT 2, all inputs high
COUT 2, all inputs low
100
50
50
pF
pF
pF
pF
100
STATIC PERFORMANCE
Integral Linearity
SP7516KN/BN, HS3160–4
SP7516JN/AN, HS3160–3
Differential Linearity
Note 5
Note 6
±0.003
±0.006
±0.006
±0.012
% FSR
% FSR
SP7516KN/BN, HS3160–4
SP7516JN/AN, HS3160–3
Monotonicity
±0.003
±0.006
±0.006
±0.012
%FSR
% FSR
SP7516KN/BN, HS3160–4
SP7516JN/AN, HS3160–3
Guaranteed to 14 bits
Guaranteed to 13 bits
STABILITY
(TMIN to TMAX)
Scale Factor
4
0.5
0.5
ppm FSR/°C
ppm FSR/°C
ppm FSR/°C
Note 7 and 8
Integral Linearity
Differential Linearity
Monotonicity Temp. Range
SP7516JN/KN, HS3160C
SP7516AN/BN
1.0
1.0
0
–40
–55
+70
+85
+125
°C
°C
°C
HS3160B–_
DYNAMIC PERFORMANCE
Digital Small Signal Settling
Digital Full Scale Settling
Reference Feedthrough Error
@ 1kHz
1.0
2.0
µS
µS
(VREF = 20Vpp)
200
2
µV
mV
@ 10kHz
Reference Input Bandwidth
1
MHz
POWER SUPPLY (VDD
Operating Voltage
Voltage Range
Current
)
+15 ±5%
V
V
mA
%/%
+8
+18
2.0
Note 9
Rejection Ratio
0.005
128
Corporation
SIGNAL PROCESSING EXCELLENCE
SPECIFICATIONS (continued)
(Typical @ 25°C, nominal power supply, VREF = +10V, unipolar unless otherwise noted)
PARAMETER
MIN.
TYP.
MAX.
UNITS
CONDITIONS
ENVIRONMENTAL AND MECHANICAL
Operating Temperature
SP7516JN/KN
SP7516AN/BN
HS3160–C
0
–40
0
–55
–55
–65
+70
+85
+70
+125
+125
+150
°C
°C
°C
°C
°C
°C
HS3160–B
HS3160–B/883
Storage Temperature
Package
SP7516_N
24-pin SOIC
HS3160
22–pin Side–Brazed DIP
Notes:
1.
2.
3.
Digital input voltage must not exceed supply voltage or go below –0.5V ; “0” <0.8V; 2.4V < “1” ≤VDD.
AC or DC; use R6758–1 for fixed reference applications
Using the internal feedback resistor and an external op amp. The Scale Factor can be adjusted externally by variable resistors in series with the
reference input and/or in series to the internal feedback resistor. Please refer to the Applications Information section.
At 25°C; the output leakage current will create an offset voltage at the external op amps output. It doubles every 10°C temperature increase.
Integral Linearity is measured as the arithmetic mean value of the magnitudes of the greatest positive deviation and the greatest negative deviation from
the theoretical value for any given input combination.
4.
5.
6.
7.
8.
9.
Differential Linearity is the deviation of an output step form the theoretical value of 1LSB for any two adjacent digital input codes.
At 25°C, the output leakage current will create an offset voltage output. It doubles every 10°C temperature increase.
Using the internal feedback resistor and an external op amp.
Use series 470ohm resistor to limit startup current.
CHARACTERISTIC CURVES
(Typical @ + 25°C, VDD = + 15VDC, VREF = + 10VDC, unless otherwise noted.)
0.048
50
40
30
20
10
0
0.024
0.012
2 LSB
0.006
0.003
1 LSB
0.01
0.1
1
10
V
-VOLTS
REF
1/2 LSB @ 16 BITS
Integral Linearity Error vs. Reference Voltage
0.048%
0
10
20
30
-mV
40
50
V
OS
Additional Linearity Error vs. Output-Amplifier
Offset-Voltage (VREF = + 10V)
0.024%
0.012%
0.01
0.006%
0.003%
4
6
8
10
V
12
14
16
18
0.008
-VOLTS
DD
Linearity vs. Supply Voltage
0.006
2.5
2.0
1.5
1.0
0.004
0.002
0
4
6
8
10
V
12
14
16
18
-VOLTS
4
6
8
10
V
12
14
16
18
DD
10
-VOLTS
DD
Gain Change vs. Supply Voltage
Power Supply Current vs. Voltage
129
Corporation
SIGNAL PROCESSING EXCELLENCE
Pin 15 – DB5 – Data Bit 11.
PIN ASSIGNMENTS
HS3160 22–PIN
Pin 16 – DB4 – Data Bit 12.
Pin 1 – IO1 – Current Output 1.
Pin 2 – IO2 – Current Output 2.
Pin 3 – GND – Ground.
Pin 17 – DB3 – Data Bit 13.
Pin 18 – DB2 – Data Bit 14.
Pin 19 – DB1 – Data Bit 15.
Pin 4 – DB15 – MSB, Data Bit 1.
Pin 5 – DB14 – Data Bit 2.
Pin 20 – DB0 – LSB, Data Bit 16.
Pin 21 – VDD – Positive Supply Voltage.
Pin 22 – VREF Sense – Reference Voltage Input.
Pin 23 – VREF Force – Reference Voltage Input.
Pin 24 – RFB – Feedback Resistor.
Pin 6 – DB13 – Data Bit 3.
Pin 7 – DB12 – Data Bit 4.
Pin 8 – DB11 – Data Bit 5.
Pin 9 – DB10 – Data Bit 6.
Pin 10 – DB9 – Data Bit 7.
FEATURES…
Pin 11 – DB8 – Data Bit 8.
The SP7516 and HS3160are precision 16-bit multi-
plying DACs. The DACs are implemented as a one-
chip CMOS circuit with a resistor ladder network.
Pin 12 – DB7 – Data Bit 9.
Pin 13 – DB6 – Data Bit 10.
Pin 14 – DB5 – Data Bit 11.
Pin 15 – DB4 – Data Bit 12.
Pin 16 – DB3 – Data Bit 13.
Pin 17 – DB2 – Data Bit 14.
Pin 18 – DB1 – Data Bit 15.
Pin 19 – DB0 – LSB, Data Bit 16.
Pin 20 – VDD – Positive Supply Voltage.
Pin 21 – VREF – Reference Voltage Input.
Pin 22 – RFB – Feedback Resistor.
ThreeoutputlinesareprovidedontheDACstoallow
unipolar and bipolar output connection with a mini-
mum of external components. The feedback resistor
is internal. The resistor ladder network termination is
externally available, thus eliminating an external re-
sistor for the 1 LSB offset in bipolar mode.
The SP7516 is available for use in commercial and
industrial temperature ranges, packaged in a 24-pin
SOIC. The HS3160 is available in commercial
and military temperature ranges, packaged in a
24–pin side–brazed DIP. For product processed
and screened to the requirements of MIL–M–
38510 and MIL–STD–883C, please consult the
factory (HS3160B only).
SP7516 24–PIN
Pin 1 – IO1 – Current Output 1.
Pin 2 – IO2 Sense – Current Output 2.
Pin 3 – IO3 Force – Current Output 3.
Pin 4 – GND – Ground.
PRINCIPLES OF OPERATION
TheSP7516/HS3160achievehighaccuracybyusing
a decoded or segmented DAC scheme to implement
this function. The following is a brief description of
this approach.
Pin 5 – DB15 – MSB, Data Bit 1.
Pin 6 – DB14 – Data Bit 2.
Pin 7 – DB13 – Data Bit 3.
Pin 8 – DB12 – Data Bit 4.
Pin 9 – DB11 – Data Bit 5.
Pin 10 – DB10 – Data Bit 6.
Pin 11 – DB9 – Data Bit 7.
Pin 12 – DB8 – Data Bit 8.
Pin 13 – DB7 – Data Bit 9.
Pin 14 – DB6 – Data Bit 10.
C
f
R
f
V
–
+
REF
E
R
O
C
i
O
R
C
p
Figure 1. SP7516/HS3160 Equivalent Output Circuit
130
Corporation
SIGNAL PROCESSING EXCELLENCE
- 1
- 2
2
(MSB)
2
Output
400Ω
470Ω
V
V
REF
DD
0
0
1
1
0
0
200Ω
1
0
1
1/4 Full-Scale
1/2 Full-Scale
3/4 Full-Scale
R
I
FEEDBACK
R
OS
-
O1
DIGITAL
INPUTS
A
+
I
O2
SP7516
HS3160
V
Table 1. Contribution of the two MSB's
OUT
The most common technique for building a D/A
converterofnbitsistousenswitchestoturnncurrent
or voltage sources on or off. The n switches and n
sourcesaredesignedsothateachswitchorbitcontrib-
utestwiceasmuchtotheD/Aconverter’soutputasthe
preceding bit. This technique is commonly known as
binary weighting and allows an n-bit converter to
generate 2n output levels by turning on the proper
combination of bits.
GND
Figure 2. Unipolar Operation
the same functional performance can be obtained.
ThusbyreplacingthetwoMSBswitchesofaconven-
tional converter with three switches properly de-
coded, the contribution ofanyswitchisreducedfrom
1/2to1/4.Thisreductioninsensitivityalsoreducesthe
accuracy required of any switch for a given overall
converter accuracy.
In such a binary-weighted converter, the switch
with the smallest contribution (the LSB) accounts
-n
for only 2 of the converter’s full-scale value.
Similarly, the switch with the largest contribution
(theMSB)accountsfor2-1orhalfoftheconverter’s
full-scale output. Thus it is easy to see that a given
percent change in the MSB will have a greater
effect on the converter’s output than would a
similar percent change in the LSB. For example, a
1% change in the LSB of a 10 bit converter would
only affect the output by 0.001% of full-scale. A
1% change in the MSB of the same converter
would affect the output by 0.5% of FSR.
With the decoded converter described above, a 1%
change in any of the converter’s switches will affect
the output by no more than 0.25% of full-scale as
compared to 0.5% for a conventional converter. In
other words the conventional D/A converter can be
made less sensitive to the quality of its individual bits
by decoding.
In the SP7516/HS3160 the first four MSB’s are
decodedinto16levelswhichdrive15equallyweighted
current sources. The sensitivity of each switch on the
output is reduced by a factor of 8. Each of the 15
sources contributes 6.25% output change rather than
an MSB change of 50% for the common approach.
In order to overcome the problem which results from
the large weighting of the MSB, the two MSB’s can
be decoded to three equally weighted sources. Table
1 shows that all combinations of the two MSB’s of a
converter result in four output levels. So by replacing
the two MSB’s with three bits equally weighted at 1/
4 full-scale and decoding the two MSB digital inputs
into three lines which drive the equally weighted bits,
400Ω 470Ω
V
V
REF
DD
200Ω
R
FEEDBACK
R
OS1
-
I
I
O1
A
1
DIGITAL
INPUTS
SP7516
HS3160
TRANSFER FUNCTION (N=16)
+
V
OUT
4KΩ
BINARY INPUT UNIPOLAR OUTPUT BIPOLAR OUTPUT
4KΩ
111...111
100...001
100...000
011...111
000…001
000...000
–VREF (1 - 2–N)
–VREF (1/2 + 2–N
–VREF /2
–VREF (1 – 2 –(N – 1)
)
O2
–(N – 1)
)
)
–VREF (2
)
R
R
OS2
GND
0
R
OS2
–VREF (1/2 – 2–N
VREF (2 –(N – 1)
)
-
A
2
–VREF (2(N – 1)
)
VREF (1 – 2 –(N – 1)
)
+
V
OUT1
, A
, OP-07
2
A
1
0
VREF
Table 2. Transfer Function
Figure 3. Bipolar Operation
131
Corporation
SIGNAL PROCESSING EXCELLENCE
HS3160, small values for Cf must be used. Resis-
torRp canbeadded, thiswillparallelRjdecreasing
the effective resistance. If Cf is reduced the band-
widthwillbeincreasedandsettlingtimedecreased.
However a system penalty for lowering Cf is to
increase noise gain. The tradeoff is noise vs. set-
tling time. If Rp is added then a large value (1µF or
greater)non-polarizedcapacitorCp shouldbeadded
in series with Rp to eliminate any DC drifts. If
settling time is not important, eliminate Rp and Cp,
and adjust Cf to prevent overshoot.
V
DD
470
V
REF
(+ 25V MAX)
400
3
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
V
LSB
15
14
13
12
11
10
9
REF
UNIPOLAR MODE
(2-QUADRANT)
V
+
DD
200
74273
CLK
R
F
2
V
OUT
REF
N
I
01
02
–
6
0 TO - V
(1-2 -
A
1
3
I
+
)
SP7516/
S
HS3160
R
D0
D1
D2
D3
D4
D5
D6
D7
0S
8
7
6
5
WR
G2A
74273
74LS138
4
3
2
BDSEL
G2B
C
A
2
MSB
GND
CLK
A
A
1
0
B
A
ADDRESS DECODER
LATCHES
Figure 4. Microprocessor Interface to SP7514
Output Offset
In most applications, the output of the DAC is fed
into an amplifier to convert the DAC’s current
output to voltage. A little known and not com-
monly discussed parameter is the linearity error
versus offset voltage of the output amplifier. All
CMOS DAC’s must operate into a virtual ground,
i.e., the summing junction of an op amp. Any
amplifier’soffsetfromtheamplifierwillappearas
an error at the output (which can be related to
LSB’s of error).
Following the decoded section of the DAC a
standard binary weighted R-2R approach is used.
This divides each of the 16 levels (or 6.25% of
F.S.) into 4096 discrete levels (the 12 LSB’s).
Output Capacitance
The SP7516/HS3160 have very low output ca-
pacitance (CO). This is specified both with all
switchesONandallswitchesOFF.Outputcapaci-
tance varies from 50pF to 100pF over all input
codes. This low capacitance is due in part to the
decoding technique used. Smaller switches are
used with resulting less capacitance. Three impor-
tant system characteristics are affected by CO and
∆CO; namely digital feedthrough, settling time,
and bandwidth. The DAC output equivalent cir-
cuit can be represented as shown in Figure 1.
Most all CMOS DAC’s currently available are
implemented using an R-2R ladder network. The
formulafornonlinearityistypically0.67mV/mVOS
(not derived here). However the SP7516 has a
coefficient of only 0.065mV/mVOS. This is due to
the decoding technique described earlier. CMOS
DAC applications notes (including this one) al-
ways show a potentiometer used to null out the
amplifier’s offset. If an amplifier is chosen having
‘pretrimmed’offsetitmaybepossibletoeliminate
this component. Consider the following calcula-
tions:
Digital feedthrough is the change in analog output
due to the toggling conditions on the converter
input data lines when the analog input VREF is at
0V. The SP7516/HS3160 very low CO and there-
fore will yield low digital feedthrough. Inputs to
the DAC can be buffered. This input latch with
microprocessor control is shown in Figure 4.
1.
2.
3.
Using LF441A amplifier (low power - 741 pinout)
Specified offset: 0.5mV max
Temperature coefficient of input offset: 10µV/°C max
Settling time is directly affected by CO. In Figure
1, CO combines with Rf to add a pole to the open
loop response, reducing bandwidth and causing
excessive phase shift - which could result in
ringing and/or oscillation. A feedback capaci-
tor,Cf mustbeaddedtorestorestability.Evenwith
Cf, there is still a zero-pole mismatch due to RiCO
which is code dependent. This code dependent
mismatch is minimized when CORi = RfCf. How-
everCf mustnowbemadelargertocompensatefor
worstcase∆RiCO-resultinginreducedbandwidth
and increased settling time. With the SP7516/
V
OS max (0°C to 70°C)
= 0.5mV + (70µV)10
= 1.2mV
Add'l nonlinearity (max)
= 1.2mV x 0.065mV/mV
= 78µV (1/2 LSB @ 16 Bits!)
Where: 78µV = 1/2 LSB @ 16 Bits (10V range)
Via the above configuration, theSP7516/HS3160
can be used to divide an analog signal by digital
code (i.e. for digitally controlled gain). The trans-
fer function is given in Table 2, where the value of
each bit is 0 or 1. Division by all “0”s is undefined
and causes the op amp to saturate.
132
Corporation
SIGNAL PROCESSING EXCELLENCE
Applications Information
Unipolar Operation
Figure 2 shows the interconnections for unipolar
operation. Connect IO1 and FB1 as shown in dia-
gram. Tie IO2 (Pin 7), FB3 (Pin 3), and FB4 (Pin 1)
to Ground (Pin 8). As shown, a series resistor is
recommended in the VDD supply line to limit
current during ‘turn-on.’ To maintain specified
linearity,externalamplifiersmustbezeroed. Apply
an ALL “ZEROES” digital input and adjust ROS
for VOUT = 0 ± 1mV. The SP7516 and HS3160
have been used successfully with OP-07, OP-27
and LF441A. For high speed applications the
SP2525 is recommended.
Bipolar Operation
Figure 3 shows the interconnections for bipolar
operation. Connect IO1, IO2, FB1, FB3, FB4 as
shown in diagram. Tie LDTR to IO2. As shown, a
series resistor is recommended in the VDD supply
line to limit current during ‘turn-on. To maintain
specified linearity, external amplifiers must be
zeroed. ThisisbestdonewithVREF settozeroand,
theDACregisterloadedwith10...0(MSB=1).Set
R0S1 for V01 = 0. Set R0S2 for VOUT = 0. Set VREF
to +10V and adjust RB for VOUT to be 0V.
Grounding
Connect all GND pins to system analog ground
and tie this to digital ground. All unused input
pins must be grounded.
133
Corporation
SIGNAL PROCESSING EXCELLENCE
ORDERING INFORMATION
Model ................................................................ Monotonicity ................................ Temperature Range .................................... Package
16-Bit Multiplying DAC
HS3160C-3Q ............................................................ 13-Bit ............................................... 0°C to +70°C ................... 22-pin, 0.4" Side-Brazed DIP
HS3160B-3Q ............................................................ 13-Bit ......................................... -55°C to +125°C ................... 22-pin, 0.4" Side-Brazed DIP
HS3160B-3/883 ....................................................... 13-Bit ......................................... -55°C to +125°C ................... 22-pin, 0.4" Side-Brazed DIP
HS3160C-4Q ............................................................ 14-Bit ............................................... 0°C to +70°C ................... 22-pin, 0.4" Side-Brazed DIP
HS3160B-4Q ............................................................ 14-Bit ......................................... -55°C to +125°C ................... 22-pin, 0.4" Side-Brazed DIP
HS3160B-4/883 ....................................................... 14-Bit ......................................... -55°C to +125°C .................. 22-pin , 0.4" Side-Brazed DIP
SP7516JN ................................................................ 13-Bit ............................................... 0°C to +70°C ......................................24-pin, 0.3" SOIC
SP7516KN ............................................................... 14-Bit ............................................... 0°C to +70°C ......................................24-pin, 0.3" SOIC
SP7516AN ............................................................... 13-Bit .......................................... –40°C to +85°C ......................................24-pin, 0.3" SOIC
SP7516BN ............................................................... 14-Bit .......................................... –40°C to +85°C ......................................24-pin, 0.3" SOIC
134
Corporation
SIGNAL PROCESSING EXCELLENCE
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