SP7651_07 [SIPEX]
Wide Input Voltage Range 3Amp 900kHz Buck Regulator; 宽输入电压范围3Amp至900kHz降压型稳压器
| 型号： | SP7651_07 |
| 厂家： | 
SIPEX CORPORATION |
| 描述： | Wide Input Voltage Range 3Amp 900kHz Buck Regulator |
| 文件： | 总15页 (文件大小：1035K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Solved by
SP7651
TM
Wide Input Voltage Range 3Amp
900kHz Buck Regulator
FEATURES
• 2.5V to 20V Step Down Achieved Using Dual Input
• Output Voltage down to 0.8V
SP7651
DFN PACKAGE
7mm x 4mm
P
GND
GND
GND
26
1
• 3A Output Capability (Up to 5A with Air Flow)
• Built in Low RDSON Power FETs (40 mΩ typ)
• Highly Integrated Design, Minimal Components
• 900 kHz Fixed Frequency Operation
• UVLO Detects Both VCC and VIN
LX
LX
LX
BOTTOM VIEW
25
24
P
2
3
4
Heatsink Pad 1
Connect to Lx
Pin 27
P
GND
23
22
LX
5
VFB
V
CC
GND
GND
GND
BST
NC
6
7
8
21
20
COMP
UVIN
GND
SS
• Over Temperature Protection
Heatsink Pad 2
Connect to GND
• Short Circuit Protection with Auto-Restart
• Wide BW Amp Allows Type II or III Compensation
• Programmable Soft Start
19
18
Pin 28
9
10
11
12
17
V
IN
• Fast Transient Response
Heatsink Pad 3
Connect to VIN
16
15
14
V
IN
IN
LX
• High Efficiency: Greater than 92% Possible
• Asynchronous Start-Up into a Pre-Charged Output
• Small 7mm x 4mm DFN Package
V
LX
Pin 29
13
V
IN
LX
• U.S. Patent #6,922,04ꢀ
DESCRIPTION
The SP7651 is a high voltage synchronous step-down switching regulator optimized for high efficiency. The part
is designed to be especially attractive for dual supply, ꢀ2V step down with 5V used to power the controller. This
lower VCC voltage minimizes power dissipation in the part. The SP765ꢀ is designed to provide a fully integrated
buck regulator solution using a fixed 900kHz frequency, PWM voltage mode architecture. Protection features
include UVLO, thermal shutdown and output short circuit protection. The SP765ꢀ is available in the space saving
7mm X 4mm DFN package.
TYPICAL APPLICATION CIRCUIT
Uꢀ
SP7651
Lꢀ
ꢀ
2
26
25
24
23
22
2ꢀ
20
ꢀ9
ꢀ8
ꢀ7
ꢀ6
ꢀ5
ꢀ4
PGND
PGND
PGND
GND
VFB
LX
LX
VOUT
3.3V
0-3A
4.7uH, Irate=3.87A
Rꢁ3
7.ꢀ5kΩ,
1%
Rꢁ2
Cꢁ2
3
LX
+5V
VCC
ꢀ5k,1%
ꢀ,000pF
C3
22uF
6.3V
4
LX
Rꢀ
CPꢀ
5
68.ꢀkΩ,ꢀ%
VCC
GND
GND
GND
BST
NC
Cꢁ3
22pF
6
ꢀ50pF
COMP
UVIN
GND
SS
CVCC
2.2uF
7
CFꢀ
ꢀ00pF
ENABLE
8
DBST
9
RSET
2ꢀ.5kΩ,ꢀ%
ꢀ0
ꢀꢀ
ꢀ2
ꢀ3
SD101AWS
VIN
CSS
ꢀ5nF
(note 2)
VIN
LX
CBST
6800pF
VIN
LX
VIN
LX
VIN
12V
fs=900Khz
Notes:
1. U1 Bottom-Side Layout should
have three contacts isolated from
one another: Vin, SWNODE, and GND.
Cꢀ
22uF
16V
GND
2. RSET=54.48/(Vout-0.8V) (KOhm)
Rev J: 3/ꢀ4/07
SP765ꢀ Wide Input Voltage Range 3A, 900kHz, Buck Regulator
© Copyright 2007 Sipex Corporation
ꢀ
ABSOLUTE MAXIMUM RATINGS
These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections
of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
All other pins............................................................-0.3V to VCC+0.3V
VCC .................................................................................................. 7V
VIN.................................................................................................. 22V
ILX .................................................................................................... 5A
BST................................................................................................ 35V
LX-BST...............................................................................-0.3V to 7V
LX........................................................................................-ꢀV to 20V
Storage Temperature................................................... -65°C to 150°C
Power Dissipation..................................................... Internally Limited
ESD Rating........................................................................... 2kV HBM
Thermal Resistance ΟJC........................................................... 5°C/W
ELECTRICAL CHARACTERISTICS
Unless otherwise specified: -40°C < TAMB < 85°C, -40°C< Tj <125°C, 4.5V < VCC < 5.5V, 3V< Vin < 20V, BST=LX + 5V,
LX = GND = 0.0V, UVIN = 3.0V, CVCC = ꢀµF, CCOMP = 0.ꢀµF, CSS = 50nF, Typical measured at VCC = 5V.
The • denotes the specifications which apply over the full temperature range, unless otherwise specified.
PARAMETER
MIN.
TYP.
MAX.
UNITS
CONDITIONS
QUIESCENT CURRENT
Vcc Supply Current (No switching)
Vcc Supply Current (switching)
BST Supply Current (No switching)
BST Supply Current (switching)
PROTECTION: UVLO
ꢀ.5
8
3
ꢀ2
0.4
6
mA
mA
mA
mA
Vfb =0.9V
•
•
0.2
4
Vfb =0.9V
Vcc UVLO Start Threshold
Vcc UVLO Hysteresis
4.00
ꢀ00
2.3
4.25
200
2.5
4.5
300
2.65
400
ꢀ
V
mV
V
•
UVIN Start Threshold
UVIN Hysteresis
200
300
mV
µA
UVIN Input Current
UVIN= 3.0V
ERROR AMPLIFIER REFERENCE
2X Gain Config., Measure
Vfb; Vcc =5 V, T=25°C
Error Amplifier Reference
0.792
0.788
0.800
0.808
0.8ꢀ2
V
Error Amplifier Reference
Over Line and Temperature
Error Amplifier Transconductance
Error Amplifier Gain
•
0.800
6
V
mA/V
dB
60
No Load
COMP Sink Current
ꢀ50
ꢀ50
50
µA
Vfb =0.9V, COMP= 0.9V
Vfb =0.7V, COMP= 2.2V
Vfb = 0.8V
COMP Source Current
Vfb Input Bias Current
Internal Pole
µA
200
nA
4
MHz
V
COMP Clamp
2.5
-2
Vfb =0.7V, TA=25¼C
COMP Clamp Temp. Coefficient
mV/°C
Rev J: 3/ꢀ4/07
SP765ꢀ Wide Input Voltage Range 3A, 900kHz, Buck Regulator
© Copyright 2007 Sipex Corporation
2
ELECTRICAL CHARACTERISTICS
Unless otherwise specified: -40°C < TAMB < 85°C, -40°C<Tj<125°C, 4.5V < VCC < 5.5V, 3V<Vin<20V, BST=LX + 5V, LX = GND =
0.0V, UVIN = 3.0V, CVCC = ꢀµF, CCOMP = 0.ꢀµF, CSS = 50nF, Typical measured at VCC = 5V.
The • denotes the specifications which apply over the full temperature range, unless otherwise specified.
PARAMETER
MIN. TYP.
MAX. UNITS
CONDITIONS
CONTROL LOOP: PWM COMPARATOR, RAMP & LOOP DELAY PATH
Ramp Amplitude
RAMP Offset
0.92
ꢀ.ꢀ
ꢀ.ꢀ
ꢀ.28
ꢀ80
990
V
V
TA = 25°C, RAMP COMP
until GH starts Switching
RAMP Offset Temp. Coefficient
GH Minimum Pulse Width
-2
mV/°C
90
ns
•
•
Maximum Duty Ratio Measured
just before pulsing begins
Maximum Controllable Duty Ratio
92
97
%
Maximum Duty Ratio
ꢀ00
8ꢀ0
%
Valid for 20 cycles
Internal Oscillator Ratio
TIMERS: SOFTSTART
SS Charge Current:
900
ꢀ0
kHz
µA
SS Discharge Current:
PROTECTION: Short Circuit & Thermal
Short Circuit Threshold Voltage
Hiccup Timeout
ꢀ
mA
•
•
Fault Present, SS = 0.2V
0.2
0.25
200
0.3
V
Measured Vref (0.8V) - VFB
Vfb = 0.5V
ms
Number of Allowable Clock Cycles at
100% Duty Cycle
20
Cycles
Minimum GL Pulse After 20 Cycles
Thermal Shutdown Temperature
Thermal Recovery Temperature
Thermal Hysteresis
0.5
ꢀ45
ꢀ35
ꢀ0
Cycles
°C
Vfb = 0.7V
Vfb = 0.7V
°C
°C
OUTPUT: POWER STAGE
Vcc = 5V ; Iout = 3A
Tamb = 25°C
High Side Rdson
40
40
mΩ
Vcc = 5V ; Iout = 3A
Tamb = 25°C
Synchronous FET Rdson
mΩ
Maximum Output Current
3
A
Rev J: 3/ꢀ4/07
SP765ꢀ Wide Input Voltage Range 3A, 900kHz, Buck Regulator
© Copyright 2007 Sipex Corporation
3
PIN DESCRIPTION
Pin #
ꢀ-3
Pin Name Description
Pgnd
Ground connection for the synchronous rectifier
4,8,ꢀ9-2ꢀ
GND
Ground Pin. The control circuitry of the IC and lower power driver are refer-
enced to this pin. Return separately from other ground traces to the (-) terminal
of Cout.
5
6
Vfb
Feedback Voltage and Short Circuit Detection pin. It is the inverting input of the
Error Amplifier and serves as the output voltage feedback point for the Buck
Converter. The output voltage is sensed and can be adjusted through an exter-
nal resistor divider. Whenever Vfb drops 0.25V below the positive reference, a
short circuit fault is detected and the IC enters hiccup mode.
COMP
Output of the Error Amplifier. It is internally connected to the inverting input of
the PWM comparator. An optimal filter combination is chosen and connected
to this pin and either ground or Vfb to stabilize the voltage mode loop.
7
9
UVIN
SS
UVLO input for Vin voltage. Connect a resistor divider between Vin and UVin to
set minimum operating voltage.
Soft Start. Connect an external capacitor between SS and GND to set the soft
start rate based on the ꢀ0µA source current. The SS pin is held low via a ꢀmA
(min) current during all fault conditions.
ꢀ0-ꢀ3
Vin
Input connection to the high side N-channel MOSFET. Place a decoupling
capacitor between this pin and Pgnd.
ꢀ4-ꢀ6,23-26
LX
NC
Connect an inductor between this pinand Vout
ꢀ7
ꢀ8
No Connect
BST
High side driver supply pin. Connect BST to the external boost diode and ca-
pacitor as shown in the Typical Application Circuit on page ꢀ. High side driver
is connected between BST pin and SWN pin.
22
Vcc
Input for external 5V bias supply
THEORY OF OPERATION
General Overview
that accurately sets the PWM frequency to
900kHz.
The SP7651 is a fixed frequency, voltage
mode, synchronous PWM regulator opti-
mized for high efficiency. The part has been
designed to be especially attractive for split
plane applications utilizing 5V to power the
controller and 2.5V to 20V for step down
conversion.
The SP765ꢀ contains two unique control
features that are very powerful in distributed
applications.First,asynchronousdrivercon-
trol is enabled during startup, to prohibit the
low side NFET from pulling down the output
until the high side NFET has attempted to
turn on. Second, a 100% duty cycle timeout
ensuresthatthelowsideNFETisperiodically
enhanced during extended periods at 100%
dutycycle.Thisguaranteesthesynchronized
refreshing of the BST capacitor during very
large duty ratios.
TheheartoftheSP765ꢀisawidebandwidth
transconductance amplifier designed to ac-
commodate Type II and Type III compensa-
tion schemes. A precision 0.8V reference,
present on the positive terminal of the error
amplifier, permits the programming of the
output voltage down to 0.8V via the VFB pin.
The output of the error amplifier, COMP,
which is compared to a ꢀ.ꢀV peak-to-peak
ramp, is responsible for trailing edge PWM
control.Thisvoltageramp,andPWMcontrol
logic are governed by the internal oscillator
The SP765ꢀ also contains a number of
valuableprotectionfeatures.Programmable
UVLO allows the user to set the exact VIN
value at which the conversion voltage can
Rev J: 3/ꢀ4/07
SP765ꢀ Wide Input Voltage Range 3A, 900kHz, Buck Regulator
© Copyright 2007 Sipex Corporation
4
THEORY OF OPERATION
safely begin down conversion, and an inter-
nal VCC UVLO ensures that the controller
itselfhasenoughvoltagetoproperlyoperate.
Other protection features include thermal
shutdown and short-circuit detection. In the
event that either a thermal, short-circuit, or
UVLOfaultisdetected,theSP765ꢀisforced
intoanidlestatewheretheoutputdriversare
held off for a finite period before a re-start
is attempted.
Thermal and Short-Circuit
Protection
Because the SP765ꢀ is designed to drive
largeoutputcurrent,thereisachancethatthe
power converter will become too hot. There-
fore, an internal thermal shutdown (145°C)
has been included to prevent the IC from
malfunctioning at extreme temperatures.
A short-circuit detection comparator has
also been included in the SP765ꢀ to protect
against an accidental short at the output
of the power converter. This comparator
constantly monitors the positive and nega-
tive terminals of the error amplifier, and if
the VFB pin falls more than 250mV (typical)
below the positive reference, a short-circuit
faultisset.BecausetheSSpinoverridesthe
internal 0.8V reference during soft start, the
SP765ꢀ is capable of detecting short-circuit
faults throughout the duration of soft start as
well as in regular operation.
Soft Start
“Soft Start” is achieved when a power con-
verter ramps up the output voltage while
controlling the magnitude of the input sup-
ply source current. In a modern step down
converter, ramping up the positive terminal
of the error amplifier controls soft start. As a
result,excesssourcecurrentcanbedefined
as the current required to charge the output
capacitor.
IVIN = COUT * (∆VOUT / ∆TSOFT-START
)
Handling of Faults:
The SP765ꢀ provides the user with the op-
tion to program the soft start rate by tying
a capacitor from the SS pin to GND. The
selection of this capacitor is based on the
ꢀ0µA pullup current present at the SS pin
and the 0.8V reference voltage. Therefore,
the excess source can be redefined as:
Upon the detection of power (UVLO), ther-
mal, or short-circuit faults, the SP765ꢀ is
forced into an idle state where the SS and
COMP pins are pulled low and the NFETS
are held off. In the event of UVLO fault, the
SP765ꢀ remains in this idle state until the
UVLO fault is removed. Upon the detection
of a thermal or short-circuit fault, an internal
200ms timer is activated. In the event of a
short-circuit fault, a re-start is attempted im-
mediately after the 200ms timeout expires.
Whereas, when a thermal fault is detected
the200msdelaycontinuouslyrecyclesanda
re-startcannotbeattempteduntilthethermal
fault is removed and the timer expires.
IVIN = COUT * (∆VOUT *ꢀ0µA / (CSS * 0.8V)
Under Voltage Lock Out (UVLO)
The SP765ꢀ contains two separate UVLO
comparatorstomonitortheinternalbias(VCC
)
andconversion(VIN)voltagesindependently.
The VCC UVLO threshold is internally set
to 4.25V, whereas the VIN UVLO threshold
is programmable through the UVIN pin.
When the UVIN pin is greater than 2.5V,
the SP765ꢀ is permitted to start up pend-
ing the removal of all other faults. Both the
VCC and VIN UVLO comparators have been
designed with hysteresis to prevent noise
from resetting a fault.
Error Amplifier and Voltage Loop
Since the heart of the SP765ꢀ voltage error
loop is a high performance, wide bandwidth
transconductance amplifier, great care
shouldbetakentoselecttheoptimalcompen-
sation network. Because of the amplifier’s
Rev J: 3/ꢀ4/07
SP765ꢀ Wide Input Voltage Range 3A, 900kHz, Buck Regulator
© Copyright 2007 Sipex Corporation
5
THEORY OF OPERATION
current- limited (+/-ꢀ50µA) transconduc-
tance, there are many ways to compensate
the voltage loop or to control the COMP pin
externally. Ifasimple,singlepole,singlezero
responseisdesired,thencompensationcan
be as simple as an RC circuit to Ground. If
a more complex compensation is required,
then the amplifier has enough bandwidth
(45° at 4 MHz) and enough gain (60dB) to
runTypeIIIcompensationschemeswithad-
equategainandphasemarginsatcrossover
frequencies greater than 50kHz.
V
BST
GH
Voltage
V
SWN
V(V
CC)
GL
Voltage
0V
V(V
)
IN
SWN
Voltage
-0V
-V(Diode) V
The common mode output of the error am-
plifier is 0.9V to 2.2V. Therefore, the PWM
voltageramphasbeensetbetweenꢀ.ꢀVand
2.2Vtoensureproper0%to100%dutycycle
capability. The voltage loop also includes
two other very important features. One is
asynchronous startup mode. Basically, the
synchronous rectifier cannot turn on unless
the high side NFET has attempted to turn
on or the SS pin has exceeded ꢀ.7V. This
featurepreventsthecontrollerfrom“dragging
down” the output voltage during startup or in
fault modes. The second feature is a 100%
dutycycletimeoutthatensuressynchronized
refreshing of the BST capacitor at very high
duty ratios. In the event that the high side
NFET is on for 20 continuous clock cycles,
a reset is given to the PWM flip-flop half
way through the 21st cycle. This forces GL
to rise for the cycle, in turn refreshing the
BST capacitor.
V(V )+V(V
)
CC
IN
BST
Voltage
V(V
)
CC
TIME
Setting Output Voltages
The SP765ꢀ can be set to different output
voltages. The relationship in the following
formula is based on a voltage divider from
the output to the feedback pin VFB, which is
settoaninternalreferencevoltageof0.80V.
Standard 1% metal film resistors of surface
mount size 0603 are recommended.
Vout = 0.80V ( Rꢀ / R2 + ꢀ ) =>
Power MOSFETs
Rꢀ
R2=
[(Vout /0.80V) -ꢀ]
TheSP765ꢀcontainsapairofintegratedlow
resistance N MOSFETs designed to drive
up to 3A of output current. Maximum output
currentcouldbelimitedbythermallimitations
of a particular application. The SP765ꢀ
incorporates a built-in over-temperature
protection to prevent internal overheating.
Where R1 = 68.1KΩ and for Vout = 0.80V
setting, simply remove R2 from the board.
Furthermore, one could select the value
of the Rꢀ and R2 combination to meet the
exact output voltage setting by restricting
R1 resistance range such that 50KΩ < R1 <
100KΩ for overall system loop stability.
Rev J: 3/ꢀ4/07
SP765ꢀ Wide Input Voltage Range 3A, 900kHz, Buck Regulator
© Copyright 2007 Sipex Corporation
6
APPLICATIONS INFORMATION
Ipp
2
Inductor Selection
Ipeak= iout(max) +
There are many factors to consider in se-
lectingtheinductor, including:corematerial,
inductance vs. frequency, current handling
capability, efficiency, size and EMI. In a typi-
cal SP765ꢀ circuit, the inductor is chosen
primarily by operating frequency, saturation
current and DC resistance. Increasing the
inductor value will decrease output voltage
ripple, but degrade transient response. Low
inductorvaluesprovidethesmallestsize,but
cause large ripple currents, poor efficiency
and require more output capacitance to
smooth out the larger ripple current. The
inductor must be able to handle the peak
current at the switching frequency without
saturating, and the copper resistance in the
winding should be kept as low as possible to
minimize resistive power loss. A good com-
promisebetweensize, lossandcostistoset
the inductor ripple current to be within 20%
to 40% of the maximum output current.
...andprovidelowcorelossatthehighswitch-
ingfrequency.Lowcostpowdered-ironcores
are inappropriate for 900kHz operation
.
Gappedferriteinductorsarewidelyavailable
for consideration. Select devices that have
operating data shown up to ꢀMHz. Ferrite
materials, on the other hand, are more
expensive and have an abrupt saturation
characteristic with the inductance dropping
sharply when the peak design current is
exceeded. Nevertheless, they are preferred
at high switching frequencies because they
present very low core loss and the design
only needs to prevent saturation. In general,
ferrite or molypermalloy materials will be
used with the SP765ꢀ.
Optimizing Efficiency
Thepowerdissipatedintheinductorisequal
to the sum of the core and copper losses. To
minimize copper losses, the winding resis-
tance needs to be minimized, but this usu-
ally comes at the expense of using a larger
inductor.Corelosseshaveamoresignificant
contribution at low output current where the
copper losses are at a minimum, and can
typically be neglected at higher output cur-
rents where the copper losses dominate.
Core loss information is usually available
from the magnetics vendor. Proper inductor
selection can affect the resulting power sup-
ply efficiency by more than 15-20%!
The switching frequency and the inductor
operatingpointdeterminetheinductorvalue
as follows:
Vout (Vin(max) - Vout)
Vin(max) fs Kr Iout(max)
L=
where:
Fs = switching frequency
Kr = ratio of the AC inductor ripple current
to the maximum output current
The copper loss in the inductor can be cal-
culated using the following equation:
The peak-to-peak inductor ripple current
is:
PL(cu)=i2L(rms) rwinding
Vout(Vin(max) - Vout)
Ipp=
Vin(max) fs L
where IL(RMS) is the RMS inductor current
that can be calculated as follows:
Once the required inductor value is se-
lected, the proper selection of core mate-
rial is based on peak inductor current and
efficiency requirements. The core must be
large enough not to saturate at the peak
inductor current...
2
Ipp
ꢀ
3
IL(rms)=iout(max) 1 + ( Iout(max))
Rev J: 3/ꢀ4/07
SP765ꢀ Wide Input Voltage Range 3A, 900kHz, Buck Regulator
© Copyright 2007 Sipex Corporation
7
APPLICATIONS INFORMATION
FS = Switching Frequency
Output Capacitor Selection
The required ESR (Equivalent Series Re-
sistance) and capacitance drive the selec-
tion of the type and quantity of the output
capacitors. The ESR must be small enough
that both the resistive voltage deviation due
to a step change in the load current and
the output ripple voltage do not exceed
the tolerance limits expected on the output
voltage. During an output load transient,
the output capacitor must supply all the ad-
ditional current demanded by the load until
the SP7651 adjusts the inductor current to
the new value.
D = Duty Cycle
COUT = Output Capacitance Value
Input Capacitor Selection
The input capacitor should be selected for
ripple current rating, capacitance and volt-
age rating. The input capacitor must meet
the ripple current requirement imposed
by the switching current. In continuous
conduction mode, the source current of
the high-side MOSFET is approximately
a square wave of duty cycle VOUT/VIN.
Most of this current is supplied by the
input bypass capacitors. The RMS value
of input capacitor current is determined at
the maximum output current and under the
assumption that the peak-
In order to maintain VOUT, the capacitance
must be large enough so that the output
voltage is held up while the inductor current
ramps up or down to the value correspond-
ing to the new load current. Additionally, the
ESR in the output capacitor causes a step
in the output voltage equal to the current.
Because of the fast transient response and
inherent 100% to 0% duty cycle capability
provided by the SP765ꢀ when exposed to
anoutputloadtransient,theoutputcapacitor
is typically chosen for ESR, not for capaci-
tance value.
to-peak inductor ripple current is low; it is given
by:
ICIN(rms) = IOUT(max) √D(ꢀ - D)
The worse case occurs when the duty cycle
D is 50% and gives an RMS current value
equal to IOUT/2. Select input capacitors with
adequate ripple current rating to ensure reli-
able operation.
The ESR of the output capacitor, combined
with the inductor ripple current, is typically
the main contributor to output voltage ripple.
The maximum allowable ESR required to
maintain a specified output voltage ripple
can be calculated by:
The power dissipated in the input capaci-
tor is:
Pon= i2on(rms) resr(cin)
This can become a significant part of power
losses in a converter and hurt the overall
energy transfer efficiency. The input volt-
age ripple primarily depends on the input
capacitor ESR and capacitance. Ignoring
the inductor ripple current, the input voltage
ripple can be determined by:
∆Vout
Resr ≤
Ipk-pk
where:
∆VOUT = Peak-to-Peak Output Voltage
Ripple
∆Vin=iout(max) resr(cin) +
IPK-PK = Peak-to-Peak Inductor Ripple Cur-
rent
Iout(max) Vout (Vin-Vout)
The total output ripple is a combination of
the ESR and the output capacitance value
and can be calculated as follows:
2
FscinVin
The capacitor type suitable for the output
capacitors can also be used for the input ca-
pacitors. However, exercise extra caution
2
IPP (ꢀ – D)
2
∆VOUT
=
(
)
+ (IPPRESR)
COUTFS
Rev J: 3/ꢀ4/07
SP765ꢀ Wide Input Voltage Range 3A, 900kHz, Buck Regulator
© Copyright 2007 Sipex Corporation
8
APPLICATIONS INFORMATION
systemstability.Crossoverfrequencyshould
be higher than the ESR zero but less than
ꢀ/5 of the switching frequency. The ESR
zero is contributed by the ESR associated
with the output capacitors and can be de-
termined by:
whentantalumcapacitorsareused.Tantalum
capacitorsareknownforcatastrophicfailure
when exposed to surge current, and input
capacitors are prone to such surge current
when power supplies are connected “live”
to low impedance power sources.
Loop Compensation Design
ƒꢁ(ESR)
=
ꢀ
.
The open loop gain of the whole system
can be divided into the gain of the error
amplifier, PWM modulator, buck converter
output stage, and feedback resistor divider.
In order to cross over at the selected fre-
quency FCO, the gain of the error amplifier
compensates for the attenuation caused by
the rest of the loop at this frequency. The
goal of loop compensation is to manipulate
loop frequency response such that its gain
crosses over 0db at a slope of -20db/dec.
The first step of compensation design is to
pick the loop crossover frequency.
2π COUT RESR
The next step is to calculate the complex
conjugate poles contributed by the LC
output filter,
ƒP(LC)
=
ꢀ
.
2π
√
L COUT
When the output capacitors are Ceramic
type, theSP765ꢀEvaluationBoardrequires
aTypeIIIcompensationcircuittogiveaphase
boostof180°inordertocounteracttheeffects
of an underdamped resonance of the output
filter at the double pole frequency.
High crossover frequency is desirable for
fasttransientresponse,butoftenjeopardizes
the higher than the ESR zero but less than
ꢀ/5 of the switching frequency. The ESR
zero is contributed by the ESR associated
with the output capacitors and can be de-
termined by:
Type III V oltage Loop
Compensation
G AMP (s) Gain Block
PWM Stage
G PWM Gain
Block
Output Stage
G OUT (s) Gain
Block
(SRz2Cz2+1)(SR1Cz3+1)
VIN
(SR
COUT + 1)
ESR
VREF
(Volts)
+
_
VOUT
(Volts)
SR1Cz2(SRz3Cz3+1)(SRz2Cp1+1)
VRAMP_PP
[S^2LC
+S(R ESR +R DC) C OUT +1]
OUT
Notes: R
= Output Capacitor Equivalent Series Resistance.
ESR
RDC = Output Inductor DC Resistance.
VRAMP_PP = SP6132 Internal RA MP Amplitude Peak to Peak V oltage.
Condition: Cz2 >> Cp1 & R1 >> Rz3
Output Load Resistance >> R
& R
DC
ESR
Voltage Feedback
G FBK Gain Block
R2
R 2
VREF
VOUT
or
(R
)
1
+
VFBK
(Volts)
SP765ꢀ Voltage Mode Control Loop with Loop Dynamic
Definitions:
R
R
R
ESR = Output Capacitor Equivalent Series Resistance
DC = Output Inductor DC Resistance
RAMP_PP = SP765ꢀ internal RAMP Amplitude Peak-to-Peak Voltage
Rev J: 3/ꢀ4/07
SP765ꢀ Wide Input Voltage Range 3A, 900kHz, Buck Regulator
© Copyright 2007 Sipex Corporation
9
APPLICATIONS INFORMATION
Gain
(dB)
Error Amplifier Gain
Bandwidth Product
Condition:
C22 >> CP1, R1 >> RZ3
20 Log (RZ2/R1)
Frequency
(Hz)
Bode Plot of Type III Error Amplifier Compensation.
CP1
RZ2
CZ2
RZ3
CZ3
V
OUT
5
VFB
-
R1
68.1k, 1%
6
+
COMP
R
SET
CF1
+
0.8V
-
R
-0.8)
=54.48/ (V
(kΩ)
SET
OUT
Type III Error Amplifier Compensation Circuit
Rev J: 3/ꢀ4/07
SP765ꢀ Wide Input Voltage Range 3A, 900kHz, Buck Regulator
© Copyright 2007 Sipex Corporation
ꢀ0
APPLICATIONS INFORMATION
data was taken for still air, not with
forced air. If forced air is used, some
improvement in thermal resistance
would be seen.
SP765X Thermal Resistance
The SP765X family has been tested with a
variety of footprint layouts along with differ-
entcopperareaandthermalresistancehas
been measured. The layouts were done on
4 layer FR4 PCB with the top and bottom
layers using 3oz copper and the power and
ground layers using ꢀoz copper.
SP765X Thermal Resistance
For the Minimum footprint, only about 0.ꢀ
square inch of 3 ounces of copper was
used on the top or footprint layer, and this
layer had no vias to connect to the 3 other
layers. For the Medium footprint, about 0.7
square inches of 3 ounces of copper was
used on the top layer, but vias were used
to connect to the other 3 layers. For the
Maximum footprint, about ꢀ.0 square inch
of 3 ounces of copper was used on the top
layer and many vias were used to connect
to the 3 other layers.
4 Layer Board:
Top Layer 3ounces Copper
GND Layer 1ounce Copper
Power Layer ꢀounce Copper
Bottom Layer 3ounces Copper
Minimum Footprint: 44°C/W
Top Layer: 0.ꢀ square inch
No Vias to other 3 Layers
Medium Footprint: 36°C/W
Top Layer: 0.7 square inch
Vias to other 3 Layers
Maximum Footprint: 36°C/W
Top Layer: ꢀ.0 square inch
Vias to other 3 Layers
Theresultsshowthatonlyabout0.7square
inches of 3 ounces of copper on the top
layer and vias connecting to the 3 other
layers are needed to get the best thermal
resistance of 36°C/W. Adding area on the
top beyond the 0.7 square inches did not
reduce thermal resistance.
Using a minimum of 0.ꢀ square inches of
(3 ounces of) Copper on the top layer with
no vias connecting to the 3 other layers
produced a thermal resistance of 44°C/W.
This thermal impedance is only 22% higher
thanthemediumandlargefootprintlayouts,
indicating that space constrained designs
canstillbenefitthermallyfromthePowerblox
familyofICs. Thisindicatesthataminimum
footprint of 0.ꢀ square inch, if used on a
4 layer board, can produce 44°C/W ther-
mal resistance. This approach is still very
worthwhile if used in a space constrained
design.
The following page shows the footprint
layouts from an ORCAD file. The thermal
Rev J: 3/ꢀ4/07
SP765ꢀ Wide Input Voltage Range 3A, 900kHz, Buck Regulator
© Copyright 2007 Sipex Corporation
ꢀꢀ
Rev J: 3/ꢀ4/07
SP765ꢀ Wide Input Voltage Range 3A, 900kHz, Buck Regulator
© Copyright 2007 Sipex Corporation
ꢀ2
TYPICAL PERFORMANCE CHARACTERISITICS
Rev J: 3/ꢀ4/07
SP765ꢀ Wide Input Voltage Range 3A, 900kHz, Buck Regulator
© Copyright 2007 Sipex Corporation
ꢀ3
PACꢀAGE: 26 PIN DFN
Rev J: 3/ꢀ4/07
SP765ꢀ Wide Input Voltage Range 3A, 900kHz, Buck Regulator
© Copyright 2007 Sipex Corporation
ꢀ4
ORDERING INFORMATION
Part Number
SP765ꢀER
Package Code
DFN26
RoHS
MIN. Temp. (°C)
MAX. Temp.(°C)
Status
Active
Active
Active
Active
Pack Quantity
Bulk
-40
-40
-40
-40
85
85
85
85
SP765ꢀER/TR
SP765ꢀER-L
SP765ꢀER-L/TR
DFN26
500 Tape & Reel
Bulk
DFN26
▪
▪
DFN26
500 Tape & Reel
Sipex Corporation
Headquarters and
Sales Office
233 South Hillview Drive
Milpitas, CA 95035
TEL: (408) 934-7500
FAX: (408) 935-7600
Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the applica-
tion or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.
Rev J: 3/ꢀ4/07
SP765ꢀ Wide Input Voltage Range 3A, 900kHz, Buck Regulator
© Copyright 2007 Sipex Corporation
ꢀ5
相关型号：
SP7652ER-L
Switching Regulator, Voltage-mode, 10A, 720kHz Switching Freq-Max, PDSO26, 7 X 4 MM, LEAD FREE, DFN-26
SIPEX
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