SP7655EB_技术文档

SP7655

Evaluation Board Manual

Easy Evaluation for the

SP7655ER 24V Input, 0 to 8A

Output Synchronous Buck

Converter

Built in Low Rds(on) Power FETs

UVLO Detects Both VCC and VIN

High Integrated Design, Minimal

Components

High Efficiency: 85%

Feature Rich: UVIN, Programmable

Softstart, External VCC Supply and

Output Dead Short Circuit Shutdown

SP7655EB SCHEMATIC

U1

SP7655

L1 IHLP-2525CZ-01-2R2MTR

1

26

PGND

LX

VOUT

2.2uH, Irate=8A

2

25

3.30V

0-8A

PGND

LX

RZ2

CZ2

DCR=10.4mOhm

RZ3

3

4

24

23

22

21

20

19

18

17

16

15

14

PGND

GND

VFB

COMP

UVIN

GND

SS

C3

8.66k,1%

7.68k,1%

2,200pF

R1

68.1k,1%

LX

47uF

CP1

5

6.3V

CZ3

120pF

VCC

GND

BST

NC

6

15pF

CVCC

2.2uF

7

fs=300Khz

CF1

GND2

C3

8

100pF

DBST

9

R2

21.5k,1%

10

11

12

13

CERAMIC

1210

CSS

SD101AWS

VIN

47nF

VIN

LX

X5R

VIN

LX

CBST

1uF

VIN

LX

VIN

24V

U2

R3

SPX5205

VIN VOUT

GND

D1

499k,1%

C1,C4

Notes:

1

2

3

5

4

CERAMIC C1

C4

U1 Bottom-Side Layout should

three Contacts which

isolated from one of another,

& QB Drain Contact

MMSZ4678T1

3.3uF

50V

1210

Y5V

3.3uF

50V

Vz=12V

EN

BYP

R4

C2

0.1uF

100k,1%

GND

Controller GND

All resistor & capacitor

0603 unless other wise

Date: 2/01/05

SP7655 Evaluation Manual

USING THE EVALUATION BOARD

1) Powering Up the SP7655EB Circuit

Connect the SP7655 Evaluation Board with an external +24V power supply. Connect

with short leads and large diameter wire directly to the “VIN” and “GND” posts. Connect

a Load between the VOUT and GND2 posts, again using short leads with large

diameter wire to minimize inductance and voltage drops.

2) Measuring Output Load Characteristics

VOUT ripple can best be seen touching probe tip to the pad for C3 and scope GND

collar touching GND side of C3 using short wrapped wire around collar – avoid a GND

lead on the scope which will increase noise pickup.

3) Using the Evaluation Board with Different Output Voltages

While the SP7655 Evaluation Board has been tested and delivered with the output set

to 3.30V, by simply changing one resistor, R2, the SP7655 can be set to other output

voltages. The relationship in the following formula is based on a voltage divider from the

output to the feedback pin VFB, which is set to an internal reference voltage of 0.80V.

Standard 1% metal film resistors of surface mount size 0603 are recommended.

Vout = 0.80V (R1 / R2 + 1 ) => R2 = R1 / [ ( Vout / 0.80V ) – 1 ]

Where R1 = 68.1KΩ and for Vout = 0.80V setting, simply remove R2 from the board.

Furthermore, one could select the value of R1 and R2 combination to meet the exact

output voltage setting by restricting R1 resistance range such that 50KΩ ≤ R1 ≤ 100KΩ

for overall system loop stability.

Note that since the SP7655 Evaluation Board design was optimized for 24V down

conversion to 3.30V, changes of output voltage and/or input voltage will alter

performance from the data given in the Power Supply Data section. In addition, the

SP7655ER provides short circuit protection by sensing Vout at GND.

POWER SUPPLY DATA

The SP7655ER is designed with a very accurate 1.0% reference over line, load and

temperature. Figure 1 data shows a typical SP7655 Evaluation Board Efficiency plot,

with efficiencies to 85% (Including generation of 5V Vcc) and output currents to 8A.

SP7655ER Load Regulation is shown in Figure 2 of only 1% change in output voltage

from 0.5A load to 8A load. Figures 3 and 4 illustrate a 5A to 8A and 0A to 6A Load Step.

Start-up Response in Figures 5, 6 and 7 show a controlled start-up with different output

load behavior when power is applied where the input current rises smoothly as the

Softstart ramp increases. In Figure 8 the SP7655ER is configured for hiccup mode in

response to an output dead short circuit condition and will Softstart until the over-load is

removed. Figure 9 and 10 show output voltage ripple less than 135mV at no load to 8A

load.

While data on individual power supply boards may vary, the capability of the SP7655ER

of achieving high accuracy over a range of load conditions shown here is quite

impressive and desirable for accurate power supply design.

2

Efficiency vs Load (24V to 3.3V)

Load Regulation (24V to 3.3V)

100.00

90.00

80.00

70.00

60.00

3.340

3.320

3.300

3.280

3.260

0.5

1

2

3

4

6

8

0.5

1

2

3

4

6

8

Load Current (A)

Output Current (A)

Figure 1. Efficiency vs Load

Figure 2. Load Regulation

Vout

Iout (2A/div)

Figure 3. Load Step Response: 5->8A

Figure 4. Load Step Response: 0->6A

Vout

Vin

SoftStart

Vin

SoftStart

Iout (2A/div)

Figure 5. Start-Up Response: No Load

Figure 6. Start-Up Response: 3.0A Load

Vout

SoftStart

Vout

Vin

SoftStart

Ichoke (10A/div)

Iout (5A/div)

Figure 7. Start-Up Response: 8A Load

Figure 8. Output Load Short Circuit

3

Vout ripple = 100mV

Ichoke (5A/div)

Vout ripple = 134mV

Ichoke (5A/div)

Figure 9. Output Ripple: No Load

Load

Figure 10. Output Ripple: 8A

TYPE III LOOP COMPENSATION DESIGN

The open loop gain of the SP7655EB can be divided into the gain of the error amplifier

Gamp(s), PWM modulator Gpwm, buck converter output stage Gout(s), and feedback

resistor divider Gfbk. In order to crossover at the selecting frequency fco, the gain of

the error amplifier has to compensate for the attenuation caused by the rest of the loop

at this frequency. The goal of loop compensation is to manipulate the open loop

frequency response such that its gain crosses over 0dB at a slope of –20dB/dec. The

open loop crossover frequency should be higher than the ESR zero of the output

capacitors but less than 1/5 to 1/10 of the switching frequency fs to insure proper

operation. Since the SP7655EB is designed with Ceramic Type output capacitors, a

Type III compensation circuit is required to give a phase boost of 180° in order to

counteract the effects of the output LC under damped resonance double pole

frequency.

4

PWM Stage

Output Stage

Type III Voltage

L

Compensation Gamp(S)

Gpwm

Gout(S)

Gain Block

(SRz2Cz2+1)(SR1Cz

(SResrCout+

Vin

Vramp_p

Vref

(Volts

Vout

(Volts

)

3+1)

1)

SR1Cz2(SRz3Cz3+1)(SRz2C

[S^2LCout+S(Resr+Rdc)Co

1+1)

t+1]

Voltage Feedback

Gfbk

Gain Block

R2

(R1+R2

)

Vref

Vout

OR

Vfbk

(Volts

)

Definition

Resr

Rdc

:= Output Capacitor Equivalent Series Resitance

:= Output Inductor DC Resistance

Vramp_pp := SP7655 Internal RAMP Amplitude Peak to Peak Voltage

Condition

Cz2 >> Cp1 and R1 >> Rz3

Output Load Resistance >> Resr and Rdc

Figure 11. Voltage Mode Control Loop with Loop Dynamic for Type III Compensation

5

The simple guidelines for positioning the poles and zeros and for calculating the

component values for Type III compensation are as follows:

a.

b.

Choose fco = fs / 5

Calculate fp_LC

fp_LC = 1 / 2π [(L) (C)] ^ 1/2

c.

Calculate fz_ESR

fz_ESR = 1 / 2π (Resr) (Cout)

d.

e.

Select R1 component value such that 50kΩ ≤ R1 ≤ 100kΩ

Calculate R2 base on the desired Vout

R2 = R1 / [(Vout / 0.80V) – 1]

f.

Select the ratio of Rz2 / R1 gain for the desired gain bandwidth

Rz2 = R1 (Vramp_pp / Vin_max) (fco / fp_LC)

g.

h.

i.

Calculate Cz2 by placing the zero at ½ of the output filter pole frequency

Cz2 = 1 / π (Rz2) (fp_LC)

Calculate Cp1 by placing the first pole at ESR zero frequency

Cp1 = 1 / 2π (Rz2) (fz_ESR)

Calculate Rz3 by setting the second pole at ½ of the switching frequency and the

second zero at the output filter double pole frequency

Rz3 = 2 (R1) (fp_LC) / fs

j.

Calculate Cz3 from Rz3 component value above

Cz3 = 1 / π (Rz3) (fs)

k.

Choose 100pF ≤ Cf1 ≤ 220pF to stabilize the SP7655ER internal Error Amplify

6

APPLICATION CIRCUIT FOR 12V INPUT

Figure 12 shows another example of the SP7655ER configured for a common Bus

Voltage conversion from +12V input to 3.3V output at 8A.

U1

SP7655

L1 IHLP-2525CZ-01-2R2MTR

1

2

26

25

24

23

22

21

20

19

18

17

16

15

14

PGND

GND

VFB

LX

VOUT

3.30V

0-8A

2.2uH, Irate=8A

RZ2

CZ2

DCR=10.4mOhm

RZ3

3

LX

C3

8.66k,1%

7.68k,1%

2,200pF

4

R1

68.1k,1%

LX

47uF

CP1

5

6.3V

CZ3

120pF

VCC

GND

BST

NC

6

15pF

fs=300Khz

COMP

UVIN

GND

SS

CVCC

2.2uF

7

CF1

GND2

C3

8

100pF

DBST

9

R2

21.5k,1%

10

11

12

13

CERAMIC

1210

CSS

47nF

VIN

SD101AWS

VIN

LX

X5R

VIN

LX

CBST

1uF

VIN

LX

VIN

12V

U2

R3

SPX5205

VIN VOUT

GND

200k,1%

C1,C4

CERAMIC

1210

Notes:

1

2

3

5

4

C1

C4

3.3uF

50V

U1 Bottom-Side Layout should has

three Contacts which are

isolated from one of another, QT

& QB Drain Contact and

3.3uF

50V

Y5V

EN

BYP

R4

100k,1%

C2

0.1uF

GND

Controller GND Contact

All resistor

& capacitor size

0603 unless other

Figure 12. SP7655ER configured for Vin = 12V, Vout = 3.3V at 0-8A^wO^iseu^st^pp^ecu^ift^yLoad

Current

Load Regulation (12V to 3.3V)

Efficiency vs Load (12V to 3.3V)

3.340

100

3.335

3.330

3.325

3.320

3.315

3.310

3.305

3.300

90

80

70

60

0

1

2

3

4

5

6

7

8

0.5

1

2

3

4

5

6

7

8

Load Current (A)

Output Current (A)

Figure 13. Efficiency vs Load

Figure 14. Load Regulation

Vout

Iout (2A/div)

Figure 15. Load Step Response: 5-8A

Figure 16. Load Step Response: 0-6A

7

PC LAYOUT DRAWINGS

Figure 17. SP7655EB Component Placement

Figure 18. SP7655EB PC Layout Top Side

Figure 19. SP7655EB PC Layout 2^ndLayer Side

8

Figure 20. SP7655EB PC Layout 3^rdLayer Side

Figure 21. SP7655EB PC Layout Bottom Side

9

Table 1: SP7655EB List of Materials

SP7655 Vin=28V Evaluation Board Rev. 00 List of Materials

6/18/04

Line

No.

1

Ref.

Qty.

Manuf.

Layout

Size

Component

Vendor

Des.

Part Number

F146-6570-00

SP7655EU

Phone Number

978-667-8700

978-667-7800

402-563-6866

800-344-4539

914-347-2474

978-779-3111

800-344-4539

PCB

1

2

1

4

Sipex

1.75"X2.75"

DFN-26

SP7655EB

2

U1

2-FETs Buck Ctrl

3

U2

SPX5205M5-5.0

SD101AWS

MMSZ4678T1

SOT-23-5

SOD-323

SOD-123

150mA LDO Voltage Reg

15mA Schottky Diode

4

DBST

Vishay Semi

ON Semi

Vishay

TDK

5

D1

12V, 500mW Zener Diode

2.2uH Coil 8A 10.4mohm

47uF Ceramic X5R 6.3V

3.3uF Ceramic X7R 50V

2.2uF Ceramic X5R 10V

1.0uF Ceramic X5R 10V

0.1uF Ceramic X7R 50V

47,000pF Ceramic X7R 50V

15pF Ceramic COG 50V

2,200pF Ceramic COG 50V

100pF Ceramic COG 50V

120pF Ceramic COG 50V

7.68K Ohm Thick Film Res 1%

21.5K Ohm Thick Film Res 1%

8.66K Ohm Thick Film Res 1%

68.1K Ohm Thick Film Res 1%

499K Ohm Thick Film Res 1%

20.0 Ohm Thick Film Res 1%

100K Ohm Thick Film Res 1%

Input/Output Terminal Posts

6

L1

IHLP-2525CZ-01-2R2MTR 6.86x6.47mm

7

C3

C3225X5R0J476M

C3225X7R1H335M

C1608X5R1A225K

GRM188R61A105KA61D

C1608X7R1H104K

CL10B473KB8NNNC

06035A150JAT2A

1210

0603

.042 Dia

8

C1,C4

TDK

9

CVCC

TDK

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

CBST

Murata

TDK

C2

CSS

Samsung

AVX

CP1

CZ2

TDK

C1608COG1H222J

MCH185A101JK

06035A121JAT2A

CF1

ROHM

AVX

CZ3

RZ2

ROHM

SEI Electronics

Vishay

ROHM

Vishay

MCR03EZPFX7681

RMC-1/16W-21.5K-1%

CRCW0603-8661FRT1

CRCW0603-6812FRT1

CRCW0603-4993FRT1

MCR03EZPEFX20R0

CRCW0603-1003FRT1

K24C/M

R2

RZ3

R1

R3

RBST

R4

VIN, VOUT, GND, GND2

Vector Electronic

ORDERING INFORMATION

Temperature Range

Model

Package Type

SP7655EB…................................-40°C to +85°C...............…SP7655 Evaluation Board

SP7655ER..............................…. -40°C to +85°C.................................……26-pin DFN

10


型号：	SP7655EB
厂家：	SIPEX CORPORATION
描述：	Evaluation Board Manual 评估板手册
文件：	总10页 (文件大小：491K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SP7655EB [SIPEX]

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