SP800LEN-L/TR_技术文档

®

SP691A/693A/800L/800M

Low Power Microprocessor Supervisory

with Battery Switch-Over

FEATURES

TOP VIEW

■ Precision 4.65V/4.40V Voltage Monitoring

■ 200ms Or Adjustable Reset Time

■ 100ms, 1.6s Or Adjustable Watchdog Time

■ 60µA Maximum Operating Supply Current

■ 2.0µA Maximum Battery Backup Current

■ 0.1µA Maximum Battery Standby Current

1

2

3

4

5

6

7

8

16

15

VBATT

VOUT

RESET

Vcc

14 WDO

GND

13

12

CEIN

CEOUT

WDI

Corporation

BATT ON

LOWLINE

11

10

■ Power Switching

OSCIN

PFO

PFI

250mA Output in Vcc Mode (0.6Ω)

25mA Output in Battery Mode (5Ω)

9

OSCSEL

■ On-Board Gating of Chip-Enable Signals

Memory Write-Cycle Completion

6ns CE Gate Propagation Delay

DIP/SO

Now Available in Lead Free Packaging

■ Voltage Monitor for Power-Fail or Low Battery

■ Backup-Battery Monitor

■ RESET Valid to Vcc=1V

■ 1% Accuracy Guaranteed (SP800L/800M)

■ Pin Compatible Upgrade to MAX691A/693A/

800L/800M

DESCRIPTION

The SP691A/693A/800L/800M is a microprocessor (µP) supervisory circuit that integrates

a myriad of components involved in discrete solutions to monitor power-supply and

battery-control functions in µP and digital systems. The SP691A/693A/800L/800M offers

complete µP monitoring and watchdog functions. The SP691A/693A/800L/800M is ideal for

a low-cost battery management solution and is well suited for portable, battery-powered

applications with its supply current of 35µA. The 6ns chip-enable propagation delay,

the 25mA current output in battery-backup mode, and the 250mA current output in

standard operation also makes the SP691A/693A/800L/800M suitable for larger scale,

high-performance equipment.

Part Number

SP691A

RESET Threshold RESET Accuracy

PFI Accuracy

+4%

Backup-Battery Switch

4.65V

4.40V

4.65V

4.40V

+125mV

+50mV

YES

SP693A

+4%

SP800L

+1%

SP800M

+1%

Date: 4/18/05

1

ABSOLUTE MAXIMUM RATINGS

These are stress ratings only and functional operation

of the device at these ratings or any other above those

indicated in the operation sections of the specifications

below is not implied. Exposure to absolute maximum

rating conditions for extended periods of time may

affect reliability.

Enhanced ESD Specifications........................+4kV Human Body Model

Power Dissipation Per Package

16-pin PDIP (derate 14.3mW/^OC above +70^OC).......................1150mW

16-pin Narrow SOIC (derate 13.6mW/^OC above 70^OC)............1090mW

16-pin Wide SOIC (derate 11.2mW/^OC above 70^OC).................900mW

Storage Temperature....................................................-65^OC to +150^OC

Lead Temperature (soldering,10 sec).........................................+300^OC

Terminal Voltages (with respect to GND)

V_CC.......................................................................................-0.3V to +6V

V_BATT.....................................................................................-0.3V to +6V

All Other Inputs........................................................-0.3V to (V_CC+0.3V)

Input Currents

V_CCPeak...........................................................................................1.0A

V_CCContinuous.............................................................................250mA

V_BATTPeak....................................................................................250mA

V_BATTContinuous............................................................................25mA

GND, BATT ON............................................................................100mA

All Other Inputs..............................................................................25mA

ELECTRICAL CHARACTERISTICS

V_CC= +4.75V to +5.5V for the SP691A/800L, V_CC= +4.5V to +5.5V for the SP693A/800M, V_BATT= +2.8V, and T_AMB= T_MINto T_MAXunless otherwise

noted. Typical values apply at T_AMB=+25^OC.

PARAMETERS

MIN.

TYP.

MAX. UNITS CONDITIONS

Operating Voltage Range,

V_CCor V_BATT, NOTE 1

0

5.5

V

Ω

Output Voltage, V_OUT

V_CC-0.05

V_CC-0.3

V_CC-0.2

V_CC-0.015

V_CC-0.15

V_CC-0.09

V_CC=4.5V, I_OUT=25mA

in Normal Operating Mode

V_CC=4.5V, I_OUT=250mA

V_CC=3.0V, V_BATT=2.8V, I_OUT=100mA

V_CC-to-V_OUTOn-Resistance

V_OUTin Battery-Backup Mode

0.6

0.9

1.2

2.0

V_CC=4.5V

V_CC=3.0V

V_BATT-0.3

V_BATT-0.1

V_BATT=4.5V, I_OUT=20mA

V_BATT=2.8V, I_OUT=10mA

V_BATT=2.0V, I_OUT=5mA

V_BATT-0.25 V_BATT-0.07

V_BATT-0.15 V_BATT-0.05

V

V_BATT-to-V_OUTOn-Resistance

5

7

15

25

30

V_BATT=4.5V

V_BATT=2.8V

V_BATT=2.0V

Ω

10

Supply Current in Normal

Operating Mode, I_Vcc

µA

35

0.001

60

2.0

V_CC>(V_BATT-1V), excluding I_OUT

Supply Current in Battery-

Backup Mode, I_BATT, NOTE 2

V_CC<(V_BATT-1.2V), V_BATT=2.8V, excluding I_OUT

V_CC>(V_BATT+0.2V), excluding I_OUT

V_BATTStandby Current, I_BATT

NOTE 3

,

-0.1

0.02

Battery Switchover Threshold

Battery Switchover Hysteresis

V_BATT+0.03

V_BATT-0.03

power-up

V

power-down

60

Peak to Peak

mV

Date: 4/18/05

2

ELECTRICAL CHARACTERISTICS

V_CC= +4.75V to +5.5V for the SP691A/800L, V_CC= +4.5V to +5.5V for the SP693A/800M, V_BATT= +2.8V, and T_AMB= T_MINto T_MAXunless otherwise

noted. Typical values apply at T_AMB=+25^OC.

PARAMETERS

MIN.

TYP. MAX. UNITS CONDITIONS

BATT ON Output Low

Voltage

0.1

0.7

0.4

1.5

I_SINK=3.2mA

I_SINK=25mA

V

BATT ON Output Short

Circuit Current

60

15

mA

sink current

1

100

µA

source current

RESET, LOWLINE, AND WATCHDOG TIMER

Reset Threshold Voltage

4.50

4.25

4.60

4.35

4.65

4.40

4.65

4.40

4.75

4.50

4.70

4.45

SP691A

SP693A

SP800L

SP800M

V

Reset Threshold Hysteresis

15

80

mV

µs

center-to-peak

power down

V

_CCto RESET Delay

LOWLINE to RESET Delay

800

ns

Reset Active Timeout Period

for the Internal Oscillator

140

200

280

ms

power-up

Reset Active Timeout Period

for the External Clock,

NOTE 4

clock

2048

cycles

Watchdog Timeout Period for

the Internal Oscillator

1.0

70

1.6

2.25

140

sec

ms

long period

short period

100

Watchdog Timeout Period for

the External Clock, NOTE 4

4096

1024

clock long period

cycles short period

Minimum Watchdog Input

Pulse Width

100

3.5

ns

V

V_IL=0.8V,V_IH=0.75xV_CC

RESET Output Voltage

0.004

0.1

0.3

0.4

I_SINK=50µA, V_CC=1V, V_CCfalling

I_SINK=3.2mA, V_CC=4.25V

I_SOURCE=1.6mA, V_CC=5V

RESET Output Short-Circuit

Current

7

20

mA

V

output source current

I_SINK=3.2mA

RESET Output Voltage Low,

NOTE 5

0.1

0.4

LOWLINE Output Voltage

I_SINK=3.2mA, V_CC=4.25V

V

3.5

I_SOURCE=1µA, V_CC=5V

LOWLINE Output Short

Circuit Current

µA

V

15

100

0.4

output source current

WDO Output Voltage

0.1

I_SINK=3.2mA

I_SOURCE=500µA, V_CC=5V

WDO Output Short-Circuit

Current

3

10

mA

output source current

Date: 4/18/05

3

ELECTRICAL CHARACTERISTICS

V_CC= +4.75V to +5.5V for the SP691A/800L, V_CC= +4.5V to +5.5V for the SP693A/800M, V_BATT= +2.8V, and T_AMB= T_MINto T_MAXunless otherwise

noted. Typical values apply at T_AMB=+25^OC.

PARAMETERS

MIN.

TYP.

MAX. UNITS CONDITIONS

WDI Threshold Voltage,

NOTE 6

0.75xV_CC

V_IH

V

0.8

50

V_IL

WDI Input Current

-50

-10

20

WDI=0V

µA

WDI=V_OUT

POWER-FAIL COMPARATOR

1.237

1.200

1.263

1.300

PFI Input Threshold

1.25

SP691A/693A, V_CC=5V

SP800L/800M, V_CC=5V

V

nA

V

1.225

1.275

+25

0.4

PFI Leakage Current

PFO Output Voltage

+0.01

0.1

I

_SINK=3.2mA

3.5

1

I_SOURCE=1µA, V_CC=5V

PFO Short Circuit Current

PFI-to-PFO Delay

60

15

mA

output sink current

100

µA

output source current

25

60

V_OD=15mV

µs

CHIP-ENABLE GATING

CE_INLeakage Current

+0.005

65

+1

µA

disable mode

enable mode

CE_INto CE_OUTResistance,

NOTE 7

150

Ω

CE_OUTShort-Circuit Current

(RESET Active)

0.1

0.75

6

2.0

10

mA

ns

disable mode, CE_OUT=0V

CE_INto CE_OUTPropagation

Delay, NOTE 8

50Ω source impedance driver, C_LOAD=50pF

CE_OUTOutput Voltage High

(RESET Active)

3.5

2.7

V_CC=5V, I_OUT= 100µA

V

V_CC=0V, V_BATT=2.8V, I_OUT=1µA

RESET to CE_OUTDelay

12

µs

power-down

INTERNAL OSCILLATOR

OSC_INLeakage Current

OSC_INInput Pull-Up Current

OSC_SELInput Pull-Up Current

OSC_INFrequency Range

0.10

10

+5.0

100

µA

OSC_SEL=0V

OSC_SEL=V_OUTor floating, OSC_IN=0V

OSC_SEL=0V

10

µA

200

kHz

OSC_SEL=0V

OSC_INExternal Oscillator

Threshold Voltage

V_OUT-0.3 V_OUT-0.6

3.65

V_IH

V_IL

V

2.0

OSC_INFrequency with

External Capacitor

2

kHz

OSC_SEL=0V, C_OSC=47pF

Date: 4/18/05

4

ELECTRICAL CHARACTERISTICS

V_CC= +4.75V to +5.5V for the SP691A/800L, V_CC= +4.5V to +5.5V for the SP693A/800M, V_BATT= +2.8V, and T_AMB= T_MINto T_MAXunless otherwise

noted. Typical values apply at T_AMB=+25^OC.

NOTE 1: Either V_CCor V_BATTcan go to 0V, if the other is greater than 2.0V.

NOTE 2: The supply current drawn by the SP691A/693A/800L/800M from the battery (excluding I_OUT) typically

goesto5µAwhen(V_BATT-1V)<V_CC<V_BATT. Inmostapplications, thisisabriefperiodasV_CCfallsthroughthisregion.

NOTE 3: "+" = battery-discharging current, "-" = battery-charging current.

NOTE 4: Although presented as typical values, the number of clock cycles for the reset and watchdog timeout

periods are fixed and do not vary with process or temperature.

NOTE 5: RESET is an open-drain output and sinks current only.

NOTE 6: WDI is internally connected to a voltage divider between V_OUTand GND. If unconnected, WDI is driven

to 1.6V (typ), disabling the watchdog function.

NOTE 7: The chip-enable resistance is tested with V_CC= +4.75V for the SP691A/800L and V_CC= +4.5V for the

SP693A/800M. CE_IN= CE_OUT= V_CC/2.

NOTE 8: The chip-enable propagation delay is measured from the 50% point at CE_INto the 50% point at CE_OUT

.

TYPICAL PERFORMANCE CHARACTERISTICS

(T_AMB= 25^oC, unless otherwise noted)

2.5

V_CC= 5V

V_BATT= 2.8V

43

40

37

34

31

28

25

V_CC= 1.6V

V_BATT= 2.8V

2.0

1.5

1.0

0.5

0.0

-0.5

-60

-30

0

30

60

90

120

-60

-30

0

30

60

90 120 150

Temperature (^oC)

Figure 1. V_CCSupply Current vs. Temperature (Normal

Operating Mode)

Figure 2. Battery Supply Current vs. Temperature

(Battery-Backup Mode)

14

75.0

V_CC= 0V

12

V_CC= 4.75V

V_BATT= 2.8V

CE IN = V_CC/2

70.0

65.0

60.0

55.0

50.0

45.0

40.0

10

8

6

4

V_BATT= 2V

V_BATT= 2.8V

V_BATT= 4.5V

2

0

-80 -60 -40 -20

0

20 40 60 80 100 120 140

-60

-30

0

30

60

90 120 150

Temperature (^oC)

Figure 4. V_BATTto V_OUTOn-Resistance vs. Temperature

Figure 3. Chip-Enable On-Resistance vs. Temperature

Date: 4/18/05

5

TYPICAL PERFORMANCE CHARACTERISTICS

1.256

V_CC= 4.5V

V_BATT= 2.8V

0.9

0.7

0.5

0.3

V_CC= 5V

V_BATT= 0V

1.252

1.248

1.244

1.240

1.236

-60

-30

0

30

60

90 120 150

-60

-30

0

30

60

90 120 150

Temperature (^oC)

Figure 6. PFI Threshold vs. Temperature

Figure 5. V_CCto V_OUTOn-Resistance vs. Temperature

4.69

400

V_BATT= 0V

4.68

Sourcing V_CC= 5V

350

Sinking V_CC= 4.25V

300

4.67

4.66

V_CCRising

V_CCFalling

250

200

150

100

50

4.65

4.64

4.63

4.62

4.61

4.60

0

-60

-30

0

30

60

90 120 150

-30

0

30

60

90 120 150

Temperature (^oC)

Figure 7. Reset Threshold vs. Temperature

Figure 8. RESET Output Resistance vs. Temperature

0.240

1.E-04

1.E-05

V_CC= 5V

V_BATT= 2.8V

0.230

V_BATT= 2.8V

1.E-06

1.E-07

1.E-08

1.E-09

1.E-10

1.E-11

1.E-12

1.E-13

1.E-14

0.220

0.210

0.200

0.190

0.180

0

1

2

3

4

5

-60

-30

0

30

60

90 120 150

Temperature (^oC)

V_CC(V)

Figure 9. Reset Delay vs. Temperature

Figure 10. Battery Current vs. Input Supply Voltage

Date: 4/18/05

6

TYPICAL PERFORMANCE CHARACTERISTICS

30

1000

100

10

Long Watchdog Timeout Period

Reset Active Timeout Period

Short Watchdog Timeout Period

V_CC= 5V

V_BATT= 2.8V

25

20

15

10

5

50Ω driver

1

V_CC= 5V

V_BATT= 2.8V

0.1

10

0

100

1000

10000

0

50

100 150 200 250 300 350

Cload (pF)

OSCIN Capacitor (pF)

Figure 11. Watchdog and Reset Timeout Period vs.

Figure 12. Chip-Enable Propagation Delay vs. CE_OUT

Load Capacitance

OSC_INTiming Capacitor (C_OSC

)

1000

100

10

1

V_CC= 4.5V

V_BATT= 0V

V_CC= 4.5V

V_BATT= 0V

10

Slope = 5Ω

Slope = 0.6Ω

1

10

100

1000

1

10

100

1000

I_OUT(mA)

Figure 13. V_CCto V_OUTvs. Output Current (Normal

Operating Mode)

Figure 14. V_BATTto V_OUTvs. Output Current (Battery-

Backup Mode)

+5V

V

CC Reset

Threshold

0V

80µs

HI

RESET

LOW

1.1µs

HI

LOWLINE

LOW

16µs

HI

CEOUT

LOW

Figure 15. V_CCto LOWLINE and CE_OUTDelay

Date: 4/18/05

7

PINOUT

Pin 7 — OSC_IN— External Oscillator Input.

When OSC_SELis unconnected or driven

HIGH, a 10µA pull-up connects from V_OUT

to this input pin, the internal oscillator sets

the reset and watchdog timeout periods, and

this input pin selects between fast and slow

watchdog timeout periods. When OSC_SELis

drivenLOW,theresetandwatchdogtimeout

periods may be set either by a capacitor from

this input pin to ground or by an external

clock at this pin (refer to Figure 21).

TOP VIEW

1

2

3

4

5

6

7

8

16

15

VBATT

VOUT

RESET

Vcc

14 WDO

GND

13

12

CEIN

CEOUT

WDI

Corporation

BATT ON

LOWLINE

11

10

OSCIN

PFO

PFI

9

OSCSEL

DIP/SO

Pin 8 — OSC_SEL— Oscillator Select. When

OSC_SELis unconnected or driven HIGH, the

internal oscillator sets the reset delay and

watchdog timeout period. When OSC_SELis

driven LOW, the external oscillator input

pin, OSC_IN, is enabled (refer to Table 1).

This input pin has a 10µA internal pull-up.

PIN ASSIGNMENTS

Pin 1 — V_BATT— Battery-Backup Input. Con-

nect to the external battery supply or super-

charging capacitor and charging circuit. If a

backup battery is not provided, connect this

pin to ground.

Pin 9 — PFI — Power-Fail Input. This is the

noninverting input to the power-fail

comparator. When PFI is less than 1.25V,

PFO goes low. Connect PFI to GND or

V_OUTwhen not used.

Pin 2 —V_OUT— Output Supply Voltage. V_OUT

connects to V_CCwhen V_CCis greater than

V_BATTand V_CCis above the reset threshold.

When V_CCfalls below V_BATTand V_CCis

below the reset threshold, V_OUTconnects to

V_BATT. Connect a 0.1µF capacitor from V_OUT

to GND.

Pin 10 — PFO — Power-Fail Output. This is

the output of the power-fail comparator.

PFO goes low when PFI is less than 1.25V.

This is an uncommitted comparator, and

has no effect on any other internal circuitry.

Pin 3 — V_CC— +5V Input Supply Voltage.

Pin 4 — GND — Ground reference for all

signals.

Pin 11 — WDI — Watchdog Input. This is a

three-level input pin. If WDI remains either

HIGH or LOW for longer than the watchdog

timeout period, WDO goes LOW and RESET

isassertedfortheresettimeoutperiod. WDO

remains LOW until the next transition at this

input pin. Leaving this input pin unconnected

disables the watchdog function. This input

pin connects to an internal voltage divider

between V_OUTand ground, which sets it to

mid-supply when left unconnected.

Pin 5 — BATT ON — Battery On Output. Goes

high when V_OUTswitches to V_BATT. Goes low

when V_OUTswitches to V_CC. Connect the

base of a PNP through a current-limiting

resistor to BATT ON for V_OUTcurrent

requirements greater than 250mA.

Pin 6 — LOWLINE — Low Line Output. This

output pin goes LOW when V_CCfalls below

the reset threshold voltage. This output pin

returns to its HIGH output as soon as V_CC

rises above the reset threshold voltage.

Date: 4/18/05

8

Pin15—RESET—ActiveLOWResetOutput.

This output pin goes LOW whenever V_CC

falls below the reset threshold. This output

pinwillremainlowtypicallyfor200msafter

V_CCcrosses the reset threshold voltage on

power-up.

Pin 12 — CE_OUT— Chip-Enable Output. This

output pin goes LOW only when CE_INis

LOW and V_CCis above the reset threshold

voltage. If CE_INis LOW when RESET is

asserted, this output pin will stay low for

16µs or until CE_INgoes HIGH, whichever

occurs first.

Pin 16 — RESET — Active HIGH Reset

Output. This output pin is open drain and

the inverse of RESET.

Pin13—CE_IN—Chip-EnableInput. Thisisthe

input pin to the chip-enable gating circuit.

If this input pin is not used, connect it to

ground or V_OUT

.

Pin 14 — WDO — Watchdog Output. If WDI

remains HIGH or LOW longer than the

watchdog timeout period, this output pin

goes LOW and RESET is asserted for the

reset timeout period. This output pin returns

HIGH on the next transition at WDI.

This output pin remains HIGH if WDI is

unconnected.

9

PFI

10

PFO

1.25V

Watchdog

Transition

Detector

11

14

WDI

WDO

15

Watchdog

Timer

RESET

Reset

16

Generator

8

7

RESET

Reset /

Watchdog

Timebase

OSCSEL

OSCIN

CEOUT

Control

6

LOWLINE

4.65V or

4.40V*

3

V

CC

2

5

V

OUT

BATT ON

GND

4

1

V

BATT

13

CEIN

* 4.65V for the SP691A/800L

4.40V for the SP693A/800M

12

CEOUT

Figure 16. Internal Block Diagram of the SP691A/693A/800L/800M

Date: 4/18/05

9

Unregulated DC

R

1

2

PFI

Regulated +5V

R

VCC

V

CC

WDO

alarm

RESET

PFO

RESET

µP

NMI

system

status

indicator

LOWLINE

WDI

I/O LINE

A0-A15

Backup VBATT

Supply

Address

Decode

BUS

BATT ON

CEIN

CMOS

RAM

to

1

VCC

VOUT

RAM

n

CEOUT

GND

0.1µF

Figure 17. Typical Application Circuit of the SP691A/693A/800L/800M

THEORY OF OPERATION

FEATURES

The SP691A/693A/800L/800M series is a

complete µP supervisor IC and provides the

following main functions:

The SP691A/693A/800L/800M devices are

microprocessor (µP) supervisory circuits that

monitor the power supplied to digital circuits

such as microprocessors, microcontrollers, or

memory. The SP691A/693A/800L/800M series

is an ideal solution for portable, battery-

powered equipment that require power supply

monitoring. The SP691A/693A/800L/800M

watchdog functions will continuously oversee

the operational status of a system. Implementing

the SP691A/693A/800L/800M series will

reduce the number of components and overall

complexity in a design that requires power

supply monitoring circuitry. The operational

features and benefits of this series are described

in more detail below.

1) µP reset ■ Reset output is asserted during

power fluxiations such as power-up,

power-down, and brown out conditions, and

is guaranteed to be in the correct state for

VCC down to 1V, even with no battery in

the circuit.

2) µP reset ■ Reset output is pulsed if the

optional watchdog timer has not been

toggled within a specified time.

3) Power Fail Comparator ■ Provides for

power-fail warning and low-battery

detection, or monitors another power

supply.

Date: 4/18/05

10

4) Watchdog function ■ Monitors µP activity

where the watchdog output goes to a logic

LOW state if the watchdog input is not

toggled for greater than the timeout period.

15

TO µP RESET

RESET

5) Internal switch ■ Switches over from V

if the V_CCfalls below the res^Ce^Ct

10kΩ

to V

thres^Bh^Ao^Tl^Td.

Corporation

RESET and RESET Outputs

The SP691A/693A/800L/800M devices'

RESET and RESET outputs ensure that the µP

powers up in a known state, and prevents

code-execution errors during power-down or

brownout conditions.

Figure 18. External Pull-down Resistor Ensures

RESET is Valid with V_CCDown to Ground.

10kΩ and the output saturation voltage is below

0.4V while sinking 40µA. When using a 10kΩ

external pull-down resistor, the high state for

the RESET output with Vcc = 4.75V is 4.5V

typical. For battery voltages less than or equal

to 2V connected to VBATT, RESET and RESET

remains valid for VCC from 0V to 5.5V.

The RESET output is active low, and typically

sinks 3.2mA at 0.1V saturation voltage in its

active state. When deasserted, RESET sources

1.6mA at typically VOUT – 0.5V. RESET output

is open drain, active high, and typically sinks

3.2mA with a saturation voltage of 0.1V. When

no backup battery is used, RESET output is

guaranteed to be valid down to VCC = 1V, and

an external 10kΩ pull-down resistor on RESET

ensures that RESET will be valid with VCC

down to GND as shown on Figure 18. As VCC

goes below 1V, the gate drive to the RESET

output switch reduces accordingly, increasing

the R (ON) and the saturation voltage. The

10kΩ^Dp^Sull-down resistor ensures the parallel

combination of switch plus resistor is around

RESET and RESET are asserted whenV_CCfalls

below the reset threshold and remain asserted

for the Reset Timeout Period (200ms nominal)

after V_CCrises above the reset threshold voltage

on power-up. Refer to Figure 19. The devices'

battery-switchover comparator does not affect

reset assertion. However, both reset outputs are

asserted in battery-backup mode sinceV_CCmust

be below the reset threshold to enter this mode.

Vcc

RESET

THRESHOLD

CE IN

CE OUT

12µ

100µs

RESET

Figure 19. Reset and Chip-Enable Timing

Date: 4/18/05

11

WDI

WDO

t

2

t

3

RESET

t1

t

1

t1

t2

t3

= RESET Timeout Period

= Normal Watchdog Timeout Period

= Watchdog Timeout Period Immediately After RESET

Figure 20. Watchdog Timeout Period and Reset Active Time

Watchdog Function

OSCIN

No Connect

X

7

8

The watchdog monitors µP activity via the

Watchdog Input (WDI). If the µP becomes

inactive, RESET and RESET are asserted.

To use the watchdog function, connect WDI to

a bus line or µP I/O line. If WDI remains high

or low for longer than the watchdog timeout pe-

riod (1.6s nominal). WDO, RESET, and RESET

are asserted, indicating a software fault or idle

conditions. Refer to RESET and RESET

Outputs and Watchdog Output sections.

OSCSEL

1.6sec Normal Watchdog Timeout

Internal Oscillator

OSCIN

7

OSCSEL

8

No Connect

X

Watchdog Input

A change of logic state (minimum 100ns

duration) at WDI during the watchdog period

will reset the watchdog timer. The watchdog

default timout is 1.6sec.

100ms Normal Watchdog Timeout

Internal Oscillator

CIN

To disable the watchdog function, leave WDI

floating. An internal resistor network (100kΩ

equivalent impedance at WDI) biases WDI to

approximately 1.6V. Internal comparators

detect this level and disable the watchdog timer.

When Vcc is below the reset threshold, the

watchdog function is disabled and WDI is

disconnected from its internal resistor network,

thus becoming high impedance.

OSCIN

7

OSCSEL

8

600 x CIN

47pF

Normal Watchdog Timeout =

External Oscillator

[ms]

Watchdog Output

OSCIN

7

WDO remains high if there is activity (transition

or pulse) at WDI during the watchdog-timeout

period. The watchdog function is disabled and

WDO is a logic high when VCC is less than the

reset threshold or when WDI is an open circuit.

In watchdog mode, if no transition occurs at

WDI during the watchdog-timeout period,

OSCSEL

8

Normal Watchdog Timeout = 1024 Clock Periods

External Clock

Figure 21. Selecting Timeout Periods

Date: 4/18/05

12

Watchdog Timeout Period

Normal Immediately After Reset

4096 clocks

OSC_SEL

OSC_IN

Reset Timeout Period

LOW

External Clock Input

External Capacitor

LOW

1024 clocks

(600/47pF x C) ms

100 ms

2048 clocks

(1200/47pF x C) ms

200 ms

(2.4/4 pf x C) sec

7

Floating

1.6 s

Floating

1.6 s

200 ms

Table 1. Reset Pulse Width and Watchdog Timeout Selections

The 10ns maximum CE propagation from CE_IN

RESET and RESET are asserted for the reset

timeout period (200ms nominal). WDO goes

to logic low and remains low until the next

transition at WDI. Refer to Figure 20. If WDI

is held high or low indefinitely, RESET and

RESET will generate 200ms pulses every 1.6s.

WDO has a 2 x TTL output characteristic.

to CE

enables the SP691A/693A/800L/

800M ^Od^Ue^Tvices to be used with most µPs.

Chip-Enable Input

CE_INis in high impedance (disabled mode)

while RESET and/or RESET are asserted.

Selecting an Alternative Watchdog

Timeout Period

During a power-down sequence whereV falls

below the reset threshold, CE assumes^Ca^Chigh

impedance state when the vol^It^Nage at CE_INgoes

high or 12µs after RESET is asserted,

whichever occurs first. Refer to Figure 19.

During a power-up sequence, CE_INremains high

impedance until RESET is deasserted.

The OSC

and OSC_INinputs control the

watchdog ^Sa^Er^Le reset timeout periods. Floating

OSC_SELand OSC_INor tying them both to V_OUT

selects the nominal 1.6s watchdog timeout

period and 200ms reset timout period.

Connecting OSC to ground and floating or

connecting OSC_SE^I_L^NtoV selects a 100ms nor-

mal watchdog timeout p^Oe^Uri^Tod and a 1.6s timeout

period immediately after reset. The reset timeout

period remains 200ms. Refer to Figure 20.

Select alternative timeout periods by connecting

OSC to ground and connecting a capacitor

betw^Se^Ee^Ln OSC_INand ground, or by externally

driving OSC_IN. A synopsis of this control can

be found in Figure 21 and Table 1.

In the high-impedance mode, the leakage

currents into CE_INare <1µA over temperature.

In the low-impedance mode, the impedance of

CE appears as a 65Ω resistor in series with

the^Il^Noad at CE_OUT

.

The propagation delay through the CE

transmission gate depends on both the source

impedance of the drive to CE and the

capacitive loading on CE_OUT^IN(see the

Chip-Enable Propagation Delay vs. CE_OUT

Load Capacitance graph in the Typical

Performance Characteristics section). The

CE propagation delay is defined from the 50%

point on CE_INto the 50% point on CE_OUTusing

a 50Ω driver and 50pF of load capacitance as in

Figure 22. For minimum propagation delay,

minimize the capacitive load at CE_OUTand use

a low output-impedance driver.

Chip-Enable Signal Gating

The SP691A/693A/800L/800M devices

provide internal gating of chip-enable (CE)

signals, to prevent erroneous data from

corrupting the CMOS RAM in the event of a

power failure. During normal operation, the CE

gate is enabled and passes all CE transitions.

When reset is asserted, this path becomes

disabled, preventing erroneous data from

corrupting the CMOS RAM. The SP691A/

693A/800L/800M devices use a series transmission

gate from CE_INto CE_OUT. Refer to Figure 16.

Date: 4/18/05

13

+5V

V

CC

VBATT

CEIN

1

13

12

V

BATT

R

1

2.8V

+2.0V

to

+5.5V

PFI

PFO

CEOUT

LOW BATT

R

2

CLOAD

4

GND

Figure 22. Chip Enable Propagation Delay Test Circuit

Figure 23. Low-Battery Indicator Circuit

Power-Fail Output

Chip-Enable Output

The Power-Fail Output (PFO) goes low when

PFI goes below 1.25V. It sinks 3.2mA with a

saturation voltage of 0.1V. With PFI above

1.25V, PFO is actively pulled to VOUT. PFO

can be used to generate an NMI for the µP, as

shown in Figure 17.

In the enabled mode, the impedance of CE_OUT

is equivalent to 65Ω in series with the source

driving CE . In the disabled mode, the 65Ω

transmissio^In^Ngate is off and CE

is actively

pulled to VOUT. This source turn^Os^Uo^Tff when the

transmission gate is enabled.

Battery-Backup Mode

LOWLINE Output

The SP691A/693A/800L/800M requires two

conditions to switch to battery-backup mode:

1) VCC must be below the reset threshold; 2)

VCC must be below VBATT. Table 2 lists the

status of the inputs and outputs in battery-

backup mode.

LOWLINE is the buffered output pin of the

reset threshold comparator. Refer to Figure 16.

LOWLINE typically sinks 3.2mA at 0.1V. For

normal operation where V_CCis above the reset

threshold, LOWLINE is pulled to V_OUT

.

Power-Fail Comparator

Battery-On Output

The power-fail comparator is an uncommitted

comparator that has no effect on the other

functions of the SP691A/693A/800L/800M

devices. Common uses include low battery

detection, as found in Figure 23, and early

power-fail detection when the unregulated power

is easily accessible as shown in Figure 17.

The Battery On Output (BATT ON) indicates

the status of the internalVCC/battery-switchover

comparator, which controls the internalVCC and

VBATT switches. For VCC greater that VBATT

(ignoring the small hysteresis effect), BATT ON

is a logic low. For V_CCless than V , BATT

ON is a logic high. Use BATT ON^Bt^Ao^TTindicate

battery-switchover status or to supply base drive

to an external pass transistor for higher-current

applications. Refer to Figure 17.

Power-Fail Input

The Power-Fail Input (PFI) has a guaranteed

input leakage of +25nA max over temperature.

The typical comparator delay is 25µs from VIL

to VOL (power failing), and 60µs from VIH to

VOH (power being restored). Connect this

input to ground if PFI is not used.

Date: 4/18/05

14

NAME

V_BATT

V_OUT

STATUS

PIN NUMBER

Supply current is 1µA maximum when V_CC<(V_BATT-1.2V).

V_OUTconnected to V_BATTthrough an internal PMOS switch.

Battery switchover comparator monitors V_CCfor active switchover. V_CCis

1

2

V_CC

3

disconnected from V_OUT

.

GND

0V reference for all signals.

4

5

BATT ON Logic HIGH. The open-circuit output voltage is equal to V_OUT

LOWLINE Logic LOW.

.

6

OSC_IN

OSC_SEL

PFI

OSC_INis ignored and is at high-Z.

OSC_SELis ignored and is at high-Z.

The power-fail comparator is disabled.

7

8

9

PFO

The power-fail comparator is disabled. PFO is forced to logic LOW.

WDI is ignored and is at high-Z.

10

11

12

13

14

15

16

WDI

CE_OUT

CE_IN

Logic HIGH. The open-circuit output voltage is equal to V_OUT

.

High-Z.

WDO

RESET

Logic HIGH. The open-circuit output voltage is equal to V_OUT

.

Logic LOW.

High-Z.

Table 2. Input and Output Status in Battery-Backup Mode; to enter the Battery-Backup Mode, V_CCmust be less than the

reset threshold and less than V_BATT

.

Input Supply Voltage

The Input Supply Voltage (VCC) should be a

regulated +5V source. VCC connects to VOUT

via a parallel diode and a large PMOS switch.

The switch carries the entire current load for

currents less than 250mA. The parallel diode

carries any current in excess of 250mA. Both

the switch and the diode have impedances

less than 1Ω each. Refer to Figure 24. The

maximum continuous current is 250mA, but

power-on transients may reach a maximum of 1A.

V

BATT

V

CC

D2

D1

SW2

SW1

0.1µF

VOUT

Backup-Battery Input

The Backup-Battery Input (VBATT) is similar

to VCC, except the PMOS switch and parallel

diode are much smaller. Refer to Figure 24.

Accordingly, the on-resistances of the diode and

the switch are each approximately 10Ω.

Figure 24. V_CCand V_BATTto V_OUTSwitch

Date: 4/18/05

15

2) Battery-backup mode where V_CCis typically

within 0.7V below V_BATT. All circuitry is

powered from V_BATTand the supply

current from the battery is typically less

than 5µA.

+5V

3

Vcc

1N4148

2

1

V

BATT

V

OUT

3) Battery-backup mode where V_CCis less than

V_BATTby at least 0.7V. V_BATTsupply

current is less than 1µA max.

0.47F

Corporation

Using High Capacity Capacitor with the

SP691A/693A/800L/800M Series

VBATT has the same operating voltage range as

VCC, and the battery-switchover threshold

voltages are typically +30mV centered atVBATT,

allowing use of a capacitor and a simple

charging circuit as a backup source. Refer to

Figure 25.

GND

4

Figure 25. High Capacity Capacitor on V_BATT

Continuous current should be limited to 25mA

and peak currents (only during power-up)

limited to 250mA. The reverse leakage of this

input is less than 1µA over temperature and

supply voltage.

If VCC is above the reset threshold and VBATT

is 0.5V above VCC, current flows to VOUT and

VCC from VBATT until the voltage at VBATT is

less than 0.5V above VCC.

Output Supply Voltage

Leakage current through the capacitor charging

diode and SP691A/693A/800L/800M internal

power diode eventually discharges the capacitor

toVCC. Also, ifVCC andVBATT start from 0.5V

above the reset threshold and power is lost at

VCC, the capacitor onVBATT discharges through

VCC untilVBATT reaches the reset threshold; the

SP691A/693A/800L/800M devices then switch

to battery-backup mode.

The Output Supply Voltage (VOUT) supplies all

the current to the external system and internal

circuitry. All open-circuit outputs will assume

theVOUT voltage in their high states rather than

the VCC voltage. At the maximum source

current of 250mA, VOUT will typically be

150mV belowVCC. VOUT should be decoupled

with 0.1µF capacitor.

TYPICAL APPLICATIONS

Using Separate Power Supplies forV_BATT

and V

If usin^Cg^Cseparate power supplies for VCC and

VBATT, VBATT must be less than 0.3V above

VCC when VCC is above the reset threshold.

As described in the previous section, if VBATT

exceeds this limit and power is lost at VCC,

current flows continuously from VBATT to

VCC via the VBATT-to-VOUT diode and the

VOUT-to-VCC switch until the circuit is broken.

Refer to Figure 24.

The SP691A/693A/800L/800M devices are not

short-circuit protected. Shorting VOUT to

ground, other than power-up transients such as

charging a decoupling capacitor, may destroy

the device. All open-circuit outputs swing

between VOUT and GND rather than VCC and

GND. If long leads connect to the chip inputs,

ensure that these lines are free from ringing and

other conditions that would forward bias the

chip's protection diodes.

Alternative Chip-Enable Gating

There are three distinct modes of operation:

Using memory devices with CE and CE inputs

allows the CE loop of the SP691A/693A/800L/

800M series to be bypassed. To do this,

connect CE_INto ground, pull up CE_OUTtoVOUT,

1) Normal operating mode with all circuitry

powered from V_CC. Typical supply current

from V_CCis 35µA, while only leakage

currents flow from the battery.

Date: 4/18/05

16

+5V

V

IN

Minimum value of R

P

is 1kΩ.

*

CC

R

1

Maximum value of R

P

is dependent

on the connected number of RAMs, n.

PFI

V

OUT

CEIN

2

13

4

R

2

R

3

*C

1

RP*

PFO

CEOUT

GND

CE

12

*optional

connect to µP

1.25

RAM

1

GND

CE

V

TRIP

=

RAM

2

R

2

R

1

+ R

2

Active-HIGH

1.25

V

=

L

- 1.25

5.0 - 1.25

CE Logic Lines

+

=

CE

R

3

R

1

for Memory Devices

RAM

3

R2

1.25

V

H

R2

|| R

3

PFO

R

1

+ R

2

|| R

3

CE

RAM

n

+5V

0V

V

IN

0V

V

L

V

TRIP

V

H

Figure 26. Alternate Chip Enable Gating

Figure 27. Adding Hysteresis to the Power-Fail

Comparator

and connect CE_OUTto the CE input of each

memory device as shown in Figure 26. The CE

input of each part then connects directly to the

chip-select logic, which does not have to gated

by the SP691A/693A/800L/800M devices.

be larger than 10kΩ to prevent it from loading

down the PFO pin. Capacitor C1 adds additional

noise rejection.

Monitoring a Negative Voltage

The power-fail comparator can be used to monitor

a negative supply voltage using the circuit shown

in Figure 28. When the negative supply is valid,

PFO is low. When the negative supply voltage

drops, PFO goes high. This circuit's accuracy is

affected by the PFI threshold tolerance, theVCC

voltage, and resistors R1 and R2.

Adding Hysteresis to the Power-Fail

Comparator

Hysteresis adds noise margin to the power-fail

comparator and prevents repeated triggering of

PFO when V_INis near the power-fail comparator

trip point. Figure 27 shows how to add hysteresis

to the power-fail comparator. Select the ratio of

R1 and R2 such that PFI sees 1.25V when V_IN

falls to the desired trip point (V ). Resistor

R3 adds hysteresis. It will typical^Tly^RIPbe an order

of magnitude greater than R1 or R2. The

current through R1 and R2 should be at least

1µA to ensure that the 25nA (max) PFI input

current does not shift the trip point. R3 should

Backup-Battery Replacement

The backup battery may be disconnected while

VCC is above the reset threshold. No precautions

are necessary to avoid spurious reset pulses.

Date: 4/18/05

17

+5V

V

160

120

80

40

0

0.1µF Capacitor

V_OUTto GND

CC

R

1

PFI

Above Line

Reset Generated

R2

PFO

V-

GND

1

10

1000

10000

Reset Comparator Overdrive

(Reset Threshold Voltage - V_CC), (mV)

1.25 - VTRIP

5.0 - 1.25

=

Figure 29. Maximum Transient Duration Without

Causing a Reset Pulse vs. Reset Comparator Overdrive

R2

R1

PFO

+5V

As the amplitude of the transient increases

(i.e., goes farther below the reset threshold), the

maximum allowable pulse width decreases.

Typically, a VCC transient that goes 100mV

below the reset threshold and lasts for 40µs or

less will not cause a reset pulse to be issued.

A 100nF bypass capacitor mounted close to the

VCC pin provides additional transient immunity.

0V

V-

*VTRIP

*VTRIP is a negative voltage

Figure 28. Monitoring a Negative Voltage

Connecting aTiming Capacitor to OSC_IN

When OSC is connected to ground, OSC_IN

disconnects^Sf^Er^Lom its internal 10µA pull-up and

is internally connected to a +100nA current

source. When a capacitor is connected from

OSC_INto ground (to select an alternative

watchdog timeout period), the current source

charges and discharges the timing capacitor to

create the oscillator that controls the reset and

watchdog timeout period. To prevent timing

errors, minimize external current leakage

sources at this pin, and locate the capacitor as

close to OSC_INas possible. The sum of any PC

board leakage plus the OSC capacitor leakage

must be small compared to +100nA.

Negative-Going V_CCTransients

While asserting resets to the µP during power-up,

power-down, and brownout conditions, these

supervisors are relatively immune to short-

duration negative-going VCC transients. It is

usually undesirable to reset the µP when VCC

experiences only small glitches.

Refer to Figure 29 for a graph of the maximum

transient duration vs. the reset-comparator over-

drive for which reset pulses are not generated.

The graph was produced using negative-going

pulses, starting at 5V and ending below the

reset threshold by the magnitude indicated

(reset comparator overdrive). The graph shows

the maximum pulse width a negative-goingVCC

transient may typically have without causing a

reset pulse to be issued.

Date: 4/18/05

18

Watchdog Software Considerations

A way to help the watchdog timer keep a closer

watch on software execution involves setting

and resetting the watchdog input at different

points in the program, rather than "pulsing" the

watchdog input high-low-high or low-high-low.

This technique avoids a "stuck" loop where the

watchdog timer continues to be reset within the

loop, keeping the watchdog from timing out.

START

SET

WDI

LOW

SUBROUTINE

OR PROGRAM LOOP

SET WDI

HIGH

Figure 30 shows an example flow diagram

where the I/O driving the watchdog input is set

high at the beginning of the program, set low at

the beginning of every subrouting or loop, then

set high again when the program returns to the

beginning. If the program should "hang" in any

subroutine, the I/O is continually set low and

the watchdog timer is allowed to time out,

causing a reset or interrupt to be issued.

RETURN

END

Figure 30. Watchdog Flow Diagram

Maximum V_CCFall Time

The VCC fall time is limited by the propagation

delay of the battery switchover comparator and

should not exceed 0.03V/µs. A standard rule of

thumb for filter capacitance on most regulators

is on the order of 100µF per amp of current.

When the power supply is shut off or the main

battery is disconnected, the associated initial

VCC fall rate is just the inverse of 1A/100µF =

0.01V/µs. TheVCC fall rate decreases with time

as VCC falls exponentially, which more than

satisfies the maximum fall-time requirement.

Date: 4/18/05

19

PACKAGE: 16 PIN NSOIC

D

e

Ø

E/2

E1

E

E1/2

L2

Ø

Seating Plane

Ø1

L

1

L1

Gauge Plane

b

INDEX AREA

(D/2 X E1/2)

VIEW C

TOP VIEW

A1

A

Seating Plane

A2

SIDE VIEW

16 Pin NSOIC JEDEC MO-012 (AC) Variation

MIN

1.35

0.1

1.25

0.31

0.17

NOM

-

MAX

1.75

0.25

1.65

0.51

0.25

SYMBOL

A

A1

A2

b

B

c

D

E

E1

e

L

9.90 BSC

6.00 BSC

3.90 BSC

1.27 BSC

-

SEE VIEW C

0.4

1.27

L1

L2

ø

1.04 REF

0.25 BSC

-

0º

5º

8º

15º

b

ø1

-

Note: Dimensions in (mm)

c

BASE METAL

SECTION B-B

WITH PLATING

Date: 4/18/05

20

PACKAGE: 16 PIN WSOIC

D

Ø1

E/2

E1

E

Gauge Plane

L2

E1/2

Ø

Seating Plane

Ø1

L

L1

1

3

2

b

INDEX AREA

(D/2 X E1/2)

VIEW C

e

TOP VIEW

B

16 Pin SOIC JEDEC MS-013 (AA) Variation

SEE VIEW C

B

MIN

2.35

0.1

2.05

0.31

0.2

NOM

-

MAX

2.65

0.3

2.55

0.51

0.33

SYMBOL

A

A1

A2

b

-

c

-

D

E

E1

e

L

10.30 BSC

10.30 DSC

7.50 BSC

1.27 BSC

-

A2

A

Seating Plane

SIDE VIEW

A1

0.4

1.27

L1

L2

ø

1.04 REF

0.25 BSC

-

0º

5º

8º

15º

ø1

-

b

WITH PLATING

Note: Dimensions in (mm)

c

BASE METAL

SECTION B-B

Date: 4/18/05

21

PACKAGE: 16 PIN PDIP

A1

D

A

N

1

INDEX

AREA

A2

D1

E

E1

L

b2

b

e

b3

2

3

N/2

E

c

eA

eB

16 PIN PDIP JEDEC MS-001 (BB) Variation

SYMBOL

MIN

-

NOM

-

MAX

0.21

-

0.195

0.022

0.07

0.045

0.014

0.755

-

A

A1

A2

b

b2

b3

c

D

D1

E

E1

e

eA

eB

L

0.15

0.115

0.014

0.045

0.3

0.008

0.735

0.005

0.3

0.13

0.018

0.06

0.039

0.01

0.75

-

0.31

0.25

.100 BSC

.300 BSC

-

b

0.325

0.28

0.24

C

-

0.43

0.15

0.115

0.13

Note: Dimensions in (mm)

Date: 4/18/05

22

ORDERING INFORMATION

Package Type

Part Number

Temperature Range

SP691ACP ............................................... 0^OC to +70^OC............................................ 16-Pin PDIP

SP691ACN ............................................... 0^OC to +70^OC......................................... 16-Pin NSOIC

SP691ACN/TR ......................................... 0^OC to +70^OC......................................... 16-Pin NSOIC

SP691ACT ............................................... 0^OC to +70^OC........................................ 16-Pin WSOIC

SP691ACT/TR ......................................... 0^OC to +70^OC........................................ 16-Pin WSOIC

SP691AEP ............................................. -40^OC to +85^OC .......................................... 16-Pin PDIP

SP691AEN ............................................. -40^OC to +85^OC ....................................... 16-Pin NSOIC

SP691AEN/TR ....................................... -40^OC to +85^OC ....................................... 16-Pin NSOIC

SP691AET ............................................. -40^OC to +85^OC ...................................... 16-Pin WSOIC

SP691AET/TR........................................ -40^OC to +85^OC ...................................... 16-Pin WSOIC

SP693ACP ............................................... 0^OC to +70^OC............................................ 16-Pin PDIP

SP693ACN ............................................... 0^OC to +70^OC......................................... 16-Pin NSOIC

SP693ACN/TR ......................................... 0^OC to +70^OC......................................... 16-Pin NSOIC

SP693ACT ............................................... 0^OC to +70^OC........................................ 16-Pin WSOIC

SP693ACT/TR ......................................... 0^OC to +70^OC........................................ 16-Pin WSOIC

SP693AEP ............................................. -40^OC to +85^OC .......................................... 16-Pin PDIP

SP693AEN ............................................. -40^OC to +85^OC ....................................... 16-Pin NSOIC

SP693AEN/TR ....................................... -40^OC to +85^OC ....................................... 16-Pin NSOIC

SP693AET ............................................. -40^OC to +85^OC ...................................... 16-Pin WSOIC

SP693AET/TR........................................ -40^OC to +85^OC ...................................... 16-Pin WSOIC

Available in lead free packaging. To order add “-L” suffix to part number.

Example: SP691AEN/TR = standard; SP691AEN-L/TR = lead free

/TR = Tape and Reel

Pack quantity is 2500 for NSOIC and WSOIC.

CLICK HERE TO ORDER SAMPLES

Corporation

ANALOG EXCELLENCE

Sipex Corporation

Headquarters and

Sales Office

233 South Hillview Drive

Milpitas, CA 95035

TEL: (408) 934-7500

FAX: (408) 935-7600

Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the

application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.

Date: 4/18/05

23

ORDERING INFORMATION

Package Type

Part Number

Temperature Range

SP800LCP ............................................... 0^OC to +70^OC............................................ 16-Pin PDIP

SP800LCN ............................................... 0^OC to +70^OC......................................... 16-Pin NSOIC

SP800LCN/TR ......................................... 0^OC to +70^OC......................................... 16-Pin NSOIC

SP800LCT................................................ 0^OC to +70^OC........................................ 16-Pin WSOIC

SP800LCT/TR.......................................... 0^OC to +70^OC........................................ 16-Pin WSOIC

SP800LEP ............................................. -40^OC to +85^OC .......................................... 16-Pin PDIP

SP800LEN ............................................. -40^OC to +85^OC ....................................... 16-Pin NSOIC

SP800LEN/TR ....................................... -40^OC to +85^OC ....................................... 16-Pin NSOIC

SP800LET.............................................. -40^OC to +85^OC ...................................... 16-Pin WSOIC

SP800LET/TR ........................................ -40^OC to +85^OC ...................................... 16-Pin WSOIC

SP800MCP .............................................. 0^OC to +70^OC............................................ 16-Pin PDIP

SP800MCN .............................................. 0^OC to +70^OC......................................... 16-Pin NSOIC

SP800MCN/TR ........................................ 0^OC to +70^OC......................................... 16-Pin NSOIC

SP800MCT............................................... 0^OC to +70^OC........................................ 16-Pin WSOIC

SP800MCT/TR ......................................... 0^OC to +70^OC........................................ 16-Pin WSOIC

SP800MEP............................................. -40^OC to +85^OC .......................................... 16-Pin PDIP

SP800MEN ............................................ -40^OC to +85^OC ....................................... 16-Pin NSOIC

SP800MEN/TR....................................... -40^OC to +85^OC ....................................... 16-Pin NSOIC

SP800MET ............................................. -40^OC to +85^OC ...................................... 16-Pin WSOIC

SP800MET/TR ....................................... -40^OC to +85^OC ...................................... 16-Pin WSOIC

Available in lead free packaging. To order add “-L” suffix to part number.

Example: SP800MEN/TR = standard; SP800MEN-L/TR = lead free

/TR = Tape and Reel

Pack quantity is 2500 for NSOIC and WSOIC.

Corporation

ANALOG EXCELLENCE

Sipex Corporation

Headquarters and

Sales Office

233 South Hillview Drive

Milpitas, CA 95035

TEL: (408) 934-7500

FAX: (408) 935-7600

Date: 4/18/05

24


型号：	SP800LEN-L/TR
厂家：	SIPEX CORPORATION
描述：	Power Supply Management Circuit, Fixed, 2 Channel, PDSO16, LEAD FREE, MS-012AC, SOIC-16 电池微处理器监控
文件：	总24页 (文件大小：242K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SP800LEN-L/TR [SIPEX]

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SP800LEN/TR

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SP800LEP-L

SP800LET

SP800LET-L

SP800LET/TR

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SP800MCN

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SP800MCN-L

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