SP805REN-L [SIPEX]
Power Supply Management Circuit, Adjustable, 2 Channel, PDSO8, SOIC-8;型号: | SP805REN-L |
厂家: | SIPEX CORPORATION |
描述: | Power Supply Management Circuit, Adjustable, 2 Channel, PDSO8, SOIC-8 光电二极管 |
文件: | 总16页 (文件大小:407K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
®
SP690A/692A/802L/
802M/805L/805M
Low Power Microprocessor Supervisory
with Battery Switch-Over
FEATURES
■ Precision Voltage Monitor:
SP690A/SP802L/SP805L at 4.65V
SP692A/SP802M/SP805M at 4.40V
■ Reset Time Delay - 200ms
1
2
3
4
8
7
6
5
VOUT
VCC
GND
PFI
VBATT
8 PIN NSOIC
RESET (RESET)*
WDI
PFO
■ Watchdog Timer - 1.6 sec timeout
■ Minimum component count
■ 60µA Maximum Operating Supply Current
■ 0.6µA Maximum Battery Backup Current
■ 0.1µA Maximum Battery Standby Current
■ Power Switching
*SP805 only
Now Available in Lead Free Packaging
■ Pin Compatible Upgrades to
MAX690A/692A/802L/802M/805L
250mA Output in VCC Mode (0.6Ω)
25mA Output in Battery Mode (5Ω)
■ Voltage Monitor for Power Fail or
Low Battery Warning
■ Available in 8 pin SO and DIP packages
■ RESET asserted down to VCC = 1V
APPLICATIONS
■ Critical µP Power Monitoring
■ Intellegent Instruments
■ Computers
■ Controllers
DESCRIPTION
The SP690A/692A/802L/802M/805L/805M are a family of microprocessor (µP) supervisory
circuits that integrate a myriad of components involved in discrete solutions to monitor power-
supply and battery-control functions in µP and digital systems. The series will significantly
improve system reliability and operational efficiency when compared to discrete solutions.
The features of the SP690A/692A/802L/802M/805L/805M include a watchdog timer, a µP
reset and backup-battery switchover, and power-failure warning, a complete µP monitoring
andwatchdogsolution. Theseriesisidealforapplicationsinautomotivesystems, computers,
controllers, and intelligent instruments. All designs where it is critical to monitor the power
supply to the µP and it’s related digital components will find the series to be an ideal solution.
RESET
Threshold
RESET
Accuracy
PART NUMBER
RESET Active
PFI Accuracy
SP690A
SP692A
SP802L
SP802M
SP805L
SP805M
4.65 V
4.40 V
4.65 V
4.40 V
4.65 V
4.40 V
125mV
125mV
75mV
LOW
LOW
LOW
LOW
HIGH
HIGH
4%
4%
2%
2%
4%
4%
75mV
125mV
125mV
Date: 1/19/05
SP690A/692A Low Power Microprocessor Supervisory with Battery Switch-Over
© Copyright 2005 Sipex Corporation
1
ABSOLUTE MAXIMUM RATINGS
These are stress ratings only and functional operation
of the device at these ratings or any other above those
indicated in the operation sections of the specifica-
tions below is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods of time
may affect reliability and cause permanent damage to
the device.
VCC........................................................-0.3V to 6.0V
VBATT.....................................................-0.3V to 6.0V
All Other Inputs (NOTE 1)..................-0.3V to (VCC to 0.3V)
Input Current:
VCC.........................................................250mA
VBATT........................................................50mA
GND........................................................20mA
Output Current:
VOUT.....Short-Circuit Protected for up to 10sec
All Other Inputs.................................20mA
Rate of Rise, VCC,VBATT..................100V/µs
Continuous Power Dissipation.......500mW
Storage Temperature.......-65°C to +160°C
ESD Rating.............................................................4KV
ELECTRICAL CHARACTERISTICS
Vcc=4.75v to 5.50V for SP690A/SP802L/SP805L, VCC=4.50V to 5.50V for SP692A/SP802M/SP805M, VBATT=2.80V, TA=TMIN to TMAX, typical specified at
25OC, unless otherwise noted.
PARAMETERS
MIN.
TYP.
MAX. UNITS CONDITIONS
Operating Voltage Range,
0
5.5
Volts
VCC or VBATT, Note 2
µA
µA
Supply Current, ISUPPLY
,
35
60
excluding IOUT
ISUPPLY in Battery Backup Mode,
VCC = 0V, VBATT = 2.8V
0.001
0.6
VBATT Standby Current, NOTE 3
VOUT Output
-0.1
VCC > VBATT + 0.2V
µA
0.02
VCC - 0.1
VCC - 0.03
VCC - 0.15
I
OUT = 50mA
Volts
IOUT = 250mA
VOUT in Battery-Backup Mode
VCC < VBATT - 0.2V
V
BATT -0.15 VBATT - 0.04
VBATT - 0.20
IOUT = 5mA
Volts
IOUT = 25mA
Battery Switch Threshold,
VCC to VBATT
20
Power-up
mV
mV
-20
Power-down
Battery Switchover Hysteresis
Reset Threshold
40
Peak to Peak
4.50
4.25
4.55
4.30
4.65
4.40
4.75
4.50
4.70
4.45
SP690A, SP802L, SP805L
SP692A, SP802M, SP805M
SP802L, TA = +25° C, VCC falling
SP802M, TA = +25° C, VCC falling
Volts
Date: 1/19/05
SP690A/692A Low Power Microprocessor Supervisory with Battery Switch-Over
© Copyright 2005 Sipex Corporation
2
ELECTRICAL CHARACTERISTICS
Vcc=4.75v to 5.50V for SP690A/SP802L/SP805L, VCC=4.50V to 5.50V for SP692A/SP802M/SP805M, VBATT=2.80V, TA=TMIN to TMAX, typical specified at 25OC,
unless otherwise noted.
PARAMETERS
MIN.
TYP.
40
MAX.
UNITS CONDITIONS
Reset Threshold Hysteresis
Reset Pulse Width, tRS
RESET Output Voltage,
NOTE 5
mV
ms
Peak to Peak
140
200
280
VCC - 1.5
ISOURCE = 800µA
0.1
0.4
0.3
Volts
I
I
SINK = 3.2mA
0.004
SINK = 50µA, VCC = 1.0
RESET Output Voltage,
NOTE 6
0.8
ISOURCE = 4µA, VCC = 1.0V,
Volts ISOURCE = 800µA
SINK = 3.2mA
V
CC - 1.5
0.1
0.4
I
Watchdog Timeout, tWD
1.00
50
1.60
2.25
sec
ns
NOTE 7
WDI Pulse Width, tWP
VIL = 0.4V, VIH = (0.8)(VCC)
WDI Input Threshold,
0.8
Logic low
Logic high
Volts
V
CC = 5V, NOTE 4
3.5
WDI Input Current
50
150
WDI =VCC
WDI = 0V
µA
-150
-50
PFI Input Threshold
1.200
1.225
1.250
1.250
1.300
1.275
SP690A/692A, SP805L/M
SP802L/M
Volts
nA
PFI Input Current
-25
0.01
25
PFO Output Voltage
V
CC - 1.5
ISOURCE = 800µA
Volts
0.1
0.4
ISINK = 3.2mA
NOTE 1: The input voltage limits on PFI (pin 4) and WDI (pin 6) may be exceeded if the current into
these pins is limited to less than 10 mA.
NOTE 2: Either VCC or VBATT can go to 0V if the other is greater than 2.0V.
NOTE 3: "-" equals the battery-charging current, "+" equals the battery-discharging current.
NOTE 4: WDI is guaranteed to be in an intermediate, non-logic level state if WDI is floating and VCC
is in the operating voltage range. WDI is internally biased to 35% of VCC with an input impedance of
50KΩ.
NOTE 5: SP690A, SP692A, SP802L, and SP802M only.
NOTE 6: SP805L and SP805M only.
NOTE 7: WDI Minimum Rise/Fall time is 2µs.
Date: 1/19/05
SP690A/692A Low Power Microprocessor Supervisory with Battery Switch-Over
© Copyright 2005 Sipex Corporation
3
BATTERY-SWITCHOVER
CIRCUITRY
VBATT
VOUT
1
2
3
4
8
7
6
5
V
OUT
V
BATT
RESET (RESET)*
VCC
V
CC
RESET
GENERATOR
RESET
(RESET)*
GND
PFI
WDI
PFO
1.25V
*( ) SP805 only
3.5V
WATCHDOG
TIMER
WDI
Figure 10. Pinout
PIN ASSIGNMENTS
0.8V
Pin 1 —VOUT — Output Supply Voltage. VOUT
connects to VCC when VCC is greater than
VBATT and VCC is above the reset thresh-
old. When VCC falls below VBATT and
VCC is below the reset threshold, VOUT
connects to VBATT. Connect a 0.1µF
capacitor from VOUT to GND.
PFI
PFO
1.25V
*( ) SP805 only
Pin 2 — VCC — +5V Supply Input
Figure 11. Internal Block Diagram
Pin3 — GND — Ground reference for all signals
Pin 7 for SP805 only — RESET (Active High)–
Reset Output is the inverse of RESET;
when RESET is asserted, the RESET
Pin 4 — PFI — Power-Fail Input. This is the
noninverting input to the power-fail com-
parator. When PFI is less than 1.25V,
PFO goes low. Connect PFI to GND or
VOUT when not used.
output voltage = VCC or VBATT
,
whichever is higher.
Pin8—VBATT — Backup-BatteryInput. When
VCC fallsbelowtheresetthreshold,VBATT
will be switched to VOUT if VBATT is
20mV greater than VCC. When VCC rises
20mV above VBATT, VOUT will be
Pin 5 — PFO — Power-Fail Output.
Pin 6 — WDI — Watchdog Input. WDI is a
three level input. If WDI remains high or
lowfor1.6sec,theinternalwatchdogtimer
triggers a reset. If WDI is left floating or
connected to a high-impedance tri-state
buffer, the watchdog feature is disabled.
Theinternalwatchdogtimerclearswhen-
ever reset is asserted.
reconnected to VCC
hysteresis prevents repeated switching if
CC falls slowly.
.
The 40mV
V
Pin 7 for SP690A/692A/802 only — RESET
(ActiveLow)–ResetOutput.RESETOut-
put goes low whenever VCC falls below
the reset threshold or whenever WDI
remains high or low longer than 1.6
seconds. RESET remains low for 200ms
after VCC crosses the reset threshold
voltage on power-up or after being trig-
gered by WDI.
Date: 1/19/05
SP690A/692A Low Power Microprocessor Supervisory with Battery Switch-Over
© Copyright 2005 Sipex Corporation
4
TYPICAL PERFORMANCE CHARACTERISTICS
PFI Threshold
vs. Temperature
V
CC Supply Current vs.
Battery Supply Current vs.
Temperature (Backup Mode)
Temperature (Normal Mode)
1.256
1.254
1.252
1.250
1.248
1.246
2.9
2.4
1.9
1.4
0.9
V =5V
51
47
43
39
35
31
27
23
19
CC
V =5V
V =0V
CC
CC
V
BATT=0
VBATT=2.8V
VBATT=2.8V
NO LOAD ON PFO
0.4
-0.1
20 40 60 80 100 120 140
-60 -40 -20
0
-60 -30
0
30 60 90 120 150
-60 -30
0
30 60 90 120 150
Temperature Deg. C
Temperature Deg. C
Temperature Deg. C
V
CC to VOUT On
V
BATT to VOUT ON
Reset Threshold
vs. Temperature
Resistance vs. Temperature
Resistance vs. Temperature
0.9
0.8
0.7
0.6
0.5
0.4
0.3
4.70
15
10
5
V
BATT=0V
V =0V
VBATT=2V
V =5V
4.69
4.68
4.67
4.66
4.65
4.64
4.63
4.62
4.61
4.60
CC
VBCACTT=0V
SP690A
Power Down
VBATT=2.8V
VBATT=4.5V
0
-60 -30
0
30
60
90
120 150
-60 -30
0
30 60 90 120 150
-60 -30
0
30 60 90 120 150
Temperature Deg. C
Temperature Deg. C
Temperature Deg. C
Reset Output Resistance
vs. Temperature
Reset Delay
vs. Temperature
Battery Current vs. VCC Voltage
212
600
V =5V,VBATT=2.8V
V =0V to 5V Step,
IE+2
IE+1
IE+0
IE-1
IE-2
IE-3
IE-4
IE-5
IE-6
IE-7
IE-8
CC
CC
210
208
206
204
202
200
Soucing Current
V
BATT=2.8V
500
400
300
200
100
0
VBATT=2.8V
V =0V,VBATT=2.8V
CC
Sink Current
.0000
5.000
-60 -30
0
30 60 90 120 150
-60 -30
0
30 60 90 120 150
VCC (0.5V/div)
Temperature Deg. C
Temperature Deg. C
(25oC, unless otherwise noted)
Date: 1/19/05
SP690A/692A Low Power Microprocessor Supervisory with Battery Switch-Over
© Copyright 2005 Sipex Corporation
5
1000
100
10
1000
100
10
V =4.5V
V
BATT=4.5V
CC
V
BATT=0V
V =0V
SloCpCe=5Ω
Slope=0.6Ω
1
1
1
10
100
1
10
100
1000
IOUT (mA)
IOUT (mA)
Figure 1. VCC to VOUT Vs. Output Current
Figure 2. VBATT to VOUT Vs. Output Current
VCC
V
BATT = 0V
T
A
= +25 C
VCC
V
TA
BATT = 0V
2V
div
= 25oC
VCC
0V
RESET
2KΩ
RESET
RESET
0V
330pF
GND
1sec/div
Figure 3A. SP690A RESET Output Voltage vs.
Supply Voltage
Figure 3B. Circuit for the SP690A/802L RESET
Output Voltage vs. Supply Voltage
V
CC
VCC
VCC
2V
div
0V
5V
RESET
RESET
V
BATT
0V
330pF
10KΩ
GND
1sec/div
Figure 4A. SP805L RESET Output Voltage vs.
Supply Voltage
Figure 4B. Circuit for the SP805 RESET Output
Voltage vs. Supply Voltage
Date: 1/19/05
SP690A/692A Low Power Microprocessor Supervisory with Battery Switch-Over
© Copyright 2005 Sipex Corporation
6
VCC
VCC
+5V
+4V
T
A
= +25 C
RESET
V
CC
RESET
+5V
10KΩ
0V
30pF
GND
2µs/div
Figure 5B. Circuit for the SP690A/802L RESET
Response Time
Figure 5A. SP690A RESET Response Time
V
CC
+5V
V
CC
V
CC
+4V
+4V
0V
RESET
RESET
V
BATT
330pF
10KΩ
GND
2µs/div
Figure 6B. Circuit for the SP805 RESET
Response Time
Figure 6A. SP805L RESET Response Time
+5V
V
CC = 5V
VBATT = 0V
+1.3V
+1.2V
PFI
V
CC = +5V
T
A
= +25 C
1KΩ
PFO
5V
PFI
PFO
0V
30pF
+1.25V
500ns/div
Figure 7B. Circuit for the Power-Fail Comparator
Response Time (FALL)
Figure 7A. Power-Fail Comparator Response Time (FALL)
Date: 1/19/05
SP690A/692A Low Power Microprocessor Supervisory with Battery Switch-Over
© Copyright 2005 Sipex Corporation
7
V
CC = 5V
VBATT = 0V
PFI
+5V
+1.3V
+1.2V
V
CC = +5V
T
A
= +25 C
PFI
PFO
3V
0V
PFO
1KΩ
30pF
+1.25V
2µs/div
Figure 8A. Power-Fail Comparator Response Time (RISE)
Figure 8B. Circuit for the Power-Fail Comparator
Response Time (RISE)
+5V
V
CC
0V
+5V
tRS
RESET*
0V
+5V
RESET**
3.0V
0V
+5V
V
OUT
3.0V
0V
+5V
0V
PFO
*SP690A/692A/802L/802M
**SP805L/805M
V
BATT = PFI = 3.0V
Figure 9. Timing Diagram
Date: 1/19/05
SP690A/692A Low Power Microprocessor Supervisory with Battery Switch-Over
© Copyright 2005 Sipex Corporation
8
FEATURES
THEORY OF OPERATION
The SP690A/692A/802L/802M/805L/805M
provide four key functions:
1. AbatterybackupswitchingforCMOSRAM,
CMOS microprocessors, or other logic.
2. Aresetoutputduringpower-up, power-down
and brownout conditions.
3. A reset pulse if the optional watchdog timer
has not been toggled within a specified time.
4. A 1.25V threshold detector for power-fail
warning, low battery detection, or to monitor a
power supply other than +5V.
The SP690A/692A/802L/802M/805L/805M
microprocessor (µP) supervisory circuits
monitor the power supplied to digital circuits
such as microprocessors, microcontrollers, or
memory. The series is an ideal solution for
portable, battery-powered equipment that
requires power supply monitoring. Implementing
this series will reduce the number of
components and overall complexity. The
watchdog functions of this product family will
continuously oversee the operational status of a
system. Theoperationalfeaturesandbenefitsof
theSP690A/692A/802L/802M/805L/805Mare
described in more detail below.
The parts differ in their reset-voltage threshold
levels and reset outputs. The SP690A/802L/
805L generate a reset when the supply voltage
drops below 4.65V. The SP692A/802M/805M
generate a reset below 4.40V.
Reset Output
The microprocessor's (µP's) reset input starts
the µP in a known state. When the µP is in an
unknown state, it should be held in reset. The
SP690A/SP692A/SP802 assert reset during
power-up and prevent code execution errors
during power-down or brownout conditions.
The SP690A/692A/802L/802M/805L/805M
are ideally suited for applications in automotive
systems, intelligent instruments, and battery-
poweredcomputersandcontrollers. Alldesigns
into an environment where it is critical to
monitor the power supply to the µP and it’s
related digital components will find the
SSP690A/692A/802L/802M/805L/805M ideal.
On power-up, once VCC reaches 1V, RESET is
guaranteed to be a logic low. As VCC rises,
RESET remains low. When VCC exceeds the
reset threshold, RESET will remain low for
200ms, Figure 9. If a brownout condition
occurs and VCC dips below the reset threshold,
RESET is triggered. Each time RESET is
triggered, it stays low for the reset pulse width
interval. If a brownout condition interrupts a
previously initiated reset pulse, the reset pulse
continues for another 200ms. On power-down,
once VCC goes below the threshold, RESET is
guaranteed to be logic low until VCC drops
below 1V.
Regulated +5V
Unregulated
DC
0.1µF
VCC
VCC
R1
RESET RESET
µP
PFI
NMI
PFO
WDI
I/O LINE
R2
VOUT
V
BATT
GND
RESET is also triggered by a watchdog timeout.
If WDI remains either high or low for a period
that exceeds the watchdog timeout period (1.6
sec), RESET pulses low for 200mS. As long as
RESET is asserted, the watchdog timer remains
clear. When RESET comes high, the watchdog
resumes timing and must be serviced within
1.6sec. If WDI is tied high or low, a RESET
pulse is triggered every 1.8sec (tWD plus tRS).
GND
BUS
3.6V
Lithium
Battery
VCC
CMOS
RAM
GND
Figure 12. Typical Operating Circuit
Date: 1/19/05
SP690A/692A Low Power Microprocessor Supervisory with Battery Switch-Over
© Copyright 2005 Sipex Corporation
9
The SP805L/M active-high RESET output is
the inverse of the SP690A/SP692A/SP802 RE-
SET output, and is valid with VCC down to 1V.
Some µP's, such as Intel's 80C51, require an
active-high reset pulse.
Power-Fail Comparator
The Power-Fail Comparator can be used as an
under-voltage detector to signal the failing of a
power supply (it is completely separate from the
rest of the circuitry and does not need to be
dedicated to this function). The PFI input is
compared to an internal 1.25V reference. If PFI
is less than 1.25V, PFO goes low. The external
voltage divider drives PFI to sense the
unregulated DC input to the +5V regulator. The
voltage-divider ratio can be chosen such that the
voltage at PFI falls below 1.25V just before the
+5V regulator drops out. PFO then triggers an
interrupt which signals the µP to prepare for
power-down.
Watchdog Input
The watchdog circuit monitors the µP's activity.
If the µP does not toggle the watchdog input
(WDI) within 1.6sec, a reset pulse is triggered.
The internal 1.6sec timer is cleared by either a
resetpulseorbyfloatingtheWDIinput. Aslong
as RESET is asserted or the WDI input is
floating, the timer remains cleared and does not
count. As soon as RESET is released and WDI
is driven high or low, the timer starts counting.
It can detect pulses as short as 50ns.
When VBATT connects to VOUT, the power-fail
comparator is turned off and PFO is forced low
to conserve backup-battery power.
Backup-Battery Switchover
In the event of a brownout or power failure, it
may be necessary to preserve the contents of
VBATT
V
CC
RAM. WithabackupbatteryinstalledatVBATT
,
the RAM is assured to have power if VCC fails.
As long as VCC exceeds the reset threshold,
VOUT connects to VCC through a 0.6Ω PMOS
power switch. Once VCC falls below the reset
threshold, VCC or VBATT, whichever is higher,
switches to VOUT. VBATT connects to VOUT
through a 5Ω switch only when VCC is below the
D2
D1
SW2
SW1
D3
VOUT
reset threshold and VBATT is greater than VCC
.
GND
When VCC exceeds the reset threshold, it is
connected to VOUT, regardless of the voltage
applied to VBATT Figure 13. During this time,
the diode (D1) between VBATT and VOUT will
conduct current from VBATT to VOUT if VBATT is
CONDITION
SW1
Open
SW2
Closed
Closed
Open
VCC > Reset Threshold
more than .6V above VOUT
.
VCC < Reset Threshold and
VCC > VBATT
Open
When VBATT connects to VOUT, backup mode is
activated and the internal circuitry will be pow-
ered from the battery Figure 14. When VCC is
just below VBATT, in the backup mode the
current drawn from VBATT will be typically
30µA. When VCC drops to more than 1V below
VBATT,theinternalswitchovercomparatorshuts
off and the supply current falls to less than 0.6µA.
VCC < Reset Threshold and
VCC < VBATT
Closed
Reset Threshold = 4.65V in SP690A/802L/805L
Reset Threshold = 4.40V in SP692A/802M/805M
Figure 13. BACKUP-BATTERY Switchover Block Diagram
Date: 1/19/05
SP690A/692A Low Power Microprocessor Supervisory with Battery Switch-Over
© Copyright 2005 Sipex Corporation
10
SIGNAL
STATUS
+5V
V
VCC
Disconnected from VOUT
CC
Connected to VBATT through
VOUT
VBATT
PFI
an internal 8Ω PMOS switch
CONNECT TO
STATIC RAM
V
OUT
V
BATT
Connected to VOUT. Current
drawn from the battery is
less than 0.6µA, as long as
CONNECT
TO µP
RESET
0.1F
(RESET)*
V
CC < VBATT - 1V.
GND
*( ) SP805L only
Power-fail comparator is
disabled.
Figure 16. Backup Power Source Using High Capacity
Capacitor with SP690A/802L/805L and a +5V ±5% Supply
PFO
RESET
RESET
WDI
Logic low
Logic low
Logic high (SP805 only)
Watchdog timer is disabled
If VCC is above the reset threshold and VBATT
is 0.5V above VCC, current flows to VOUT and
VCC from VBATT until the voltage at VBATT is
less than 0.5V above VCC.
Figure 14. Input and Output Status in Battery-Backup Mode.
To enter the Battery-Backup mode, VCC must be less than the
Reset threshold and less than VBATT
.
Leakage current through the capacitor charging
diode and the SP690A/SP802L/SP805L internal
power diode eventually discharges the capacitor
to VCC. Also, if VCC and VBATT start from 0.5V
above the reset threshold and power is lost at
VCC, the capacitor onVBATT discharges through
VCC untilVBATT reaches the reset threshold; the
SP690A/SP802L/SP805L then switches to
battery-backup mode.
Using a High Capacity Capacitor
as a Backup Power Source
VBATT has the same operating voltage range as
VCC, and the battery-switchover threshold volt-
ages are typically +20mV centered at VBATT,
allowing use of a capacitor and a simple charging
circuit as a backup source (see Figure 16).
MAXIMUM
PART
+5V
BACKUP-BATTERY
NUMBER
VOLTAGE [V]
V
CC
CONNECT TO
STATIC RAM
V
OUT
SP690A
SP802L
SP805L
V
BATT
4.80
4.55
0.1F
CONNECT
RESET
(RESET)*
TO µP
100KΩ
SP692A
SP802M
SP805M
GND
*( ) SP805M only
Figure 15. Allowable BACKUP-BATTERY Voltages
Figure 17. Backup Power Source Using High Capacity
Capacitor with SP692A/802M/805M and a +5V ±10% Supply
Date: 1/19/05
SP690A/692A Low Power Microprocessor Supervisory with Battery Switch-Over
© Copyright 2005 Sipex Corporation
11
Operation Without a Backup Power
Source
+5V
V
V
IN
CC
If a backup power source is not used, ground
VBATT and connect VOUT to VCC. Since there is
no need to switch over to any backup power
source, VOUT does not need to be switched. A
direct connection to VCC eliminates any voltage
drops across the switch which may push VOUT
R
1
PFI
R
2
R
3
*C
1
PFO
below VCC
.
*optional
connect to µP
1.25
GND
Replacing the Backup Battery
V
TRIP
=
The backup battery can be removed while VCC
remains valid, without danger of triggering
RESET/RESET. AslongasVCC staysabovethe
reset threshold, battery-backup mode cannot be
entered.
R
2
R1
+ R
2
1.25
VL
- 1.25
5.0 - 1.25
+
=
R
3
R1
R2
1.25
VH
=
Adding Hysteresis to the Power-Fail
Comparator
R2
|| R
3
PFO
R1
+ R
2
|| R
3
Hysteresis adds a noise margin to the power-fail
comparator and prevents repeated triggering of
PFO when VIN is close to its trip point. Figure 18
shows how to add hysteresis to the power-fail
comparator. Select the ratio of R1 and R2 such
that PFI sees 1.25V when VIN falls to its trip
point (VTRIP). R3 adds the hysteresis. It will
typicallybeanorderofmagnitudegreater(about
10 times) than R1 or R2. The current through R1
and R2 should be at least 1µA to ensure that the
25nA (max) PFI input current does not shift the
trip point. R3 should be larger than 10KΩ so it
does not load down the PFO pin. Capacitor C1
adds additional noise rejection.
+5V
0V
VIN
0V
VL
VTRIP
VH
Figure 18. Adding Hysteresis to the POWER-FAIL
Comparator
Allowable Backup Power-Source
Batteries
Lithium batteries work very well as backup
batteries due to very low self-discharge rate and
high energy density. Single lithium batteries
with open-circuit voltages of 3.0V to 3.6V are
ideal. Any battery with an open-circuit voltage
less than the minimum reset threshold plus 0.3V
can be connected directly to the VBATT input of
this series with no additional circuitry; see
FIGURE 12. However, batteries with open-
circuit voltages that are greater than this value
cannot be used for backup, as current is sourced
into VOUT through the diode (D1 in Figure 13)
when VCC is close to the reset threshold.
Monitoring a Negative Voltage
The power-fail comparator can be used to monitor
a negative supply rail using the circuit of Figure
19. When the negative rail is valid, PFO is low.
When the negative supply voltage drops, PFO
goes high. This circuit's accuracy is
affected by the PFI threshold tolerance, the VCC
voltage, and the resistors, R1 and R2.
Date: 1/19/05
SP690A/692A Low Power Microprocessor Supervisory with Battery Switch-Over
© Copyright 2005 Sipex Corporation
12
+5V
V
Buffered RESET connects to System Components
CC
R1
+5V
V
+5V
V
PFI
CC
CC
R2
PFO
µP
RESET
RESET
V-
4.7KΩ
GND
1.25 - VTRIP
GND
GND
5.0 - 1.25
=
R2
R1
PFO
Figure 20. Interfacing to Microprocessors with
Bidirectional RESET I/O
+5V
0V
0V
V-
*VTRIP
*VTRIP is a negative voltage
Figure 19. Monitoring a Negative Voltage
Interfacing to Microprocessors with
Bidirectional Reset Pins
Microprocessors with bidirectional reset pins,
such as the Motorola 68HC11 series, can con-
tend with this series' RESET output. If, for
example, the RESET output is driven high and
the µP wants to pull it low, indeterminate logic
levels may result. To correct this, connect a
4.7KΩ resistor between the RESET output and
the µP reset I/O, as in Figure 20. Buffer the
RESET output to other system components.
Date: 1/19/05
SP690A/692A Low Power Microprocessor Supervisory with Battery Switch-Over
© Copyright 2005 Sipex Corporation
13
PACKAGE: 8 PIN PDIP
N
E
INDEX
AREA
E
E1
2
3
N/2
1
c
eA
A1
eB
D
A
e
A2
D1
L
b
b2
b3
b
c
8 PIN PDIP JEDEC MS-001 (BA) Variation
SYMBOL
MIN
-
NOM
-
-
MAX
0.21
-
0.195
0.022
0.07
0.045
0.014
0.4
A
A1
A2
b
b2
b3
c
D
D1
E
E1
e
eA
eB
L
0.15
0.115
0.014
0.045
0.3
0.008
0.355
0.005
0.3
0.13
0.018
0.06
0.039
0.01
0.365
-
0.31
0.25
.100 BSC
.300 BSC
-
-
0.325
0.28
0.24
-
0.43
0.15
0.115
0.13
Note: Dimensions in (mm)
Date: 1/19/05
SP690A/692A Low Power Microprocessor Supervisory with Battery Switch-Over
© Copyright 2005 Sipex Corporation
14
PACKAGE: 8 PIN NSOIC
D
Ø
e
E/2
L2
E1
E1/2
E
Ø
Seating Plane
Ø1
L
L1
Gauge Plane
VIEW C
1
b
INDEX AREA
(D/2 X E1/2)
TOP VIEW
A1
A
Seating Plane
A2
SIDE VIEW
8 Pin NSOIC JEDEC MO-012 (AA) Variation
MIN
1.35
0.1
1.25
0.31
0.17
NOM
-
-
-
-
-
MAX
1.75
0.25
1.65
0.51
0.24
SYMBOL
A
A1
A2
b
B
B
SEE VIEW C
c
D
E
E1
e
L
4.90 BSC
6.00 BSC
3.90 BSC
1.27 BSC
-
0.4
1.27
b
L1
L2
ø
1.04 REF
0.25 BSC
-
0º
5º
8º
15º
ø1
-
c
Note: Dimensions in (mm)
BASE METAL
SECTION B-B
WITH PLATING
Date: 1/19/05
SP690A/692A Low Power Microprocessor Supervisory with Battery Switch-Over
© Copyright 2005 Sipex Corporation
15
ORDERING INFORMATION
Model
Temperature Range
Package Types
SP690ACN........................................................0°C to +70°C.....................................................8-Pin NSOIC
SP690ACN/TR...................................................0°C to +70°C.....................................................8-Pin NSOIC
SP690ACP........................................................0°C to +70°C.........................................................8-Pin PDIP
SP690AEN......................................................-40°C to +85°C.....................................................8-Pin NSOIC
SP690AEN/TR.................................................-40°C to +85°C.....................................................8-Pin NSOIC
SP690AEP.......................................................-40°C to +85°C.......................................................8-Pin PDIP
SP692ACN........................................................0°C to +70°C......................................................8-Pin NSOIC
SP692ACN/TR..................................................0°C to +70°C......................................................8-Pin NSOIC
SP692ACP........................................................0°C to +70°C.........................................................8-Pin PDIP
SP692AEN......................................................-40°C to +85°C.....................................................8-Pin NSOIC
SP692AEN/TR................................................-40°C to +85°C.....................................................8-Pin NSOIC
SP692AEP.......................................................-40°C to +85°C.......................................................8-Pin PDIP
SP802LCN........................................................0°C to +70°C......................................................8-Pin NSOIC
SP802LCN/TR..................................................0°C to +70°C......................................................8-Pin NSOIC
SP802LCP........................................................0°C to +70°C.........................................................8-Pin PDIP
SP802LEN.......................................................-40°C to +85°C....................................................8-Pin NSOIC
SP802LEN/TR.................................................-40°C to +85°C....................................................8-Pin NSOIC
SP802LEP.......................................................-40°C to +85°C.......................................................8-Pin PDIP
SP802MCN.......................................................0°C to +70°C......................................................8-Pin NSOIC
SP802MCN/TR.................................................0°C to +70°C......................................................8-Pin NSOIC
SP802MCP.......................................................0°C to +70°C.........................................................8-Pin PDIP
SP802MEN......................................................-40°C to +85°C....................................................8-Pin NSOIC
SP802MEN/TR................................................-40°C to +85°C....................................................8-Pin NSOIC
SP802MEP......................................................-40°C to +85°C.......................................................8-Pin PDIP
SP805LCN........................................................0°C to +70°C......................................................8-Pin NSOIC
SP805LCN/TR..................................................0°C to +70°C......................................................8-Pin NSOIC
SP805LCP........................................................0°C to +70°C.........................................................8-Pin PDIP
SP805LEN.......................................................-40°C to +85°C....................................................8-Pin NSOIC
SP805LEN/TR.................................................-40°C to +85°C....................................................8-Pin NSOIC
SP805LEP.......................................................-40°C to +85°C.......................................................8-Pin PDIP
SP805MCN.......................................................0°C to +70°C......................................................8-Pin NSOIC
SP805MCN/TR..................................................0°C to +70°C......................................................8-Pin NSOIC
SP805MCP.......................................................0°C to +70°C.........................................................8-Pin PDIP
SP805MEN......................................................-40°C to +85°C....................................................8-Pin NSOIC
SP805MEN/TR................................................-40°C to +85°C....................................................8-Pin NSOIC
SP805MEP......................................................-40°C to +85°C.......................................................8-Pin PDIP
Available in lead free packaging. To order add “-L” suffix to part number.
Example: SP802LCN/TR = standard; SP802LCN-L/TR = lead free
/TR = Tape and Reel
Pack quantity 2,500 for NSOIC.
CLICK HERE TO ORDER SAMPLES
Sipex Corporation
Corporation
Headquarters and
Sales Office
233 South Hillview Drive
Milpitas, CA 95035
TEL: (408) 934-7500
FAX: (408) 935-7600
ANALOG EXCELLENCE
Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the
application or use of any product or circuit described hereing; neither does it convey any license under its patent rights nor the rights of others.
Date: 1/19/05
SP690A/692A Low Power Microprocessor Supervisory with Battery Switch-Over
© Copyright 2005 Sipex Corporation
16
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