SP9604AP [SIPEX]
D/A Converter, 4 Func, Parallel, Word Input Loading, 30us Settling Time, PDIP28, 0.600 INCH, PLASTIC, DIP-28;
| 型号： | SP9604AP |
| 厂家： | 
SIPEX CORPORATION |
| 描述： | D/A Converter, 4 Func, Parallel, Word Input Loading, 30us Settling Time, PDIP28, 0.600 INCH, PLASTIC, DIP-28 转换器 射频 微波 |
| 文件： | 总11页 (文件大小：189K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
SP9604
Quad, 12–Bit, Low Power Voltage
Output D/A Converter
■ Low Cost
■ Four 12–Bit DAC’s on a Single Chip
■ Very Low Power — 30 mW (8mW/DAC)
■ Double-Buffered Inputs
■ + 5V Supply Operation
■ Voltage Outputs, + 4.5V Range
■ Midscale Preset, Zero Volts Out
■ Guaranteed +0.5 LSB Max INL
■ Guaranteed +0.75 LSB Max DNL
■ 250kHz 4-Quadrant Multiplying Bandwidth
■ 28–pin SOIC and Plastic DIP
Packages
■ Either 12 or 8 bit µP bus
DESCRIPTION
The SP9604 is a very low power replacement for the popular SP9345, Quad 12-Bit Digital-to-
Analog Converter. It features ±4.5V output swings when using ±5 volt supplies. The converter
is double-buffered for easy microprocessor interface. Each 12-bit DAC is independently
addressableandallDACsmaybesimultaneouslyupdatedusingasingletransfercommand. The
output settling-time is specified at 30µs. The SP9604 is available in 28–pin SOIC and plastic DIP
packages, specified over commercial temperature range.
Ref In
INPUT
REGISTERS
DAC
REGISTERS
–
+
DATA
VOUT1
VOUT2
VOUT3
LATCH
LATCH
LATCH
LATCH
LATCH
LATCH
DAC
DAC
DAC
INPUTS
8 MSB's
4 LSB's
–
+
–
+
–
+
VOUT4
LATCH
LATCH
DAC
CONTROL LOGIC
A0
A1
CS WR1 B1/B2 WR2 XFER CLR
SP9604DS/03
SP9604 Quad, 12-Bit, Low Power Voltage Output D/A Converter
© Copyright 2000 Sipex Corporation
1
ABSOLUTE MAXIMUM RATINGS
These are stress ratings only and functional operation of the device
at these or any other above those indicated in the operation
sections of the specifications below is not implied. Exposure to
absolute maximum rating conditions for extended periods of time
may affect reliability.
VDD - GND ..................................................................... -0.3V,+6.0V
VSS - GND .................................................................... +0.3V, -6.0V
VDD - VSS ...................................................................................................................... -0.3V, +12.0V
VREF ..................................................................................... VSS, VDD
DIN ....................................................................................... VSS, VDD
Power Dissipation
Plastic DIP .......................................................................... 375mW
(derate 7mW/°C above +70°C)
Small Outline ...................................................................... 375mW
(derate 7mW/˚C above +70˚C)
SPECIFICATIONS
(Typical @ 25˚C, TMIN ≤ TA≤TMAX; VDD = +5V, VSS = -5V, VREF = +3V; CMOS logic level digital inputs; specifications apply to all grades unless otherwise noted.)
PARAMETER
MIN.
TYP.
MAX.
UNITS
CONDITIONS
DIGITAL INPUTS
Logic Levels
V
V
2.4
Volts
Volts
IH
0.8
IL
4 Quad, Bipolar Coding
Offset Binary
REFERENCE INPUT
Voltage Range
Input Resistance
+3
2.2
+4.5
Volts
kΩ
Note 5
D = 1,877; code dependent
1.5
IN
ANALOG OUTPUT
Gain
-K
+0.5
+1.0
+1.0
+0.25
+3.0
+2.0
+4.0
+5.0
+3.0
+4.5
LSB
LSB
LSB
LSB
Volts
mA
V
V
V
= +3V; Note 3
= +3V; Note 3
= +4.5V; Note 3
REF
REF
REF
-J
Initial Offset Bipolar
Voltage Range Bipolar
Output Current
D = 2,048
IN
+5.0
+0.5
V
V
= +3V
= +4.5V
REF
REF
mA
STATIC PERFORMANCE
Resolution
12
Bits
Integral Linearity
-K
-J
+0.25
+0.5
+0.5
+0.5
+1.0
+3.0
LSB
LSB
LSB
V
V
V
= +3V; Note 3
= +3V; Note 3
= +4.5V; Note 3
REF
REF
REF
Differential Linearity
-K
-J
+0.25
+0.25
+0.75
+1.0
LSB
LSB
Monotonicity
Guaranteed
DYNAMIC PERFORMANCE
Settling Time
Small Signal
Full Scale
4
30
µs
µs
to 0.024%
to 0.024%
Slew Rate
Multiplying Bandwidth
0.3
250
V/µs
KHz
SP9604DS/03
SP9604 Quad, 12-Bit, Low Power Voltage Output D/A Converter
© Copyright 2000 Sipex Corporation
2
SPECIFICATIONS (continued)
(Typical @ 25˚C, TMIN ≤ TA≤TMAX; VDD = +5V, VSS = -5V, VREF = +3V; CMOS logic level digital inputs; specifications apply to all grades unless otherwise noted.)
PARAMETER
MIN.
TYP.
MAX.
UNITS
CONDITIONS
STABILITY
Gain
Bipolar Zero
15
15
ppm/˚C
ppm/˚C
tMIN to tMAX
tMIN to tMAX
SWITCHING CHARACTERISTICS
tDS Data Set Up Time
tDN Data Hold Time
140
100
ns
ns
ns
ns
ns
to rising edge of WR1
Figure 4
0
tWR Write Pulse Width
tXFER Transfer Pulse Width
tWC Total Write Command
140
140
280
100
100
200
POWER REQUIREMENTS
Note 5
VDD
+5V, +3%; Note 4, 5
–J, –K
VSS
–J, –K
3
4
4
mA
-5V, +3%; Note 4, 5
3
mA
Power Dissipation
30
mW
ENVIRONMENTAL AND MECHANICAL
Operating Temperature
-J, -K
Storage
Package
-_P
0
-60
+70
+150
°C
°C
28-pin Plastic DIP
28-pin SOIC
-_S
Notes:
1.
Integral Linearity, for the SP9604, is measured as the arithmetic mean value of the magnitudes of
the greatest positive deviation and the greatest negative deviation from the theoretical value for any
given input condition.
2.
Differential Linearity is the deviation of an output step from the theoretical value of 1 LSB for any two
adjacent digital input codes.
1 LSB = 2*VREF/4,096.
VREF = 0V.
3.
4.
5.
The following power up sequence is recommended to avoid latch up: VSS (-5V), VDD (+5V), REF IN.
+0.25 lsb
DNLE
-0.25 lsb
+0.25 lsb
INLE
-0.25 lsb
0
CODE
4095
DNLE, INLE Plots
SP9604DS/03
SP9604 Quad, 12-Bit, Low Power Voltage Output D/A Converter
© Copyright 2000 Sipex Corporation
3
PIN ASSIGNMENTS
PINOUT — 28–PIN PLASTIC DIP & SOIC
Pin 1 — VOUT 4 — Voltage Output from DAC4.
V
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
OUT4
OUT3
Pin 2 — VSS — –5V Power Supply Input.
Pin 3 — VDD — +5V Power Supply Input.
V
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
V
SS
0
V
3
DD
1
CLR
4
2
Pin 4 — CLR — Clear. Gated with WR2 (pin 11).
Active low. Clears all DAC outputs to 0V.
REF IN
GND
5
3
6
4
B1/B2
7
5
Pin 5 — REF IN — Reference Input for DACs.
Pin 6 — GND — Ground.
SP9604
A
0
8
6
A
1
9
7
XFER
WR2
WR1
CS
10
11
12
13
14
8
Pin 7 — B1/B2 — Byte 1/Byte 2 — Selects Data
Input Format. A logic “1” on pin 7 selects the 12–bit
mode,andall12databitsarepresentedtotheDAC(s)
unchanged;alogic“0”selectsthe8–bitmode,andthe
four LSBs are connected to the four MSBs, allowing
an 8–bit MSB–justified interface.
9
10
11
V
OUT1
OUT2
Pins 8 and 9 — A & A1 — Address for DAC
Selection. A1/A = 00/0 = DAC1; 0/1 = DAC2; 1/0 =
DAC3; 1/1 = D0AC4.
Pin 14 — VOUT1 — Voltage Output from DAC1.
Pin 15 — VOUT2 — Voltage Output from DAC2.
Pin16 —DB11 —DataBit11;MostSignificantBit.
Pin 17 — DB10 — Data Bit 10.
Pin 18 — DB9 — Data Bit 9.
Pin 10 — XFER — Transfer. Gated with WR2 (pin
11); loads all DAC registers simultaneously. Active
low.
Pin 11 — WR2 — Write Input 2 — In conjunction
with XFER (pin 10), controls the transfer of data
from the input registers to the DAC registers. In
conjunction with CLR (pin 4), the DAC registers are
forced to 1000 0000 0000 and the DAC outputs will
settle to 0V. Active low.
Pin 19 — DB8 — Data Bit 8.
Pin 20 — DB7 — Data Bit 7.
Pin 21 — DB6 — Data Bit 6.
Pin 12 — WR1 — Write Input1 — In conjunction
withCS(pin13), enablesinputregisterselection,and
controls the transfer of data from the input bus to the
input registers. Active low.
Pin 22 — DB5 — Data Bit 5.
Pin 23 — DB4 — Data Bit 4.
Pin 24 — DB3 — Data Bit 3.
Pin13 —CS —ChipSelect—Enableswritingdata
to input registers and/or transferring data from input
bus to DAC registers. Active low.
Pin 25 — DB2 — Data Bit 2.
Pin 26 — DB1 — Data Bit 1.
Pin 27 — DB0 — Data Bit 0; LSB
Pin 28 — VOUT3 — Voltage Output from DAC3.
SP9604DS/03
SP9604 Quad, 12-Bit, Low Power Voltage Output D/A Converter
© Copyright 2000 Sipex Corporation
4
FEATURES
using the CS signal in both modes. The digital inputs
are designed to be both TTL and 5V CMOS compat-
ible.
The SP9604 is a low–power replacement for the
popularSP9345,Quad12-BitDigital-to-AnalogCon-
verter. ThisQuad,VoltageOutput,12-BitDigital-to-
Analog Converter features ±4.5V output swings
whenusing±5voltsupplies.Theinputcodingformat
usedisstandardoffsetbinary.(PleaserefertoTable1.)
InordertoreducetheDACfullscaleoutputsensitivity
tothelargeweightingoftheMSB’sfoundinconven-
tionalR-2Rresistorladders,the3MSB’saredecoded
into 8 equally weighted levels. This reduces the
contributionofeachbitbyafactorof4,thus,reducing
the output sensitivity to mis–matches in resistors and
switches by the same amount. Linearity errors and
stability are both improved for the same reasons.
The converterutilizesdouble-bufferingoneachofthe
12 parallel digital inputs, for easy microprocessor
interface. Each12-bitDACisindependentlyaddres-
sable and all DACs may be simultaneously updated
using a single XFER command. The output settling-
time is specified at 30µs to full 12–bit accuracy when
driving a 5Kohm, 50pf load combination. The
SP9604,Quad12-BitDigital-to-AnalogConverteris
ideally suited for applications such as ATE, process
controllers,robotics,andinstrumentation. TheSP9604
is available in 28–pin plastic DIP or SOIC packages,
specified over the commercial (0°C to +70°C)
temperature range.
Each D/A converter is separated from the data bus by
two registers, each consisting of level-triggered
latches, Figure 1. Thefirstregister(inputregister)is
12-bits wide. The input register is selected by the
addressinputA andA1 andis enabledbytheCSand
WR1 signals. In0 the 8-bit mode, the enable signal to
the 8 MSB’s is disabled by a logic low on B1/B2 to
allow the 4 LSB’s to be updated. The second register
(DACregister), acceptsthedecoded3MSB’splusthe
9 LSB’s. The four DAC registers are updated simul-
taneously for all DAC’s using the XFER and WR2
signals. Using the CLR and WR2 signals or the
power-on-reset,(enabledwhenthepowerisswitched
on) the DAC registers are set to 1000 0000 0000 and
the DAC outputs will settle to 0V.
THEORY OF OPERATION
The SP9604 consists of five main functional blocks
—inputdatamultiplexer,dataregisters,controllogic,
four 12-bit D/A converters, and four bipolar output
voltage amplifiers. The input data multiplexer is
designed to interface to either 12- or 8-bit micropro-
cessordatabusses. Theinputdataformatiscontrolled
by the B1/B2 signal — a logic “1” selects the 12-bit
mode, while a logic “0” selects the 8-bit mode. In the
12-bitmodethedataistransferredtotheinputregisters
without changes in its format. In the 8-bit mode, the
four least significant bits (LSBs) are connected to the
four most significant bits (MSBs), allowing an 8-bit
MSB-justified interface. All data inputs are enabled
Usingthecontrollogicinputs,theuserhasfullcontrol
of address decoding, chip enable, data transfer and
clearing of the DAC’s. The control logic inputs are
level triggered, and like the data inputs, are TTL and
CMOS compatible. The truth table (Table 2) shows
the appropriate functions associated with the states of
the control logic inputs.
TheDACsthemselvesareimplementedwithapreci-
sion thin–film resistor network and CMOS transmis-
sion gate switches. Each D/A converter is used to
convert the 12–bit input from its DAC register to a
precision voltage.
INPUT
OUTPUT
MSB
1111
1111
1000
1000
0000
0000
LSB
1111 1111
1111 1110
0000 0001
0000 0000
0000 0001
0000 0000
1 LSB =
VREF - 1 LSB
VREF - 2 LSB
0 + 1 LSB
0
The bipolar voltage output of the SP9604 is created
on-chip from the DAC Voltage Output (VDAC) by
using an operational amplifier and two feedback
resistors connected as shown in Figure 2.
This configuration produces a ±4.5V bipolar
output range with standard offset binary coding.
-VREF + 1 LSB
-VREF
2VREF
2 12
Table 1. Offset Binary Coding
SP9604DS/03
SP9604 Quad, 12-Bit, Low Power Voltage Output D/A Converter
© Copyright 2000 Sipex Corporation
5
Ref In
INPUT
REGISTER
DAC
REGISTER
40 KΩ 40 KΩ
4
4
4
4
DB11 - DB8
DB7 - DB4
8–BIT
8
4
LATCH
3 TO 7
DECODE
&
5 BITS
LATCH
–
+
VOUT
12 DAC
4
4-BIT
LATCH
MUX
DB3 - DB0
4
4
Figure 1. Detailed Block Diagram (only one DAC shown)
USING THE SP9604 WITH
DOUBLE-BUFFERED INPUTS
Loading Data
To load a 12-bit word to the input register of
each DAC, using a 12-bit data bus, the sequence
is as follows:
To load a 12-bit word to the input register of
each DAC, using an 8-bit data bus, the sequence
is as follows:
1) SetXFER=1,B1/B2=1,CLR=1,WR1=1,
WR2=1, CS=1.
2) Set D11 through D4 to the 8 MSB’s of the
desired digital input code.
3) Load the 8 MSB’s of the digital word to
theselectedinputregisterbycyclingWR1
and CS through the “1” — “0” — “1”
sequence.
4) Reset B1/B2 from “1” —— “0”
5) SetD11(MSB)throughD8tothe4LSB’s
of the digital input code.
1) SetXFER=1,B1/B2=1,CLR=1,WR1=1,
WR2=1, CS=1.
2) Set A1 and A0 (the DAC address) to the
desired DAC —0,0 = DAC ; 0,1 = DAC2
1,0 = DAC3; 1,1 = DAC4 .1
3) Set D11 (MSB) through D0 (LSB) to the
desired digital input code.
6) Loadthe4LSB’sbycyclingWR1andCS
through the “1” — “0” — “1” sequence.
7) Repeat sequence for each input register.
4) Load the word to the selected DAC by
cycling WR1 and CS through the follow-
ing sequence:
“1” — “0” — “1”
5) Repeat sequence for each input register.
A1
A0
CS
WR1 B1/B2
WR2
XFER CLR
FUNCTION
0
0
0
0
1
1
1
1
X
X
X
0
0
1
1
0
0
1
1
X
X
X
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
Address DAC 1 and load input register
Address DAC 1 and load 4 LSBs
Address DAC 2 and load input register
Address DAC 2 and load 4 LSBs
Address DAC 3 and load input register
Address DAC 3 and load 4 LSBs
Address DAC 4 and load input register
Address DAC 4 and load 4 LSBs
**
X
1
**
X
1
X
X
X
Transfer data from input registers to DAC registers
Sets all DAC output voltages to 0V
1
0
0
Temporarily force all DAC output voltages to 0V,
while CLR is low
X
X
X
X
1
X
1
X
X
X
X
X
X
X
X
Invalid state with any other control line active
Invalid state with any other control line active
X
X = Don’t care; ** = Don’t care; however, CS and WR1 = 1 will inhibit changes to the input registers.
Table 2. Control Logic Truth Table
SP9604DS/03
SP9604 Quad, 12-Bit, Low Power Voltage Output D/A Converter
© Copyright 2000 Sipex Corporation
6
REF IN
D
VOut
=
–1 x
REF IN
(
)
–
+
2048
VOut
D
D
4,096
VDAC
=
x
REF IN
VDAC
Figure 2. Transfer Function
TRANSFERRING DATA
To transfer the four 12-bit words in the four
input registers to the four DAC registers:
bringing WR1 low will transfer the data to the
addressed DAC. The user should be sure to
bring WR1 high again so that the next selected
DAC will not be overwritten by the last digital
code. This mode of operation may be useful in
applications where preloading of the input reg-
isters is not necessary, Figure 3a.
1) Set CLR=1, CS=1, WR1=1.
2) Cycle WR2 and XFER through the “1”
— “0” — “1” sequence.
TosettheoutputsofthefourDAC’sto0V, cycle
WR2 and CLR through the “1” — “0” — “1”
sequence, while keeping XFER=1.
A fully transparent mode is realized by tying
WR1, CS, WR2, and XFER all low. In this
mode, anything that is written on the 12-bit data
bus will be passed directly to the selected DAC.
Since both latches are not being used, the previ-
ous digital word will be overwritten by the new
data assoonasthe addresschanges. Thismaybe
useful should the user want to calibrate a circuit,
by taking full scale or zero scale readings for all
four DAC’s, Figure 3b.
One Latch, or No Latches
The latches that form the registers can be used in
a“semi-”transparentmode,anda“fully-”trans-
parent mode. In order to use the SP9604 in
either mode the user must be interfaced to a
12-bit bus only (B1=1).
The semi-transparent mode is set up such that
the second set of latches is transparent and the
first set is used to latch the incoming data. Data
is latched into the first set rather than the second
set, in order to minimize glitch energy induced
from the data formatting. In this mode, XFER,
WR2 and CS are tied low, and WR1 is used to
strobe the data to the addressed DAC. Each
DAC is addressed using the address lines A0 and
A1. After the appropriate DAC has been se-
lected and the data is settled at the digital inputs,
Zeroing DAC Outputs
WhilekeepingXFERpinhigh,theDACoutputs
can be set to zero volts two different ways. The
first involves the CLR and WR2 pins. In normal
operation, the CLR pin is tied high, thus, dis-
abling the clear function. By cycling WR2 and
CLR through "1"—"0"—"1" sequence, a digital
code of 1000 0000 0000 is written to all four
DAC registers, producing a half scale output or
zerovolts.Thesecondutilizesthebuiltinpower-
SP9604DS/03
SP9604 Quad, 12-Bit, Low Power Voltage Output D/A Converter
© Copyright 2000 Sipex Corporation
7
on-reset. Using this feature, the SP9604 can be
configured such that during power-up, the sec-
ond register will be digitally “zeroed”, produc-
ing a zero volt output at each of the four DAC
outputs. This is achieved by powering the unit
up with XFER in a high state. Thus, with no
externalcircuitry, theSP9604canbepoweredup
with the analog outputs at a known, zero volt
output level.
Temporarily forcing all DAC outputs to 0V
Set WR1=1, CS=1, WR2=0, XFER=0. The DAC
registers can be temporarily forced to 1000 0000
0000 by bringing the CLR pin low. This will force
theDACoutputsto0V,whiletheCLRpinremains
low. When the CLR pin is brought back high, the
digital code at the DAC registers will again appear
at the DAC's digital inputs, and the analog outputs
will return to their previous values.
+3V
+3V
Reference GND +5V –5V
Reference GND +5V –5V
V
V
V
OUT3
OUT3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
V
V
V
V
V
V
V
OUT3
DB
0
DB
1
DB
2
DB
3
DB
4
DB
5
DB
6
V
OUT4
OUT4
SS
OUT4
OUT4
SS
OUT3
DB
0
DB
1
DB
2
DB
3
DB
4
DB
5
DB
6
DD
DD
CLR
REF IN
GND
B1/B2
A
0
CLR
REF IN
GND
B1/B2
A
0
12–Bit
Data
Bus
12–Bit
Data
Bus
SP9604
SP9604
A
1
A
1
DB
7
DB
8
DB
9
DB
7
DB
8
DB
9
XFER
WR2
WR1
CS
XFER
WR2
WR1
CS
DB
DB
10
11
10
11
(MSB) DB
V
(MSB) DB
V
V
V
V
V
V
V
OUT1
OUT1
OUT1
OUT1
OUT2
OUT2
OUT2
OUT2
DAC Strobe
Address
Decode &
Control
Address
Decode &
Control
(a)
(b)
Figure 3. Latch Control Options — (a) Semi–Transparent Latch Mode; (b) Fully–Transparent Latch Mode
H
L
H
L
WR2
CS
CLR
XFER
WR2
H
L
H
L
H
L
H
L
WR1
140ns, tWR
140ns, tXFER
Data Transfer from
Input Register to DAC's
Loads Input Data to
First Set of Latches
Figure 4. Timing
SP9604DS/03
SP9604 Quad, 12-Bit, Low Power Voltage Output D/A Converter
© Copyright 2000 Sipex Corporation
8
PACKAGE: PLASTIC
DUAL–IN–LINE
(WIDE)
E
E1
D1 = 0.005" min.
(0.127 min.)
A1 = 0.015" min.
(0.381min.)
D
A = 0.25" max.
(6.350 max).
C
A2
Ø
L
B1
B
e
= 0.600 BSC
e = 0.100 BSC
(2.540 BSC)
A
(15.240 BSC)
DIMENSIONS (Inches)
Minimum/Maximum
(mm)
24–PIN
28–PIN
32–PIN
40–PIN
48–PIN
0.125/0.195
(3.175/4.953)
A2
0.125/0.195
0.125/0.195
0.125/0.195
0.125/0.195
(3.175/4.953) (3.175/4.953)
(3.175/4.953) (3.175/4.953)
0.014/0.022
(0.366/0.559
B
0.014/0.022
(0.366/0.559
0.014/0.022
(0.366/0.559
0.014/0.022
0.014/0.022
(0.366/0.559) (0.366/0.559)
0.030/0.070
B1
C
0.030/0.070
0.030/0.070
0.030/0.070
0.030/0.070
(0.762/1.778)
(0.762/1.778) (0.762/1.778)
(0.762/1.778) (0.762/1.778)
0.008/0.015
(0.203/0.381)
0.008/0.015
(0.203/0.381) (0.203/0.381)
0.008/0.015
0.008/0.015 0.008/0.015
(0.203/0.381) (0.203/0.381)
1.980/2.095 2.385/2.480
1.150/1.290
(29.21/32.76)
D
1.380/1.565
(35.05/39.75) (41.78/42.04)
1.645/1.655
(50.29/53.21) (60.57/62.99)
0.600/0.625
E
0.600/0.625 0.600/0.625
0.600/0.625 0.600/0.625
(15.24/15.87)
(15.24/15.87) (15.24/15.87)
0.485/0.580 0.485/0.580
(15.24/15.87) (15.24/15.87)
0.485/0.580 0.485/0.580
0.485/0.580
(12.31/14.73)
E1
L
(12.31/14.73) (12.31/14.73)
(12.31/14.73) (12.31/14.73)
0.115/0.200
(2.921/5.080)
0.115/0.200 0.115/0.200
(2.921/5.080) (2.921/5.080)
0.115/0.200 0.115/0.200
(2.921/5.080) (2.921/5.080)
0°/ 15°
(0°/15°)
Ø
0°/ 15°
(0°/15°)
0°/ 15°
(0°/15°)
0°/ 15°
(0°/15°)
0°/ 15°
(0°/15°)
SP9604DS/03
SP9604 Quad, 12-Bit, Low Power Voltage Output D/A Converter
© Copyright 2000 Sipex Corporation
9
PACKAGE: PLASTIC
SMALL OUTLINE (SOIC)
E
H
D
A
Ø
A1
L
e
B
DIMENSIONS (Inches)
Minimum/Maximum
(mm)
28–PIN
A
A1
B
D
E
0.090/0.100
(2.29/2.54)
0.004/0.010
(0.102/0.254)
0.014/0.020
(0.36/0.48)
0.706/0.718
(17.93/18.24)
0.340/0.350
(8.64/8.89)
e
0.050 BSC
(1.270 BSC)
H
L
0.463/0.477
(11.76/12.12)
0.020/0.042
(0.51/1.07)
Ø
0°/8°
(0°/8°)
SP9604DS/03
SP9604 Quad, 12-Bit, Low Power Voltage Output D/A Converter
© Copyright 2000 Sipex Corporation
10
ORDERING INFORMATION
Model
Temperature Range
Package
Monolithic 12-Bit Quad DAC Voltage Output:
SP9604JP .................................................................................. 0˚C to +70˚C ...................................................................... 28-pin, 0.6" Plastic DIP
SP9604KP ................................................................................. 0˚C to +70˚C ...................................................................... 28-pin, 0.6" Plastic DIP
SP9604JS .................................................................................. 0˚C to +70˚C ............................................................................. 28–pin, 0.35" SOIC
SP9604KS ................................................................................. 0˚C to +70˚C ............................................................................. 28–pin, 0.35" SOIC
Please consult the factory for pricing and availability on a Tape-On-Reel option.
Co rp o ra tio n
SIGNAL PROCESSING EXCELLENCE
Sipex Corporation
Headquarters and
Sales Office
22 Linnell Circle
Billerica, MA 01821
TEL: (978) 667-8700
FAX: (978) 670-9001
e-mail: sales@sipex.com
Sales Office
233 South Hillview Drive
Milpitas, CA 95035
TEL: (408) 934-7500
FAX: (408) 935-7600
Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the
application or use of any product or circuit described hereing; neither does it convey any license under its patent rights nor the rights of others.
SP9604DS/03
SP9604 Quad, 12-Bit, Low Power Voltage Output D/A Converter
© Copyright 2000 Sipex Corporation
11
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