SP9840KN [SIPEX]
8-Bit Octal, 4-Quadrant Multiplying, BiCMOS DAC; 8位八路， 4象限乘法， BiCMOS工艺DAC
| 型号： | SP9840KN |
| 厂家： | 
SIPEX CORPORATION |
| 描述： | 8-Bit Octal, 4-Quadrant Multiplying, BiCMOS DAC |
| 文件： | 总10页 (文件大小：128K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SP9840/43
8-Bit Octal, 4-Quadrant Multiplying, BiCMOS DAC
■ Replaces 8 Potentiometers and 8 Op amps
■ Operates from Single +5V Supply
■ 5 MHz 4-Quadrant Multiplying Band-
width
■ Eight Inputs/Eight Outputs (SP9840)
Four Inputs/Eight Outputs (SP9843)
■ 3-Wire Serial Input
■ 0.8MHz Data Update Rate
■ +3.25V Output Swing
■ Midscale Preset
■ Programmable Signal Inversion
■ Low 70mW Power Dissipation
(9mW/DAC)
DESCRIPTION…
The SP9840 and SP9843 are general purpose octal DACs in a single package. The SP9840
features eight individual reference inputs, while the SP9843 provides four pair of voltage
reference inputs. Both parts feature 5MHz bandwidth, four–quadrant multiplication, and a three–
wire serial interface. Other features include midscale preset, programmable signal inversion and
low power dissipation from a single +5V supply. Devices are available in commercial and
industrial temperature ranges.
VIN1
–
V
OUT1
8
+
Data
8
DAC 1
Clock
Serial Data Input
Serial Data Output
SERIAL
REGISTER
8 x 8
DAC
REGISTER
Preset
Load
4
VIN8
LOGIC
8
V
OUT8
8
Decoded
Address
DAC 8
V
REF Low
SP9840 shown
257
ABSOLUTE MAXIMUM RATINGS
These are stress ratings only and functional operation of the device
at these or any other above those indicated in the operation
sections of the specifications below is not implied. Exposure to
absolute maximum rating conditions for extended periods of time
may affect reliability.
CAUTION:
Whileallinputandoutputpinshave
internal protection networks, these
parts should be considered ESD
(ElectroStatic Discharge) sensitive de-
vices. Permanent damage may occur on
unconnected devices subject to high en-
ergy electrostatic fields. Unused devices
must be stored in conductive foam or
shunts. Personnel should be properly
grounded prior to handling this device.
The protective foam should be discharged
to the destination socket before devices are
removed.
VDD to GND ...................................................................... -0.3V, +7V
VINX to GND ............................................................................... VDD
VREFL to GND ............................................................................. VDD
VOUTX to GND ............................................................................ VDD
Short Circuit IOUTX to GND ............................................ Continuous
Digital Input & Output Voltage to GND ....................................... VDD
Operating Temperature Range
Commercial ............................................................... 0°C to +70°C
Extended Industrial ................................................. -40°C to +85°C
Maximum Junction Temperature (TJ max) .......................... +150°C
Storage Temperature ................................................. -65° to 150°C
Lead Temperature (Soldering, 10 sec) ............................... +300°C
Package Power Dissipation .................................. (TJ max - TA)/8JA
Thermal Resistance 8JA
P-DIP .................................................................................. 57°C/W
SOIC-24 .............................................................................. 70°C/W
SPECIFICATIONS
(VDD = +5V, All VINX= 0V, VREFL = 1.625V, TA = 25° C for commercial–grade parts;
T
MIN ≤ TA = TMAX for industrial–grade parts; specifications apply to
all DAC's unless noted otherwise.)
PARAMETER
MIN.
TYP.
MAX.
UNITS
CONDITIONS
SIGNAL INPUTS
Input Voltage Range
Input Resistance
SP9840
0
3.25
V
VDD = 4.75V, VREFL = 1.625V
D = 2BH, Code Dependent
3.1
1.55
6.2
3.1
kΩ
kΩ
SP9843
Input Capacitance
SP9840
SP9843
VREFL Resistance
VREFL Capacitance
Note 1
19
38
1.3
190
30
60
pF
pF
kΩ
pF
0.68
2.4
Note 1 and 2
Note 1
250
DIGITAL INPUTS
Logic High
Logic Low
Input Current
Input Capacitance
Input Coding
V
V
µA
pF
0.8
±10
8
Offset Binary
Note 3
STATIC ACCURACY
Resolution
Integral Nonlinearity
Differential Nonlinearity
Half-Scale Output Voltage
Minimum Output Voltage
Output Voltage Drift
8
Bits
LSB
LSB
V
mV
µV/°C
±0.75
±0.3
1.625
20
±1.5
±1
1.650
100
Note 4
Note 4
1.600
3
PR = LOW, V
= 1.625V
D=FF ; I
=R0EF.1L mA
25
PR = HLOSWINK
DYNAMIC PERFORMANCE
Multiplying Gain Bandwidth
Slew Rate
5
MHz
VIN(X) = 100mVP–P + 1.625V dc
Measured 10% to 90%
∆V = 3.2V
Positive
Negative
Total Harmonic Distortion
3.0
–3.0
7.9
–8.3
0.003
V/µs
V/µs
%
∆V = –3.2V
V (X) = 3VP–P +1.625V dc,
DI=NFFH; 1KHz, fLP=80KHz
±1 LSB Error Band
Note 5
Output Settling Time
Crosstalk
0.7
70
µs
dB
60
Digital Feedthrough
Wideband Noise
SINAD
6
42.5
89
nVs
µVrms
dB
D = 0H to FF
VOUT = 3.25V,H400Hz to 80kHz
V (X) = 3VP–P +1.625V dc,
DI=NFFH; 1KHz, fLP=80KHz
Note 6
Digital Crosstalk
6
nVs
258
SPECIFICATIONS (continued)
VDD = +5V, All VINX= +0V, VREFL = 1.625, TA = 25° C for commercial–grade parts;
TMIN ≤ TA = TMAX for industrial–grade parts; specifications apply to all
DAC's unless noted otherwise.)
PARAMETER
MIN.
TYP.
MAX.
UNIT
CONDITIONS
DAC OUTPUTS
Voltage Range
Output Current
Capacitive Load
0
±10
VDD – 1.5
V
mA
pF
RL = 5kΩ, VDD = 4.75V
Note 7
No Oscillation
±15
47,000
DIGITAL OUTPUT
Logic High
Logic Low
3.5
V
V
IOH = –0.4mA
IOL = 1.5mA
0.4
POWER REQUIREMENTS
Power Supply Range
Positive Supply Current
Power Dissipation
4.75
5.00
14
70
5.25
V
mA
mW
To rated specifications
PR = LOW
PR = LOW
ENVIRONMENTAL AND MECHANICAL
Operating Temperature Range
Commercial
Industrial
Storage Temperature Range
Package
0
–40
–65
+70
+85
+150
°C
°C
°C
SP9840N
SP9840S
24–pin, 0.3" Plastic DIP
24–pin 0.3" SOIC
SP9843S
20–pin, 0.3" SOIC
Note 8
Notes:
1.
2.
3.
Code dependent
All VIN(x) = GND; D = 55H
Offset binary refers to the output voltage with respect to the signal ground at VREFL. For a positive
VIN(x), the output will increase from negative fullscale to VREFL to positive (fullscale–1 LSB) as the
input code is incremented from 0 to 128 to 255. Note that when VIN(x) is tied to ground and VREFL is
driven to +1.625V, as in the production tests above, then the resulting DC at VOUT(x) will decrease
from +2VREFL to VREFL/128 as the code is increased from 00H to FFH, due to the VIN(x) input being tied
negative with respect to VREFL
.
4.
5.
The op amp limits linearity for VOUT <100mV. When VIN(x) is driven above ground such that the
output voltage remains above 100mV, then the linearity specifications apply to all codes. For
VREFL=1.625V, and VIN(x)=GND, codes 248 through 255 are not included in differential or integral
linearity tests. Integral and differential linearity are computed with respect to the best fit straight line
through codes 0 through 248.
SP9840 is measured between adjacent channels, F=100kHz. SP9843 is measured between
adjacent pairs, F=100kHz.
6.
7.
8.
SP9843 only; measured between channels with shared input; D = 7FH to 80H
∆VOUT < 10mV, VREFL = 1.625V, PR = LOW.
For plastic DIP, consult factory
259
Pin17—CLOCK—SerialClockInput;positive-edge
triggered.
SP9840 PINOUT
V
C
1
2
3
4
5
6
7
8
9
24 V
23 V
22 V
21 V
D
OUT
OUT
V
B
C
IN
Pin18—SDO—SerialDataOutput;activetotem-pole
output.
OUT
V
A
B
A
D
IN
DD
OUT
V
V
IN
IN
20 SDI
SP9840
Pin 19 — GND — Ground.
V
19 GND
18 SDO
REFL
PRESETL
V
IN
E
17 CLOCK
16 LOADH
Pin 20 — SDI — Serial Data Input.
V
IN
F
V
E 10
F 11
15 V
14 V
13 V
H
OUT
IN
IN
Pin 21 — V — Positive 5V Power Supply.
DD
V
G
OUT
V
OUT
G 12
H
OUT
Pin 22 — V D — DACD Reference Voltage Input.
IN
Pin 23 — V C — DACC Reference Voltage Input.
IN
Pin 1 — V C — DACC Voltage Output.
OUT
Pin 24 — V D — DACD Voltage Output.
OUT
Pin 2 — V B — DACB Voltage Output.
OUT
SP9843 PINOUT
Pin 3 — V A — DACA Voltage Output.
OUT
V
C
1
2
3
4
5
6
7
8
9
20 V
D
OUT
OUT
Pin 4 — V B — DAC B Reference Voltage Input.
IN
V
B
19 V C/D
IN
OUT
V
A
18 V
DD
OUT
Pin 5 — V A — DAC A Reference Voltage Input.
IN
V
A/B
17 SDI
IN
V
L
16 GND
15 SDO
REF
SP9843
PRESETL
E/F
Pin6—V L—DACReferenceVoltageInputLow,
REF
V
14 CLOCK
13 LOADH
IN
common to all DACs.
V
E
OUT
V
F
12 V G/H
IN
OUT
Pin 7 — PRESETL — Preset Input; active low; all
V
OUT
G 10
11 V
H
OUT
DAC registers forced to 80 .
H
Pin 8 — V E — DAC E Reference Voltage Input.
IN
Pin 1 — V C — DACC Voltage Output.
OUT
Pin 9 — V F — DAC F Reference Voltage Input.
IN
Pin 2 — V B — DACB Voltage Output.
OUT
Pin 10 — V E — DACE Voltage Output.
OUT
Pin 3 — V A — DACA Voltage Output.
OUT
Pin 11 — V F — DACF Voltage Output.
OUT
Pin 4 — V A/B — DACA and B Reference Voltage
Input.
IN
Pin 12 — V G — DACG Voltage Output.
OUT
Pin 13 — V H — DACH Voltage Output.
Pin 5 — VREFL — DAC Reference Voltage
Input Low, common to all DACs.
OUT
Pin 14 — V G — DACG Reference Voltage Input.
IN
Pin 6 — PRESETL — Preset Input; active low; all
Pin 15 — V H — DACH Reference Voltage Input.
DAC registers forced to 80 .
IN
H
Pin 16 — LOADH — Load DAC Register
Strobe; active high input that transfers the data
bits from the Serial Input Register into the
decoded DAC Register. Refer to Table 1.
Pin 7 — V E/F — DAC E and F Reference Voltage
Input.
IN
Pin 8 — V E — DACE Voltage Output.
OUT
260
Pin 9 — V F — DACF Voltage Output.
Eachchannelconsistsofavoltage–outputDAC,
realized using CMOS switches and thin–film
resistors in an inverted R–2R configuration.
Each DAC drives the positive terminal of an op
amp, configured for a gain of –1 to +1 using
equalvaluethin–filmfeedbackandgain–setting
resistors. Signal return is the VREFL pin, the
common reference input return for the eight
DAC–op amp channels.
OUT
Pin 10 — V G — DACG Voltage Output.
OUT
Pin 11 — V H — DACH Voltage Output.
OUT
Pin12—V G/H—DACGandHReferenceVoltage
IN
Input.
Pin 13 — LOADH — Load DAC Register Strobe;
active high input that transfers the data bits from the
SerialInputRegisterintothedecodedDACRegister.
Refer to Table 1.
As shown in Figure 1, the DAC section can be
thought of as a potentiometer across VIN(X) to
VREFL. If this potentiometer is set to its minimum
value of 0/256, the potentiometer will have no
effect on the gain, and the output will be –RF/RIN
= –1 times the input. If the potentiometer could
be set to 256/256, then the amplifier positive
terminal would see 100% of any input and no
current would flow through RIN. The circuit
would behave as a non–inverting unity gain
circuit, although with a noise gain of two, not
one. In reality, the "potentiometer" can only be
set to 255/256, and the maximum positive gain
is 0.992 times the voltage between VIN(X) and
Pin14—CLOCK—SerialClockInput;positive-edge
triggered.
Pin15—SDO—SerialDataOutput;activetotem-pole
output.
Pin 16 — GND — Ground.
Pin 17 — SDI — Serial Data Input.
Pin 18 — V — Positive 5V Power Supply.
VREFL.
DD
Pin19—V C/D—DACCandDReferenceVoltage
Input.
The true relation between the DC levels at the
VIN(X) pins, VREFL and the output can be de-
scribed as:
IN
Pin 20 — V D — DACD Voltage Output.
OUT
D
F1
(
)
VOUT
=
−1
VIN −VREFL +VREFL
((
)
)
128
SP9840/SP9843
Theory of Operation
where D is programmable from 0 to 255.
Each of the eight channels of the SP9840/9843
can be used for signal reconstruction, as a pro-
grammable DC source, or as a programmable
signed attenuator of –1 to +0.992 times a multi-
plyingACreferenceinput.Theruggedwideband
output amplifiers provide both current sink and
source capability to DC applications, even into
difficult loads. The DC source mode mimics the
functionality of a programmable trimpot, with
the added benefit of a low–impedance buffered
output.Theamplifier'sbandwidthandhighopen
loop gain allow use in programmable signed
attenuator applications where even low–distor-
tion, highresolutionsignals, suchasaudio, must
begatedonandoff,programmablephaseshifted
by 0° or 180° or gain controlled over a –42 to
0dB range at either phase.
For single supply operation VREFL is usually
externally driven to some voltage above ground
— typically 1.5 to 2.5V. IF V
is driven to
1.5V, and VIN(X) is groundeRdE,FLthen code 0
wouldoutput+3.0V, andcode255wouldoutput
+11.7mV. If V
were grounded and VIN(X)
driven to 1.5V,RtEhFLen codes between 0 and 128
would attempt to drive the output below ground,
which will saturate the output amplifier at some
voltage slightly above ground.
USING THE SP9840/9843
Multiplication of Input Voltages
While both the SP9840 and SP9843 are capable of
four–quadrant multiplication, this terminology is not
261
LAST
FIRST
D
D
D
D
D
D
D
D
A
A
A
A
3
0
1
2
3
4
5
6
7
0
1
2
LSB
MSB LSB
MSB
DATA
ADDRESS
A
A
A
DAC Updated
A
2
3
1
0
0
0
0
0
1
1
1
1
0
0
.
0
0
0
0
0
0
0
0
1
1
.
0
0
1
1
0
0
1
1
0
0
.
No Operation
DACA
0
1
0
1
0
1
0
1
0
1
.
DACB
DACC
DACD
DACE
DACF
DACG
DACH
No Operation
.
.
.
.
.
.
1
1
1
No operation
1
D
D
D
D
D
D
D
D
DAC Output Voltage
7
6
5
4
3
2
1
0
D
V
=
−1
VIN −VREFL +VREF
( )
OUT
128
–2V
L
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
REF
0
.
.
.
0
1
1
1
0
0
1
0
0
1
0
0
1
0
0
.
1
0
0
1
0
0
1
0
1
.
.
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
Table 1. Serial Input Decoded Truth Table
very precise when describing a system which runs
fromasinglepositivesupply.Traditionally,thequad-
rants have been defined with respect to 0V. A two–
quadrant multiplying DAC could produce negative
output voltages only if a negative voltage reference
were applied. A four–quadrant device could also
produce a code–controlled negative output from a
positive reference, or a code–controlled positive out-
put from a negative reference. If ground is used to
delineate the quadrants, then the SP9840/SP9843
should be considered single–quadrant multiplying
devices, as their output op amps cannot produce
voltages below ground.
In reality, it is possible to define a DC voltage as a
signal ground in a single supply system. If the DAC's
V
pin is driven to the voltage chosen as pseudo–
grRoEuFnL d, then each voltage output will exhibit 4–
quadrant behavior with respect to pseudoground. For
codes greater than 128, the output voltage will enter
the quadrant below the pseudoground voltage when
the input voltage goes below pseudoground. For
codes less than 128, the output voltage will be below
pseudogroundwhentheinputisabovepseudoground.
When V
is driven to some positive voltage and
VIN(X) iRsEFgLrounded, the device performs as if it
were a buffered trimpot tied between ground and
a voltage equal to two times V . This mode of
operation can be used as anRE"FiLnverted single–
quadrant"sourcewithanapproximaterangeof0to
(VREFL*2)Volts. Because the output voltage will
decrease as the code is increased, this mode is
considered to be inverted with respect to normal
single–quadrant operation. Note that the mini-
mum output voltage will be 1LSB above VIN(X).
+5V
VDD
VIN(X)
–
+
VOUT
VREFL
DAC
D
128
3
VOUT
=
−1 VIN −VREFL +VREFL
(
)
Figure 2a and 2b show "inverted single–quadrant"
and 4–quadrant performance of the SP9840/9843.
Figure 1. DAC and Output Amplifier Circuit
262
a)
b)
Figure 2. a) Inverted Single–Quadrant Operation; b) 4–Quadrant Operation
Applications which require two–quadrant operation
with respect to pseudoground should use the SIPEX
SP9841orSP9842two–quadrantmultiplyingDACs.
amplifier cannot drive. This minimum voltage
is in the 15 to 25mV range. It varies within a
package with each op amp's offset voltage and
biasingvariations. Ifaninputvoltagelowerthan
this minimum, such as code 255 when VIN(X) is
grounded, is requested, feedback within the op
amp circuit will force internal nodes to the rails,
while the output will remain saturated near this
minimum value. Non–saturated monotonic be-
havior returns between 25mV and 100mV at the
output, but full open loop gain and linearity are
not apparent until the output voltage is nearly
100mV above the negative supply. Four–quad-
rant (programmable signed attenuator) applica-
tions usually bias VREFL up at system
pseudoground, well above this saturation re-
gion, and therefore maintain linearity even at
high attenuations (i.e. near code 80HEX).
The choice of voltage to use for the pseudoground is
limitedbythelegalvoltageswingattheopampoutput.
The op amp exhibits excellent linearity for output
voltages between, conservatively, 100mV and VDD
–
1.5V. The op amp BiCMOS output stage consists of
annpnfollowerloadedbyanNMOScommonsourced
to ground. This circuit exhibits wide bandwidth and
cansourcelargecurrents, whileretainingthecapabil-
ity of driving the output to voltages close to ground.
Atoutputvoltagesbelow25mV,feedbackforces
some op amp internal nodes toward the supply
rails. The NMOS pull–down device gets driven
hard and the NMOS device enters the linear
region — it begins to function in the same
manner as a 50 ohm resistor. In reality, the
wideband amplifier output stage sinks some
internalquiescentcurrentevenwhendrivingthe
output towards ground. This sunk current drops
across the output stage NMOS transistor ON–
resistance and internal routing resistance to pro-
videaminimumoutputvoltagebelowwhichthe
Driving the Reference Inputs
The eight independent VIN inputs of the SP9840, and
the four–pair of inputs in theSP9843, exhibit a code–
dependentinputresistance, asshowninthespecifica-
tions, and as a typical graph. In general, these inputs
should be driven by an amplifier capable of handling
SDI
X
CLK
LOADH
PRESETL
LOGIC OPERATION
L
L
L
H
H
No Change
Data
Shift In One Bit from SDI
Shift Out 12–clock delayed data at SDO
X
X
X
L
X
H
L
All DAC Registers Preset to 80H (Note 1)
H
Load Serial Register Data into DAC(X) Register
Note 1: "Preset" may not persist at all DACs if LOADH is high when PRESETL returns high.
Table 2. Logic Control Input Truth Table.
263
the specified load resistance and capacitance. The
reference inputs are useful for both AC and DC input
sources. However, series resistance into these pins
will degrade the linearity of the DAC — 50 Ohms of
seriesresistancecancauseupto0.5LSBofadditional
integrallinearitydegradationforcodesnearzero, due
to the code–dependent input current dropping across
thiserrorresistance.AC–coupledapplicationsshould
use the largest capacitor value (lowest series imped-
ance) which is practical, or use an external buffer to
drive the inputs.
Interfacing to the SP9840/SP9843
A simple serial interface, similar to that used in a
74HC594 shift–register with output latch, has been
implemented in these products. A serial clock is used
to strobe serial data into a 12–stage shift–register at
eachrisingclockedge.Thefirstfourserialbitscontain
theaddressoftheDACtobeupdated, MSBfirst. The
next 8 bits contain the binary value to be loaded into
thedesiredDAC,againMSBfirst.Afterthe12thserial
bit is clocked in, the LOADH line can be strobed to
latchthe8bitsofdataintothedataholdingregisterfor
the desired DAC. The address bits feed a decoding
network which steers the LOADH pulse to the clock
input of the desired DAC data holding register. The
output of the 12th shift–register is also buffered and
brought out as the SERIAL DATA OUT (SDO),
which can be used to cascade multiple devices, or for
data verification purposes.
TheDACswitchesfunctioninabreak–before–make
manner in order to minimize current spikes at the
reference inputs. The reference inputs can withstand
drivingvoltagesslightlybeyondthepowerrailswith-
out harm; the gain of ±1 at the op amps limits the
choice of V /VREFL combinations if clipping is to be
avoidedatvIeNryhighorverylowcodes.Notethatrail–
to–rail inputs can always be attenuated by choosing a
code nearer midscale, if clipping of the output is
undesirable.
The address field is set up such that DACA is ad-
dressed at 0001 (binary) and the others consecutively
through DACH at 1000(binary). Address 0000(bi-
nary) will not affect the operation of any channel, as
this combination is easily generated inadvertently at
power–up. Other no–operation addresses exist at
1001(binary) through 1111(binary). Another use for
no–operation addresses is to mask off updates of any
DAC channel in a multiple–part system with cas-
caded serial inputs and outputs. By sending a valid
address and data only to the desired channel, it is
possible to simplify the system hardware by driving
the LOADH pin at each part in parallel from a single
source. Table 1 shows a register–level diagram of the
addresses, data, and the resulting operation.
Output Considerations
Each DAC output amplifier can easily drive 1Kohm
loads in parallel with 15pF at its rated slew rate. The
uniqueBiCMOSamplifierdesignalsoensuresstabil-
ity into heavily capacitive loads — up to 47,000pF.
Undertheseconditions,theslewratewillbelimitedby
the instantaneous current available for charging the
capacitance—theslewratewillbeseverelydegraded,
and some damped ringing will occur. Especially
under heavy capacitive loading, a large, low imped-
ancelocalbypasscapacitorwillberequired.A0.047µF
ceramic in parallel with a low–ESR 2.2 to 10µF
tantalum are recommended for worst–case loads.
A fourth control pin, PRESETL, can be used to
simultaneously preset all DAC data holding registers
to their mid–scale (80H) values. This will asynchro-
nouslyforceallDACoutputstobufferthevoltagesat
theirrespectiveinputstotheiroutputswithunitygain.
Thisfeatureisusefulatpower–up,asasimpleresistor
to the supply and capacitor to ground can insure that
all DAC outputs start at a known voltage. For four–
channel multiplying applications, this sets the default
start–upgaintozero;only–70dBoffeedthroughfrom
the VIN(X) inputs will be present at the outputs. Table
2 summarizes the operation of the four digital inputs.
The amplifier outputs can withstand momentary
shorts to V or ground. Continuous short circuit
operation cDaDn result in thermally induced damage,
and should be avoided.
If the input reference voltage is reduced to 0.6V, then
both the amplifier and DAC are functional at room
temperatureatsupplyvoltagesaslowas2.5V.AtVDD
= 2.7V, power dissipation is 9.3mW typical, with the
serialclockat4MHz,or7.0mWtypicalwiththeserial
clock gated off.
264
The four digital control input pins have been
designed to accept TTL (0.8V to 2.0V minimum)
or full 5V CMOS input levels. The serial data
output can drive either TTL or CMOS inputs.
Timing information is shown in Figure 3. Serial
data is fully clocked into the shift–register after 12
clock rising edges, subject to the described setup
and hold times. After the shift–register data is
valid, the LOADH line can be pulsed high to load
data into the desired DAC data register, which
switchestheDACtothenewinputcode.Theserial
clock input should not see a rising edge while the
LOADH pulse is high in order to prevent shift–
register data from corruption during data register
loading.
Theserialclockanddatainputpinsaredesignedtobe
compatibleasslavesunderNationalSemiconductor's
Microwire™ and MicrowirePlus™ protocols and
under Motorola's SPI™ and QSPI™ protocols. In
somemicro–controllers,theinterfaceiscompletedby
programming a bit in a general–purpose I/O port as a
level, used to strobe the LOADH line at the DACs.
This is done in a manner similar to that used for
generating a Chip Select signal, which is necessary
when driving some other Microwire™ peripherals.
tPR
1
0
PRESET
tS
(FFH)
V
±1 LSB
ERROR BAND
OUT (08H)
1
0
SDI
A
A
A
A
D
D
D
D
D
D
D
D
0
3
2
1
0
7
6
5
4
3
2
1
1
0
CLOCK
LOAD
1
0
FS
VOUT
0
SERIAL DATA INPUT TIMING DETAIL (PRESET = Logic "1"; VIN(X) = 1.5V; VREFL = 0V)
AX or DX
1
0
SERIAL
DATA IN
tDS
tDH
SERIAL
DATA OUT
1
0
tPD
tCH
1
0
CLOCK
LOAD
tCL
tCLKD
tLD
tLDCK
1
0
tS
(FFH)
V
±1 LSB
ERROR BAND
OUT (08H)
CHARACTERISTICS
(Typical @ 25°C with VDD = +5V unless otherwise noted.)
PARAMETER
Input Clock Pulse Width (tCH, tCL)
MIN.
50
TYP.
MAX.
UNIT
ns
CONDITIONS
Data Setup Time (tDS
Data Hold Time (tDH
CLK to SDO Propagation Delay (tPD
DAC Register Load Pulse Width (tLD)
Preset Pulse Width (tPR
Clock Edge to Load Time (tCKLD
)
30
20
ns
ns
ns
ns
ns
ns
)
)
100
50
50
30
)
)
Load Edge to Next Clock Edge (tLDCK)
60
ns
Figure 3. Timing
265
ORDERING INFORMATION
Model
Reference Inputs
Temperature Range
Package
SP9840KN ................................... Eight, independent ............................................... 0° to + 70°C ................................. 24–pin, 0.3" Plastic DIP
SP9840BN ................................... Eight, independent ............................................... –40° to + 85°C ............................. 24–pin, 0.3" Plastic DIP
SP9840KS ................................... Eight, independent ............................................... 0° to + 70°C ........................................... 24–pin, 0.3" SOIC
SP9840BS ................................... Eight, independent ............................................... –40° to + 85°C ....................................... 24–pin, 0.3" SOIC
SP9843KS ................................... Four pair ............................................................... 0° to + 70°C ........................................... 20–pin, 0.3" SOIC
SP9843BS ................................... Four pair ............................................................... –40° to + 85°C ....................................... 20–pin, 0.3" SOIC
266
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