SP9841KS [SIPEX]
8-Bit Octal, 2-Quadrant Multiplying, BiCMOS DAC; 8位8通道， 2象限乘法， BiCMOS工艺DAC
| 型号： | SP9841KS |
| 厂家： | 
SIPEX CORPORATION |
| 描述： | 8-Bit Octal, 2-Quadrant Multiplying, BiCMOS DAC |
| 文件： | 总32页 (文件大小：736K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SP9841/42
8-Bit Octal, 2-Quadrant Multiplying, BiCMOS DAC
■ Replaces 8 Potentiometers and 8 Op Amps
■ Operates from Single +5V Supply
■ 6.3 MHz 2-Quadrant Multiplying Gain Band-
width
■ No Signal Inversion
■ Eight Reference Inputs, Eight Voltage
Outputs (SP9841)
■ Four Reference Inputs, Eight Voltage
Outputs (SP9842)
■ 3-Wire Serial Input
■ 0.8MHz Data Update Rate
■ +3.25 Volt Output Swing
■ Midscale Preset
■ Low 65 mW Power Dissipation (8mW/DAC)
DESCRIPTION…
The SP9841 and SP9842 are general purpose octal DACs in a single package. The SP9841
features eight individual reference inputs, while the SP9842 provides four pair of voltage
reference inputs. Both parts feature 6.3MHz bandwidth, two–quadrant multiplication, and a
three–wire serial interface. Other features include midscale preset, no signal inversion and low
power dissipation from a single +5V supply. Devices are available in commercial and industrial
temperature ranges.
VINA
DAC A
+
–
V
OUTA
8
Data
8
Clock
Serial Data Input
Serial Data Output
SERIAL
REGISTER
8 x 8
DAC
REGISTER
SP9842 Block Diagram
Preset
Load
4
DAC A
DAC B
V
INH
+
–
LOGIC
8
8
VOUTA
DAC H
V
OUTH
8
Decoded
Address
V
V
INA/B
OUTB
Data
Clock
Serial Data Input
Serial Data Output
+
–
SERIAL
REGISTER
8 x 8
DAC
REGISTER
8
8
SP9841
VREF Low
Preset
Load
SP9841 Block Diagram
4
LOGIC
8
DAC G
+
8
8
VOUTG
–
Decoded
Address
V
V
ING/H
OUTH
DAC H
+
SP9842
–
VREF Low
267
ABSOLUTE MAXIMUM RATINGS
These are stress ratings only and functional operation of the device
at these or any other above those indicated in the operation
sections of the specifications below is not implied. Exposure to
absolute maximum rating conditions for extended periods of time
may affect reliability.
CAUTION:
While all input and output pins have inter-
nalprotectionnetworks, thesepartsshould
be considered ESD (ElectroStatic Dis-
charge) sensitive devices. Permanent dam-
age may occur on unconnected devices sub-
ject to high energy electrostatic fields. Un-
used devices must be stored in conductive
foam or shunts. Personnel should be prop-
erly grounded prior to handling this device.
The protective foam should be discharged to
the destination socket before devices are re-
VDD to GND ...................................................................... -0.3V, +7V
VINX to GND ............................................................................... VDD
VREFL to GND ............................................................................. VDD
VOUTX to GND ............................................................................ VDD
Short Circuit IOUTX to GND ............................................ Continuous
Digital Input & Output Voltage to GND ....................................... VDD
Operating Temperature Range
Commercial: SP9841K/SP9842K .............................. 0°C to +70°C
Extended Industrial: SP9841B/SP9842B ................ -40°C to +85°C
Maximum Junction Temperature (TJ max) .......................... +150°C
Storage Temperature ................................................. -65° to 150°C
Lead Temperature (Soldering, 10 sec) ............................... +300°C
Package Power Dissipation ................................. (TJ max - TA)/ JA
Thermal Resistance
moved.
P-DIP .........................J..A....................................................... 57°C/W
SOIC-24 .............................................................................. 70°C/W
SPECIFICATIONS
(VDD = +5V, All VINX= +1.625V, VREFL = 0V, TA = 25° C for commercial–grade parts;
TMIN ≤ TA = TMAX for industrial–grade parts; specifications apply to
all DAC's unless noted otherwise.)
PARAMETER
MIN.
TYP.
MAX.
UNITS
CONDITIONS
SIGNAL INPUTS
Input Voltage Range
Input Resistance
SP9841
0
1.625
V
V
REFL = GND, VDD = 4.75V
D = 55H; Code Dependent
5
2.5
10
5
kΩ
kΩ
SP9842
Input Capacitance
SP9841
SP9842
VREFL Resistance
VREFL Capacitance
DIGITAL INPUTS
Logic High
Logic Low
Input Current
Input Capacitance
Input Coding
Code Dependent
19
38
0.75
190
30
60
pF
pF
kΩ
pF
0.375
2.4
All D = ABH; Code Dependent
Code Dependent
250
V
V
µA
pF
0.8
±10
8
Binary
STATIC ACCURACY
Resolution
Integral Nonlinearity
Differential Nonlinearity
Half-Scale Output Voltage
Zero-Scale Output Voltage
Output Voltage Drift
DYNAMIC PERFORMANCE
Multiplying Gain Bandwidth
Slew Rate
8
Bits
LSB
LSB
V
mV
µV/°C
±0.25
±0.2
1.625
20
±1.0
±1.0
1.650
100
Note 1
Note 1
PR = LOW, Sets D = 80H
D = 00H
PR = LOW, Sets D = 80H
1.600
4
25
6.3
MHz
VINX = 100 mV p-p+ 1.0V dc
Measured 10% to 90%
VOUTX = 100mV to +3.1V
VOUTX = +3.1V to 100mV
VINX = 0.8VDC + 1.4V p-p
D= FFH; 1kHz, fLP = 80 kHz
±1 LSB Error Band, 8H to
255H
Positive
Negative
Total Harmonic Distortion
3.0
–3.0
7.9
–8.3
0.005
V/µs
V/µs
%
Output Settling Time
0.7
µs
Crosstalk
Digital Feedthrough
Wideband Noise
60
70
6
42.5
dB
nVs
µV rms
Note 2
VREFL = +1.625V, D = 0 to FFH
VOUT = 3.25V; 400Hz to 80kHz
268
SPECIFICATIONS (continued)
(VDD = +5V, All VINX= +1.625V, VREFL = 0V, TA = 25° C for commercial–grade parts;
TMIN ≤ TA = TMAX for industrial–grade parts; specifications apply to
all DAC's unless noted otherwise.)
PARAMETER
MIN.
TYP.
MAX.
UNIT
dB
CONDITIONS
DYNAMIC PERFORMANCE
SINAD
85
6
VINX = 0.8VDC + 1.4V p-p
D= FFH; 1kHz, fLP = 80 kHz
SP9842 only; measured
Digital Crosstalk
nVs
between adjacent channels of
same pair; D = 7FH to 80H
DAC OUTPUTS
Voltage Range
Output Current
0
±10
VDD–1.5
V
mA
RL = 5kΩ; VDD = 4.75V
∆VOUT < 10mV, VINX=1.625V,
PR = LOW
±15
Capacitive Load
47,000
pF
No Oscillation
DIGITAL OUTPUT
Logic High
Logic Low
3.5
V
V
IOH = -0.4mA
IOL = 1.6mA
0.4
POWER REQUIREMENTS
Power Supply Range
Positive Supply Current
Power Dissipation
4.75
5.00
13
65
5.25
V
mA
mW
To rated specifications
PR = LOW
ENVIRONMENTAL AND MECHANICAL
Operating Temperature Range
Commercial
Industrial
Storage Temperature Range
Package
0
–40
–65
+70
+85
+150
°C
°C
°C
SP9841N
SP9841S
24–pin Plastic DIP
24–pin SOIC
SP9842S
20–pin SOIC
Note 3
Notes:
1
The op amp limits the linearity for VOUT ≤ 100mV. When VREFL is driven above ground such that the
output voltage remains above 100mV, then the linearity specifications apply to all codes. For VREFL
=
GND, VIN = 1.5V, codes 0 through 7 are not included in differential or integral linearity tests. Integral
and differential linearity are computed with respect to the best fit straight line through codes 8
through 255.
2
3
SP9841 is measured between adjacent channels, f = 100kHz; SP9842 is measured between
adjacent pairs, f = 100kHz.
For plastic DIP packaging of SP9842, please consult factory.
269
Plot 1. Integral Linearity Error versus Code.
Plot 2. Differential Non–linearity Error versus Code.
Plot 3. Integral Linearity Matching; VOUT A through VOUT D.
270
Plot 4. Integral Linearity Matching; VOUT E through VOUT H.
Plot 5. THD versus Frequency.
Plot 6. PSRR versus Frequency.
271
Plot 7. Small Signal Gain versus Frequency.
VDD = 5V
VIN = 0.05V to 1.55V
VOUT = 0.1V to 3.1V
Plot 8. Full Scale Pulse Response.
VDD = 5V
VIN = 0.05V to 1.55V
VOUT = 0.1V to 3.1V
Plot 9. Positive Full Scale Settling.
272
VDD = 5V
VIN = 0.05V to 1.55V
V
OUT = 0.1V to 3.1V
Plot 10. Negative Full Scale Settling.
Plot 11. VIN(X) Current versus Code.
Plot 12. IREFL Current Input Current versus Code.
273
Plot 13. Typical Midscale Output versus Temperature.
Plot 14. Supply Current versus Temperature.
Plot 15. Output Short Circuit Current versus VOUT(X).
274
Plot 16. Sink Current at Zero Scale.
Plot 17. Typical VOUTmax versus VDD
.
Plot 18. Typical VOUT min versus VDD versus ISINK
.
275
Plot 19. Integral Error versus Code versus VDD; VIN(X) = 0.5V.
Plot 20. Integral Error versus Code versus VDD; VIN(X) = 0.6V.
276
a)
b)
c)
d)
Plot 21. Pulse Response — a) CLOAD = 470pF, RLOAD = 10MOhm; b) CLOAD = 470pF, RLOAD = 1kOhm; c) 50Ohms in series
with CLOAD = 470pF; d) RLOAD = 1kOhm, 50Ohms in series with CLOAD = 470pF.
277
a)
b)
c)
d)
Plot 22. Pulse Response — a) CLOAD = 4,700pF; b) CLOAD = 4,700pF, RLOAD = 1kOhm; c) 30 Ohms in series with CLOAD
4,700pF; d) RLOAD = 1kOhm, 30Ohms in series with CLOAD = 4,700pF.
=
278
a)
b)
c)
d)
Plot 23. Pulse Response — a) CLOAD = 47,000pF; b) CLOAD = 47,000pF, RLOAD = 1kOhm; c) 15 Ohms in series with CLOAD
47,000pF; d) RLOAD = 1kOhm, 15 Ohms in series with CLOAD = 47,000pF.
=
279
a)
b)
c)
d)
Plot 24. Pulse Response — a) CLOAD = 0.47µF; b) CLOAD = 0.47µF, RLOAD = 1kOhm; c) 8.2 Ohms in series with CLOAD
0.47µF; d) RLOAD = 1kOhm, 8.2 Ohms in series with CLOAD = 0.47µF.
=
280
PINOUT
V
C
1
2
3
4
5
6
7
8
9
24 V
23 V
22 V
21 V
D
V
C
1
2
3
4
5
6
7
8
9
20 V
D
OUT
OUT
OUT
OUT
V
OUT
B
C
D
V
OUT
B
19 V C/D
IN
IN
V
A
B
A
V
A
18 V
DD
OUT
IN
OUT
V
V
V
A/B
17 SDI
IN
IN
DD
IN
20 SDI
V
L
16 GND
15 SDO
REF
SP9841
SP9842
V
19 GND
18 SDO
PRESETL
E/F
REFL
PRESETL
V
IN
14 CLOCK
13 LOADH
V
IN
E
17 CLOCK
16 LOADH
V
E
OUT
V
IN
F
V
F
12 V G/H
IN
OUT
V
E 10
F 11
15 V
14 V
13 V
H
G
V
OUT
G 10
11 V
H
OUT
IN
OUT
V
OUT
IN
V
OUT
G 12
H
OUT
SP9841 PINOUT
Pin 18 — SDO — Serial Data Output; active totem–
pole output.
Pin 1 — VOUTC — DAC C Voltage Output.
Pin 2 — VOUTB — DAC B Voltage Output.
Pin 3 — VOUTA — DAC A Voltage Output.
Pin 4 — VINB — DAC B Reference Voltage Input.
Pin 5 — VINA — DAC A Reference Voltage Input.
Pin 19 — GND — Ground.
Pin 20 — SDI — Serial Data Input.
Pin 21 — VDD — Positive 5V Power Supply.
Pin 22 — VIND — DAC D Reference Voltage Input.
Pin 23 — VINC — DAC C Reference Voltage Input.
Pin 24 — VOUTD — DAC D Voltage Output.
Pin 6 — VREFL — DAC Reference Voltage Input
Low, common to all DACs.
Pin 7 — PRESETL — Preset Input; active low; all
DAC registers forced to 80H.
SP9842 PINOUT
Pin 1 — VOUTC — DAC C Voltage Output.
Pin 8 — VINE — DAC E Reference Voltage Input.
Pin 9 — VINF — DAC F Reference Voltage Input.
Pin 10 — VOUTE — DAC E Voltage Output.
Pin 11 — VOUTF — DAC F Voltage Output.
Pin 12 — VOUTG — DAC G Voltage Output.
Pin 13 — VOUTH — DAC H Voltage Output.
Pin 14 — VING — DAC G Reference Voltage Input.
Pin 15 — VINH — DAC H Reference Voltage Input.
Pin 2 — VOUTB — DAC B Voltage Output.
Pin 3 — VOUTA — DAC A Voltage Output.
Pin4—VINA/B—DACAandBReferenceVoltage
Input.
Pin 5 — VREFL — DAC Reference Voltage Input
Low, common to all DACs.
Pin 6 — PRESETL — Preset Input; active low; all
DAC registers forced to 80H.
Pin 16 — LOADH — Load DAC Register Strobe;
active high input that transfers the data bits from the
SerialInputRegisterintothedecodedDACRegister.
Refer to Table 1.
Pin 7 — VINE/F — DAC E and F Reference Voltage
Input.
Pin 8 — VOUTE — DAC E Voltage Output.
Pin 9 — VOUTF — DAC F Voltage Output.
Pin 17 — CLOCK — Serial Clock Input; positive–
edge triggered.
281
Pin 10 — VOUTG — DACG Voltage Output.
Pin 11 — VOUTH — DACH Voltage Output.
FEATURES…
The SP9841 and SP9842 include eight separate op
amp–buffered eight–bit DACs. These can be used to
replace up to eight trimpots with eight low–imped-
ance programmable sources. The SP9841 uses eight
separate multiplying reference inputs, while the
SP9842 provides four pair of multiplying inputs. All
of the reference inputs, in either case, are returned to
acommonvoltagereferencelowpin.Theinherent2X
gain from the two–quadrant multiplying reference
inputs to the outputs allows the use of AC or DC
multiplying reference inputs generated from a single,
low supply voltage.
Pin 12 — VING/H — DACG and H Reference
Voltage Input.
Pin 13 — LOADH — Load DAC Register Strobe;
active high input that transfers the data bits from the
SerialInputRegisterintothedecodedDACRegister.
Refer to Table 1.
Pin 14 — CLOCK — Serial Clock Input; positive–
edge triggered.
Pin 15 — SDO — Serial Data Output; active totem–
pole output.
Each DAC has its own data register which holds its
output state. These data registers are updated from an
internalserial-to-parallelshiftregisterwhichisloaded
from a standard 3-wire serial input digital interface.
Twelve data bits make up the data word clocked into
the serial input register. This data word is decoded
such that the first 4 bits determine the address of the
DAC register to be loaded and the last 8 bits are the
data. Aserialdataoutputpinattheoppositeendofthe
serial register allows simple daisy-chaining in mul-
Pin 16 — GND — Ground.
Pin 17 — SDI — Serial Data Input.
Pin 18 — VDD — Positive 5V Power Supply.
Pin 19 — VINC/D — DACC and D Reference
Voltage Input.
Pin 20 — VOUTD — DACD Voltage Output.
LAST
FIRST
D
D
D
D
D
D
D
D
A
A
A
A
3
0
1
2
3
4
5
6
7
0
1
2
LSB
MSB LSB
MSB
DATA
ADDRESS
A
A
DAC Updated
A
A
2
3
1
0
0
0
0
0
1
1
1
1
0
0
.
0
0
0
0
0
0
0
0
1
1
.
0
0
1
1
0
0
1
1
0
0
.
No Operation
DACA
0
1
0
1
0
1
0
1
0
1
.
DACB
DACC
DACD
DACE
DACF
DACG
DACH
No Operation
.
.
.
.
.
.
1
1
1
No operation
1
D
D
D
D
D
D
D
D
DAC Output Voltage
7
6
5
4
3
2
1
0
V
= D/128 (V – V
L) + V L
REF
OUT
IN
REF
V
L
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
REF
1/128 (V – V
L) + V
L
0
IN
REF
.
.
.
REF
.
.
.
127/128 (V – V
IN
L) + V
L) + V
L
L
0
1
1
1
0
0
1
0
0
1
0
0
1
0
0
.
1
0
0
1
0
0
1
0
1
IN
REF
REF
V
(Preset Value)
129/128 (V – V
IN
REF
.
REF
.
.
.
.
1
1
254/128 (V – V
L) + V
L) + V
L
L
1
1
1
1
1
1
1
1
1
1
1
1
0
1
IN
REF
REF
REF
REF
255/128 (V – V
IN
Table 1. Serial Input Decoded Truth Table
282
tiple DAC applications without additional external
decoding logic.
VIN
VDAC
VOUT
The SP9841/9842 consume only 65 mW from a
single+5Vpowersupply. TheSP9841isavailablein
24-pin plastic DIP and SOIC packages. The SP9842
is available in a space–saving 20–pin SOIC package.
DAC 1
R
+
–
8
R
VREFL
VOUT = 2 X VDAC when VREFL = 0V
= 2(D/256) X VIN
For applications requiring code–controlled output
polarityreversalregardlessofthereferenceinputlevel
(i.e. four–quadrant multiplication), please see the
SP9840/SP9843 product data sheet.
= D/128 X VIN
V
OUT = D/128 X (VIN – VREFL) +VREFL
Figure 1. DAC and Output Amplifier Circuit
USING THE SP9841/9842
Theory of Operation
configured for a non–inverting gain of 2 using equal
value thin–film feedback and gain–setting resistors.
SignalgroundistheVREFL pin, thecommonreference
input return for the 8 DAC–op amp channels. As
showninFigure1,theDACsectioncanbethoughtof
as a potentiometer across VIN(X) to VREFL. When this
potentiometer reaches its maximum output value of
255/256timesVIN,theoutputwillbe1+(R /RGAIN)or
2 times the value of VDAC (actually up toF1B.9921875
times the input voltage, with VREFL tied to ground).
When the potentiometer is at its minimum value of 0/
256,theoutputwilltrytobe0V,againassumingVREFL
is tied to ground.
EachoftheeightchannelsoftheSP9841/SP9842can
be used for signal reconstruction, as a programmable
dc source, or as a programmable gain/attenuation
block, multiplying an ac reference input by factors of
0 to 1.992. The rugged, wideband output amplifiers
provide both current sink and source capability for dc
applications, eventhosedrivingdifficultloads.Thedc
source mode mimics the functionality of a program-
mable trimpot with the added benefit of a low imped-
ance buffered output. The amplifier's bandwidth and
high open–loop gain allow its use in programmable
gain applications where even a low distortion, high
resolutionsignal(suchasaudio)mustbegatedonand
off or gain–controlled over a –42 to +6dB range.
The true relation between the dc levels at the VIN pin,
VREFL and the output can be described as:
Each channel consists of a voltage–output DAC,
implemented using CMOS switches and thin–film
resistors in a inverted R–2R ladder configuration.
Each DAC drives the positive terminal of an op amp
VOUT = ((1 + RFB/RG) * (Data/256) * (VIN – VREFL)) + VREFL
where Data is programmable from 0 to 255, and RFB = RG.
V L= 1.5V
REF
V
L= 0V
REF
3.0
3.0
D = FF
H
2.5
2.0
2.5
2.0
D = 00
D = 80
H
H
H
1.5
1.0
1.5
1.0
D = 80
0.5
0
0.5
0
D = 00
1.0 1.5
H
0.75
1.5
V (Volts)
IN(X)
2.25
0
0.5
V
(Volts)
IN(X)
a)
b)
Figure 2. a) Single–Quadrant, and b) Two–Quadrant Operation
283
When VREFL is tied to ground, this expression
reduces to:
than VREFL are possible, and the device performs
single–quadrant multiplication, much like a buffered
programmable trimpot across a single supply. Fig-
ures2aand2bshowsingle–quadrantand2–quadrant
performance of the SP9841/SP9842. Applications
which require 4–quadrant operation with respect to
pseudoground should use the SIPEX SP9840 or
SP9843 4–quadrant multiplying DACs.
VOUT = (Data/128) *VIN
Multiplication of Input Voltages
While both the SP9841 and SP9842 are capable of
two–quadrant multiplication, this terminology is not
very precise when describing a system which runs
fromasinglepositivesupply.Traditionally,thequad-
rants have been defined with respect to 0V. A two–
quadrant multiplying DAC could produce negative
output voltages only if a negative voltage reference
were applied. A four–quadrant device could also
produce a code–controlled negative output from a
positive reference, or a code–controlled positive out-
put from a negative reference. If ground is used to
delineate the quadrants, then the SP9841/SP9842
should be considered single–quadrant multiplying
devices, as their output op amps cannot produce
voltages below ground.
The choice of voltage to use for the pseudoground is
limited by the legal voltage swing at the op amp
output. The op amp exhibits excellent linearity for
outputvoltagesbetween,conservatively,100mVand
VDD – 1.5V. The op amp BiCMOS output stage
consists of an npn follower loaded by an NMOS
common sourced to ground. This circuit exhibits
wide bandwidth and can source large currents, while
retaining the capability of driving the output to volt-
ages close to ground.
At output voltages below 25mV, feedback forces
some op amp internal nodes toward the supply rails.
The NMOS pull–down device gets driven hard and
the NMOS device enters the linear range — it begins
to function in the same manner as a 50 ohm resistor.
In reality, the wideband amplifier output stage sinks
someinternalquiescentcurrentevenwhendrivingthe
output towards ground. This sunk current drops
across the output stage NMOS transistor ON–resis-
tance and internal routing resistance to provide a
minimumoutputvoltage,belowwhichtheamplifier
cannot drive. This minimum voltage is in the 15
to 25mV range. It varies within a package with
each op amp's offset voltage and biasing varia-
tions. If an input voltage lower than this mini-
mum, such as code 0 or 1, when VREFL is ground,
Inreality,itispossibletodefineadcvoltageasasignal
ground in a single supply system. If the DAC's VREFL
pin is driven to the voltage chosen as pseudoground,
then each voltage output will exhibit 2–quadrant
behavior with respect to pseudoground; that is the
output voltage will enter the quadrant below the
pseudoground only when the reference input voltage
goes below pseudoground. This mode of operation is
useful when implementing programmable gain/at-
tenuator sections, especially when the input signal is
bipolar with respect to pseudoground, or is ac–
coupled into the VIN(X) pin. When VREFL is tied to
power supply ground, only output voltages greater
V
= 4.75V minimum; V
>100mV
OUTMAX
V
= 4.75V minimum; V
< +3.25V
DD
DD
OUTMAX
3.0
3.0
2.5
2.0
2.5
2.0
1.5
1.0
1.5
1.0
0.5
0
0.5
0
0
0.5
1.0
1.5
2.0
(Volts)
2.5
3.0
0
0.5
1.0
1.5
2.0
(Volts)
2.5
3.0
V
V
REFL
REFL
a)
b)
Figure 3. Reference Voltages a) Normal Operation; b) Maximum Linearity Near Code 1
284
is requested, feedback within the op amp circuit
will force internal nodes to the rails, while the
output will remain saturated near this minimum
value. Non–saturated monotonic behavior returns
between 25mV and 100mV at the output, but full
open loop gain and linearity are not apparent until
the output voltage is nearly 100mV above the
negative supply. Applications which require good
linearity for codes near zero should drive the V
input at least 100mV above the ground pin, as RthEFisL
insures that the output voltage will not go below
100mV for any legal input voltage. Two–quadrant
applications (programmable gain/attenuator) usually
biasVREFL upatsystempseudoground,wellabovethis
saturation region, and therefore maintain linearity
even at high attenuations (i.e. at code 1).
inputs should be driven by an amplifier capable of
handling the specified load resistance and capaci-
tance. The reference inputs are useful for both ac and
dcinputsources.However,seriesresistanceintothese
pins will degrade the linearity of the DAC. A series
resistance of 50 Ohms can cause up to 0.5LSB of
additional integral linearity degradation for codes
near full scale, due to the code–dependent input
current dropping across this error resistance. AC–
coupled applications should use the largest capacitor
value (lowest series resistance) which is practical, or,
use an external buffer to drive the inputs.
TheDACswitchesfunctioninabreak–before–make
manner in order to minimize current spikes at the
reference inputs. As previously noted, the reference
inputscanwithstanddrivingvoltagesslightlybeyond
the power supply rails without harm. The gain of 2 at
the op amps limits the choice of VIN/V combina-
tions if clipping is to be avoided at theRhEiFgLher codes.
The allowable, useful values of VIN(X) and VREFL are
limited if a legal output value is to be expected for all
inputcodes.Atmaximumgain(DACcode255)VOUT
isapproximatelyequalto2VIN(X)–VREFL.Bysolving
thisequationtwice,oncewithVOUT setto0V,andthen
again with Vout set to VDD–1.5V, the chart of Figure
3a results. This chart can be used to find the maximal
VIN(X) voltage excursions for any given voltage
driven into VREFL. The upper line plots the maximum
voltage at VIN(X) and the lower line plots the mini-
mum voltage at VIN(X) at each value of VREFL drive.
Normal operation would be for V (X) anywhere
between the two lines. For example,IaNssume a 4.75V
supplyvoltage, andthattheDACcodeissetto255. If
Output Considerations
Each DAC output amplifier can easily drive 1Kohm
loads in parallel with 15pF at its rated slew rate. The
uniqueBiCMOSamplifierdesignalsoensuresstabil-
ity into heavily capacitive loads — up to 47,000pF.
Undertheseconditions,theslewratewillbelimitedby
the instantaneous current available for charging the
capacitance—theslewratewillbeseverelydegraded,
and some damped ringing will occur. Especially
under heavy capacitive loading, a large, low imped-
ance local bypass capacitor will be required. A
0.047µF ceramic in parallel with a low–ESR 2.2 to
10µFtantalumarerecommendedforworst–caseloads.
V
is driven to 1.6V, VIN(X) below 0.8V would
reRqEuFiLre the output amplifier to swing below ground.
VIN(X) above 2.425V would require output voltages
greater than VDD – 1.5V, or 3.25V.
The amplifier outputs can withstand momentary
shorts to V or ground. Continuous short circuit
operation cDaDn result in thermally induced damage,
and should be avoided.
Figure 3b shows the limits on VIN when the mini-
mumVOUT isconstrainedtobegreaterthan100mV,
for extremely linear operation, even at DAC code
1. In this case, the lower line is 50mV above its
position in Figure 3a, except that below VREFL
=
If the input reference voltage is reduced to 0.6V, then
both the amplifier and DAC are functional at room
temperatureatsupplyvoltagesaslowas2.5V.AtVDD
= 2.7V, power dissipation is 9.3mW typical, with the
serialclockat4MHz,or7.0mWtypicalwiththeserial
clock gated off.
100mV, the minimum input voltage stays at
100mV. It should be noted that V (X) can always
be driven to or slightly beyondINthe supply rails
withoutharm.Undersuchcircumstances,theDAC
codecanalwaysbesettoprovidesufficientattenu-
ation to get an undistorted output.
Interfacing to the SP9841/SP9842
Driving the Reference Inputs
The VIN inputs exhibit a code–dependent input resis-
tance,asshowninthespecifications.Ingeneral,these
A simple serial interface, similar to that used in a
74HC594 shift–register with output latch, has been
implemented in these products. A serial clock is used
285
tPR
1
0
PRESET
tS
(FFH)
V
±1 LSB
ERROR BAND
OUT (08H)
1
SDI
0
A
A
A
1
A
D
D
D
D
D
D
D
D
0
3
2
0
7
6
5
4
3
2
1
1
CLOCK
0
1
LOAD
0
FS
VOUT
0
SERIAL DATA INPUT TIMING DETAIL (PRESET = Logic "1"; VIN(X) = 1.5V; VREFL = 0V)
AX or DX
1
0
SERIAL
DATA IN
tDS
tDH
SERIAL
DATA OUT
1
0
tPD
tCH
1
0
CLOCK
LOAD
tCL
tCLKD
tLD
tLDCK
1
0
tS
(FFH)
V
±1 LSB
ERROR BAND
OUT (08H)
CHARACTERISTICS
(Typical @ 25°C with VDD = +5V unless otherwise noted.)
PARAMETER
MIN.
TYP.
MAX.
UNIT
CONDITIONS
Input Clock Pulse Width (tCH, tCL)
50
30
20
ns
ns
ns
ns
ns
ns
ns
ns
Data Setup Time (tDS
Data Hold Time (tDH
CLK to SDO Propagation Delay (tPD
DAC Register Load Pulse Width (tLD)
Preset Pulse Width (tPR
Clock Edge to Load Time (tCKLD
)
)
)
100
50
50
30
)
)
Load Edge to Next Clock Edge(tLDCK
)
60
Figure 4. Timing.
SDI
X
CLK
LOADH
PRESETL
LOGIC OPERATION
L
L
L
H
H
No Change
Data
Shift In One Bit from SDI
Shift Out 12–clock delayed data at SDO
All DAC Registers Preset to 80H (Note 1)
Load Serial Register Data into DAC(X) Register
X
X
X
L
X
H
L
H
Note 1: "Preset" may not persist at all DACs if LOADH is high when PRESETL returns high.
Table 2. Logic Control Input Truth Table.
286
to strobe serial data into a 12–stage shift–register at
eachrisingclockedge.Thefirstfourserialbitscontain
theaddressoftheDACtobeupdated, MSBfirst. The
next 8 bits contain the binary value to be loaded into
thedesiredDAC,againMSBfirst.Afterthe12thserial
bit is clocked in, the LOADH line can be strobed to
latchthe8bitsofdataintothedataholdingregisterfor
the desired DAC. The address bits feed a decoding
network which steers the LOADH pulse to the clock
input of the desired DAC data holding register. The
output of the 12th shift–register is also buffered and
brought out as the SERIAL DATA OUT (SDO),
which can be used to cascade multiple devices, or for
data verification purposes.
DACdataregister, whichswitchestheDACtothe
new input code. The serial clock input should not
see a rising edge while the LOADH pulse is high
inordertopreventshift–registerdatafromcorrup-
tion during data register loading.
Theserialclockanddatainputpinsaredesignedtobe
compatibleasslavesunderNationalSemiconductor's
Microwire™ and MicrowirePlus™ protocols and
under Motorola's SPI™ and QSPI™ protocols. In
somemicro–controllers,theinterfaceiscompletedby
programming a bit in a general–purpose I/O port as a
level, used to strobe the LOADH line at the DACs.
This is done in a manner similar to that used for
generating a CS signal, which is necessary when
driving some other Microwire™ peripherals.
The address field is set up such that DAC A is
addressed at 0001 (binary). Address 0000(binary)
will not affect the operation of any channel, as this
combination is easily generated inadvertently at
power–up. Other no–operation addresses exist at
1001(binary) through 1111(binary). Another use for
no–operation addresses is to mask off updates of any
DAC channel in a multiple–part system with cas-
caded serial inputs and outputs. By sending a valid
address and data only to the desired channel, it is
possible to simplify the system hardware by driving
the LOADH pin at each part in parallel from a single
source. Table 1shows a register–level diagram of the
addresses, data, and the resulting operation.
Low Voltage Operation
At nominal VDD, the CMOS switches used in the
DAC obtain sufficient drive to maintain an ON-
resistance much lower than the thin–film resistors.
Thiskeepsthenon–linearvoltage–dependentportion
of their ON-resistances low, and guarantees both
excellentDAClinearityversuscode, andlow–distor-
tionmultiplicationoflarge–swingingACinputs. The
devices in the op amp also receive sufficient drive to
guarantee the specified bandwidth and output drive
current. However, all circuits within the DACs are
quite "functional" at very low values of V . By
reducing the reference voltages such that theDmD axi-
mum V is near the target of VDD-1.5V, the DACs
will proOvUidTe better than 0.5LSB typical integral per-
formance for DC output voltages between 100mV
and V -1.5V. Reducing the reference voltage actu-
ally aiDdDs the linearity of the DACs, even at nominal
VDD. This occurs because the NMOS half of the
CMOS switches are more fully utilized at reference
voltages closer to ground, thus further reducing the
ON–resistance of the switches. Reference input cur-
rents are proportional to the reference voltages and
will also decrease with the reference voltages.
A fourth control pin, PRESETL, can be used to
simultaneously preset all DAC data holding registers
to their mid–scale (80H) values. This will asynchro-
nouslyforceallDACoutputstobufferthevoltagesat
theirrespectiveinputstotheiroutputswithunitygain.
Thisfeatureisusefulatpower–up,asasimpleresistor
to the supply and capacitor to ground can insure that
all DAC outputs start at a known voltage. It can also
beusedtoimplementstand-alone(non–programmed)
applications, such as a unity gain octal cable driver.
Table 2 summarizes the operation of the four digital
control inputs.
Plot 19 shows typical DC output linearity for VIN(X)
set to 0.5V, with VDD at 2.5, and then 3.5V. Note that
at 3.5V, the linearity is actually much better than the
±0.25LSB typical performance at VIN(X) = 1.625V
and VDD = 5V. Similarly, Plot 20 shows that this
performance level persists for VDD = 4.5V and 5.5V,
withVIN(X)setto0.6V.Thepricepaidforlowvoltage
operation is in op amp gain, bandwidth and es–
pecially current sinking at the DAC output. Plots 17
The four digital control input pins have been
designed to accept TTL (0.8V to 2.0V minimum)
orfull5VCMOSinputlevels.Timinginformation
is shown in Figure 4. Serial data is fully clocked
into the shift–register after 12 clock rising edges,
subjecttothedescribedsetupandholdtimes.After
the shift–register data is valid, the LOADH line
can be pulsed high to load data into the desired
287
+5V
R
PULLUP
1.5kOhms
1/8 of SP9841
1.22V
ICL8069
45µF*
+
–
DCOUT
(*Optional Noise Reduction)
3
DCOUT = 20mV to +2.44V for DATA = 00 to FF .
H
H
At PRESET, DCOUT = +1.22V
Figure 5. Inexpensive DC Source.
through 19 show that for lower output current values
less than 1 mA, the SP9841/9842 can be used effec-
tively even with VDD in the range of 2.7 to 3.3V.
operate at 4.75V, 1.75kOhms is required; the
1.5kOhms shown will suffice even if its value is
5% high. To drive a single input, a 10kOhm
valuecouldbeused. Inordertoreducereference
and supply generated noise, an optional capaci-
tor of 1 to 100µF bypasses the reference.
Application Circuits
Figure 5 shows an inexpensive single–quadrant
DC source for generating voltages from near
ground to near 2.44V. When using a two–termi-
nal reference, the pull–up resistor should be
chosen so that the minimum input resistance of
5kOhms at each VIN(X) can be driven at the
lowestexpectedV . AtVDD =4.75V, andVREFL
=1.25V,eachinpuDtDtobedrivenneeds0.248mA,
and the regulator needs 0.1mA to stay well
regulated. Thus, to drive all eight inputs, RPULLUP
should be chosen to supply at least 2mA. To
Figure 6 shows a circuit which generates DC
voltages roughly symmetric with respect to
2.446V. Two bandgap references are stacked to
firstdriveVREFL to1.223V,andtheinputto2.446V.
The pull–up resistor value should again be scaled
forworst–caseloading—inordertodrivealleight
inputs at 4.75V, a value of 620 Ohms is required.
At fullscale, the DAC output is near 3.65V. While
typical units will source 5mA at an output voltage
+5V
2kOhm
+2.44V
1/8 of SP9841
+
1.22V
ICL8069
45µF*
DCOUT
–
+1.22V
1.22V
ICL8069
45µF*
3
DCOUT = +1.22V to +3.66V for DATA = 00 to FF .
H
H
At PRESET, DCOUT = +2.44V
(*Optional Noise Reduction)
Figure 6. Pseudo Bipolar Source Generates Voltages Above and Below 2.44V.
288
+1.8V
1/8 of SP9841
R1
10KΩ
V
I
+
–
OP–90
DCOUT
45µF*
+
–
R2
4.75KΩ
+
–
3
ICL8069
1.22V
R3
1.2KΩ
DCOUT = 20mV to +3.6V for DATA = 00 to FF .
H
H
At PRESET, DCOUT = +1.8V
(*Optional Noise Reduction)
Figure 7. Generating Programmable DC Voltages.
Figure8showsanon–programmedstandaloneappli-
cation.BytyingPRESETLtoground,allchannelsare
permanently set to unity gain. While preset, the input
impedance at each input is set to 40kOhms nominal
(20kOhms minimum), which minimizes required
input current drive. The TL431 reference is pro-
grammedbyresistorsR1 andR2 for3.3V.R3 ischosen
to provide at least 165µA for each input driven, plus
0.5mAforthereferenceattheminimumsupplyvalue
to be considered. In the Figure, the 560 Ohms shown
will drive all eight inputs. The excellent capacitive
load capability of the output amplifiers handles any
value of capacitive bypass loads without oscillation;
however, to minimize ringing at powerup, load ca-
pacitance can be chosen to be greater than 0.1µF or
less than 1,000pF.
of 3.75V while running from a 4.75V supply, this
behavior is not tested in device production. If
maximum linearity is required near the 3.66V
fullscale voltage, then output loading should be
kept under 1mA.
Figure7usesa1.8Vreferencetoprovideanoutput
voltage range from near ground to almost 3.6V.
Theexternalmicropowerreferenceusesabandgap
in abootstrapped configuration, whichguarantees
excellent supply rejection. Voltage at V1 is set by
R2
1.223
(R1 + R2)
VOUT is 1.223V +V . R is used to set the quies-
cent current throug1h th3e bandgap, I=V1/R3. The
op amp will easily drive one to all eight inputs.
+5V
560Ω
DIGIN
1/8 of SP9841
+
32KΩ
+
–
AC04
DCOUT
–
2.5V
100KΩ
TL431
PRESET
DIGIN DCOUT
0
1
3.3V
0V
Eight independent 3.3V @ 10mA supplies with
logic–level controlled shutdown.
Figure 8. Generating Up to Eight (8) 3.3V @ 10mA DC Supplies with Logic–Level Controlled Shutdown (Non–Programmed).
289
LM317
Out
Adjust
In
+12V
VOUT
R1
499Ohms
10µF
10kOhms
V
DD
R2
1kOhms
1/8 of SP9841
R4
ICL8069
1.22V
681Ohms
+
–
V
A
R3
511Ohms
3
VOUT = 4.5V TO 5.5V at 1Amp for DATA = 00 to FF .
H
H
At PRESET, VOUT = 5.0V
Figure 9. Programmable 1Amp Power Source.
around 150mV. Codes above 17 will then provide
equally spaced output voltage increments.
Figure9showsaDACchannelcontrollingtheoutput
voltage of an LM317 voltage regulator. By program-
ming the code, the DAC changes its own supply
voltage. Thiscircuitcanbemodifiedforwideroutput
voltagerangesbyreducingthevalueofR4. However,
thecircuitasshownrequirestheDACtosink1mAto
the negative rail at code 0 at its lowest V , at which
pointtheoutputvoltageis62mV.Thus,prDoDgramming
codes0through5willdolittletoinfluencetheoutput.
If R4 is replaced with a short circuit, useful operation
would be between 3.9V and 6.15V output; however,
theDACoutputmustthensink2.5mAatVDD =3.9V,
which results in a minimum DAC output voltage of
Figure 10 shows how the gain of an external non–
inverting op amp can be programmed. RF and RG are
chosen for nominal gain. RTRIMRANGE is then ratioed to
RF to provide the desired range of gain trim. A wide
gain grange is achievable — for example, with RF =
11kOhms,R =1kOhmsandR
=2.74kOhms,
gain would Gbe programmed TliRnIMeRaArNlyGEfrom 8 to just
under 16.
The OP–491 shown in Figure 10 is capable for
+5V
2.2µF
1/4 of OP–491
+
–
SIG OUT
+5V
VREFL
1VP-P
R
GAIN
2.5kOhms
VDD
R
F
10kOhms
1/8 of SP9841
R
TRIMRANGE
20kOhms
R
IBIAS
+
–
50kOhms
R
R
F
D
R
F
VREFL
, D = 0 to 255
AV
=1+
+ 1−
G
128
R
TRIMRANGE
= Up to V /2
DD
(2.5V nominal for
rail–to–rail output
at SIG OUT)
3
Set RTRIMRANGE for desired gain-trim range.
For RTRIMRANGE = 20kOhms:
Code 0, AV = +5.5
Code 128, AV = +5.0
Code 255, AV = +4.51
Figure 10. Adjustable Gain of External Non–Inverting Opamp Circuit; VOUT = Rail–to–rail.
290
rail–to–rail output swing. In order to obtain this
performance, VREFL must be externally driven to
V /2, perhapsbyuseofthecircuitofFigure11.
while an AC–coupled input is shown, this cir-
cuit is just as useful for DC–coupled inputs
which are generated with respect to the V
pseudoground voltage. RIBIAS is used for RtEhFeL
AC–coupled circuit for opamp bias current re-
turn when the DAC is programmed to code 0, as
no current flows into V (X) at code 0.
ADtDV
near 2.5V and VDD = 4.75V, the typical
positRivEFeLoutput headroom at the DAC is limited
to1.15Vabove2.5V, sothatthiscircuitisuseful
for rail–to–rail outputs for gains higher than
4.35 (i.e. 1.15VPP maximum input). Note that
Figure 11 shows a minimIN al parts count method
VINH
1/8 of SP9841
+
–
VOUT
H
At PRESET, VOUT = 1.3V
(not well–regulated)
3
Load code 112 for 1.4VOUT = VREFL
96 for 1.6VOUT = VREFL
VINB
1/8 of SP9841
70 for 2.2VOUT = VREFL
+
–
VOUT
B
3
VINA
1/8 of SP9841
+
–
VOUT
A
VREFL
3
ICL8069
R
301Ohm
ISRC
+
–
2kOhm
45µF*
1.22V
*(Optional Noise Reduction)
+5V
The usable range for the bootstrapped VREFL circuit is 1.4 to 2.4VOUT at VDD = 5V, RISRC = 2kOhms.
To increase the upper usable limit, decrease value of RISRC
.
Figure 11. Programmable, Bootstrapped, 1.4V to 2.2V VREFL Drive.
291
of generating a programmable pseudoground
voltageattheVREFL terminal. Apseudogroundis
veryusefulifanychannelsaretobeusedinAC–
multiplying applications. In such applications,
the pseudoground will set the DC offset of the
output signal. The voltage output of this circuit
as the code is decreased is non–linear because
the DAC bootstraps the increased output volt-
age by a larger fraction at each code. It is really
meant to be programmed only over a range of
codes between 104 and perhaps 60. It does
exhibit a fairly well–defined output, even if
non–intentional codes are programmed. For
codes above 112, the output stage resembles a
50 Ohm resistor to ground, and the VREFL output
willbenear1.3V, dependingupontheloadingat
the other VIN(X) inputs. For codes below 60, the
output voltage will continue to rise until limited
by available current through RISRC. Note that
RISRC supplies the actual current into VREFL, and
must be chosen in order to supply enough cur-
rent for all channels, especially if any of the
other eight inputs are to be grounded. A plot of
V
versus code is shown with the Figure, for
alRlEoFLther inputs either grounded or tied to the
supply.
Figure 12 shows a programmable gain/attenua-
tor section using the programmable VREFL
drive. The VREFL of each DAC is actually
internally connected. When the optional 45µF
noise reduction capacitor is included, this cir-
cuit is capable of 86dB of SNR and 74 to 84dB
of SINAD at 1kHz, depending on the pro-
VINB
1/8 of SP9841
2.2µF
±0.75V
+
–
VOUT
B
A
VREFL
VINA
1/8 of SP9841
+
–
VOUT
VREFL
3
R
ICL8069
ISRC
2kOhm
301Ω
+
–
45µF*
+5V
1.22V
*(Optional Noise Reduction)
Load DACA with code 90; sets VREFL =1.7V.
Then, load DACB with desired gain:
code 255 = +6dB
code 128 = 0dB
code 64 = –6dB
code 1 = –42dB
code 0 = –70dB
Figure 12. AC–Coupled, Programmable Gain/Attenuator with Bootstrapped Programmable Output DC Offset (VREFL Drive).
292
grammed gain. Please refer to the THD versus
Frequency plot, which was generated by termi-
nating a 600 Ohm source with 150 Ohms to
ground, then into this circuit. For the best gain
linearity versus code, use the largest (lowest
series impedance) coupling capacitor available,
or externally buffer the input.
channel can be set up with a programmable DC
offsetadjustmentwithitsoutputsummedthrough
a large resistor into the OP–491 inverting termi-
nal.NotethatwhenRTRIMRANGEissetupfor
only unity gain change range as in Figure 12,
only –0.5 times the DAC output offset will
appear at SIG OUT.
Figure 13 shows an external op amp with an
inverting programmable gain. In this circuit the
maximumoutputswingattheDACoccursatthe
maximum circuit gain. Thus, the headroom re-
striction at the DAC output applies at the maxi-
mum gain, which, for rail–to–rail outputs (V
= 2.5V or VDD/2) should be greater than 4.3.RBEFyL
making the programmable gain range large, this
circuit can be used to provide rail–to–rail out-
puts even at the lower gains. This circuit has
been ratioed to provide exact integer gain incre-
ments for every increase in 25 codes, over the
range of –1 to –11. This large range of gain
comes at a slight cost — the output offset of the
DAC amplifier will be gained up by –5.12 times
at SIG OUT. If this is a problem, a second DAC
Another application for the circuits of both
Figure 10 and 13 could be to force precise gains
from circuits made from imprecise resistors. By
restricting the programmable gain range to ±2%
(by setting R
to be 100 times R ), the
resistors coulTdRIbMeRA1N%GE values and the proFgram-
mable gain resolution would increase to better
than 12–bits (0.0156%). In this case, only 1% of
the DAC output offset voltage would appear at
SIG OUT.
Figure 14 shows a window comparator and two
channels of programmable-gain input. While
the input signal is shown as AC–coupled, DC
signals of up to rail–to–rail amplitude could be
measured by setting the attenuation at the signal
+5V
VREFL
1/4 of OP–491
2.2µF
+
–
SIG OUT
1.25VP-P
R
GAIN
+5V
7.68kOhms
VDD
1/8 of SP9841
R
F
7.68kOhms
R
TRIMRANGE
1.5kOhms
+
–
R
R
F
D
RF
VREFL
= Up to V /2
AV
= −
−
, D = 0 to 255
G
128
RTRIMRANGE
DD
3
Set RTRIMRANGE for desired gain-trim range.
For RTRIMRANGE = 1.5kOhms:
Code 0, AV = -1
Code 25, AV = -2
Code 75, AV = -4
Code 175, AV = -8
Code 225, AV = -10
Code 250, AV = -11
Gain resolution = 4%
Figure 13. Adjustable Gain of External Inverting Opamp Circuit, VOUT = Rail–to–Rail.
293
Figure 14. Two–Channel Multiplexed Window Comparator with Programmable Gain and Limits.
294
input DACs to the proper code. The LM339
does not really drive the LED to full illumina-
tion, due to limited output current, but a pull–up
resistor alone will yield a functional TTL error
signal. External op amps could use the VREFL
voltageaspseudoground.Theoutputsofthetwo
signal DACs must be isolated with resistors if
the two signals are to be multiplexed. This will
reduce the signal gain to 255/256 maximum,
due to the resistive divider created at the com-
parator input. If only a single channel was to be
window–compared, then the maximum gain to
the comparator would be the usual 255/128.
for breadboarding circuits, such as in Figures 1
through 14. If the reference voltage is adjusted
down to 0.5V, the DAC and the board should
function with VDD as low as 2.5V.
Driving Capacitive Loads
Unlike many other products, the SP9841/9842
will not oscillate under purely capacitive load-
ing. However, fullscale step outputs will show
overshoot and ringing of up to 40% at worst–
case purely capacitive loading (between 1,000
and 10,000pF). Figures 17 through 20 show
near fullscale steps under capacitive loads of
between 470pF and 0.47µF. For capacitance up
to 10,000pF, the addition of a resistive load to
ground at the op amp output will decrease set-
tling times without adversely affecting the posi-
tive–going slew rate. For higher capacitances,
this settling time enhancement comes at the
expense of positive slew rate, as not all instan-
taneouscurrentcanbeusedtochargethecapaci-
tor. For all values of capacitive load, settling
time can be dramatically reduced by adding a
small resistor in series with the DAC outputs.
Such series resistors will degrade the current
sinking ability at the DAC outputs for voltages
near ground; while the DACs typically sink
2mA at V =5V at VOUT = 110mV, the addition
of a 50OhDmD resistor would require 210mV after
the resistor to sink 2mA. Large capacitances
require lower values of series resistance in order
to obtain critical damping.
Figure 15 shows the schematic of an evaluation
board, which can be used with an IBM–compat-
ible (XT or AT) computer and the simple
QuickBasic routine of Figure 16 to load each
DAC channel with its desired code. A straight–
through 25-pin cable can be used, or the board
can be plugged directly into the back of the PC.
Data is first latched into each 'HC165 parallel–
to–serial converter. Then a small state machine
is initiated by strobing INI. It clocks the latched
data into the serial data input and strobes the
LOADH input at the DAC. A pair of banana
jacks is used for applying V from an external
supply. A trimpot–adjustablDeDvoltage reference
istiedtoalleightDACinputs. Ontheevaluation
board, jumpers will allow this reference to drive
any VIN(X) input or the VREFL pin. The other
three op amps in the quad OP–491 are available
295
Figure 15. Evaluation Board — Loads SP9841/9842 from IBM PC Parallel Port
296
SP9841.BAS
'This program accepts an address (1 through 8) and data (0 through 255)
'in decimal and sends them to the DAC. Addresses 1 through 8 will
'correspond to converters A through H respectively. The appropriate
'output will be: Vout-(data/128)*VREF volts.
'We found that for our IBM PC/AT the LPT1 port address was 378H (Data
'Register 378H and control register 37AH) while for our IBM PC/XT the
'LPT1 port address was 3BCH (Data Register #BCH and control register 3BEH).
DIM lsb AS INTEGER
DIM msb AS INTEGER
DIM datareg AS INTEGER
DIM contrlreg AS INTEGER
DIM n AS INTEGER
CLS
DO
INPUT "Enter type of PC, AT or XT: ", type$
IN UCASE$(type$) = "AT" OR UCASE$(type$) = "XT" THEN
EXIT DO
ELSE PRINT "Please enter either AT or XT.": PRINT
END IF
LOOP
IF UCASE$(type$) = "AT" THEN datareg = &H378: cntrlreg = &H37A
IF UCASE$(type$) = "XT" THEN datareg = &H3BC: cntrlreg = &H3BE
CLS
n=0
DO
WHILE n=0
DO
test$ =""
INPUT "Enter Address (1 through 8): ", lsb
IF lsb < 1 or lsb> 8 THEN test$ = "false"
IF test$ = "false" THEN PRINT "Please enter a valid address.": PRINT
LOOP UNTIL test$ <> "false"
DO
test$ = ""
PRINT
INPUT
"Enter Data (0 through 255 in decimal): ", msb
IF msb < 0 or msb > 255 THEN test$ = "false"
IF test$ = "false" THEN PRINT "Please enter valid data.": PRINT
LOOP UNTIL test$ <> "false"
OUT cntrlreg, $H3
OUT datareg, &H0 + msb
OUT cntrlreg, &H2
'set both latch clocks low
'send most significant byte to port
'clock U1
OUT datareg, &H0 + lsb
OUT cntrlreg, &H0
OUT cntrlreg, &H4
'send least significant byte to port
'clock U2
'enable U7, set U1 & U2 to serial out mode
PRINT :
PRINT "Strike spacebar to enter new data or Q to quit."
DO
X$ = INKEY$
IF UCASE$(X$) = "Q" THEN n=1
LOOP UNTIL X$ = " " OR UCASE$(X$) = "Q"
LOOP
END
Figure 16. Microsoft qbasic Program to Load Evaluation Board with Desired Codes.
297
ORDERING INFORMATION
Model
Reference Inputs
Temperature Range
Package
SP9841KN ................................... Eight, independent ................................................... 0° to + 70°C .............................. 24–pin, 0.3" Plastic DIP
SP9841KS ................................... Eight, independent ................................................... 0° to + 70°C ........................................ 24–pin, 0.3" SOIC
SP9842KS ................................... Four pair ................................................................... 0° to + 70°C ........................................ 20–pin, 0.3" SOIC
SP9841BN ................................... Eight, independent ............................................... –40° to + 85°C .............................. 24–pin Plastic, 0.3" DIP
SP9841BS ................................... Eight, independent ............................................... –40° to + 85°C ........................................ 24–pin, 0.3" SOIC
SP9842BS ................................... Four pair ............................................................... –40° to + 85°C ........................................ 20–pin, 0.3" SOIC
298
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