SLD-1000 [SIRENZA]
4 Watt Discrete LDMOS FET-Bare Die; 4瓦离散LDMOS FET -裸模
| 型号： | SLD-1000 |
| 厂家： | 
SIRENZA MICRODEVICES |
| 描述： | 4 Watt Discrete LDMOS FET-Bare Die |
| 文件： | 总5页 (文件大小：332K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SLD-1000
Product Description
4 Watt Discrete LDMOS FET -Bare Die
Sirenza Microdevices’ SLD-1000 is a robust 4 Watt high performance
LDMOS transistor die, designed for operation from 10 to 2700MHz. It
is an excellent solution for applications requiring high linearity and effi-
ciency. The SLD-1000 is typically used as a driver or output stage for
power amplifier, or transmitter applications. These robust power tran-
sistors are fabricated using Sirenza’s high performance XEMOS IITM
process.
Functional Schematic Diagram
Product Features
• 4 Watt Output P1dB
ESD
• Single Polarity Operation
• 19dB Gain at 900 MHz
Protection
• XeMOS IITM LDMOS
• Integrated ESD Protection, Class 1B
• Aluminum Topside Metallization
• Gold Backside Metallization
Gate
Applications
Manifold
• Base Station PA Driver
• Repeaters
Drain
Manifold
• Military Communications
• RFID
Source - Backside Contact
• GSM, CDMA, Edge, WDCDMA
RF Specifications
Symbol
Frequency
Gain
Parameter
Unit
MHz
dB
Min
10
-
-
-
-
-
Typ
-
Max
2700
Frequency of Operation
3.5 Watts CW, 900 MHz
Drain Efficiency at 3.5 Watts CW, 900 MHz
19
43
-30
4
-
-
-
-
-
Efficiency
%
3
rd Order IMD at 3.5 Watts PEP (Two Tone) 900 MHz
dBc
Watts
ºC/W
Linearity
1dB Compression (P1dB) 900 MHz
RTH
Thermal Resistance (Junction-to-Case, mounted in package)
11
Test Conditions: Mounted in ceramic package and tested in Sirenza Evaluation Board VDS = 28.0V, IDQ = 30mA, TMounting Surface = 25ºC
T
DC Specifications
Symbol
gm
Parameter
Forward Transconductance @ 30mA IDS
IDS=3mA
1mA IDS Current
Input Capacitance (Gate to Source) VGS=0V, VDS=28V
Reverse Capacitance (Gate to Drain) VGS=0V, VDS=28V
Output Capacitance (Drain to Source) VGS=0V, VDS=28V
Drain to Source Resistance, VGS=10V VDS=250mV
Unit
mA / V
Volts
Volts
pF
Min
Typical
150
4.2
70
5.2
0.2
3.2
3.0
Max
VGS Threshold
VDS Breakdown
Ciss
3.0
65
5.0
Crss
Coss
RDSon
pF
pF
Ω
3.5
The information provided herein is believed to be reliable at press time. Sirenza Microdevices assumes no responsibility for inaccuracies or omissions. Sirenza Microdevices assumes no responsibility for the use of this information, and all such
information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any thrid party. Sirenza Microdevices
3do0e3s nSot.aTutehocrhizneoorlowgaryraCntoanuyrtS,irenza Microdevices product for use in life-support devices and/or syPstehmosn. eC:op(y8ri0gh0t)20S0M5 SI-irMenMzaIMCicrodevices, Inc. All worldwide rights reserved.
http://www.sirenza.com
EDS-104291 Rev C
Broomfield, CO 80021
1
SLD-1000 10-2700 MHz 4 Watt LDMOS FET - Bare Die
Quality Specifications
Parameter
Description
Human Body Model
200oC Channel
Unit
Volts
Hours
Typical
750
1.2 X 106
ESD Rating
MTTF
Contact Description
Pad #
Function
Gate
Description
1
2
Aluminum metallized manifold MOSFET Gate with ESD protection structure. (Topside contact)
Aluminum metallized manifold MOSFET Drain. (Topside contact)
Drain
Chrome Gold metallized MOSFET Source contact. Appropriate electrical, mechanical and thermal connection required for
proper operation. (Backside contact)
3
Source
Pad Diagram
ESD
Note 1:
Protection
Gate voltage must be applied to to the device
concurrently or after application of drain voltage to
prevent potentially destructive oscillations. Bias voltages should
never be applied to the transistor unless it is properly termi-
nated on both input and output.
Note 2:
The required VGS corresponding to a specific IDQ will vary from
device to device due to the normal die-to-die variation in thresh-
old voltage with LDMOS transistors.
Pad #3
Backside Source = Ground
Note 3:
Pad #1
Gate
The threshold voltage (VGSTH) of LDMOS transistors varies with
device temperature. External temperature compensation may
be required. See Sirenza application notes AN-067 LDMOS
Bias Temperature
Manifold
Pad #2
Drain
Manifold
Compensation.
Absolute Maximum Ratings
Parameters
Value
35
20
Unit
Volts
Volts
dBm
Drain Voltage (VDS
)
Gate Voltage (VGS), VDS =0
RF Input Power
+30
Load Impedance for Continuous Operation
10:1
VSWR
Without Damage
Output Device Channel Temperature
Storage Temperature Range
+200
-40 to +150
ºC
ºC
Operation of this device beyond any one of these limits may cause
permanent damage. For reliable continuous operation see typical
setup values specified in the table on page one.
Caution: ESD Sensitive
Appropriate precaution in handling, packaging
and testing devices must be observed.
303 S. Technology Court
Broomfield, CO 80021
Phone: (800) SMI-MMIC
http://www.sirenza.com
EDS-104291 Rev C
2
SLD-1000 10-2700 MHz 4 Watt LDMOS FET - Bare Die
De-embedding Information
Impedance Data
Description
Gate
2
Drain
3
0.040
0.006
0.005
0.002
Frequency (MHz)
Zsource
Zload
Number of Bond Wires
Length of Bond Wires
Height of Bond Wires
Pitch of Bond Wires
Bond Wire Diameter
880
960
1840
1960
2140
2.7 + j 13.1
1.9 + j 10.6
1.7 + j 3.4
1.3 + j 2.0
1.2 + j 0.7
12.5 + j 22.5
11.8 + j 18.3
1.0 + j 4.7
1.2 + j 5.7
1.7 + j 6.4
0.040
0.006
0.005
0.002
All Dimensions in Inches.
Wirebond Heights Referenced to Top Surface of Die.
Impedances Referenced to Wirebond/PCB Interface.
Device
under test
Output
Input
Matching
Network
Matching
Network
Z
Z
load
source
when operating at 28V, Idq=30mA, Pout=3.5 W PEP.
Zsource and Zload are the optimal impedances presented to the SLD-1000
303 S. Technology Court
Broomfield, CO 80021
Phone: (800) SMI-MMIC
http://www.sirenza.com
EDS-104291 Rev C
3
SLD-1000 10-2700 MHz 4 Watt LDMOS FET - Bare Die
Typical Performance Curves for packaged die tested in SLD-1083CZ 900 MHz Application Circuit
CW Gain, Efficiency, IRL vs Frequency
Vdd=28V, Idq=50mA, Pout=3W
CW Gain, Efficiency vs Pout
Vdd=28V, Idq=50mA, Freq=915 MHz
24
23
22
21
20
19
18
60
50
40
30
20
10
0
50
45
40
35
30
25
20
15
10
5
0
-4
Gain
Efficiency
IRL
-8
-12
-16
-20
Gain
Efficiency
0
900
0
1
2
3
4
5
905
910
915
920
925
Pout (W)
Frequency (MHz)
2 Tone Gain, Efficiency, Linearity vs Pout
Vdd=28V, Idq=50mA, Freq=915 MHz, Delta F=1 MHz
2 Tone Gain, Efficiency, Linearity and IRL vs Frequency
Vdd=28V, Idq=50mA, Pout=3W PEP, Delta F=1 MHz
50
-20
-25
-30
-35
-40
-45
-50
-55
-60
-65
-70
60
0
Gain
IM3
IM7
Efficiency
IM5
IRL
45
40
35
30
25
20
15
10
5
50
40
30
20
10
0
-10
-20
-30
-40
-50
-60
Gain
IM3
Efficiency
IM5
IM7
0
0
1
2
3
4
5
6
900
905
910
915
920
925
Pout (W PEP)
Frequency (MHz)
303 S. Technology Court
Broomfield, CO 80021
Phone: (800) SMI-MMIC
4
http://www.sirenza.com
EDS-104291 Rev C
SLD-1000 10-2700 MHz 4 Watt LDMOS FET - Bare Die
Die Map
Dimensions Inches [mm]
0.030 [0.76]
GATE
DRAIN
SOURCE - BACKSIDE CONTACT - NOT SHOWN
DIE THICKNESS - 0.004 [0.10]
AuSi, AuSn, or AuGe eutectic die attach is recommended. AlSi bond wires are recommended.
Part Number Ordering Information
Part Number
SLD-1000
Gel Pack
100 pcs. per pack
Die are screened prior to dicing to DC parameters and
are shipped per Sirenza application note AN-039
Visual Criteria of Unpackaged Die.
303 S. Technology Court
Broomfield, CO 80021
Phone: (800) SMI-MMIC
5
http://www.sirenza.com
EDS-104291 Rev C
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