CX74063-36_技术文档

DATA SHEET

CX74063-3x: RF Transceiver with Power Ramping Controller

and Integrated Crystal Oscillator with 13 MHz Output for

Multi-Band GSM, GPRS, and EDGE Applications

APPLICATIONS

DESCRIPTION

The CX74063-3x transceiver (including –34, -35, and –36

package options) is a highly integrated device for multi-band

Global System for Mobile Communications™ (GSM™) or

General Packet Radio Service (GPRS) applications. The device

requires a minimal number of external components to

complete a GSM radio subsystem. The CX74063-3x supports

GSM850, EGSM900, DCS1800, and PCS1900 applications. The

receiver also supports downlink Enhanced Data-Rate GSM

Evolution (EDGE).

• GSM850, EGSM900, DCS1800, and PCS1900 handsets

• GPRS handsets and modules

• EDGE downlink support

FEATURES

• Direct down-conversion receiver eliminates the external

image reject/IF filters

• Three separate LNAs with single-ended inputs

• RF gain range: GSM = 20 dB, DCS = 22 dB,

PCS = 20 dB. Baseband gain range = 100 dB

• Gain selectable in 2 dB steps

• Integrated receive baseband filters with tunable bandwidth

• Integrated DC offset correction sequencer

• Reduced filtering requirements with translational loop

transmit architecture

The receive path implements a direct down-conversion

architecture that eliminates the need for Intermediate

Frequency (IF) components. The CX74063-3x receiver consists

of three integrated Low Noise Amplifiers (LNAs), a quadrature

demodulator, tunable receiver baseband filters, and a DC-

offset correction sequencer.

In the transmit path, the device consists of an In-phase and

Quadrature (I/Q) modulator within a frequency translation loop

designed to perform frequency up-conversion with high output

spectral purity. This loop also contains a phase-frequency

detector, charge pump, mixer, programmable dividers, and

high power transmit Voltage Controlled Oscillators (VCOs) with

no external tank required. With the integrated gain controller

(and an integrator ), the device realizes the Power Amplifier

Control (PAC) functionality when combined with a coupler, a

Radio Frequency (RF) detector and a Power Amplifier (PA).

• Integrated transmit VCOs

• Wide RF range for quad band operation

• Integrated PAC loop

• Single integrated, fully programmable fractional-N

synthesizer suitable for multi-slot GPRS operation

• Fully integrated wideband Ultra High Frequency (UHF) VCO

• Integrated crystal oscillator

• Separate enable lines for power management transmit,

receive, and synthesizer modes

The CX74063-3x also features an integrated, fully

programmable, sigma-delta fractional-N synthesizer suitable

for GPRS multi-slot operation. Except for the loop filter, the

frequency synthesizer function, including a wideband VCO, is

completely on-chip. The reference frequency for the

synthesizer is supplied by the integrated crystal oscillator

circuitry.

• Supply voltage down to 2.6 V

• Band select and front-end enable states may be exercised

on output pins to control external circuitry.

• Low external component count

• Optional bypass of baseband filtering for use with high

dynamic range Analog to Digital Converters (ADCs) for

current savings

• Interfaces to low dynamic range ADC

• Meets AM suppression requirements without baseband

interaction.

• 56-pin RFLGA 8x8 mm package (low temperature option,

CX74063-34; high temperature option, CX74063-35 and

CX74063-36)

The 56-pin 8x8 RF Land Grid Array (RFLGA™) device package

and pin configuration are shown in Figure 1. A functional block

diagram is shown in Figure 2. Signal pin assignments,

functional pin descriptions, and equivalent circuitry are

provided in Table 1.

• Low power standby mode

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Data Sheet I CX74063-34/-35/-36

T

0

T

V

VCC4

RXI

RX

VCC3

VCCUHF

U

43

42

41

40

39

38

37

36

35

VDDBB

LE

RXENA

1

2

3

4

5

6

7

8

56

5

54

53

52

51

50

49

48

47

46

45

4

TXENA

PCO

CLK

DATA

VCXO_EN

PDETVCC

VCC1

XTALTUNE

SXENA

VCCFN_CP

UHFCPO

GNDFN

XTAL

TXCPO

TXINP

LNA900IN

GNDLNA900

LNA1800IN

PDET

9

34

33

10

11

VCCF

32

31

30

29

VCCD

12

13

14

15

GNDD

LNA1900IN

NC

XTALBUF

LPFADJ

16

17

18

19

20

21

2

23

24

25

26

27

28

NC

TXI

VCC2

TXQ

T

TXIFN

C

PAVA

B

C1328

Figure 1. CX74063-3x Pinout – 56-Pin RFLGA (8 x 8 mm) (Top View)

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Data Sheet I CX74063-34/-35/-36

TXQN

TXQP

TXIN

TXIP

P

PA GAIN CONTROLLER

LE

DATA

CLK

PCO

+

–

DET

VCC

OFFSET

GEN

GSM850/EGSM900

Tx PATH

TxIFP

TxIFN

TX900

TXINP

+

D2

TXVCOTUNE

CP

PFD

TXCPO

TX1800/TX1900

FILTN

FILTP

D1

DCS1800/PCS1900

Sx

VCXO_EN

XTAL

Frac-N

LO

UHFTUNE

UHFCPO

XTALTUNE

XTALBUF

Rx PATH

GSM

LNA

VGA1

VGA2

RXIP

RXIN

LNA900IN

CAPIP

CAPIN

DCOC

VGA2

DCOC

Indicates

Off-chip

DCS

LNA

VGA1

RXQP

RXQN

LNA1800IN

LNA1900IN

C900

CAPQP

CAPQN

DCOC

PCS

LNA

Figure 2. CX74063-3x Transceiver Block Diagram

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Data Sheet I CX74063-34/-35/-36

Table 1. CX74063-3x Signal Descriptions (1 of 5)

Pin #

Name

Description

Equivalent Circuit

1

RXENA

Receiver enable input

2

3

TXENA

PCO

Transmitter enable input

Bi-directional band select

4

5

VCXO_EN

PDETVCC

VCXO enable pin

Bias for the RF Detector

Vout

Vref

6

7

VCC1

LNA and TX charge pump supply

VCC1

TXCPO

Translational loop charge pump output

8

9

TXINP

Translational loop feedback input

LNA900IN

Low band LNA input for GSM850, EGSM900

4

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Data Sheet I CX74063-34/-35/-36

Equivalent Circuit

Table 1. CX74063-3x Signal Descriptions (2 of 5)

Pin #

Name

Description

10

GNDLNA900

Low band LNA emitter ground

11

12

LNA1800IN

PDET

DCS LNA input

Feedback Input to power control loop

13

LNA1900IN

PCS LNA input

14

15

16

NC

No connect

NC

No connect

PAVAPC

PA control output

Vout

17

BBVAPC

PA control Baseband input

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Data Sheet I CX74063-34/-35/-36

Table 1. CX74063-3x Signal Descriptions (3 of 5)

Pin #

Name

Description

Equivalent Circuit

18

TXIP

TXIN

TXQP

TX I baseband input positive

19

20

TX I baseband input negative

TX Q baseband input positive

21

22

TXQN

TXFP

TX Q baseband input negative

TX IF filter output positive

23

TXFN

TX IF filter output negative

24

25

26

27

28

VCC2

RX mixer and TX loop supply

Capacitor filter I positive

Capacitor filter I negative

Capacitor filter Q positive

Capacitor filter Q negative

VCC2

CAPIP

CAPIN

CAPQP

CAPQN

29

LPFADJ

LPF frequency setting resistor

30

XTALBUF

Crystal oscillator buffer output

31

GNDD

Synthesizer digital ground

Synthesizer digital supply

32

33

VCCD

VCCF

VCCD

VCCF

Synthesizer analog supply and crystal oscillator

supply

34

XTAL

Crystal input

6

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Data Sheet I CX74063-34/-35/-36

Equivalent Circuit

Table 1. CX74063-3x Signal Descriptions (4 of 5)

Pin #

Name

Description

35

GNDFN

Synthesizer analog ground

36

UHFCPO

Synthesizer charge pump output

37

38

VCCFN_CP

SXENA

Synthesizer charge pump supply

Synthesizer enable input

VCCFN_CP

39

XTALTUNE

Crystal oscillator varactor control

40

41

DATA

CLK

Serial bus data input

Serial bus clock input

42

LE

Serial bus latch enable input

43

44

VDDBB

Digital CMOS supply

VDDBB

UHFBYP

Bypass capacitor for UHF VCO

45

UHFTUNE

UHF VCO control input

46

47

VCCUHF

VCC3

UHF VCO supply

LO chain supply

VCCUHF

VCC3

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Data Sheet I CX74063-34/-35/-36

Table 1. CX74063-3x Signal Descriptions (5 of 5)

Pin #

Name

Description

Equivalent Circuit

48

RXQN

RXQP

Receiver output Q negative

49

Receiver output Q positive

50

51

RXIN

RXIP

VCC4

Receiver output I negative

Receiver output I positive

52

53

54

Baseband supply

VCC4

VCCTXVCO

TX900

Transmit VCO supply

Low band transmit VCO

VCCTXVCO

55

56

TX1800/TX1900

TXVCOTUNE

DCS and PCS transmit VCO output

Transmit VCO control input

A 3-wire serial interface controls the transceiver and

synthesizer. The receiver gain control, as well as the division

ratios and charge pump currents in the synthesizer and

transmitter, can be programmed using 24-bit words. These

24-bit words are programmed using the 3-wire input signals

CLK, DATA, and LE. To ensure that the data stays latched in

power down mode, pin 43 (VDDBB) must be continuously

supplied with voltage. This pin is provided for the digital

sections to allow power supply operation compatible with

modern digital baseband devices.

Technical Description

The CX74063-3x transceiver contains the following sections,

as shown in Figure 2.

• Receive section. Includes three integrated LNAs, a

quadrature demodulator section that performs direct down

conversion, baseband amplifier circuitry with I/Q outputs,

and three stages of DC offset correction. The receiver can

be calibrated to optimize IP2 performance.

• Synthesizer section. Includes an integrated on-chip VCO

locked by a fractional-N synthesizer loop, and a crystal

oscillator to supply the reference frequency.

• Transmit section. The TX path is a translational loop

architecture consisting of an I/Q modulator, integrated high

power VCOs, offset mixer, programmable divider, PFD, and

charge pump. The device also provides integrated gain

controller for the PAC loop, plus the bias generator for an

external diode detector.

The TXENA, RXENA, and SXENA signals separately enable the

CX74063-3x transmitter, receiver, and synthesizer sections.

TXENA and RXENA should be held low during programming.

SXENA should be held high during the programming of the R3

IP2 Calibration Register. (These timing signals are detailed in

Figures 9, 10, and 11.)

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Data Sheet I CX74063-34/-35/-36

DC Offset Correction

Receive Section

Three DC offset correction (DCOC) loops ensure that DC

offsets, generated in the CX74063-3x, do not overload the

baseband chain at any point. After compensation, the

correction voltages are held on capacitors for the duration of

the receive slot(s). Internally, on-chip timing is provided to

generate the track and hold (T_H) signals for the three

correction loops.

LNA and Quadrature Demodulator

Three separate LNAs are integrated to address different bands

of operation. These LNAs have separate single-ended inputs,

which are externally matched to 50 Ω. The gain is switchable

between high (i.e., 15 dB typical) and low (i.e., –5 dB GSM,

–7 dB DCS, and –5 dB PCS typical) settings. The LNA outputs

feed into a quadrature demodulator that downconverts the RF

signals directly to baseband. Two external 470 pF capacitors

are required at the demodulator output to suppress the out-of-

band blockers.

The timing diagram for the DC offset correction sequence with

reference to the receive slot is shown in Figure 4. A rising edge

on either the RXENA signal, selected via the serial interface,

places the DC compensation circuitry in the track mode.

Baseband Section

The timing parameters for each of the three compensation

loops, t_{t_H1}, t_{t_H2}, and t_{t_H3}, and the time between compensation

start and the LNA being turned on, t_FEENA, are defined via an

internal state machine. The state machine is preprogrammed

with fixed default values, but may be readjusted via the serial

interface.

An off-chip capacitor and three fixed poles of on-chip, low

pass filtering provide rejection of strong in- and out-of-band

interferers. In addition, a tunable, four-pole gmC filter provides

rejection of the adjacent channel blockers. Incorporated within

the fixed-pole filters are two switchable gain stages of 18 dB

and 12 dB gain steps, respectively. There is an additional

programmable gain amplifier with a gain range from 0 to + 34

dB, selectable in 2 dB steps in the four-pole tunable filter. The

final filter output feeds an amplifier with a gain range from 0 to

30 dB, selectable in 6 dB steps.

The timing parameters for the three compensation loops and

the LNA power-up are each independently defined, relative to

the compensation start. Therefore, they may be programmed

to occur in any order, but the sequences shown in Figure 4 and

Figure 5 are recommended. The device default timing is shown

in Figure 5, with a total time of 60 μs. Individual default timings

are given in Table 17. For user-programmed timing, the total

time may be set as short as approximately 10 μs when FREF

has a 13 MHz clock applied. However, the shortest

There is an additional gain stage on the four-pole tunable filter

output, the auxiliary gain stage, selectable at 0 dB or + 6 dB.

The gain control ranges are shown in Figure 3.

Recommended combinations of individual block gain settings

are shown in Table 22 for GSM900, Table 23 for DCS1800, and

Table 24 for PCS1900.

recommended total time is approximately 30 μs, since at the

highest gain settings, the resulting DC may degrade as

correction time is reduced.

For added baseband interface flexibility, the four-pole filter, its

associated Variable Gain Amplifier (VGA), and DC offset

correction loop can be bypassed and turned off for current

savings.

AM Suppression and IP2 Calibration

For direct conversion GSM applications, it is imperative to have

extremely low second-order distortion. Mathematically,

second-order distortion of a constant tone generates a DC-

term proportional to the square of the amplitude. A strong

interfering amplitude-modulated (AM) signal is therefore

demodulated by second-order distortion in the receiver front

end, and generates an interfering baseband signal.

In Table 2 the typical locations of all eight receiver baseband

poles are given. The final four poles are produced by the

tunable gmC filter, as set by the external resistor

(recommended value is 39.2 kΩ, 1%) placed from pin 29 to

ground.

For these tunable poles, Table 2 gives the pole location as a

function of this resistor.

Table 2. Receive Pole Locations

Stage

Typical Pole Location (rad/sec)

–1.0 x 10⁶

Pole Type

Real (capacitors at pins 25-26 and 27-28 fixed at 470 pF)

Real

Mixer + RC Filter

–1.65 x 10⁶

(–0.91 x 10⁶) j(1.35 x 10⁶)

(–0.91 x 10⁶) x (39.2 kΩ/R)

[(–0.46 x 10⁶) j(1.0 x 10⁶)] x (39.2 kΩ/R)

LPF1

Conjugate

VGA1 + gmC filter

Real (adjust with resistor at pin 29)

Conjugate (adjust with resistor at pin 29)

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Data Sheet I CX74063-34/-35/-36

VGA1 + GMC Filter

+ Aux

LNA

Mixer + RC Filter

LPF1

VGA2

RXIP

RXIN

RXQP

RXQN

Mixer

+ RC Filter

VGA1 +GMC

Max 30 dB

VGA2

GSM LNA

LPF1

Max 30 dB

High 15 dB

Low –5 dB

High 40 dB

Low 22 dB

High 10 dB

Low –2 dB

(in 6 dB steps)

DCS LNA

Min

0 dB

Min

0 dB

High 15 dB

Low –7 dB

VGA1 Fine

Max 4 dB

Additional Interstage Losses

GSM900

4.2 dB

DCS1800

5.0 dB

PCS1900

6.2 dB

Mid

Min

2 dB

0 dB

PCS LNA

High 15 dB

Low –5 dB

AUX

High 6 dB

Low 0 dB

S092

Figure 3. Gain Control Settings

RXENA

Hold mode (Loop

1)

Track mode

DC Offset Correction Loop 1

t_{T_H1}

(Note 1)

Hold mode (Loop

2)

DC Offset Correction Loop 2 Track mode

t_{T_H2}

(Note 1)

Hold mode (Loop

3)

DC Offset Correction Loop 3 Track mode

t_{T_H3}

(Note 1)

Front End

Enable

(LNA off)

(LNA on)

Start of RX slot

t_FEENA

(Note 1)

Note 1. t_{T_H1}, t_{T_H2}, t_{T_H3}, and t_FEENAare programmed in Register 2.

101953A 3_012902

Figure 4. DC Offset Correction Timing (LNA Off During All of the DC Offset Correction Sequence)

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Data Sheet I CX74063-34/-35/-36

RXENA

Hold mode (Loop

1)

Track mode

DC Offset Correction Loop 1

t_{T_H1}

(Note 1)

Hold mode (Loop

2)

DC Offset Correction Loop 2 Track mode

DC Offset Correction Loop 3 Track mode

t_{T_H2}

(Note 1)

Hold mode (Loop

3)

t_{T_H3}

(Note 1)

Front End

Enable

(LNA off)

(LNA on)

Start of RX slot

t_FEENA

(Note 1)

Note 1. t_{T_H1}, t_{T_H2}, t_{T_H3}, and t_FEENAare programmed in Register 2.

101953A 4_012902

Figure 5. DC Offset Correction Timing (LNA On During Part of the DC Offset Correction Sequence)

A commonly used measure for receiver second-order distortion

The IP2 calibration is a one-time factory calibration that should

be done for each band and each individual device for optimum

performance. The determined coefficients must be stored in

nonvolatile memory and programmed to the CX74063-3x upon

each power-up as part of device initialization. There are on-

chip registers that must be programmed through Register 3

with the appropriate IP2 coefficients for the band in use.

is the second-order intercept point, IP2. For example, to ensure

that the unwanted baseband signals are 9 dB below the

wanted signal required under the AM suppression test for type

approval (see 3GPP TS 51.010-1), an input IP2 of 43 dBm is

required:

The CX74063-3x receiver includes a circuit that minimizes

second-order distortion. This IP2 calibration circuit effectively

compensates any second-order distortion in the receive chain

that would otherwise generate unwanted baseband signals in

the presence of strong interfering signals. When calibrated

correctly, the CX74063-3x IP2 meets the GSM AM suppression

test requirements in all bands with good margin.

As long as a supply voltage is maintained on pin 43, VDDBB,

the IP2 coefficients for I^LOWBAND, IHIGHBAND, QLOWBAND, QHIGHBAND

,

programmed to the device remain in the registers. After the

supply voltage has been removed from VDDBB, the coefficients

must be re-programmed to the device again.

Receive/Transmit I/Q Baseband Signals. Separate pins are

provided for receive I/Q outputs and transmit I/Q inputs.

However, for basebands that multiplex these signals, the

receive I/Q outputs and transmit I/Q inputs can be tied

together.

To calibrate IP2, apply a strong RF signal at the receiver input

and observe the resulting DC voltage level change at the

receiver I/Q outputs. The exact frequency and level of the

signal applied for the purpose of the calibration are not critical.

The signal should, however, be within the receive band, but at

least 6 MHz offset from the frequency to which the receiver is

tuned. The level should be high enough to cause a notable DC

shift at the I/Q outputs. A recommended value is –30 dBm at

the LNA input, which applies to all three LNAs.

Synthesizer Section

The CX74063-3x includes a fully integrated UHF VCO with an

on-chip LC tank.

A single sigma-delta fractional-N synthesizer can phase-lock

the local oscillator used in both transmit and receive paths to a

precision frequency reference input. Fractional-N operation

offers low phase noise and fast settling times, allowing for

multiple slot applications such as GPRS. The CX74063-3x

frequency stepping function with a 3 Hz resolution allows triple

band operation in both transmit and receive bands using a fully

integrated single integrated on-chip UHF VCO. The fine

synthesizer resolution allows direct compensation or

adjustment for reference frequency errors.

A set of I/Q compensation coefficients can then be

programmed to the device to minimize the DC voltage shift

resulting from the second-order distortion. When the DC due to

the interfering signal is minimized, the IP2 performance is

optimized.

Note: SXENA, pin 38, must be held high, and a clock signal

must be present on XTAL, pin 34, during the

programming of the IP2 calibration coefficients in

Register 3, see Table 18.

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Data Sheet I CX74063-34/-35/-36

The fractional-N synthesizer consists of the following:

3

4

•

f_VCO

=

f_RXfor DCS1800 and PCS1900

• VCO

• High frequency prescaler

• N-divider with a sigma-delta modulator

• Reference buffer and divider

• Fast phase frequency detector and charge pump

For the transmitter VCO frequency, refer to the equations

shown in Figure 6.

Digital Frequency Centering

The CX74063-3x uses a novel technique whereby the UHF VCO

frequency range is re-centered each time the synthesizer is

programmed. This technique is called Digital Frequency

Centering (DFC). The DFC technique:

The user must provide the following three parameters:

• The reference divider value, from 1 to 15

• The N-divider value, in a manner similar to an integer-N

synthesizer

• Extends the VCO frequency coverage

• Speeds up settling time

• A fractional ratio

• Ensures robust performance since the VCO is always

operated at the center of its tuning range.

The generated frequency is given by the following equation:

FN













N + 3.5+

f

ref

Each time the synthesizer is programmed, the DFC circuit is

activated, and the VCO is centered to the programmed

frequency in less than 20 µs. After this, normal Phase Locked

Loop (PLL) operation is resumed and the fine settling of the

frequency is finalized. The DFC typically adjusts the VCO center

frequency to within a few MHz and no more than 5 MHz offset,

and presets the tuning voltage to the center of the range before

the PLL takes over. This speeds up frequency settling and

ensures that the PLL control voltage never operates close to

the rails.

2²²

f_VCO

=

R

where: f^VCO= Generated VCO frequency

= N-divider ratio integer part

FN = Fractional setting

= R-divider ratio

N

R

f^REF= Reference frequency

UHF VCO Frequency Setting

For the receiver, to tune the receive frequency, f^RX, set the VCO

frequency, f^VCO, as follows:

3

2

•

f_VCO

=

f_RXfor GSM850/900

External

Loop

Filter

Phase

Detect

f_Tx

Tx VCO

D2

Tx I

Ext

o

+

90

D1

L/C Filter

Tx Q

X2

where:

f_Tx= f_LO(2 D1 -- D2)/D1

GSM: f_LO= (f_VCO)/3

DCS/PCS: f_LO= (2f_VCO)/3

X2

Fractional-N

PLL

÷3

f_VCO

UHF VCO

C1308

Figure 6. Transmitter Frequency Generation

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Data Sheet I CX74063-34/-35/-36

The DFC is an adaptive circuit that corrects for any VCO center

frequency errors caused by variations of the integrated VCO

circuit, temperature, supply voltage, aging etc. The VCO can be

centered at any frequency in the range from 1.2 GHz to

1.55 GHz. Once centered, the VCO has a minimum analog

tuning range of 30 MHz.

low if an external reference oscillator is used. The buffer may

be disabled by programming bit 3 in the SX1 Control Register

(see Table 13) to logic 0.

Transmit Section

To minimize the post-PA filtering requirements and any

additional post-PA losses, the transmit path consists of a

vector modulator within a frequency translation loop. The

translation loop consists of the following:

No calibration or data storage is needed for DFC operation. It is

activated by one of two events:

• When the synthesizer is programmed, the rising edge of the

LE signal starts the DFC cycle and,

• When changing the level of the SXENA signal from low to

high, thereby turning on the synthesizer, the rising edge of

the SXENA signal starts the DFC cycle.

• Phase Frequency Detector (PFD) and charge pump

• Mixer with an operating range of 800 MHz to 2 GHz

• An in-loop modulator

• Two programmable dividers

• Two transmit VCOs

Crystal Oscillator

Translational Loop

A crystal oscillator is designed to provide the reference

frequency for the synthesizer. As shown in Figure 7, the

oscillator uses an external crystal to generate an accurate

oscillation frequency. The reference frequency can be changed

through coarse tuning with an integrated capacitor array or fine

tuning with the integrated varactor diode. The coarse tuning is

done by switching in and out (using a digital word programmed

via the serial interface) the capacitor network (CAP_A and

CAP_B) located at the input of the integrated buffer. The fine

tuning is done by providing a tuning voltage to the integrated

varactor diode. Table 20 describes the control bits.

The translational loop takes baseband analog I/Q signals and

modulates them with the mixed product of transmitter output

and LO signal, as shown in Figure 6. The unmodulated result is

compared with a divided down LO at the PFD and the

difference is used to control the transmit VCO. The on-chip

Low Pass Filter (LPF) following the mixer attenuates the

unwanted sidebands as well as harmonics.

Transmit VCOs

Two on-chip transmit VCOs are designed to meet GSM850,

EGSM900, DCS1800, and PCS1900 requirements. The

transmit VCOs use the same DFC technique as described in the

Synthesizer section to lock the translational loop. The rising

edge on TXENA initializes the transmit DFC.

An output buffer is provided to drive the baseband circuitry

(XTALBUF, pin 30). The VCXO and buffer circuitry are powered

from pin 33 (VCCF). When VCCF is ramped to a voltage greater

than 2.6 V, the output buffer powers on. The oscillator core

powers up when pin 4 (VCXO_EN) is set to logic 1. If pin 4 is

tied permanently to logic 1, the R6 VCXO Control Register is set

to a defined state by a power-on reset. Pin 4 should be held

VCCF (Pin 33)

100 kΩ

XTALTUNE (Pin 39)

VCXO_EN (Pin 4)

PLL

XTAL (Pin 34)

CAP_B

CAP_A

÷2

VCCF (Pin 33)

Baseband

Buffer

XTAL_BUF (Pin 30)

to baseband

[SX Register 1

(bit 3)]

BUF_EN

C1337

Figure 7. VCXO Block Diagram

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Data Sheet I CX74063-34/-35/-36

Register 4

Coupler

VCC2

8

PA

PAC Delay

Timer

TXENA (pin 2)

PAVAPC

(pin 16)

+

–

PDETVCC

(pin 5)

5 pF

Power Detector

from baseband

PDET

(pin 12)

10 kΩ

BBVAPC (pin 17)

1

Bias

Generator

Rx/Tx Control Register

(bit 21), PDETVCC

0 = 0.5 V

1 = 1.0 V

C1338a

Figure 8. PA Controller Block Diagram

The RX/TX Control Register is used to program the transceiver

and to preset other test word states by setting bit 22 as a

logic 1. If any test words are to be altered from their preset

states, bit 22 must be sent to the RX/TX Control Register again

as a logic 0. Typically, this is done only on power-up since the

device has a zero-power standby mode that retains

programmed test memory.

Power Amplifier Gain Controller

The device contains an error amplifier/integrator to provide

transmit burst control for an external power amplifier (PA). As

shown in Figure 8, when the device is connected to a PA, an

RF detector, and a coupler, a loop is formed that controls the

transmit power in a multi-band wireless application. The error

amplifier amplifies and integrates the voltage difference

between the RF detector output (PDET) and the power control

input (BBVAPC). The output of the integrator is fed to an

internal gain shaper that drives the gain control input (PAVAPC)

of the external RF PA. The device. provides a bandgap voltage

(PDETVCC) which can be used as the supply voltage for the

external peak detector and can source up to 200 µA.

There are eight additional registers used to program various

functions of the CX74063-3x. The SX1 Control Register is used

to program the fractional-N synthesizer and the SX2

Fractional-N Modulo Register is used to program the modulus.

Four auxiliary registers are used to program the transceiver

besides the RX/TX Control Register, and two 24-bit registers

are used to program the synthesizer:

The PA pre-bias is activated after a programmable delay and

time-referenced from the rising edge of TXENA. The time delay

is set using the serial interface. See Table 19 for details.

• SX1 Synthesizer Control

• SX2 Fractional-N Modulo

• RX/TX Control

Digital Interface

• R0 Auxiliary Control

• R2 DC Offset Timing

• R3 IP2 Calibration

• R4 PAC Timing Control

• R6 VCXO Control

The transceiver and synthesizer are controlled by a single

three-wire serial interface. The transmitter, receiver, and

synthesizer are each enabled through external inputs

according to typical timing requirements as shown in Figures

10 and 11.

• R7 VCXO Control

Band selection for the CX74063-3x is through the three-wire

serial interface. The PCO signal (pin 3) provides a band

selection control output. DC offset calibration and front-end

activation timing can also be controlled by an on-chip signal

sequencer, precluding the need for separate control signals. All

the logic and the three-wire interface inputs are referenced to

the PCO signal (pin 3).

SX1 Control Register. This register is used to program the

fractional-N synthesizer, and set the values of the integral-N

divider and the input-R divider. The polarity of the

Phase/Frequency Detector (PFD) may also be defined by this

register. Refer to Table 13.

14

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Data Sheet I CX74063-34/-35/-36

SX2 Fractional-N Modulo Register. This register is used to

program the 24-bit modulo of the fractional-N synthesizer. The

data is a 22-bit binary coded decimal word that allows the PLL

to lock to precise frequencies. Refer to Table 14.

Package and Handling Information

Because this device package is sensitive to moisture

absorption, it is baked and vacuum packed before shipment

according to IPC J-STD 033 guidelines. Instructions on the

shipping container label regarding exposure to moisture after

the container seal is broken must be followed. These

instructions adhere to IPC J-STD 020A guidelines for handling

moisture sensitive devices. If these instructions are not

followed, problems related to moisture absorption may occur

when the part is subjected to high temperature during solder

assembly.

RX/TX Control Register. This register is used to control divide

ratios and charge pump currents in the transmitter, and to

control gain in the receiver along with the band select function.

Refer to Table 15.

R0 Auxiliary Control Register. This register is used to bypass

the DC offset correction loops and the baseband filters. It also

enables and disables the two on-chip transmit VCOs and

defines the directionality of the LO port, which allows an

external VCO or LO reference to be used or enables the internal

VCO to be monitored. Refer to Table 16.

The CX74063-3x transceiver is available in both low

temperature and high temperature attachment packages. The

RFLGA package for the low temperature attachment option

provides a circular-shaped ground pad (CX74063-34). The

RFLGA package for the high temperature options is available

with both a circular-shaped ground pad and a four-quadrant,

split center ground pad (CX74063-35 and CX74063-36,

respectively). Refer to Figures 28 and 29 for package

dimensions.

R2 DC Offset Timing Register. This register sets the timing of

the tracking of the three DC offset cancellation loops and the

time at which the front end turns on relative to the RXENA

signal (pin 1). It allows the front-end to be enabled using the

internal timer. Refer to Table 17.

R3 IP2 Calibration Register. This register is used to perform

2^ndorder Intercept Point (IP2) calibration by manually adjusting

calibration coefficients. A total of four words need to be set:

IP2 coefficients for I-high band, I-low band, Q-high band, and

Q-low band. Refer to Table 18.

Guidelines for CX74063-3x low and high temperature

attachment techniques are provided below. For additional

details on attachment techniques, precautions, and

recommended handling procedures, refer to the Skyworks’

Application Note, PCB Design & SMT Assembly Guidelines for

RFLGA Packages, document number 103147.

The IP2 coefficient is eight bits long (including polarity) and is

intended to be a factory calibration. An algorithm using a test

tone needs to be used to determine the coefficient for each

individual part.

For The –34 Low Temperature Package Option: If the

CX74063-34 is attached in a reflow oven, the temperature

ramp rate should not exceed 3 °C per second. Maximum

temperature should not exceed 240 °C and the time spent at a

temperature that exceeds 235 °C should be limited to less than

10 seconds.

R4 PAC Timing Control Register. This register is used to set

timing for the PAC pedestal. Refer to Table 19.

R6 and R7 VCXO Control Registers. These registers are used

to control the tuning range and oscillation frequency of the

VCXO. See Tables 20 and 21, respectively.

If the part is manually attached, precaution should be taken to

ensure that the part is not subjected beyond a maximum

temperature of 240 °C or exceeds 235 °C for more than

10 seconds. Care must be taken when this product is attached,

whether it is done manually or in a production solder reflow

environment, to NOT heat the part beyond the recommended

temperature. Measure the temperature on the package itself

by attaching thermocouples to the package body.

Electrical and Mechanical Specifications

The absolute maximum ratings of the CX74063-3x are

provided in Table 3. The recommended operating conditions

are specified in Table 4. Electrical specifications are provided

in Tables 5 through 11. Tables 12 through 21, and Figures 9

through 11 provide the serial interface programming states,

functions, and timing curves. Receiver data is shown in Tables

22 through 33 and illustrated in Figures 12 through 20.

Transmit data is illustrated in Figures 21 through 26.

For The –35 and –36 High Temperature Package Options: If

the CX74063-35 or the CX74063-36 are attached in a reflow

oven, the temperature ramp rate should not exceed 3 °C per

second. Maximum temperature should not exceed 260 °C and

the time spent at a temperature that exceeds 255 °C should be

limited to less than 15 seconds.

A typical application circuit using the CX74063-3x is shown in

Figure 27. The 56-pin RFLGA package dimensions are

provided in Figure 28 (-34 and -35 package options) and

Figure 29 (-36 package option). Tape and reel dimensions are

shown in Figure 30 (-34 and -36 package options) and

Figure 31 (-35 package option). Typical package case

markings are explained in Figure 32.

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Data Sheet I CX74063-34/-35/-36

If the part is manually attached, precaution should be taken to

ensure that the part is not subjected beyond a maximum

temperature of 260 °C or exceeds 255 °C for more than

15 seconds. Care must be taken when this product is attached,

whether it is done manually or in a production solder reflow

environment, to NOT heat the part beyond the recommended

temperature. Measure the temperature on the package itself

by attaching thermocouples to the package body.

Electrostatic Discharge

The CX74063-3x contains Class 1 devices. The following

Electrostatic Discharge (ESD) precautions are recommended:

• Protective outer garments

• Handle device in ESD safeguarded work area

• Transport device in ESD shielded containers

• Monitor and test all ESD protection equipment

• Treat the CX74063-3x as extremely sensitive to ESD

Production quantities of this product are shipped in a standard

tape and reel format. For packaging details, refer to the

Skyworks’ Application Note, Tape and Reel, document number

101568. Typical case markings for the CX74063-3x are shown

in Figure 31.

Table 3. CX74063-3x Absolute Maximum Ratings

Parameter

Minimum

–0.3

Maximum

+3.6

Units

V

Supply voltage (VCC)

Ambient operating temperature range

Storage temperature range

Input voltage range

–40

+95

°C

–50

+125

VCC

°C

GND

V

Maximum power dissipation

600

mW

Note: Stresses above these absolute maximum ratings may cause permanent damage. These are

stress ratings only and functional operation at these conditions is not implied. Exposure to

maximum rating conditions for extended periods may reduce device reliability.

Table 4. CX74063-3x Recommended Operating Conditions

Parameter

Minimum

Typical

Maximum

Units

LNA input level (pins 9, 11, 13)

RXEN = Off

10

dBm

Power supply

2.6

1.8

2.8

3.3

V

Digital power supply, VDDBB

Operating junction temperature

Operating ambient temperature

–40

–30

+110

+85

°C

16

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Data Sheet I CX74063-34/-35/-36

Table 5. Power Consumption Specifications

(T^A= 25° C, VCC = 2.8 V unless otherwise noted)

Parameter

Symbol

Test Condition

Min

Typical

Max

Units

Total supply current:

I^CC

Rx section, EGSM/GSM850

Tx section, EGSM/GSM850 (includes TX VCO)

RXENA=H; SXENA=L

TXENA=H; SXENA=L

41

121

48

137

mA

Synthesizer section, EGSM/GSM850

(includes UHF VCO)

SXENA=H

39

46

mA

Rx section, DCS/PCS

Tx section, DCS/PCS (includes TX VCO)

RXENA=H; SXENA=L

TXENA=H; SXENA=L

49

126

58

143

mA

Synthesizer section, DCS/PCS (includes UHF VCO)

Sleep mode

SXENA=H

39

20

46

mA

@ VCC = 3.3 V

RXENA=L; TXENA=L;

SXENA=L

100

µA

Table 6. CX74063-3x Electrical Specifications – EGSM/GSM850 Receiver (1 of 3)

(T^A= 25° C, VCC = 2.8 V unless otherwise noted)

Parameter

Symbol

Test Condition

(Note 1)

Min

Typical

Max

Units

Input impedance. See Figure 12 for

unmatched input impedance.

ZIN

With external match

50

Ω

Input operating frequency

Receiver maximum voltage gain

Receiver minimum voltage gain

Receiver gain temperature variation

Gain step

Band 1

GRXMAX

GRXMIN

869

120

960

MHz

dB

Highest gain mode

Lowest gain mode

T^A= –30 °C to +85 °C

126

11

17

dB

G

TEMVAR

4.5

dB

2

dB

∆A^V

Gain step accuracy

GSTEP

Over range

–0.75

+0.75

dB

recommended in

Table 25

Gain variation versus frequency

GFREQ

Over 869-894 MHz

Over 925-960 MHz

G = 15/40/10/12/0/18

2

dB

2

Noise Figure

NFGAIN1

NFTEMP

3.2

3.9

5.0

5.2

Noise Figure (temperature)

T^A= +75 °C

T^A= +85 °C

G = 15/40/10/12/0/18

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Data Sheet I CX74063-34/-35/-36

Table 6. CX74063-3x Electrical Specifications – EGSM/GSM850 Receiver (2 of 3)

(T^A= 25° C, VCC = 2.8 V unless otherwise noted)

Parameter

Symbol

Test Condition

(Note 1)

Min

Typical

Max

Units

Noise Figure degradation in presence of NFBLOC

blocker

With –26 dBm input

blocker @ 3 MHz offset

(ideal LO)

2

dB

Internal LO

4

dB

G = 15/40/10/12/0/18

Input 2nd order intercept point

DC shift in presence of blocker

IIP2

Referred to LNA input

calibrated and

measured at middle of

EGSM or GSM850

band.

50

65

dBm

AM Supp

LOREV

With –34 dBm

@ 6 MHz offset

G = 15/40/10/12/0/18

17

mV

LO re-radiation @ LNA input

Selectivity

@ wanted frequency

–110

–100

dBm

@ 3 MHz offset

143

128

61

37

9

dB

@ 1.6 MHz offset

@ 600 kHz offset

@ 400 kHz offset

@ 200 kHz offset

T^A= –30 °C to +85 °C

137

68

44

13

I/Q amplitude imbalance

I/Q phase imbalance

1

dB

T^A= –30 °C to +85 °C

–3

+3

degrees

dBm

Input 1 dB compression point

IP1dB

F = 200 kHz,

G = 15/40/-2/8/0/18

–65

–60

–40

–30

–28

–22

–12

F = 400 kHz,

G = 15/40/-2/8/0/18

–45

–35

–32

–25

–15

dBm

F = 600 kHz,

G = 15/40/10/12/0/18

F = 1.6 MHz,

G = 15/40/10/12/0/18

F = 3.0 MHz,

G = 15/40/10/12/0/18

IIP3

F = 3.0 MHz

G = 15/40/10/12/0/18

3rd order intercept point @ +25 °C

3rd order intercept point @ –20 °C

F = 3.0 MHz

G = 15/40/10/12/0/18

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Data Sheet I CX74063-34/-35/-36

Table 6. CX74063-3x Electrical Specifications – EGSM/GSM850 Receiver (3 of 3)

(T^A= 25° C, VCC = 2.8 V unless otherwise noted)

Parameter

Symbol

Test Condition

(Note 1)

Min

Typical

Max

Units

Output offset voltage

With DC offset

corrected while LNA is

off

200

mV

220

20

mV

T^A= +85°C

With DC offset

corrected while LNA is

on

G=15/40/10/12/0/18

25

mV

T^A= +85 °C

(60 µs total DC

correction time)

Offset drift (long term)

Offset drift (short term)

DCDRFT1

DCDRFT2

50 ms after correction

G = 15/40/10/12/0/18

100

10

mV

577 µs after correction

G = 15/40/10/12/0/18

Baseband Tunable Active Filter

3 dB corner frequency (tunable)

Corner frequency variation

FC

80

100

+11

kHz

%

dFC

–11

39.2 kΩ at pin 29

470 pF at pins 25-26

and 27-28

Receiver Output Stage

VGA2 = 30 dB

Differential output amplitude

(pk/pk differential)

3.7

0.3

V

VGA2 = 0 dB

Output common mode voltage

Maximum current drive

Output resistance

VCC/2 – 0.1

VCC/2

VCC/2 + 0.1

0.5

T^A= –30 °C to +85 °C

IOUT

mA

ROUT

RXENA = H,

160

200

40k

240

Ω

RXENA = L, differential

RXENA = L, single-

ended

>1M

Output capacitance

COUT

1

pF

Note 1: Gain codes refer to LNA/Mixer/LPF1/VGA1/AUX/VGA2 gains in dB.

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Data Sheet I CX74063-34/-35/-36

Table 7. CX74063-3x Electrical Specifications – DCS1800 Receiver (1 of 3)

(T^A= 25° C, VCC = 2.8 V unless otherwise noted)

Parameter

Symbol

Test Condition

(Note 1)

Min

Typical

Max

Units

Input impedance See Figure 13 for

unmatched input impedance.

ZIN

With external match

50

Ω

Input operating frequency

Receiver maximum voltage gain

Receiver minimum voltage gain

Gain step

Band 2

GRXMAX

GRXMIN

∆A^V

DCS Rx band

1805

117

1880

15

MHz

dB

Highest gain mode

Lowest gain mode

123

9

dB

2

dB

Receiver gain temperature variation

Gain step accuracy

GTEMPVAR

GSTEP

4.5

dB

T^A= –30 °C to +85 °C

Over range

–0.75

+0.75

dB

recommended in

Table 26

Gain variation versus frequency

Noise Figure

GFREQ

Over band 2

2

dB

NFGAIN1

NFTEMP

G = 15/40/10/12/0/18

3.6

2

4.3

Noise Figure (temperature)

5.4

5.6

T^A= +75 °C

T^A= +85 °C

Noise Figure degradation in presence of NFBLOC

blocker

With –30 dBm input

blocker @ 3 MHz offset

(ideal LO)

dB

Internal LO

4

dB

G = 15/40/10/12/0/18

Input 2nd order intercept point

DC shift in presence of blocker

IIP2

Referred to LNA input

calibrated and

measured at middle of

DCS1800 band.

50

65

dBm

AM Supp

LOREV

With –33 dBm

@ 6 MHz offset

G = 15/40/10/12/0/18

17

mV

LO re-radiation @ LNA input

Selectivity

@ wanted frequency

@ 3 MHz offset

–110

–100

dBm

dB

143

128

61

37

9

@ 1.6 MHz offset

@ 600 kHz offset

@ 400 kHz offset

@ 200 kHz offset

T^A= –30 °C to +85 °C

137

68

dB

41

dB

13

dB

I/Q amplitude imbalance

I/Q phase imbalance

1

dB

T^A= –30 °C to +85 °C

–3

+3

degrees

20

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Data Sheet I CX74063-34/-35/-36

Table 7. CX74063-3x Electrical Specifications – DCS1800 Receiver (2 of 3)

(T^A= 25° C, VCC = 2.8 V unless otherwise noted)

Parameter

Symbol

Test Condition

(Note 1)

Min

Typical

Max

Units

Input 1 dB compression point

IP1dB

F = 200 kHz,

G = 15/40/-2/8/0/18

–65

–45

–35

–32

–25

–15

–60

–40

–30

–28

–22

–12

dBm

mV

F = 400 kHz,

G = 15/40/-2/8/0/18

F = 600 kHz,

G = 15/40/10/12/0/18

F = 1.6 MHz,

G = 15/40/10/12/0/18

F = 3.0 MHz,

G = 15/40/10/12/0/18

IIP3

F = 3.0 MHz

G = 15/40/10/12/0/18

3rd order intercept point @ +25 °C

3rd order intercept point @ –20 °C

Output offset voltage

F = 3.0 MHz

G = 15/40/10/12/0/18

With DC offset

corrected while LNA is

off

200

220

20

mV

T^A= + 85°C

With DC offset

corrected while LNA is

on

G = 15/40/10/12/0/18

25

mV

T^A= + 85 °C

(60 µs total DC

correction time)

Offset drift (long term)

Offset drift (short term)

DCDRFT1

DCDRFT2

G = 15/40/10/12/0/18

50 ms after correction

100

10

mV

G = 15/40/10/12/0/18

577 µs after correction

Baseband Tunable Active Filter

3 dB corner frequency (tunable)

Corner frequency variation

FC

80

100

kHz

%

dFC

– 11

+ 11

39.2 kΩ at pin 29

470 pF at pins 25-26

and 27-28

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Data Sheet I CX74063-34/-35/-36

Table 7. CX74063-3x Electrical Specifications – DCS1800 Receiver (3 of 3)

(T^A= 25° C, VCC = 2.8 V unless otherwise noted)

Parameter

Symbol

Test Condition

(Note 1)

Min

Typical

Max

Units

Receiver Output Stage

VGA2 = 30 dB

Differential output amplitude (pk/pk

differential)

3.7

0.3

V

VGA2 = 0 dB

Output common mode voltage

Maximum current drive

Output Resistance

VCC/2 – 0.1

VCC/2

VCC/2 + 0.1

0.5

V

IOUT

mA

ROUT

RXENA = H,

160

200

40k

240

Ω

RXENA = L, differential,

RXENA = L, single-

ended

>1M

Output Capacitance

COUT

1

pF

Note 1: Gain codes refer to LNA/Mixer/LPF1/VGA1/AUX/VGA2 gains in dB.

Table 8. CX74063-3x Electrical Specifications – PCS1900 Receiver (1 of 3)

(T^A=2 5° C, VCC = 2.8 V unless otherwise noted)

Parameter

Symbol

Test Condition

(Note 1)

Min

Typical

Max

Units

Input impedance. See Figure 14 for

unmatched input impedance.

ZIN

With external match

50

Ω

Input operating frequency

Receiver maximum voltage gain

Receiver minimum voltage gain

Receiver gain temperature variation

Gain step

Band 3

PCS Rx band

1930

117

1990

MHz

dB

GRXMAX

Highest gain mode

Lowest gain mode

T^A= –30 °C to +85 °C

123

7

G

RXMIN

13

dB

GTEMPVAR

4.5

dB

2

dB

∆A^V

Gain step accuracy

GSTEP

Over range

–0.75

+0.75

dB

recommended in

Table 27

Gain variation versus frequency

Noise Figure

GFREQ

Over band 3

2

dB

NFGAIN1

NFTEMP

G = 15/40/10/14/0/18

4.2

4.9

Noise Figure (temperature)

6.0

6.2

T^A= +75 °C

T^A= +85 °C

Noise Figure degradation in presence of NFBLOC

blocker

With –30 dBm input

blocker @ 3MHz offset

(ideal LO)

2

4

dB

Internal LO

G = 15/40/10/14/0/18

22

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103116C

Data Sheet I CX74063-34/-35/-36

Table 8. CX74063-3x Electrical Specifications – PCS1900 Receiver (2 of 3)

(T^A=2 5° C, VCC = 2.8 V unless otherwise noted)

Parameter

Symbol

Test Condition

(Note 1)

Min

Typical

Max

Units

Input 2nd order intercept point

IIP2

Referred to LNA input

calibrated and

50

65

dBm

measured at middle of

PCS1900 band

DC shift in presence of blocker

AM Supp

LOREV

With –33 dBm

@ 6 MHz offset

G = 15/40/10/14/0/18

17

mV

LO Re-radiation @ LNA input

Selectivity

@ wanted frequency

@ 3 MHz offset

–110

–100

dBm

dB

143

128

61

37

9

@ 1.6 MHz offset

@ 600 kHz offset

@ 400 kHz offset

@ 200 kHz offset

T^A= –30 °C to +85 °C

137

68

dB

41

dB

13

dB

I/Q amplitude imbalance

I/Q phase imbalance

1

dB

T^A= –30 °C to +85 °C

–3

+3

degrees

dBm

Input 1 dB compression point

IP1dB

F = 200 kHz,

G = 15/40/-2/8/0/18

–65

–60

–40

–30

–28

–22

–12

F = 400 kHz,

G = 15/40/-2/8/0/18

–45

–35

–32

–25

–15

dBm

mV

F = 600 kHz,

G = 15/40/10/14/0/18

F = 1.6 MHz,

G = 15/40/10/14/0/18

F = 3.0 MHz,

G = 15/40/10/14/0/18

IIP3

F = 3.0 MHz

G = 15/40/10/14/0/18

3rd order intercept point @ +25 °C

3rd order intercept point @ –20 °C

Output offset voltage

F = 3.0 MHz

G = 15/40/10/14/0/18

With DC offset

corrected while LNA is

off

200

220

20

mV

T^A= +85°C

With DC offset

corrected while LNA is

on

25

mV

T^A= +85 °C

G = 15/40/10/12/0/18

(60 µs total DC

correction time)

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Data Sheet I CX74063-34/-35/-36

Table 8. CX74063-3x Electrical Specifications – PCS1900 Receiver (3 of 3)

(T^A=2 5° C, VCC = 2.8 V unless otherwise noted)

Parameter

Symbol

Test Condition

(Note 1)

Min

Typical

Max

Units

Offset drift (long term)

DCDRFT1

DCDRFT2

50 ms after correction

G = 15/40/10/14/0/18

100

10

mV

Offset drift (short term)

577 µs after correction

G = 15/40/10/14/0/18

Baseband Tunable Active Filter

3 dB corner frequency (tunable)

Corner frequency variation

F

C

80

100

+11

kHz

%

dF

C

–11

39.2 kΩ at pin 29

470 pF at pins 25-26

and 27-28

Receiver Output Stage

VGA2 = 30 dB

Differential output amplitude (pk/pk

differential)

3.7

0.3

V

VGA2 = 0 dB

Output common mode voltage

Maximum current drive

Output resistance

VCC/2 – 0.1

VCC/2

VCC/2 + 0.1

0.5

V

I

OUT

mA

R

OUT

RXENA = H,

160

200

40k

240

Ω

RXENA = L, differential,

RXENA = L, single-

ended

>1M

Output capacitance

C

OUT

1

pF

Note 1: Gain codes refer to LNA/Mixer/LPF1/VGA1/AUX/VGA2 gains in dB.

Table 9. CX74063-3x Electrical Specifications – Transmitter (1 of 4)

(T^A=2 5° C, VCC = 2.8 V unless otherwise noted)

Parameter

Symbol

Test Condition

I/Q Modulator

Min

Typical

Max

Units

Input impedance

ZIN

TXENA = H, differential,

TXENA = L, differential,

TXENA = L, single-

ended

400k

>1M

Ω

60k

Input signal level

Differential

0.8

1

1.35

3

1.2

Vp-p

V

Input common mode voltage range

Input frequency 3 dB bandwidth

Input common mode rejection ratio

V

CM

0.85

VCC – 1.3

MHz

dB

f

IN = 100 kHz

IN = 1 MHz

65

45

75

55

Output operating frequency

Output impedance

Output voltage

FOUT

ZOUT

VOUT

70

130

230

MHz

Ω

Per side

170

200

–33

dBV

24

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103116C

Data Sheet I CX74063-34/-35/-36

Table 9. CX74063-3x Electrical Specifications – Transmitter (2 of 4)

(T^A=2 5° C, VCC = 2.8 V unless otherwise noted)

Parameter

Symbol

Test Condition

I/Q Modulator (continued)

@ 10 MHz offset

Min

Typical

Max

Units

Output noise power

N

O

–132

–130

35

–128

–126

dBc/Hz

dBc

@ 1.8 MHz offset

LO suppression

30

Sideband suppression

35

dBc

Translational Loop

Modulation 2nd order

Modulation 3rd order

Spurious

–70

–60

–40

–55

2000

130

dBc

Transmit frequency (input from VCO)

IF frequency

F

TX

IF

800

70

MHz

dBm

F

Transmit input power

P

IN

–20

–15

–10

With external 50 Ω

termination

Transmit input impedance

Z

300//

0.3

Ω//

pF

Transmitter output phase noise

(includes TX VCO and LO PLL)

NO

@ 400 kHz offset

@ 1.8 MHz offset

–120

–130

–152

–118

–124

–150

dBc/Hz

@ 10 MHz offset

EGSM/GSM850

@ 20 MHz offset

EGSM/GSM850

–164

–156

2.0

–162

–154

dBc/Hz

degrees

@ 20 MHz offset

DCS/PCS

Tx phase error

TxPHERR

rms (employs reference

frequency source, and

loop filters as shown in

the reference design)

Charge pump output current: high

impedance source/sink

I

OUT

RX/TX Control Register

bits

S17 S16

CP =

0

1

0

1

0

1

mA

0.5

0.75

1.0

1.25

Charge pump current variation

0.3 ≤ VCPO ≤ VCC – 0.5

TA = –30 °C to +85 °C

20

%

Charge pump current variation over

temperature

10

D1 divide ratio range

D2 divide ratio

9

1

12

2

Tx mixer

TXMIX

Tx mixer

–60

dBm

LO leakage

LEAKAGE

50 Ω terminated

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Data Sheet I CX74063-34/-35/-36

Table 9. CX74063-3x Electrical Specifications – Transmitter (3 of 4)

(T^A=2 5° C, VCC = 2.8 V unless otherwise noted)

Parameter

Symbol

Test Condition

Min

Typical

Max

930

20

Units

Low Band Translation Loop VCO

Center frequency

f

C

800

MHz

µs

T^A= –30 °C to +85 °C

Digital frequency centering resolution

Digital frequency centering time

e

DFC

2.5

12

t

DFC

From rising edge of

TXENA (13 MHz clock

frequency)

Digital frequency centering voltage

V

DFC

Control voltage at end

of DFC/start of analog

lock

VCC/2 – 0.2

20

VCC/2

VCC/2 + 0.2

V

Analog frequency control range

Absolute control sensitivity

fMAX – fMIN

0.5 < VCTL < 2.2

MHz

K

VCO

(0.9 V < VCTL and

1.9 V > V^CTL

)

820 MHz < f

MHz

C

< 850

< 915

16

18

21

25

26

32

MHz/V

870 MHz < f

MHz

Output harmonics

Phase noise

2nd harmonic

3rd harmonic

–50

– 55

–125

–164

–30

dBc

@ 400 kHz offset

@ 20 MHz offset

–120

–162

2:1

dBc/Hz

Output VSWR

With external 50 Ω

match

Pushing

2

4

MHz/V

MHz

Pulling

VSWR 2:1

Output power

POUT

F

OUT = 897.5 MHz with

10.5

11.5

0.7

12.5

dBm

external 50 Ω match

Output power temperature variation

dB

T

A

= –30°C to +85°C

High Band Translation Loop VCO

Center frequency

f

C

1700

1930

20

MHz

µs

T = –30 °C to +85 °C

A

Digital frequency centering resolution

Digital frequency centering time

e

DFC

6

t

DFC

From rising edge of

TXENA (13 MHz clock

frequency)

12

Digital frequency centering voltage

VDFC

Control voltage at end

of DFC/start of analog

lock

VCC/2 – 0.2

VCC/2

VCC/2 + 0.2

V

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103116C

Data Sheet I CX74063-34/-35/-36

Table 9. CX74063-3x Electrical Specifications – Transmitter (4 of 4)

(T^A=2 5° C, VCC = 2.8 V unless otherwise noted)

Parameter

Symbol

Test Condition

Min

Typical

Max

Units

High Band Translation Loop VCO (continued)

Analog frequency control range

Absolute control sensitivity

f

MAX – fMIN

0.5 < VCTL < 2.2

20

14

MHz

K

VCO

1710 MHz < f

MHz

C

< 1785

18

23

22

27

MHz/V

1850 MHz < f

MHz

< 1910

19

MHz/V

0.9 V < V^CTLand

1.9 V > V^CTL

Output harmonics

Phase noise

2nd harmonic

–50

–55

–30

dBc

3rd harmonic

@ 400 kHz offset

@ 20 MHz offset

–125

–158

–120

–155

2:1

dBc/Hz

Output VSWR

with external 50 Ω

match

Pushing

2

4

MHz/V

MHz

Pulling

VSWR 2:1

Output power

P_OUT

F_out= 1747.5 MHz with

external 50 Ω match

5.5

7

1

8.5

dBm

Output power variation

dB

TA

= –30 °C to +85 °C

PA Gain Controller

PAVAPC output swing

PAVAPC offset voltage

PAVAPC sink current

PAVAPC source current

Open loop gain

0.22

VCC – 0.3

V

TXENA = H

0.68

550

750

I_SINK

I_SOURCE

G

µA

dB

V

104

0

111

2.7

Input common mode range

PDETVCC source current

PDETVCC output voltage

I_PDETVCC

200

0.5

µA

V

PDETVCC = 0 (bit 21 of

RX/TX Control Register)

PDETVCC = 1 (bit 21 of

RX/TX Control Register)

1.0

V

Output load

10pF //

10kΩ

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Data Sheet I CX74063-34/-35/-36

Table 10. CX74063-3x Electrical Specifications – Synthesizer (1 of 3)

(T^A= 25° C, VCC = 2.8 V unless otherwise noted)

Parameter

Prescaler operating input frequency

Reference input frequency

Phase detector frequency

Symbol

Test Condition

Min

1000

10

Typical

Max

1700

26

Units

MHz

dBm

13

15

External crystal oscillator input

sensitivity

–15

0.4

+3

Reference oscillator sensitivity

In-band phase noise

VCC

VPEAK

Measured within the

loop bandwidth

–85

100

dBc/Hz

Charge pump output current (can be

programmed in four steps)

VCP = VCCFN_CP/2

(SX1 Control Register,

bit[6:5] = 00)

µA

V

CP = VCCFN_CP/2

200

300

400

µA

(SX1 Control Register,

bit[6:5] = 01)

VCP = VCCFN_CP/2

(SX1 Control Register,

bit[6:5] = 10)

VCP = VCCFN_CP/2

(SX1 Control Register,

bit[6:5] = 11)

Charge pump leakage current

0.5 < VCP < VCCFN_CP

– 0.5

0.1

5

nA

%

Charge pump sink versus source

mismatch

VCP = VCCFN_CP/2

Charge pump current versus voltage

0.5 < VCP < VCCFN_CP

– 0.5

10

Charge pump current versus

temperature

VCP = VCCFN_CP/2

TA

= –30°C to +85°C

UHF VCO

Center frequency

f

C

1200

1550

20

MHz

µs

T

A

= –30 °C to +85 °C

Digital frequency centering resolution

Digital frequency centering time

e

DFC

2

t

DFC

From rising edge of

SXENA or LE when

programming SX word

(13 MHz clock

12

frequency)

Digital frequency centering voltage

Analog frequency control range

V

DFC

Control voltage at end

of DFC/start of analog

lock

V^CCUHF/2 –

0.2

VCCUHF/2

VCCUHF/2 +

V

0.2

fMAX – fMIN

0.5 < VCTL < 2.2

30

MHz

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103116C

Data Sheet I CX74063-34/-35/-36

Table 10. CX74063-3x Electrical Specifications – Synthesizer (2 of 3)

(T^A= 25° C, VCC = 2.8 V unless otherwise noted)

Parameter

Symbol

Test Condition

Min

Typical

Max

Units

UHF VCO (continued)

Relative control sensitivity

KVCO/f

C

After DFC, within the

range of e^VCTL

1200 MHz < f

MHz

C

< 1300

< 1400

< 1475

< 1550

1.3

1.5

1.7

1.9

1.7

2.0

2.2

2.4

2.1

2.4

2.6

2.8

%/V

1300 MHz < f

MHz

1400 MHz < f

MHz

1475 MHz < f

MHz

Absolute control sensitivity

KVCO

VDCF + eVCTL,MIN < VCTL

and

V^DCF+ eVCTL MAX > VCTL

,

1200 MHz < f

MHz

C

< 1300

< 1400

< 1475

< 1550

15

19

24

28

21

27

32

36

28

34

39

44

MHz/V

1300 MHz < f

MHz

1400 MHz < f

MHz

1475 MHz < f

MHz

Phase noise

@ 400 kHz offset

@ 3 MHz offset

–123

–140

–121

–137

+5

dBc/Hz

Slow center frequency drift

–5

MHz/sec

∆f

C/∆t

TA

= –30°C to + 85°C

26 MHz Crystal Oscillator

Operating frequency

26

13

MHz

Buffer output frequency

Phase noise:

@ 100 Hz

@ 1 kHz

–98

–127

–145

dBc/Hz

@ 10 kHz

Clock jitter

16

ps

dBc

ppm

V

Spurious rejection

–20

70

–15

Digital tuning (Note 1)

Analog tuning (Note 1)

Analog varactor voltage range

Analog varactor DC impedance

45

0

VTUNE = 0.05 to 2.5 V

23

VCC

1

MΩ

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Data Sheet I CX74063-34/-35/-36

Table 10. CX74063-3x Electrical Specifications – Synthesizer (3 of 3)

(T^A= 25° C, VCC = 2.8 V unless otherwise noted)

Parameter

Symbol

Test Condition

Min

Typical

Max

Units

26 MHz Crystal Oscillator (continued)

Supply voltage dependence

1

2

ppm/V

µA

2.8 0.1 V

Operating current (start) @ 26 MHz

2600

Operating current (equilibrium)

@ 26 MHz

µA

Voltage swing @ crystal

Voltage swing @ buffer

Buffer output load

1.1

Vpp

10pF ||

10 kΩ

Start-up time

4

ms

Note 1: Using a crystal with equivalent 6 mH inductor and ESR ≤ 100 Ω.

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103116C

Data Sheet I CX74063-34/-35/-36

Table 11. CX74063-3x Electrical Specifications – Digital Interface

(T^A= 25° C, VCC = 2.8 V unless otherwise noted)

Parameter

Symbol

Test Condition

Min

30

10

30

50

30

Typical

Max

Units

ns

Data to clock setup time (Note 1)

Data to clock hold time (Note 1)

Clock pulse width high (Note 1)

Clock pulse width low (Note 1)

Clock to load enable setup time (Note 1)

Load enable pulse width (Note 1)

T

CS

CH

ns

CWH

CWL

ES

ns

EW

ns

LE falling edge to clock rising edge

(Note 1)

EFC

ns

RXENA setup time

TXENA setup time

SXENA setup time

30

ns

High level input voltage for RXENA,

TXENA, DATA, CLK, LE, PCO, VCXO_EN,

and SXENA

V^IH

V^IL

I^IH

V

0.8 ×

VDDBB

Low level input voltage for RXENA,

TXENA, DATA, CLK, LE, PCO, VCXO_EN,

and SXENA

V

0.2 ×

VDDBB

High level input current for RXENA,

TXENA, DATA, CLK, LE, PCO, VCXO_EN,

and SXENA

–1

+1

10

µA

pF

Low level input current for RXENA,

TXENA, DATA, CLK, LE, PCO, VCXO_EN,

and SXENA

I^IL

Digital input pin capacitance for RXENA, C^ID

TXENA, DATA, CLK, LE, PCO, VCXO_EN,

and SXENA

High level output voltage for PCO

Low level output voltage for PCO

VOH

VOL

CLD

IOH = –1.0 mA

IOL = 1.0 mA

VDDBB – 0.4

V

0.4

15

Digital output pin load capacitance for

PCO

pF

Note 1: See Figure 9.

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Data Sheet I CX74063-34/-35/-36

Serial Interface Programming

Table 12. Control and Output States

Register

Address Bits

B6

X

B5

X

B4

X

B3

X

B2

X

B1

0

B0

0

SX Register 1: Synthesizer Control

SX Register 2: Fractional-N Modulo

RX/TX Control Register

R0: Auxiliary Control

R2: DC Offset Timing

R3: IP2 Calibration

X

1

0

X

1

X

0

1

X

1

0

1

X

0

1

0

1

R4: PAC Timing Control

R6: VCXO Control

X

0

1

0

1

0

1

0

1

0

1

R7: VCXO Control

1

0

1

0

1

Table 13. SX Register 1: Synthesizer Control Functions

Symbol

Function

State Description

ADDR

Address bits [1:0]. Must be set to

00b (see Table 12)

EN

Enable mode [2]

0 enables synthesizer

1 disables synthesizer

BUF_EN

SP

Buffer enable [3]

0 sets buffer to off state

1 sets buffer to on state

Phase detector output polarity [4]

Charge pump output current [6:5]

0 sets phase detector output for negative VCO gain

1 sets phase detector output for positive VCO gain

SC

Bit [6:5]

0 0 sets charge pump current to 100 µA

0 1 sets charge pump current to 200 µA

1 0 sets charge pump current to 300 µA

1 1 sets charge pump current to 400 µA

RSVD

Reserved

Bit [8:7]: set bit 8 = 1, bit 7 = 0

N

R

Main divider [19:9]

Reference divider [23:20]

Sets 11-bit main divider ratio range (64…2047)

Sets 4-bit reference divider ratio range (1…15)

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103116C

Data Sheet I CX74063-34/-35/-36

Table 14. SX Register 2: Fractional-N Modulo

Symbol

Function

State Description

ADDR

Address bits [1:0]. Must be set to

10b (see Table 12)

FN

Fractional-N modulo [23:2]

Sets fractional-N modulo up to 2²²range (0…4,194,303)

Table 15. RX/TX Control Register (1 of 2)

Symbol

Function

State Description

ADDR

Address bits [1:0]. Must be set to

11b (see Table 12)

LNA

LNA gain step control [2]

0 selects low gain mode of LNA

1 selects high gain mode of LNA

MIX

Mixer gain step [3]

0 selects low gain mode of RX mixer

1 selects high gain mode of RX mixer

LPF1

VGA2

1st LPF gain step [4]

VGA2 gain steps [7:5]

0 selects low gain mode of the first active LPF

1 selects high gain mode of the first active LPF

Bit 7 to bit 5 program the VGA2 gain in 6 dB increments

Bit 7, Bit 6, Bit 5

0

1

0

1

0

1

0

1

0

1

0

1

0

1

sets the gain to 30 dB

sets the gain to 24 dB

sets the gain to 18 dB

sets the gain to 12 dB

sets the gain to 6 dB

sets the gain to 0 dB

not used

AUX

Auxiliary gain [8]

0 sets 0 dB auxiliary gain post gmC filter

1 sets 6 dB auxiliary gain post gmC filter

VGA1

VGA1 gain steps [11:9]

Bit 11 to bit 9 program the VGA1 gain in the following

increments:

Bit 11,Bit 10, Bit 9

0

1

0

1

0

1

0

1

0

1

0

1

0

1

sets the gain to 0 dB

sets the gain to 24 dB

sets the gain to 12 dB

not used

sets the gain to 6 dB

sets the gain to 30 dB

sets the gain to 18 dB

not used

VGA1FINE

VGA1 fine gain step [13:12]

Bit 13 and bit 12 program VGA1 in 2 dB increments

Bit 13, Bit 12

0

1

0

1

0

1

sets gain to 0 dB

sets gain to 4 dB

sets gain to 2 dB

not used

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Data Sheet I CX74063-34/-35/-36

Table 15. RX/TX Control Register (2 of 2)

Symbol

Function

State Description

SOFTSEL

Software band select [15:14]

Bit 15, Bit 14

0

1

0

1

0

1

not used

selects EGSM/GSM850, PCO = 0

selects DCS, PCO = 1

selects PCS, PCO = 1

TXCP

TX charge pump bits [17:16]

Translational loop charge pump current setting

Bit 17, Bit 16

0

1

0

1

0

1

sets TXCP to 0.5 mA

sets TXCP to 0.75 mA

sets TXCP to 1.0 mA

sets TXCP to 1.25 mA

TXD1

TX divider D1 [19:18]

Translational loop D1 divider setting

Bit 19, Bit 18

0

1

0

1

0

1

sets D1 to 9

sets D1 to 11

sets D1 to 10

sets D1 to 12

TXD2

TX divider D2 [20]

Translational loop D2 divider setting:

0 sets D2 to 1

1 sets D2 to 2

PDETVCC

PREENA

Power detector bias [21]

Load default words [22]

Bit [21] sets bias voltage for the Schottky diode pair:

0 = 0.5 V

1 = 1.0 V

0 allows changing contents of R0 to R7

1 allows loading default words into R0 to R7

Upon power up, program RX/TX control register with

PREENA = 1 to load the default words into R0 to R5. If

changing the default words is required, program RX/TX

control register with PREENA = 0 and then program any or all

of R0 to R5. PREENA should also be set to 0 when sending SX

R1, SX R2, and RX/TX control register words before each

time slot in normal operation. The data is stored in R0 to R5

as long as VDDBB (pin 43) is supplied with power.

NU

Not used [23]

Not used

34

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103116C

Data Sheet I CX74063-34/-35/-36

Default (Binary)

Table 16. Register 0: Auxiliary Control

State Description

Symbol

Function

ADDR

Address bits [3:0]. Must be set to

0001b (see Table 12)

GMC_BYP

SK_BYP

Bypass GMC stage [4]

0 enables gmC filter stage

1 disables and bypasses gmC filter stage

0

Bypass S-K stage [5]

0 enables Sallen-Key filter stage

1 disables and bypasses Sallen-Key filter stage

DC_BYP1

Bypass first DC OC loop [6]

0 enables first DC offset correction loop

1 disables and bypasses first DC offset correction

loop

DC_BYP2

DC_BYP3

Bypass second DC OC loop [7]

Bypass second DC OC loop [8]

0 enables second DC offset correction loop

1 disables and bypasses second DC offset correction

0

0 enables third DC offset correction loop

1 disables and bypasses third DC offset correction

NU

Not used [9]

Not used

0

1

TVCOEN

TXVCO Select [10]

0 disables TXVCO

1 enables TXVCO via TXENA (Pin4)

RSVD

NU

Reserved [12:11]

Not Used [13]

Reserved [14]

Reserved [15]

Reserved, must be programmed to default value

Not Used

10

0

RSVD

Reserved, must be programmed to default value

0

DFCPLLENA DFC Enable [16]

0 disables DFC

1 enables DFC

1

UHFVCOENA UHFVCO Enable [17]

0 disables internal UHF VCO

1 enables internal UHF VCO

1

RSVD

Reserved[20:18]

Reserved, must be programmed to default value

011

1

CALENA

Enable IP2 Cal [21]

0 disables IP2 calibration

1 enables IP2 calibration

NU

Not used[22]

Not used[23]

Not used

0

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Data Sheet I CX74063-34/-35/-36

Table 17. Register 2: DC Offset Timing

State Description

Symbol

Function

Default (Binary)

ADDR

Address bits [3:0]. Must be set to

1001b (see Table 12)

DCOCL1

DCOCL2

DCOCL3

FEENA_TIM

DCOC control [7:4]

DCOC control [12:8]

DCOC control [16:13]

Tracking timing for DCOC1 (tT_H1 = (DCOCL1 x 64 x

R)/Fref ) (Note 1)

0100 (20 µs with 13 MHz f_REF

)

Tracking timing for DCOC2 (tT_H2 = (DCOCL2 x 64 x

R)/Fref ) (Note 1)

01100 (60 µs with 13 MHz f_REF

)

Tracking timing for DCOC3 (tT_H3 = (DCOCL3 x 128 x

R)/Fref ) (Note 1)

0110 (60 µs with 13 MHz f_REF

0100 (40 µs with 13 MHz f_REF

)

FEENA relative to initial track

[20:17]

Front end enable timing (tFEENA = (FEENA_TIM x 128

x R)/Fref ) (Note 1)

NU

Not used [21]

Not used [22]

Not used [23]

Not used

0

Note 1: See Figure 4 and Figure 5.

Table 18. Register 3: IP2 Calibration

Symbol

Function

State Description

ADDR

Address bits [5:0]. Must be set to

001101b (see Table 12)

ADDR_SEL

Channel selection [6]

0 selects Q channel

1 selects I channel

RSVD

Reserved [7]

Must be set to 1 for correct operation

Coefficient for adjustment of receiver IP2

CORR_DATA IP2 correction coefficient [15:8]

Bit [15] sets polarity:

0 = Positive

1 = Negative

Bit [14:8]

1111111 minimum correction

•

0000000 maximum correction

Bit [14] = MSB

Bit [8] = LSB

NU

Not used [23:16]

Not used

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103116C

Data Sheet I CX74063-34/-35/-36

Default (Binary)

Table 19. Register 4: PAC Timing Control

State Description

Symbol

Function

ADDR

Address bits [5:0]. Must be set to

011101b (see Table 12)

RSVD

Reserved [11:6]

Reserved. Must be set to default value.

000010

PAC_TIME

PAC timing control [19:12]

Bit [19:12] sets timing for PAC pedestal.

When all bits = 0, no pedestal.

10011010 = 54.769 µs

Bit [12] = MSB = 1024/f^PFD= 78.7 µs for

f^PFD= 13 MHz

Bit [19] = LSB = 8/f^PFD= 0.615 µs for fPFD = 13 MHz

RSVD

Reserved [23:20]

Reserved. Must be set to default value.

0100

Table 20. Register 6: VCXO Control

Symbol

Function Description

Internal

Power-On

Value (Binary)

Recommended

Operational Value

(Binary)

ADDR

Address bits [6:0]. Must be set to 0101101b (see Table 12)

CAP_A

Bit [11:7] capacitor A array control. Binary weighted.

Bit [11] = LSB = 1/8 pF

00001

Bit [7] = MSB = 2 pF

Array composition = 2 pF, 1 pF, 0.5 pF, 0.25 pF, 0.125 pF

Bit [15:12] capacitor B array control. Binary weighted.

Bit [15] = LSB = 1/32 pF

Determined during a one-

time factory calibration

CAP_B

0000

Bit [12] = MSB = 1/4 pF

Array composition = 0.25 pF, 0.125 pF, 0.065 pF,

0.03125 pF

RSVD

Bit [23:16] reserved

00000000

Note: Programmed values in this register are not maintained with VDDBB (pin 43).

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Data Sheet I CX74063-34/-35/-36

Table 21. Register 7: VCXO Control

Symbol

Function Description

Internal

Power-On

Value (Binary)

Recommended

Operational Value

(Binary)

ADDR

Address bits [6:0]. Must be set to 1101101b (see Table 12)

I_VCXO

Bit [10:7] negative resistance current control. Binary

weighted.

0101

1001

Negative logic (on = low, off = high)

Bit [10] = LSB = 8 µA

Bit [7] = MSB = 64 µA

Stepped values = 64 µA, 32 µA, 16 µA, 8 µA

Bit [23:11] reserved. Must be set to default value.

RSVD

0000000000000

0000000001110

(Must Use)

Note: Programmed values in this register are not maintained with VDDBB (pin 43).

S23

S22

S1

S0

t_CH

DATA

t_CS

CLOCK

t_ES

t_CWH

t_CWL

t_EW

LE

C898

Figure 9. Serial Data Input Timing Diagram For Transceiver

38

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103116C

Data Sheet I CX74063-34/-35/-36

7

0

1

2

3

4

5

6

RX

TX

Mon

RXENA

120 µs

Internal DCOC 1

Internal DCOC 2

20 µs

40 µs

60 µs

Internal DCOC 3

Internal FEENA

10 µs

50 µs

SXENA

240 µs

LE

10 µs (Note 1)

TXENA

PAC_TIME

OFFSET GEN TIMING

PAVAPC

PA RAMP

Voltage

0.7 V

TX I/Q

TRSW Enable

25 µs (Note 1)

FREF

(not to scale)

Note 1: This timing depends on circuitry other than the CX74063.

C1330

Figure 10. CX74063-3x Signal Timing Example (Normal Operation)

SXENA

Preset=0

Band=GSM

GSM

IP2 I

GSM

Preset=0

DCS/PCS

IP2 I

DCS/PCS

IP2 Q

DCOC

timing

VCXO

Control 1

VCXO

Control 2

Preset=1

IP2 Q Band=DCS/PCS

DATA

CLK

Note 1

LE

VDDBB

(pin 43)

Note 2

FREF

(not to scale)

Note 1. LE should be low before the next clock goes high.

Note 2. VDDBB, pin 43, is required to hold the register settings. If VDDBB is not maintained high, the power-on

programming sequence needs to be added in front of each normal slot programming sequence.

C1329

Figure 11. CX74063-3x Register Programming Sequence and Timing Example (Initialization After Power Up)

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Data Sheet I CX74063-34/-35/-36

Receiver Data

Table 22. Recommended EGSM900/GSM850 AGC Data (1 of 2)

(AGC Setpoint = –25.2 dBV = 55.0 mVrms)

Antenna Input External

Internal

Inter-

Stage

Losses

(dB)

I/Q Output

(dBV)

Total

Voltage

Gain

(dBm)

Front

End

VGA1

Fine

(dB)

LNA

(dB)

Mixer

(dB)

LPF

(dB)

VGA1

(dB)

Aux

(dB)

VGA2

(dB)

Losses

(dB)

From

To

From

To

(dB)

–110

–108

–106

–104

–102

–100

–98

–96

–94

–92

–90

–88

–86

–84

–82

–80

–78

–76

–74

–72

–70

–68

–66

–64

–62

–60

–58

–56

–54

–108

–106

–104

–102

–100

–98

–96

–94

–92

–90

–88

–86

–84

–82

–80

–78

–76

–74

–72

–70

–68

–66

–64

–62

–60

–58

–56

–54

–52

–4.0

15

–5

40

22

10

–2

10

–2

10

18

12

6

4

2

0

4

2

0

4

2

0

4

2

0

4

2

0

4

2

0

4

2

0

4

2

0

4

2

0

4

0

18

–4.2

96.8

94.8

92.8

90.8

88.8

86.8

84.8

82.8

80.8

78.8

76.8

74.8

72.8

70.8

68.8

66.8

64.8

62.8

60.8

58.8

56.8

54.8

52.8

50.8

48.8

46.8

44.8

42.8

40.8

–26.2

–24.2

6

0

6

0

6

0

6

0

40

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103116C

Data Sheet I CX74063-34/-35/-36

Table 22. Recommended EGSM900/GSM850 AGC Data (2 of 2)

(AGC Setpoint = –25.2 dBV = 55.0 mVrms)

Antenna Input External

Internal

Inter-

Stage

Losses

(dB)

I/Q Output

(dBV)

Total

Voltage

Gain

(dBm)

Front

End

VGA1

Fine

(dB)

LNA

(dB)

Mixer

(dB)

LPF

(dB)

VGA1

(dB)

Aux

(dB)

VGA2

(dB)

Losses

(dB)

From

To

From

To

(dB)

–52

–50

–48

–46

–44

–42

–40

–38

–36

–34

–32

–30

–28

–26

–24

–22

–20

–18

–16

–50

–48

–46

–44

–42

–40

–38

–36

–34

–32

–30

–28

–26

–24

–22

–20

–18

–16

–14

–4.0

–5

22

10

–2

0

6

0

2

0

4

2

0

4

2

0

4

2

0

4

2

0

4

2

0

18

12

6

–4.2

38.8

36.8

34.8

32.8

30.8

28.8

26.8

24.8

22.8

20.8

18.8

16.8

14.8

12.8

10.8

8.8

–26.2

–24.2

–22.2

–24.2

–22.2

–20.2

6

0

6.8

0

6.8

0

6.8

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Data Sheet I CX74063-34/-35/-36

Antenna Input External

Table 23. Recommended DCS1800 AGC Data (1 of 2)

(AGC Setpoint = –24.2 dBV = 61.7 mVrms)

Internal

Inter-

Stage

Losses

(dB)

I/Q Output

(dBV)

Total

Voltage

Gain

(dBm)

Front

End

Losses

(dB)

VGA1

LNA

(dB)

Mixer

(dB)

LPF

VGA1

(dB)

Aux

(dB)

VGA2

(dB)

Fine

(dB)

From

To

From

To

(dB)

–110

–108

–106

–104

–102

–100

–98

–96

–94

–92

–90

–88

–86

–84

–82

–80

–78

–76

–74

–72

–70

–68

–66

–64

–62

–60

–58

–56

–54

–52

–108

–106

–104

–102

–100

–98

–96

–94

–92

–90

–88

–86

–84

–82

–80

–78

–76

–74

–72

–70

–68

–66

–64

–62

–60

–58

–56

–54

–52

–50

–4.2

15

–7

40

22

10

–2

10

–2

10

24

18

12

6

0

4

2

0

4

2

0

4

2

0

4

2

0

4

2

0

4

2

0

4

2

0

4

2

0

4

2

0

2

0

18

–5.0

97.8

95.8

93.8

91.8

89.8

87.8

85.8

83.8

81.8

79.8

77.8

75.8

73.8

71.8

69.8

67.8

65.8

63.8

61.8

59.8

57.8

55.8

53.8

51.8

49.8

47.8

45.8

43.8

41.8

39.8

–25.2

–23.2

6

0

6

0

6

0

6

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103116C

Data Sheet I CX74063-34/-35/-36

Table 23. Recommended DCS1800 AGC Data (2 of 2)

(AGC Setpoint = –24.2 dBV = 61.7 mVrms)

Antenna Input External

Internal

Inter-

Stage

Losses

(dB)

I/Q Output

(dBV)

Total

Voltage

Gain

(dBm)

Front

End

VGA1

Fine

(dB)

LNA

(dB)

Mixer

(dB)

LPF

(dB)

VGA1

(dB)

Aux

(dB)

VGA2

(dB)

Losses

(dB)

From

To

From

To

(dB)

–50

–48

–46

–44

–42

–40

–38

–36

–34

–32

–30

–28

–26

–24

–22

–20

–18

–16

–48

–46

–44

–42

–40

–38

–36

–34

–32

–30

–28

–26

–24

–22

–20

–18

–16

–14

–4.2

–7

-7

22

10

–2

0

6

0

4

2

0

4

2

0

4

2

0

4

2

0

4

2

0

4

2

0

18

12

6

–5.0

37.8

35.8

33.8

31.8

29.8

27.8

25.8

23.8

21.8

19.8

17.8

15.8

13.8

11.8

9.8

–25.2

–23.2

–21.2

-7

6

-7

6

-7

0

7.8

-7

0

5.8

-7

0

5.8

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Data Sheet I CX74063-34/-35/-36

Antenna Input External

Table 24. Recommended PCS1900 AGC Data (1 of 2)

(AGC Setpoint = –25.4 dBV = 53.7 mVrms)

Internal

Inter-

Stage

Losses

(dB)

I/Q Output

(dBV)

Total

Voltage

Gain

(dBm)

Front

End

Losses

(dB)

VGA1

LNA

(dB)

Mixer

(dB)

LPF

VGA1

(dB)

Aux

(dB)

VGA2

(dB)

Fine

(dB)

From

To

From

To

(dB)

–110

–108

–106

–104

–102

–100

–98

–96

–94

–92

–90

–88

–86

–84

–82

–80

–78

–76

–74

–72

–70

–68

–66

–64

–62

–60

–58

–56

–54

–52

–108

–106

–104

–102

–100

–98

–96

–94

–92

–90

–88

–86

–84

–82

–80

–78

–76

–74

–72

–70

–68

–66

–64

–62

–60

–58

–56

–54

–52

–50

–4.2

15

–5

40

22

10

–2

10

–2

10

24

18

12

6

0

4

2

0

4

2

0

4

2

0

4

2

0

4

2

0

4

2

0

4

2

0

4

2

0

4

2

0

4

0

18

–6.2

96.6

94.6

92.6

90.6

88.6

86.6

84.6

82.6

80.6

78.6

76.6

74.6

72.6

70.6

68.6

66.6

64.6

62.6

60.6

58.6

56.6

54.6

52.6

50.6

48.6

46.6

44.6

42.6

40.6

38.6

–26.4

–24.4

6

0

6

0

6

0

6

0

44

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103116C

Data Sheet I CX74063-34/-35/-36

Table 24. Recommended PCS1900 AGC Data (2 of 2)

(AGC Setpoint = –25.4 dBV = 53.7 mVrms)

Antenna Input External

Internal

Inter-

Stage

Losses

(dB)

I/Q Output

(dBV)

Total

Voltage

Gain

(dBm)

Front

End

VGA1

Fine

(dB)

LNA

(dB)

Mixer

(dB)

LPF

(dB)

VGA1

(dB)

Aux

(dB)

VGA2

(dB)

Losses

(dB)

From

To

From

To

(dB)

–50

–48

–46

–44

–42

–40

–38

–36

–34

–32

–30

–28

–26

–24

–22

–20

–18

–16

–48

–46

–44

–42

–40

–38

–36

–34

–32

–30

–28

–26

–24

–22

–20

–18

–16

–14

–4.2

–5

22

10

–2

0

6

0

2

0

4

2

0

4

2

0

4

2

0

4

2

0

4

2

0

18

12

6

–6.2

36.6

34.6

32.6

30.6

28.6

26.6

24.6

22.6

20.6

18.6

16.6

14.6

12.6

10.6

8.6

–26.4

–24.4

–22.4

6

0

6.6

0

4.6

0

4.6

101514D 10_071101

Figure 12. Typical Baseband Frequency Response

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Data Sheet I CX74063-34/-35/-36

µsec

101514D 11_071101

Figure 13. Typical Differential Delay Response

Table 25. EGSM900/GSM850 LNA S11 (Normalized to 50 Ω)

Frequency (MHz)

869.0

S11

0.386 – 0.632j

0.438 – 0.630j

0.454 – 0.629j

0.420 – 0.639j

0.403 – 0.642j

0.398 – 0.646j

0.371 – 0.653j

0.376 – 0.653j

0.379 – 0.657j

0.343 – 0.664j

0.350 – 0.664j

878.1

887.2

896.3

905.4

914.5

923.6

932.7

941.8

950.9

960.0

46

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103116C

Data Sheet I CX74063-34/-35/-36

Table 26. DCS1800 LNA S11 (Normalized to 50 Ω)

Frequency (MHz)

1805.0

S11

0.0205 – 0.649j

0.205 – 0.689j

0.275 – 0.704j

0.299 – 0.710j

0.319 – 0.713j

0.326 – 0.718j

0.316 – 0.722j

0.306 – 0.722j

0.307 – 0.722j

0.300 – 0.724j

0.287 – 0.724j

1812.5

1820.0

1827.5

1835.0

1842.5

1850.0

1857.5

1865.0

1872.5

1880.0

Table 27. PCS1900 LNA S11 (Normalized to 50 Ω)

Frequency (MHz)

1930

S11

0.237 – 0.583j

0.362 – 0.595j

0.432 – 0.591j

0.472 – 0.589j

0.489 – 0.591j

0.488 – 0.597j

0.483 – 0.600j

0.485 – 0.600j

0.484 – 0.600j

0.475 – 0.603j

0.465 – 0.605j

1936

1942

1948

1954

1960

1966

1972

1978

1984

1990

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Data Sheet I CX74063-34/-35/-36

Table 28. Typical EGSM and GSM850 Band Noise Figure vs. Gain Data

Gain

100.8

98.8

96.8

94.8

92.8

90.8

88.8

86.8

NF

Gain

84.8

82.8

80.8

78.8

76.8

74.8

72.8

70.8

NF

Gain

68.8

66.8

64.8

62.8

60.8

58.8

56.8

54.8

NF

Gain

52.8

50.8

48.8

46.8

44.8

42.8

40.8

38.8

NF

Gain

36.8

34.8

32.8

30.8

28.8

26.8

24.8

22.8

NF

Gain

20.8

18.8

16.8

14.8

12.8

10.8

NF

3.17

3.18

3.20

3.22

3.26

3.31

3.38

3.48

3.59

3.73

4.90

5.44

6.08

6.82

7.60

22.50

23.76

24.92

30.21

31.29

32.37

33.39

38.32

39.71

41.11

42.46

43.73

44.89

42.70

44.02

45.24

43.56

45.01

46.39

45.89

47.58

49.25

8.39

11.80

12.77

13.71

18.43

19.79

21.16

60.00

50.00

40.00

30.00

20.00

10.00

0.00

0

20

40

60

80

100

120

RX Voltage Gain (dB)

101514F 15_111201

Figure 14. Typical EGSM and GSM850 Band Noise Figure vs. Voltage Gain Curve

(CX74063-3x Only, No Front End Loss)

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103116C

Data Sheet I CX74063-34/-35/-36

Table 29. Typical EGSM and GSM850 Band Dynamic Range Data (Includes 4.0 dB Front End Loss)

Input

Noise

Floor

P1dB

Gain

Input

Noise

Floor

P1dB

Gain

Input

Noise

Floor

P1dB

Gain

–109.0

–107.0

–105.0

–103.0

–101.0

–99.0

–97.0

–95.0

–93.0

–91.0

–89.0

–87.0

–85.0

–83.0

–81.0

–79.0

–113.0

–112.9

–112.8

–112.7

–112.5

–112.3

–112.1

–110.8

–110.0

–109.2

–78.6

–76.6

–74.6

–72.6

–70.6

–68.7

–66.9

–65.2

–63.7

–62.4

–61.4

–60.5

–59.9

–54.8

–53.8

–53.0

97.8

95.8

93.8

91.8

89.8

87.8

85.8

83.8

81.8

79.8

77.8

75.8

73.8

71.8

69.8

67.8

–77.0

–75.0

–73.0

–71.0

–69.0

–67.0

–65.0

–63.0

–61.0

–59.0

–57.0

–55.0

–53.0

–51.0

–49.0

–47.0

–108.2

–107.1

–106.0

–102.9

–101.6

–100.4

–96.4

–94.9

–93.4

–91.8

–90.3

–88.9

–83.8

–82.6

–81.3

–79.9

–52.4

–52.0

–51.8

–43.4

–42.5

–41.9

–36.9

–35.9

–35.2

–34.6

–34.3

–34.0

–24.3

–23.2

–22.3

–21.7

65.8

63.8

61.8

59.8

57.8

55.8

53.8

51.8

49.8

47.8

45.8

43.8

41.8

39.8

37.8

35.8

–45.0

–43.0

–41.0

–39.0

–37.0

–35.0

–33.0

–31.0

–29.0

–27.0

–25.0

–23.0

–21.0

–19.0

–17.0

–15.0

–78.6

–74.5

–72.9

–71.4

–69.8

–68.3

–66.9

–65.2

–63.4

–62.3

–60.3

–58.4

–56.7

–54.7

–52.7

–21.2

–18.1

–17.7

–17.4

–17.2

–17.0

–16.9

–16.8

33.8

31.8

29.8

27.8

25.8

23.8

21.8

19.8

17.8

15.8

13.8

11.8

9.8

7.8

5.8

3.8

-10.00

-20.00

-40.00

P1dB

-60.00

-80.00

Input

Noise Floor

-100.00

-120.00

-120.0

-100.0

-80.0

-60.0

Antenna Input (dBm)

-40.0

-20.0

0.0

+ 4.0 dB Front End Loss

101514F 16_111901

Figure 15. Typical EGSM and GSM850 Band Dynamic Range vs. Antenna Input Curve

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Data Sheet I CX74063-34/-35/-36

Table 30. Typical DCS1800 Band Noise Figure vs. Gain Data

Gain

100

98

NF

3.7

3.8

Gain

84

NF

3.9

4.0

4.1

4.3

5.5

6.1

6.7

7.5

Gain

68

NF

8.3

Gain

52

NF

Gain

36

NF

Gain

20

NF

23.3

24.6

25.7

32.0

33.0

34.1

35.2

36.2

41.1

42.5

43.9

45.3

46.5

47.7

45.5

46.8

48.0

46.4

47.8

49.2

48.7

50.4

82

66

9.1

50

34

18

96

80

64

12.6

13.6

14.5

19.2

20.6

22.0

48

32

16

94

78

62

46

30

14

92

76

60

44

28

12

90

74

58

42

26

10

88

72

56

40

24

86

70

54

38

22

60.00

50.00

40.00

30.00

20.00

10.00

0.00

0

20

40

60

80

100

120

RX Voltage Gain (dB)

101514F 17_111201

Figure 16. Typical DCS1800 Band Noise Figure vs. Voltage Gain Curve

(CX74063-3x Only; No Front End Loss)

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103116C

Data Sheet I CX74063-34/-35/-36

Table 31. Typical DCS1800 Band Dynamic Range Data (Includes 4.2 dB Front End Loss)

Input

Noise

Floor

P1dB

Gain

Input

Noise

Floor

P1dB

Gain

Input

Noise

Floor

P1dB

Gain

–109.0

–107.0

–105.0

–103.0

–101.0

–99.0

–97.0

–95.0

–93.0

–91.0

–89.0

–87.0

–85.0

–83.0

–81.0

–79.0

–113.0

–112.9

–112.8

–112.7

–112.5

–112.3

–112.1

–110.8

–110.0

–109.2

–78.6

–76.6

–74.6

–72.6

–70.6

–68.7

–66.9

–65.2

–63.7

–62.4

–61.4

–60.5

–59.9

–54.8

–53.8

–53.0

97.8

95.8

93.8

91.8

89.8

87.8

85.8

83.8

81.8

79.8

77.8

75.8

73.8

71.8

69.8

67.8

–77.0

–75.0

–73.0

–71.0

–69.0

–67.0

–65.0

–63.0

–61.0

–59.0

–57.0

–55.0

–53.0

–51.0

–49.0

–47.0

–108.2

–107.1

–106.0

–102.9

–101.6

–100.4

–96.4

–94.9

–93.4

–91.8

–90.3

–88.9

–83.8

–82.6

–81.3

–79.9

–52.4

–52.0

–51.8

–43.4

–42.5

–41.9

–36.9

–35.9

–35.2

–34.6

–34.3

–34.0

–24.3

–23.2

–22.3

–21.7

65.8

63.8

61.8

59.8

57.8

55.8

53.8

51.8

49.8

47.8

45.8

43.8

41.8

39.8

37.8

35.8

–45.0

–43.0

–41.0

–39.0

–37.0

–35.0

–33.0

–31.0

–29.0

–27.0

–25.0

–23.0

–21.0

–19.0

–17.0

–15.0

–78.6

–74.5

–72.9

–71.4

–69.8

–68.3

–66.9

–65.2

–63.4

–62.3

–60.3

–58.4

–56.7

–54.7

–52.7

–21.2

–18.1

–17.7

–17.4

–17.2

–17.0

–16.9

–16.8

33.8

31.8

29.8

27.8

25.8

23.8

21.8

19.8

17.8

15.8

13.8

11.8

9.8

7.8

5.8

3.8

-10.00

-20.00

-40.00

P1dB

-60.00

-80.00

Input

Noise Floor

-100.00

-120.00

-120.0

-100.0

-80.0

-60.0

Antenna Input (dBm)

-40.0

-20.0

0.0

+ 4.2 dB Front End Loss

101514F 18_111201

Figure 17. Typical DCS1800 Band Dynamic Range vs. Antenna Input Curve

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Data Sheet I CX74063-34/-35/-36

Table 32. Typical PCS1900 Band Noise Figure vs. Gain Data

Gain

98.8

96.8

94.8

92.8

90.8

88.8

86.8

84.8

NF

Gain

82.8

80.8

78.8

76.8

74.8

72.8

70.8

68.8

NF

Gain

66.8

64.8

62.8

60.8

58.8

56.8

54.8

52.8

NF

Gain

50.8

48.8

46.8

44.8

42.8

40.8

38.8

36.8

NF

Gain

34.8

32.8

30.8

28.8

26.8

24.8

22.8

20.8

NF

Gain

18.8

16.8

14.8

12.8

10.8

8.8

NF

4.2

4.5

9.3

24.5

42.3

49.2

4.2

4.3

4.4

4.6

4.7

4.9

6.3

6.9

7.6

8.4

10.1

13.7

14.7

15.6

20.4

21.8

23.1

25.8

26.9

33.2

34.2

35.3

36.4

37.4

43.7

45.1

46.5

47.7

48.9

46.7

48.0

47.6

49.0

50.4

49.9

51.6

53.3

6.8

60.00

50.00

40.00

30.00

20.00

10.00

0.00

0

20

40

60

80

100

120

RX Voltage Gain (dB)

101514F 19_111901

Figure 18. Typical PCS1900 Band Noise Figure vs. Voltage Gain Curve

(CX74063-3x Only; No Front End Loss)

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103116C

Data Sheet I CX74063-34/-35/-36

Table 33. Typical PCS1900 Band Dynamic Range Data (Includes 4.2 dB Front End Loss)

Input

Noise

Floor

P1dB

Gain

Input

Noise

Floor

P1dB

Gain

Input

Noise

Floor

P1dB

Gain

–109.0

–107.0

–105.0

–103.0

–101.0

–99.0

–97.0

–95.0

–93.0

–91.0

^–89.0

–112.5

–112.4

–112.3

–112.1

–112.0

–111.8

–111.5

–110.0

–109.3

–108.4

–77.4

–75.4

–73.4

–71.4

–69.4

–67.5

–65.7

–64.0

–62.5

–61.2

–60.2

–59.3

–58.7

–53.6

–52.6

–51.8

96.6

94.6

92.6

90.6

88.6

86.6

84.6

82.6

80.6

78.6

76.6

74.6

72.6

70.6

68.6

66.6

–77.0

–75.0

–73.0

–71.0

–69.0

–67.0

–65.0

–63.0

–61.0

–59.0

–57.0

–55.0

–53.0

–51.0

–49.0

–47.0

–107.4

–106.3

–105.2

–102.0

–100.7

–99.5

–95.4

–93.9

–92.4

–90.9

–89.4

–88.0

–82.8

–81.6

^–80.3

–51.2

–50.8

–50.6

–42.2

–41.3

–40.7

–35.7

–34.7

–34.0

–33.4

–33.1

–32.8

–23.3

–22.2

–21.4

–20.8

64.6

62.6

60.6

58.6

56.6

54.6

52.6

50.6

48.6

46.6

44.6

42.6

40.6

38.6

36.6

34.6

–45.0

–43.0

–41.0

–39.0

–37.0

–35.0

–33.0

–31.0

–29.0

–27.0

–25.0

–23.0

–21.0

–19.0

–17.0

–15.0

–77.7

–73.5

–72.0

–70.4

–68.9

–67.4

–66.0

–66.3

–64.6

–62.9

–61.8

–59.9

–58.0

–56.3

–54.3

–52.4

–20.3

–17.6

–17.2

–17.0

–16.8

–16.7

–16.6

–16.5

32.6

30.6

28.6

26.6

24.6

22.6

20.6

18.6

16.6

14.6

12.6

10.6

8.6

–87.0

–85.0

–83.0

–81.0

–79.0

6.6

4.6

–79.0

2.6

-10.00

-20.00

-40.00

-60.00

-80.00

P1dB

Input

Noise Floor

-100.00

-120.00

-120.0

-100.0

-80.0

-60.0

Antenna Input (dBm)

-40.0

-20.0

0.0

+4.2 dB Front End Loss

101514F 20_111901

Figure 19. Typical PCS1900 Band Dynamic Range vs. Antenna Input Curve

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Data Sheet I CX74063-34/-35/-36

50

45

40

35

30

25

20

15

10

5

Specification Limits

Typical

Performance

0

1100

1200

1300

1400

1500

1600

VCO Frequency (MHz)

101514F 21_111901

Figure 20. Typical Control Sensitivity, UHF VCO

35

30

25

20

15

Specification Limits

Typical

Performance

10

5

0

750

800

850

900

950

VCO Frequency (MHz)

101514F 22_111901

Figure 21. Typical Control Sensitivity, Low Band TX VCO

30

25

20

Specification Limits

15

10

5

Typical

Performance

0

1600

1650

1700

1750

1800

1850

1900

1950

101514F 23_111901

2000

VCO Frequency (MHz)

Figure 22. Typical Control Sensitivity, High Band TX VCO

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103116C

Data Sheet I CX74063-34/-35/-36

Transmitter Data

RBW 30 kHz RF Att

VBW 30 kHz Mixer –20 dBm

SWT 5 ms Unit dBm

20 dB

5

0

1

[T1] = 2.61 dBm

836.40000000 MHz

–10

1

[T1] = –67.91 dB

–400.00000000 kHz

–20

–30

–40

–50

–60

–70

–80

2

[T1] = –67.69 dB

400.00000000 kHz

P

R e l a t i v e

1

2

–90

–95

Center 836.4 MHz

100 kHz/

Span 1 MHz

S094

Figure 23. Typical GSM850 Band Output Spectrum

RBW 30 kHz RF Att

20 dB

VBW 30 kHz Mixer –20 dBm

SWT 5 ms

Unit

dBm

5

0

1

[T1] = 3.02 dBm

902.40000000 MHz

–10

1

[T1] = –68.37 dB

–400.00000000 kHz

–20

–30

–40

–50

–60

–70

–80

2

[T1] = –87.71 dB

400.00000000 kHz

P

R e l a t i v e

2

1

–90

–95

Center 902.4 MHz

100 kHz/

Span 1 MHz

S095

Figure 24. Typical EGSM Band Output Spectrum

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Data Sheet I CX74063-34/-35/-36

RBW 30 kHz RF Att

VBW 30 kHz Mixer –20 dBm

SWT 5 ms Unit dBm

20 dB

5

1

0

[T1] = 0.09 dBm

1.74780000 GHz

1

–10

1

[T1] = –67.66 dB

–400.00000000 kHz

–20

–30

–40

–50

–60

–70

–80

2

[T1] = –67.32 dB

400.00000000 kHz

P

R e l a t i v e

1

2

–90

–95

Center 1.7478 GHz

100 kHz/

Span 1 MHz

S096

Figure 25. Typical DCS Band Output Spectrum

RBW 30 kHz RF Att

20 dB

VBW 30 kHz Mixer –20 dBm

SWT 5 ms

Unit

dBm

5

0

1

[T1] = 0.75 dBm

1.88000000 GHz

1

–10

1

[T1] = –64.79 dB

–400.00000000 kHz

–20

–30

–40

–50

–60

–70

–80

2

[T1] = –64.58 dB

400.00000000 kHz

P

R e l a t i v e

2

1

–90

–95

Center 1.88 GHz

100 kHz/

Span 1 MHz

S097

Figure 26. Typical PCS Band Output Spectrum

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103116C

Data Sheet I CX74063-34/-35/-36

V _ R F

F

C 1 3

C 1 1

1

0 . 1 µ

V S Y

C 5

6

1

V _ R F

V

C 1 4

0 . 1 µ F

C 7

8

C

L E

T

C L

Ω

D A T A

Ω

V

R 2

S

Ω

2

C 2 6

1

R 7

3

R 1

X

5 . 6

4 3

4 2

4 1

4 0

3 9

3 8

3 7

3 6

3 5

3 4

3

3 2

3 1

3 0

2 9

C 2 7

0

L E

C 2

C L

X T A L

T x Q N

T x Q P

T x I N

T x I P

V _ R F

V

D A T A

V

G N D D

2

S

V D D B B

G N D F N

L P F A D

U

C 1 6

4

X

C 4

1

V

X

C A P Q N

U H F B Y P

U H F T U

V C C U H F

C A P Q P

+

28

N E

4

C 1 5

4

C A P I N

27

45

C A P I P

26

V C C 3

R X Q N

R X Q P

R X I N

R X I P

V C C 4

46

C 2 2

1

V C C 2

25

47

V

2

T X I F N

24

48

T X I F P

23

49

8

T X Q N

2

50

T X Q P

21

51

T X I N

20

M u l t i - B a n d

V C C T X V C O

52

T X I P

19

T X 9 0 0

53

G

18

T X 1 8 0 0 / T X 1 9 0 0

B B V A P C

54

C

T X V C O T U N E

5

17

P A V A P C

C 3

1

R X I N

R X I P

56

16

R X Q

C 2 5

1

R X E

T

P C O

V

T X I N

G

L N A 1 8 0 0 I N

P

L N A 1 9 0 0 I N

N C

P

L N A 9 0 0 I N

T

C 1

1

2

3

4

5

6

9

7

8

1 3

1 0

1

1 2

1 4

1 5

1

V _ R F

V

T

P

B

T

R

R F

L 3

Ω

V

L 2

3 .

D

6

R 8

5 0

L 1

C

1

C 2 8

Ω

C 2 4

1

C 2 1

1

C 2 3

0

R 4

5 1 0

L 4

L 5

1

R

Ω

5

R 5

3 9 0

6

4

O U T

4

O U T

3

1

G R O U N D

I N

G R O U N D

I N

F

2

V _ R F

L 6

C 8

3

Ω

2

R 3

C 1 2

P A V A

1

2 7 0

P A

G

Ω

R 6

D

C 1 8

D C

P

G

6 8 0

3

C 1 7

R

3

Figure 27. Typical CX74063-3x Application Circuit

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Data Sheet I CX74063-34/-35/-36

8.00 0.10

0.38 0.08

Pin 1

R2.70 Ref

0.50 Ref

8.00 0.10

0.30 0.05

Bottom View

Top View

1.00 0.10

Side View

C1339

All dimensions are in millimeters

Figure 28. 56-Pin RFLGA Package Dimension Drawing (CX74063-34 and CX74063-35 Options)

8.00 0.10

Pin 1

0.38 0.08

0.56 Ref

Pin 1

R2.70 Ref

0.50 Ref

8.00 0.10

R0.25

(12x)

0.30 0.05

Bottom View

Top View

Side View

1.00 0.10

S288

All dimensions are in millimeters

Figure 29. 56-Pin RFLGA Package Dimension Drawing (CX74063-36 Option)

58

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103116C

Data Sheet I CX74063-34/-35/-36

12.00 0.10

1.50 0.10

2.00 0.10

4.00 0.10

Pin #1

indicator

1.75 0.10

B

A

7 . 5 0

1

B

1.50 0.25

0.318 .02

Notes:

o

8

Max

7

Max

1. Carrier tape material: black conductive polycarbonate

or polystyrene

2. Cover tape material: transparent conductive PSA

3. Cover tape size: 13.3 mm width

4. All measurements are in millimeters

1.73 0.10

8.40 0.10

S109a

A

B

Figure 30. 56-Pin RFLGA Tape and Reel Dimensions (CX74063-34/36 Options)

12.00 0.10

2.00 0.10

4.00 0.10

1.50 0.10

1.75 0.10

B

Pin #1

indicator

A

7 . 5 0

1

B

1.50 0.25

0.318 .02

Notes:

o

8

Max

7

Max

1. Carrier tape material: black conductive polycarbonate

or polystyrene

2. Cover tape material: transparent conductive PSA

3. Cover tape size: 13.3 mm width

4. All measurements are in millimeters

1.73 0.10

8.40 0.10

S109

A

B

Figure 31. 56-Pin RFLGA Tape and Reel Dimensions (CX74063-35 Option)

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Data Sheet I CX74063-34/-35/-36

Mark Pin 1 ID (Note 1)

CX74063-DD

K16102.5

Brand line 1: Part Number (Note 2)

Brand line 2: Lot Number and Lot Split Identifier (Note 2)

Brand line 3: Date Code, Country of Origin (Note 2)

0325 USA

Note 1: The Pin 1 ID is a triangle or circle.

Note 2: Brand line 1. The Part Number format is CXPPPPP-DD. The CX prefix is the company identifier. P = five-digit part number,

D = dash number (for example, -34, -35). The CX prefix may not appear on small devices. The Part Number may be

followed by a "P" to indicate a prototype device. (Note 3)

Brand line 2. Lot Number and Lot Split Identifier. The Lot Number format = 6 alphanumeric characters followed by a 1- or

2-digit Lot Split Identifier separated by a decimal point. The format is A12345.2 or A12345.21. (Note 3)

Brand line 3. Date Code and Country of Origin. The Date Code should be the same for the entire Lot Number and Lot Split

Identifier. The first two digits of the Date Code are the current accounting calendar year. The last two digits are the current

accounting calendar week. The format is YYWW (for example, 0225). The Country of Origin is the full name of the country

where assembly is completed (for example, Mexico). The Country of Origin may be abbreviated (for example, USA or CN) if

backside marking is not possible because of size restrictions. (Note 3)

A vendor-specified logo may appear below Brand line 3 (for example, ARM).

Note 3: As long as the device form, fit, and function remain the same, the data in Brand lines 1-3 may change. For example, the Lot

Number and Lot Split Identifier may change; the Date Code and Country of Origin may change if Skyworks selects a

second assembly source.

C1403c

Figure 32. Typical Case Markings

60

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103116C

Data Sheet I CX74063-34/-35/-36

Product Revision

Ordering Information

Model Name

Manufacturing Part Number

CX74063:

MSL3/240, circular ground pad

MSL3/260, circular ground pad

MSL3/260, four-quadrant ground pad

CX74063-34

CX74063-35

CX74063-36

Information in this document is provided in connection with Skyworks Solutions, Inc. ("Skyworks") products. These materials are provided by Skyworks as a service to its

customers and may be used for informational purposes only. Skyworks assumes no responsibility for errors or omissions in these materials. Skyworks may make changes

to its products, specifications and product descriptions at any time, without notice. Skyworks makes no commitment to update the information and shall have no

responsibility whatsoever for conflicts, incompatibilities, or other difficulties arising from future changes to its products and product descriptions.

No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as may be provided in Skyworks’ Terms

and Conditions of Sale for such products, Skyworks assumes no liability whatsoever.

THESE MATERIALS ARE PROVIDED "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED, RELATING TO SALE AND/OR USE OF SKYWORKS™

PRODUCTS INCLUDING WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, PERFORMANCE, QUALITY OR NON-INFRINGEMENT OF ANY

PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. SKYWORKS FURTHER DOES NOT WARRANT THE ACCURACY OR COMPLETENESS OF THE INFORMATION,

TEXT, GRAPHICS OR OTHER ITEMS CONTAINED WITHIN THESE MATERIALS. SKYWORKS SHALL NOT BE LIABLE FOR ANY SPECIAL, INDIRECT, INCIDENTAL, OR

CONSEQUENTIAL DAMAGES, INCLUDING WITHOUT LIMITATION, LOST REVENUES OR LOST PROFITS THAT MAY RESULT FROM THE USE OF THESE MATERIALS.

Skyworks™ products are not intended for use in medical, lifesaving or life-sustaining applications. Skyworks’ customers using or selling Skyworks™ products for use in

such applications do so at their own risk and agree to fully indemnify Skyworks for any damages resulting from such improper use or sale.

The following are trademarks of Skyworks Solutions, Inc.: Skyworks™, the Skyworks symbol, “Single Package Radio”™, SPR™, and “Breakthrough Simplicity”™.

Product names or services listed in this publication are for identification purposes only, and may be trademarks of third parties. Third-party brands and names are the

property of their respective owners.

GSM™, “Global System for Mobile Communications™,” and the GSM logo are trademarks of the GSM Association. RFLGA™ is a trademark of Conexant Systems, Inc.

Additional information, posted at www.skyworksinc.com, is incorporated by reference.

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NOVEMBER 25, 2003

General Information

Skyworks Solutions, Inc.

20 Sylvan Rd.

Woburn, MA 01801

www.skyworksinc.com


型号：	CX74063-36
厂家：	SKYWORKS SOLUTIONS INC.
描述：	RF Transceiver with Power Ramping Controller and Integrated Crystal Oscillator with 13 MHz Output for Multi-Band GSM, GPRS, and EDGE Applications RF收发器，功率斜坡控制器和集成晶体振荡器与13 MHz输出的多频GSM ， GPRS和EDGE应用振荡器晶体振荡器控制器 GSM
文件：	总62页 (文件大小：1177K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CX74063-36 [SKYWORKS]

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