HC161 [SLS]
Presettable Counters; 可预置计数器
| 型号： | HC161 |
| 厂家： | 
SYSTEM LOGIC SEMICONDUCTOR |
| 描述： | Presettable Counters |
| 文件： | 总9页 (文件大小：87K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SL74HC161
Presettable Counters
High-Performance Silicon-Gate CMOS
The SL74HC161 is identical in pinout to the LS/ALS161. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.
The SL74HC161 is programmable 4-bit synchronous counter that
feature parallel Load, asynchronous Reset, a Carry Output for
cascading and count-enable controls.
The SL74HC161 is binary counter with asynchronous Reset.
·
·
·
·
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 mA
High Noise Immunity Characteristic of CMOS Devices
ORDERING INFORMATION
SL74HC161N Plastic
SL74HC161D SOIC
TA = -55° to 125° C for all packages
LOGIC DIAGRAM
PIN ASSIGNMENT
PIN 16 =VCC
PIN 8 = GND
FUNCTION TABLE
Inputs
Outputs
Q1 Q2
Reset Load
Enable
P
Enable
T
Clock
X
Q0
Q3
Function
L
H
H
H
H
H
X
L
X
X
X
L
X
X
L
L
L
L
L
Reset to “0”
Preset Data
No count
No count
Count
P0
P1
P2
P3
H
H
H
X
No change
No change
Count up
X
H
X
H
X
No change
No count
X=don’ t care
P0,P1,P2,P3 = logic level of Data inputs
Ripple Carry Out = Enable T · Q0 · Q1 · Q2 · Q3
System Logic
Semiconductor
SLS
SL74HC161
MAXIMUM RATINGS*
Symbol
Parameter
Value
-0.5 to +7.0
-1.5 to VCC +1.5
-0.5 to VCC +0.5
±20
Unit
V
VCC
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
V
IN
V
VOUT
IIN
V
mA
mA
mA
mW
IOUT
ICC
DC Output Current, per Pin
±25
DC Supply Current, VCC and GND Pins
±50
PD
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
750
500
Tstg
TL
Storage Temperature
-65 to +150
260
°C
°C
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Parameter
Min
2.0
0
Max
6.0
Unit
V
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
V , VOUT
IN
VCC
V
TA
-55
+125
°C
ns
tr, tf
Input Rise and Fall Time (Figure 1)
VCC =2.0 V
VCC =4.5 V
VCC =6.0 V
0
0
0
1000
500
400
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, V and VOUT should be constrained to the range
IN
GND£(V or VOUT)£VCC.
IN
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V ).
CC
Unused outputs must be left open.
System Logic
SLS
Semiconductor
SL74HC161
DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND)
VCC
V
Guaranteed Limit
Symbol
Parameter
Test Conditions
25 °C
to
£85
°C
£125
°C
Unit
V
-55°C
V
IH
Minimum High-Level
Input Vo ltage
VOUT=0.1 V or VCC-0.1 V
êIOUTê£ 20 mA
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
IL
Maximum Low -Level
Input Voltage
VOUT=0.1 V or VCC-0.1 V
êIOUTê £ 20 mA
2.0
4.5
6.0
0.5
1.35
1.8
0.5
1.35
1.8
0.5
1.35
1.8
V
VOH
Minimum High-Level
Output Voltage
V =V or V
IL
êIOUTê £ 20 mA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
IN
IH
V =V or V
IL
IN
IH
êIOUTê £ 6.0 mA
êIOUTê £ 7.8 mA
4.5
6.0
3.98
5.48
3.84
5.34
3.7
5.2
VOL
Maximum Low-Level
Output Voltage
V =V or V
IL
êIOUTê £ 20 mA
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
IN
IH
V =V or V
IL
IN
IH
êIOUTê £ 6.0 mA
êIOUTê £ 7.8 mA
4.5
6.0
0.26
0.26
0.33
0.33
0.4
0.4
IIN
Maximum Input
Leakage Current
V =VCC or GND
6.0
±0.1
±1.0
±1.0
mA
mA
IN
ICC
Maximum Quiescent
Supply Current
(per Package)
V =VCC or GND
6.0
4.0
40
160
IN
IOUT=0mA
System Logic
Semiconductor
SLS
SL74HC161
AC ELECTRICAL CHARACTERISTICS(CL=50pF,Input tr=tf=6.0 ns)
VCC
Guaranteed Limit
Symbol
fmax
Parameter
V
25 °C to £85°C
-55°C
£125°C
Unit
Maximum Clock Frequency (Figures 1,6)
2.0
4.5
6.0
6
5
4
20
24
MHz
30
35
24
28
tPLH
tPHL
tPHL
tPLH
2.0
4.5
6.0
120
20
16
160
23
20
200
28
22
ns
ns
ns
ns
Maximum Propagation Delay Clock to Q
(Figures 1,6)
2.0
4.5
6.0
145
22
18
185
25
20
320
30
23
Maximum Propagation Delay Reset to Q
(Figures 2 and 6)
2.0
4.5
6.0
145
20
17
185
22
19
220
25
21
2.0
4.5
6.0
110
16
14
150
18
15
190
20
17
Maximum Propagation Delay Enable T to Ripple
Carry Out
tPHL
tPLH
tPHL
tPHL
(Figures 3,6)
2.0
4.5
6.0
135
18
15
175
20
16
210
22
20
ns
ns
ns
ns
ns
pF
2.0
4.5
6.0
120
22
18
160
27
22
200
30
25
Maximum Propagation Delay Clock to Ripple
Carry Out (Figures 1,6)
2.0
4.5
6.0
145
22
20
185
28
24
220
35
28
Maximum Propagation Delay Reset to Ripple Carry 2.0
Out (Figures 2,6)
155
22
18
190
26
22
230
30
25
4.5
6.0
tTLH, tTHL Maximum Output Transition Time, Any Output
(Figures 1 and 6)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
CIN
Maximum Input Capacitance
-
10
10
10
Power Dissipation Capacitance (Per Gate)
Typical @25°C,VCC=5.0 V
CPD
Used to determine the no-load dynamic power
consumption:
30
pF
PD=CPDVCC2f+ICCVCC
System Logic
Semiconductor
SLS
SL74HC161
TIMING REQUIREMENTS (CL=50pF,Input tr=tf=6.0 ns)
VCC
V
Guaranteed Limit
Symbol
tSU
Parameter
25 °C to £85°C
£125°C
Unit
ns
-55°C
Minimum Setup Time, Preset Data Inputs to Clock
(Figure 4)
2.0
4.5
6.0
40
15
12
60
20
18
80
30
20
tSU
tSU
th
Minimum Setup Time, Load to Clock
(Figure 4)
2.0
4.5
6.0
60
15
12
75
20
18
90
30
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
Minimum Setup Time, Enable T or Enable P to
Clock (Figure 5)
2.0
4.5
6.0
80
20
17
95
25
23
110
35
25
Minimum Hold Time, Clock to Load or Preset Data
Inputs (Figure 4)
2.0
4.5
6.0
3
3
3
3
3
3
3
3
3
th
Minimum Hold Time, Clock to Enable T or Enable
P (Figure 5)
2.0
4.5
6.0
3
3
3
3
3
3
3
3
3
trec
trec
tw
Minimum Recovery Time, Reset Inactive to Clock
(Figure 2)
2.0
4.5
6.0
80
15
12
95
20
17
110
26
23
Minimum Recovery Time, Load Inactive to Clock
(Figure 4)
2.0
4.5
6.0
80
15
12
95
20
17
110
26
23
Minimum Pulse Width, Clock (Figure 1)
Minimum Pulse Width, Reset (Figure 2)
2.0
4.5
6.0
60
12
10
75
15
13
90
18
15
tw
2.0
4.5
6.0
60
12
10
75
15
13
90
18
15
tr, tf
Maximum Input Rise and Fall Times
(Figure 1)
2.0
4.5
6.0
1000
500
400
1000
500
400
1000
500
400
System Logic
Semiconductor
SLS
SL74HC161
Figure 1. Switching Waveforms
Figure 2. Switching Waveforms
Figure 3. Switching Waveforms
Figure 4. Switching Waveforms
Figure 5. Switching Waveforms
Figure 6. Test Circuit
System Logic
Semiconductor
SLS
SL74HC161
VCC=Pin 16
GND=Pin 8
The flip-flops shown in the circuit diagrams are Toggle-Enable flip-flops. A Toggle-Enable flip-flop is a
combination of a D flip-flop and a T flip-flop. When loading data from Preset inputs P0, P1, P2, and P3, the Load
signal is used to disable the Toggle input (Tn) of the flip-flop. The logic level at the Pn input is then clocked to
the Q output of the flip-flop on the next rising edge of the clock.
A logic zero on the Reset device input forces the internal clock (C) high and resets the Q output of the flip-
flop low.
Figure 7.Expanded logic diagram
System Logic
SLS
Semiconductor
SL74HC161
Sequence illustrated in waveforms:
1. Reset outputs to zero.
2. Preset to binary twelve.
3. Count to thirteen, fourteen, fifteen, zero, one, and two.
4. Inhibit.
Figure 8. Timing Diagram
System Logic
Semiconductor
SLS
SL74HC161
TYPICAL APPLICATIONS CASCADING
Note:When used in these cascaded configurations the clock fmax guaranteed limits may not apply.
Actual performance will depend on number of stages. This limitation is due to set up times
between Enable (Port) and clock.
Figure 9. N-Bit Synchronous Counters
Figure 10. Nibble Ripple Counter
System Logic
Semiconductor
SLS
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