SL3010 [SLS]

INFRARED REMOTE CONTROL TRANSMITTER RC-5; 红外遥控发射器RC- 5
SL3010
型号: SL3010
厂家: SYSTEM LOGIC SEMICONDUCTOR    SYSTEM LOGIC SEMICONDUCTOR
描述:

INFRARED REMOTE CONTROL TRANSMITTER RC-5
红外遥控发射器RC- 5

遥控 远程控制
文件: 总8页 (文件大小:99K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
SL3010  
INFRARED REMOTE CONTROL  
TRANSMITTER RC-5  
The SL3010 is intended as a general purpose (RC-5) infrared  
remote control system for use where a low voltage supply and a large  
debounce time are expected. The device can generate 2048 different  
commands and utilizes a keyboard with a single pole switch for each  
key. The command are arranged so that 32 systems can be addressed,  
each  
system containing 64 different commands. The keyboard  
interconnection is illustrated by Fig.1.  
·
·
·
·
Low voltage requirement  
Single pin oscillator  
Biphase transmission technique  
Test mode facility  
ORDERING INFORMATION  
SL3010N Plastic  
SL3010D SOIC  
TA = -25° to 85° C  
for all packages.  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
System Logic  
Semiconductor  
SLS  
SL3010  
PIN DESCRIPTION  
PIN No  
DESIGNATION  
DESCRIPTION  
1
2
3-6  
7
X7 (IPU)  
SSM (I)  
Z0-Z3 (IPU)  
MDATA (OP3)  
sense input from key matrix  
system mode selection input  
sense inputs from key matrix  
generated output data modulated with 1/2 the oscillator frequency at a 25%  
duty factor  
8
9-13  
14  
DATA (OP3)  
DR7-DR3 (ODN)  
GND  
generated output information  
scan drivers  
ground (0V)  
15-17  
18  
19  
DR2-DR0 (ODN)  
OSC (I)  
TP2 (I)  
scan drivers  
oscillator input  
test point 2  
20  
TP1 (I)  
test point 1  
21-27  
28  
X0-X6 (IPU)  
Vcc (I)  
sense inputs from key matrix  
voltage supply  
(I)  
(IPU)  
= input  
= input with p-channel pull-up transistor  
(ODN) = output with open drain n-channel transistor  
(OP3) = output 3-state  
FUNCTIONAL DESCRIPTION  
Keyboard operation  
Every connection of one X-input and one DR-output will be recognized as a legal key operation and will cause  
the device to generate the corresponding code. The same applies to every connection of one Z-input to one DR-  
output with the proviso that SSM must be LOW. When SSM is HIGH a wired connection must exist between a Z-  
input and DR-output. If no connection is present the system number will not be generated. Activating two or  
more X-inputs, Z-inputs or Z-inputs and X-inputs at the same time is an illegal action and inhibits further activity  
(oscillator will not start).  
When one X- or Z-input is connected to more than one DR-output, the last scan signal will be considered as legal.  
The maximum value of the contact series resistance of the switched keyboard is 7KW.  
Inputs  
In the quiescent state the command inputs X0 to X7 are held HIGH by an internal pull-up transistor. When the  
system mode selection (SSM) input is LOW and the system is quiescent, the system inputs Z0 to Z3 are also held  
HIGH by an internal pull-up transistor. When SSM is HIGH the pull-up transistor for the Z-inputs is switched off,  
in order to prevent current flow, and a wired connection in the Z-DR matrix provides the system number.  
Outputs  
The output signal DATA transmits the generated information in accordance with the format illustrated by Fig.2  
and Tables 1 and 2. The code is transmitted using a biphase technique as illustrated by Fig.3. The code consists  
of four parts:  
·
·
·
·
Start part - 1.5 bits (2 x logic 1)  
Control part - 1 bit  
System part - 5 bits  
Command part - 6 bits  
The output signal MDATA transmits the generated information modulated by 1/12 of the oscillator frequency  
with a 50% duty factor.  
In the quiescent state both DATA and MDATA are non-conducting (3-state outputs).  
The scan driver outputs DR0 to DR7 are open drain n-channel transistors and conduct when the circuit is  
quiescent. After a legal key operation the scanning cycle is started and the outputs switched to the conductive  
state one by one. The DR-outputs were switched off at the end of the preceding debounce cycle.  
System Logic  
SLS  
Semiconductor  
SL3010  
Table 1 Command matrix (X-DR)  
Code  
no.  
0
1
2
3
4
5
6
X-lines  
DR-lines  
Command bits  
0
x
x
x
x
x
x
x
x
1
2
3
4
5
6
7
0
x
1
x
2
x
3
4
5
x
6
x
7
x
x
x
x
x
x
5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
x
x
7
8
9
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
System Logic  
Semiconductor  
SLS  
SL3010  
Table 1 Command matrix (X-DR) (Continued)  
Code  
no.  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
X-lines  
DR-lines  
Command bits  
0
1
2
3
4
5
6
x
x
x
x
x
x
x
7
0
1
x
2
x
3
4
5
x
6
x
7
5
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
3
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
2
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
6
x
7
Table 2 System matrix (Z-DR)  
Code  
no.  
0
1
2
3
4
5
6
X-lines  
DR-lines  
System bits  
0
x
x
x
x
x
x
x
x
1
2
3
4
5
6
7
0
x
1
x
2
x
3
4
5
x
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
3
2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
x
x
x
x
x
x
7
8
9
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
System Logic  
Semiconductor  
SLS  
SL3010  
MAXIMUM RATINGS*  
Symbol  
Parameter  
Value  
Unit  
V
VCC  
DC Supply Voltage (Referenced to GND)  
DC Input Voltage (Referenced to GND)*  
DC Output Voltage (Referenced to GND)*  
DC Input Current  
-0.5 to +8.5  
V
IN  
-0.5 to VCC +0.5  
V
VOUT  
IIN  
-0.5 to VCC +0.5  
V
±10  
mA  
mA  
±10  
IOUT  
DC Output Current  
Maximum Power Dissipation  
OSC output  
other outputs  
PDO  
PDO  
50  
100  
mW  
mW  
PD  
Power Dissipation in Still Air  
Storage Temperature  
200  
mW  
Tstg  
-65 to +150  
°C  
*VCC + 0.5 must not exceeed 9.0V..  
*Maximum Ratings are those values beyond which damage to the device may occur.  
Functional operation should be restricted to the Recommended Operating Conditions.  
+Derating - Plastic DIP: - 10 mW/°C from 65° to 85°C  
SOIC Package: : - 7 mW/°C from 65° to 85°C  
RECOMMENDED OPERATING CONDITIONS  
Symbol  
VCC  
V
IH  
Parameter  
Min  
Max  
Unit  
DC Supply voltage (Reference to GND)  
DC Input voltage (HIGH)  
2.0  
0.7VCC  
7.0  
VCC  
V
V
V
VOUT  
IIN  
DC Input voltage (LOW)  
DC Output Voltage (MDATA, DATA)  
DC Input Current  
0
-
-
0.3VCC  
7.0  
±10  
V
V
mA  
IL  
IOL  
DC Output Current (LOW)  
pins 7,8  
-
0.6  
0.3  
mA  
pins 9-13; 15-17  
-
-0.4  
mA  
oC  
IOH  
TA  
DC Output Current (MDATA, DATA)  
-25  
85  
Operating Temperature, All Package Types  
This device contains protection circuitry to guard against damage due to high static voltages or electric  
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated  
voltages to this high-impedance circuit. For proper operation, V and VOUT should be constrained to the range  
IN  
GND£(V or VOUT)£VCC.  
IN  
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V ).  
CC  
Unused outputs must be left open.  
System Logic  
SLS  
Semiconductor  
SL3010  
DC ELECTRICAL CHARACTERISTICS (Voltage Reference to GND)  
(VCC= 2.0 to 7.0V unless otherwise specified, TA=-25 to +70°C)  
Guaranteed Limits  
Symbol  
ICC  
Parameter  
Test Conditions  
Min  
Max  
Unit  
Quiscent supply  
current  
UIL=0B; V =VCC  
40  
mA  
IH  
IOUT=0 mA at all outputs  
INPUTS  
IIN  
Input current  
Pins 01, 03-06; 21-27  
Pin 18  
V =0V  
mA  
mA  
IL  
-10  
3.0  
-600  
33  
V =0V; V =VCC  
IL  
IH  
ILI  
Input leakage current  
Pins 01-06;19-27  
Pin 18  
V =0V; V =VCC  
IL IH  
-
-
±10  
-20  
OUTPUTS  
VOH  
Output voltage HIGH, IOH=-0.4mA  
VCC-0.3  
-
-
V
V
pins 07-08  
V =0.3 VCC  
IL  
VOL  
Output voltage LOW  
Pins 07-08  
IOL=0.6mA  
0.3  
V =0V, VHI=0.7VCC  
IL  
Pins 9-13; 15-17  
IOL=0.3mA, V =0V,  
V =0.7VCC  
IH  
-
-
0.3  
10  
V
IL  
ILO  
ILO  
IOH  
Output leakage  
current  
VO=VCC, V =VCC, VOH=VCC  
mA  
IH  
Pins 07-13; 15-17  
-
-
Output leakage  
current  
VO=0V, V =VCC, VOL=0V  
-20  
10  
mA  
mA  
IH  
Pins 07-08  
-
DC Output Current  
Pins 9-13; 15-17  
V =0V; V =VCC; VOH=VCC  
IL  
IH  
AC ELECTRICAL CHARACTERISTICS  
TA=-25 to +85°C; VCC=2.0 to 7.0 V unless otherwise specified  
Symbol  
Parameter  
Test Condition  
Guaranteed Limits  
Typ  
Max  
Unit  
Oscillator frequency  
operational  
CL=160pF  
fOSC  
432  
450  
KHz  
System Logic  
Semiconductor  
SLS  
SL3010  
Figure 1. Keyboard interconnection  
System Logic  
Semiconductor  
SLS  
SL3010  
Where: debounce time+scan time=18 bit-temes  
repetition time=4x16 bit times  
Figure 2. Data output format  
Where: 1 bit-time=3.28 x TOSC=1.778 ms (typ.)  
Figure 3. Biphase transmission technique  
System Logic  
Semiconductor  
SLS  

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