SL4001B [SLS]
Quad 2-Input NOR Gate; 四路2输入NOR门型号: | SL4001B |
厂家: | SYSTEM LOGIC SEMICONDUCTOR |
描述: | Quad 2-Input NOR Gate |
文件: | 总4页 (文件大小:34K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
SL4001B
Quad 2-Input NOR Gate
High-Voltage Silicon-Gate CMOS
The SL4001B NOR gates provide the system designer with direct
emplementation of the NOR function.
·
·
Operating Voltage Range: 3.0 to 18 V
Maximum input current of 1 mA at 18 V over full package-
temperature range; 100 nA at 18 V and 25°C
Noise margin (over full package temperature range):
1.0 V min @ 5.0 V supply
·
ORDERING INFORMATION
2.0 V min @ 10.0 V supply
2.5 V min @ 15.0 V supply
SL4001BN Plastic
SL4001BD SOIC
TA = -55° to 125° C for all packages
LOGIC DIAGRAM
PIN ASSIGNMENT
FUNCTION TABLE
Inputs
Output
A
L
B
L
Y
H
L
L
L
PIN 14 =VCC
PIN 7 = GND
L
H
L
H
H
H
System Logic
SLS
Semiconductor
SL4001B
MAXIMUM RATINGS*
Symbol
Parameter
Value
-0.5 to +20
-0.5 to VCC +0.5
-0.5 to VCC +0.5
±10
Unit
V
VCC
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
V
IN
V
VOUT
IIN
V
mA
mW
PD
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
750
500
PD
Tstg
TL
Power Dissipation per Output Transistor
Storage Temperature
100
-65 to +150
260
mW
°C
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
°C
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Parameter
Min
3.0
0
Max
18
Unit
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
V
V
V , VOUT
IN
VCC
TA
-55
+125
°C
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, V and VOUT should be constrained to the range
IN
GND£(V or VOUT)£VCC.
IN
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V ).
CC
Unused outputs must be left open.
System Logic
SLS
Semiconductor
SL4001B
DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND)
VCC
V
Guaranteed Limit
Symbol
Parameter
Test Conditions
VOUT=0.5V
VOUT=1.0 V
VOUT=1.5V
³ -55°C
25°C
£125
°C
Unit
V
V
IH
Minimum High-Level
Input Voltage
5.0
10
15
3.5
7
3.5
7
3.5
7
11
11
11
V
Maximum Low -Level VOUT=0.5 V or VCC - 0.5 V
5.0
10
15
1.5
3
4
1.5
3
4
1.5
3
4
V
V
V
IL
Input Voltage
VOUT=1.0 V or VCC - 1.0 V
VOUT=1.5 V or VCC - 1.5 V
VOH
Minimum High-Level
Output Voltage
V =GND
IN
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
4.95
9.95
14.95
VOL
Maximum Low-Level
Output Voltage
V =GND or VCC
IN
5.0
10
15
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
IIN
Maximum Input
Leakage Current
V = GND or VCC
18
±0.1
±0.1
±1.0
mA
mA
IN
ICC
Maximum Quiescent
Supply Current
(per Package)
V = GND or VCC
IN
5.0
10
15
20
0.25
0.5
1.0
5.0
0.25
0.5
1.0
5.0
7.5
15
30
150
IOL
Minimum Output Low V = GND or VCC
mA
mA
IN
(Sink) Current
UOL=0.4 V
UOL=0.5 V
UOL=1.5 V
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.36
0.9
2.4
IOH
Minimum Output High V = GND or VCC
IN
(Source) Current
UOH=2.5 V
UOH=4.6 V
UOH=9.5 V
UOH=13.5 V
5.0
5.0
10
-2.0
-0.64
-1.6
-1.6
-0.51
-1.3
-1.15
-0.36
-0.9
15
-4.2
-3.4
-2.4
System Logic
Semiconductor
SLS
.
SL4001B
AC ELECTRICAL CHARACTERISTICS(CL=50pF, RL=200kW, Input tr=tf=20 ns)
VCC
V
Guaranteed Limit
Symbol
Parameter
³ -55°C
25°C
£125°C
Unit
ns
tPLH, tPHL Maximum Propagation Delay, Input A or B to
Output Y (Figure 1)
5.0
10
15
250
120
90
250
120
90
500
240
180
tTLH, tTHL Maximum Output Transition Time, Any Output
(Figure 1)
5.0
10
15
200
100
80
200
100
80
400
200
160
ns
CIN
Maximum Input Capacitance
-
7.5
pF
Figure 1. Switching Waveforms
EXPANDED LOGIC DIAGRAM
(1/4 of the Device)
System Logic
Semiconductor
SLS
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