KBD42W11 [SMSC]
Keyboard controller is programmed to support; 键盘控制器被编程，以支持
| 型号： | KBD42W11 |
| 厂家： | 
SMSC CORPORATION |
| 描述： | Keyboard controller is programmed to support |
| 文件： | 总16页 (文件大小：101K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
KBD42W11
Keyboard Controller
FEATURES
·
·
·
Supports IBM PC and Compatible System
Designs
Runs Much Faster Than Traditional
Keyboard Controllers
Host interface Compatible with Traditional
Keyboard Controller
·
·
·
·
6 MHz – 12 MHz Operating Frequency
Communicates with Keyboard Directly
High-reliability CMOS Technology
40 Pin DIP and 44 Pin PLCC Package
GENERAL DESCRIPTION
The KBD42W11 keyboard controller is
programmed to support the IBM® compatible
personal computer keyboard serial interface. The
keyboard controller receives serial data from the
keyboard, checks the parity of the data,
translates the scan code, and presents the data
to the system as a byte of data in its output
buffer. The controller will interrupt the system
when data is placed in its output buffer. The byte
of data will be sent to the keyboard serially with
an odd parity bit automatically inserted. The
keyboard is required to acknowledge all data
transmissions. No transmission should be sent to
the keyboard until acknowledgment is received
for the previous byte sent.
is used in this keyboard controller instead of a
software implementation, as in the traditional
8042 keyboard BIOS. This enables the keyboard
controller to respond instantly to all commands
sent from the keyboard to the CPU BIOS.
The KBD42W11 enables popular programs such
as AutoCAD®, Microsoft® Windows™, NOVELL®,
and other programs to run much faster.
IBM is a registered trademark of International Business
Machines Corporation. AutoCAD is a registered trademark
of Autodesk, Inc. Microsoft is a registered trademark and
Windows is
a trademark of Microsoft Corporation.
NOVELL is a registered trademark of Novell, Inc.
Standard Microsystems is
a registered trademark and
SMSC is trademark of Standard Microsystems
a
The KBD42W11 keyboard controller and BIOS to
improve the performance of IBM PC machines
and their compatibles. A hardwire methodology
Corporation. Other product and company names are
trademarks or registered trademarks of their respective
holders.
TABLE OF CONTENTS
FEATURES....................................................................................................................................... 1
GENERAL DESCRIPTION ................................................................................................................ 1
PIN CONFIGURATION...................................................................................................................... 3
PIN DESCRIPTION ........................................................................................................................... 4
BLOCK DIAGRAM............................................................................................................................ 5
AC TIMING........................................................................................................................................ 6
TIMING WAVEFORMS...................................................................................................................... 7
WRITE CYCLE TIMING ........................................................................................................................ 7
READ CYCLE TIMING.......................................................................................................................... 7
SEND DATA TO K/B........................................................................................................................... 8
RECEIVE DATA FROM K/B................................................................................................................... 8
XIN/XOUT CLOCK ........................................................................................................................... 8
ABSOLUTE MAXIMUM RATINGS..................................................................................................... 9
ELECTRICAL CHARACTERISTICS & CAPACITANCE..................................................................... 9
STATUS REGISTER ....................................................................................................................... 10
OUTPUT BUFFER........................................................................................................................... 10
INPUT BUFFER .............................................................................................................................. 10
I/O PORTS...................................................................................................................................... 10
COMMANDS (I/O ADDRESS HEX 64)............................................................................................. 12
APPLICATION CIRCUIT ................................................................................................................. 13
ASYNCHRONOUS............................................................................................................................. 13
SYNCHRONOUS............................................................................................................................... 14
PACKAGE DIMENSIONS................................................................................................................ 15
80 Arkay Drive
Hauppauge, NY 11788
(516) 435-6000
FAX (516) 273-3123
2
PIN CONFIGURATION
T0
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
V
DD
T1
1
2
3
4
5
6
7
8
X
IN
X
P27(KDAT)
P26(KCLK)
P25(IEMP)
P24(INIT)
P17(KINH)
P16(DISP)
P15(JUMP)
P14(RAM)
P13
P12
P11
P10
NC
OUT
nRESET
VDD
nCS
VSS
nRD
A2
9
nWR
NC
D0
D1
D2
D3
D4
D5
D6
10
11
12
13
14
15
16
17
18
19
20
40 Pin DIP
VDD
P23
P22
P21(nGA20)
P20(nRC)
D7
VSS
nCS
39
7
8
9
P24
38
37
36
35
34
33
32
31
30
29
VSS
nRD
A2
nWR
NC
NC
D0
D1
D2
D3
P17
P18
P15
P14
NC
P13
P12
P11
P10
NC
10
11
12
13
14
15
16
17
44 Pin PLCC
3
PIN DESCRIPTION
PIN NO.
PIN NO.
(40 Pin DIP)
(44 Pin PLCC)
I/O
I
I
O
I
-
I
NAME
T0
XIN
XOUT
nRESET
VDD
nCS
FUNCTION
K/B Clock Input
Crystal Clock I/P
Crystal Clock O/P
Chip Reset
1
2
3
4
5
2
3
4
5
6
Optional +5V Power Supply
Chip Select
6
7
7
8
8
9
-
I
VSS
nRD
Optional Ground Power
I/O Read
9
10
10
11
I
I
-
A2
nWR
NC
Connect to Address A2
I/O Write
Reserved
11,26
12,13,14,
15,16,17,
18, 19
20
1,12,13,23,29, 34
14,15,16,17,18,
19,20,21
I/O
D0-D7
Data Bus D0 - D7
22
24
-
O
VSS
P20
Ground Power Supply
Bit 0 of Port 2 (RCB: System
Reset)
21
22
23
24
25
27
28
29
30
31
25
26
27
28
30
31
32
33
35
O
I/O
I/O
-
I/O
I/O
I/O
I/O
I
P21
P22
P23
VDD
P10
P11
P12
P13
P14
Bit 1 of Port 2 (GA20: GATE A20)
Bit 2 of Port 2
Bit 3 of Port 2
Optional +5V Power Supply
Bit 0 of Port 1
Bit 1 of Port 1
Bit 2 of Port 1
Bit 3 of Port 1
Bit 4 of Port 1 (RAM Jumper
Select)
32
33
34
35
36
37
38
39
40
36
37
38
39
40
41
42
43
44
I
I
I
O
O
O
O
I
P15
P16
P17
P24
P25
P26
P27
T1
Bit 5 of Port 1 (JUMP)
Bit 6 of Port 1 (Display Select)
Bit 7 of Port 1 (K/B Inhibit Switch)
Bit 4 of Port 2 (OBF O/P Interrupt)
Bit 5 of Port 2 (I/P Buffer Empty)
Bit 6 of Port 2 (K/B Clock O/P)
Bit 7 of Port 2 (K/B Data O/P)
K/B Data Input
-
VDD
+5V Power Supply
4
BLOCK DIAGRAM
TRANSMIT
CONTROL
T0
T1
RECEIVE
SCAN
CODE
ROM
CONTROL
TRANSMIT
REGISTER
XOUT
XIN
HARDWIRE
CONTROL &
SELECT
nWR
nRD
STATUS
REGISTER
nCS
A2
LOGIC
nRESET
P10
P11
STATUS
BUFFER
REGISTER
R64
INPUT &
OUTPUT
PORT
P12
P13
W60
W64
P14 (RAM Select)
P15 (Manufacture Mode)
DATA
BUFFER
INPUT
BUFFER
REGISTER
D0- D7
INTERFACE
P16 (Display)
P17 (KBNH)
REGISTER
OUTPUT
BUFFER
REGISTER
R60
(nRC)
P20
P21 (Gate A20)
P22
P23
P24
P25
OUTPUT
PORT
INTERFACE
P26 (Keyboard Clock)
(Keyboard Data)
P27
5
AC TIMING
NO.
T1
T2
T3
T4
T5
T6
T7
T8
DESCRIPTION
Address Setup Time from nWR
Address Setup Time from nRD
nWR Strobe Width
MIN.
0
0
20
20
0
0
50
0
MAX.
UNIT
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
mS
mS
mS
mS
mS
mS
mS
mS
mS
nS
nRD Strobe Width
Address Hold Time from nWR
Address Hold Time from nRD
Data Setup Time
Data Hold Time
T9
Gate Delay Time from nWR
nRD to Drive Data Delay
nRD to Floating Data Delay
Data Valid After Clock Falling (SEND)
K/B Clock Period
10
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
20
20
4
0
20
10
4
20
2
K/B Clock Pulse Width
Data Valid Before Clock Falling (RECEIVE)
K/B ACK After Finish Receiving
nRC Fast Reset Pulse Delay (8 MHz)
nRC Pulse Width (8 MHz)
Transmit Timeout
3
2
6
Data Valid Hold Time
XIN/XOUT Period ( 6-12 MHz )
0
83
167
6
TIMING WAVEFORMS
Write Cycle Timing
A2, nCS
T1
T5
T3
nWR
ACTIVE
T8
T7
D0 - D7
DATA IN
T9
A20
OUTPUT PORT
T18
T17
FAST RESET PULS nRC
FE COMMAND
Read Cycle Timing
A2, nCS
AEN
T2
T6
T4
ACTIVE
nRD
T10
T11
D0 - D7
DATA OUT
7
Send Data to K/B
CLOCK
( KCLK )
T12
T13
D4
T16
T14
SERIAL DATA
( KDAT )
START
D0
D1
D2
D3
D5
D6
D7
P
STOP
T19
Receive Data from K/B
CLOCK
( KCLK )
T15
T13
T14
D2
SERIAL DATA
( T1 )
START
T20
D0
D1
D3
D4
D5
D6
D7
P
STOP
XIN/XOUT Clock
XIN CLK
T21
8
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Ambient Operating Temperature
Storage Temperature
Supply Voltage to Ground Potential
Applied Input/Output Voltage
Power Dissipation
RATING
-0 to +85
-65 to +150
-0.3 to +7.0
-0.3 to +7.0
50
UNIT
°C
°C
V
V
mW
Note:
Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely
affect the life and reliability of the device.
ELECTRICAL CHARACTERISTICS & CAPACITANCE
(Ta = 0° C to +70° C, VDD = +5V ±5%)
SYMBOL
VDD
DESCRIPTION
Power Supply
Operating Temperature
MIN.
4.75
0
TYP.
5.0
25
MAX.
5.25
70
UNIT
V
V
V
TA
VIH
High Level Voltage for TTL Min.
2.0
VDD
I/P
VIL
VOH
VOL
Low Level Voltage for TTL Max.
I/P
High Level Voltage for TTL Min.
O/P
-0.3
0.8
0.5
V
V
V
VDD-0.5
Low Level Voltage for TTL Max.
O/P
RIP
ILI
ILO
IOL
CL
Min. I/P Resist
10K
-10
-10
4
W
mA
mA
mA
pF
I/P Leakage Current
O/P Leakage Current
O/P Sink Current
10
10
O/P Load Capacity
15
50
9
STATUS REGISTER
The status register is an 8-bit read-only register at I/O address hex 64 that holds information about the
state of the keyboard controller and interface. It may be read at any time.
BIT
BIT DESCRIPTION
FUNCTION
0
Output Buffer Full
0: Output Buffer Empty
1: Output Buffer Full
0: Input Buffer Empty
1: Input Buffer Full
This bit may be set to 0 or 1 by writing to the system flag bit in
the command byte of the keyboard controller. It is set to 0 after a
power-on reset
1
2
Input Buffer Full
System Flag
3
4
5
6
7
Command/data
Inhibit Switch
0: Data Byte
1: Command Byte
0: Keyboard is Inhibited
1: Keyboard is Not Inhibited
0: No Transmit Time Out Error
1: Transmit Time Out Error
0: No Receive Time Out Error
1: Receive Time Out Error
Transmit Time Out
Receive Time Out
Parity Error
0: Odd Parity (No Error)
1: Even Parity (Error)
OUTPUT BUFFER
The output buffer is an 8-bit read-only register at I/O address hex 60. The keyboard controller uses the
output buffer to send the scan code received from the keyboard and data bytes required by command to
the system. The output buffer should be read only when the output buffer full bit in the register is 1.
INPUT BUFFER
The input buffer is an 8-bit write-only register at I/O address hex 60 or 64. Writing to address hex 60
sets a flag that indicates a data write; writing to address hex 64 sets a flag that indicates a command
write. Data written to I/O address hex 60 are sent to the keyboard (unless the keyboard controller is
expecting a data byte) following the controller's input buffer only if the input buffer full bit in the status
register is set to 0.
I/O PORTS
The keyboard controller has two 8-bit I/O ports and two test inputs. One of the ports is assigned for
input and the other for output. The controller uses the test inputs to read the state of the keyboard's
clock line and data line.
10
The following figures show bit definitions for the input, output, and test-input ports.
(A) Input Port Definitions
BIT
0
FUNCTION
Undefined
1
Undefined
2
Undefined
3
Undefined
4
RAM on System Board
0: Disable 2nd 256 KB of System Board RAM
1: Enable 2nd 256 KB of System Board RAM
Manufacturing Jumper Installed
0: Manufacturing Jumper
1: Jumper Not Installed
Display Type Switch
0: Primary Display Attached to Color/graphics
0: Primary Display Attached to Monochrome
Keyboard Inhibit Switch
5
6
7
0: Keyboard Inhibited
1: Keyboard Not Inhibited
(B) Output Port Definitions
BIT
FUNCTION
0
1
2
3
4
5
6
7
System Reset
Gate A20
Undefined
Undefined
Output Buffer Full
Input Buffer Empty
Keyboard Clock (Output)
Keyboard Data (Output)
(C) Test-Input Definitions
BIT
FUNCTION
0
1
Keyboard Clock (Input)
Keyboard Data (Input)
11
COMMANDS (I/O ADDRESS HEX 64)
COMMAND
FUNCTION
20
60
Read Command Byte of Keyboard Controller
Write Command Byte of Keyboard Controller
BIT
7
BIT DEFINITIONS
Reserved
6
5
IBM PC Compatible Mode
IBM PC Mode
4
3
Disable Keyboard
Inhibit Override
2
System Flag
1
Reserved
0
Enable Output Buffer Full Interrupt
AA
Self-test
BIT
00
BIT DEFINITIONS
No Error Detected
01
02
03
04
K/B Clock Line is Stuck Low
K/B Clock Line is Stuck High
K/B Data Line is Stuck Low
K/B Data Line is Stuck High
AB
AD
AE
Interface Test
Disable Keyboard Feature
Enable Keyboard Interface
Read Input Port
C0
D0
D1
E0
Read Output Port
Write Output Port
Read Test Inputs
F0-FF
Pulse Output Port
12
APPLICATION CIRCUIT
Asynchronous
25
2
X1
V
DD
27
28
29
30
31
32
33
34
P10
P11
P12
P13
P14
P15
P16
P17
3
X2
4
RESET
RESETB
SA2
RAM SELECT JUMPER
1
39
9
T0
MANUFACTURING MODE JUMPER
T1
A2
6
nCS
DISPLAY TYPE SWITCH
5
DD
V
21
22
23
24
35
36
37
38
8
nRD
IORB
IOWB
D0 - D7
RCB
P20
P21
10
nWR
GATE A20
KEYBOARD INHIBIT SWITCH
KEYBOARD INTERRUPT
P22
12
13
14
15
16
17
18
19
D0
D1
D2
D3
D4
D5
D6
D7
P23
P24/OB
P25/nBF
P26/KCLK
P27/KDAT
KEYBOARD CLOCK
11
KEYBOARD DATA
NC
V
DD
7
V
SS
U?A
U?A
1
2
1
3
2
4
KEYBOARD CLOCK
KEYBOARD DATA
VCC
74ALS04
7407
U?B
7407
13
Synchronous
2
3
PCLK
X1
X2
27
28
29
30
31
32
33
34
P10
P11
P12
4
1
RESETB
SA2
RAM SELECT JUMPER
MANFACTURING MODE JUMPER
RESET
T0
T1
A2
nCS
P13
P14/RAM
P15/MOD
P16/DIS
P17/INH
39
9
6
DISPLAY TYPE SWITCH
8
21
22
23
24
35
36
37
38
nRD
nWR
IORB
IOWB
D0 - D7
RCB
P20/RCB
P21/A20
P22
10
GATE A20
KEYBOARD INHIBIT SWITCH
KEYBOARD INTERRUPT
12
13
14
15
16
17
18
19
D0
D1
D2
D3
D4
D5
D6
D7
P23
P24
P25
P26/KCLK
P27/KDAT
KEYBOARD CLOCK
KEYBOARD DATA
VDD
U?A
U?A
1
2
1
3
2
KEYBOARD CLOCK
DD
V
74ALS04
7407
U?B
4
KEYBOARD DATA
7407
14
PACKAGE DIMENSIONS
40 Pin PDIP
Dimension in inch
Dimension in mm
Symbol
A
1
A
A2
Nom.
Nom.
Min.
Max. Min.
0.210
Max.
5.33
0.010
0.150
0.25
0.155 0.160
3.81
0.41
1.22
0.20
3.94
0.46
1.27
0.25
4.06
0.56
1.37
0.36
0.016 0.018
0.022
0.054
B
0.050
0.048
0.008
1
B
c
0.010 0.014
2.055 2.070
52.20 52.58
D
E
1
E
D
15.49
13.97
2.79
0.610
15.24
0.590 0.600
14.99
40
21
13.72 13.84
0.540
0.545
0.550
0.110
0.090 0.100
2.29
3.05
0
2.54
3.30
e1
0.120
0
0.140
15
0.130
3.56
15
L
a
1
E
17.02
0.630 0.650 0.670 16.00 16.51
0.090
A
e
S
2.29
Notes:
1
20
1. Dimensions D Max & S include mold flash or
tie bar burrs.
E
S
2. Dimension E1 does not include interlead flash.
c
2
1
A
3. Dimensions D & E1 include mold mismatch and
A
A
L
.
Base Plane
are determined at the mold parting line.
4. Dimension B1 does not include dambar
protrusion/intrusion.
Seating Plane
5. Controlling dimension: Inches.
6. General appearance spec. should be based on
final visual inspection spec.
B
e1
eA
a
B1
44 Pin PLCC
H D
D
1
Dimension in inch
Dimension in mm
6
44
40
Symbol
A
Nom.
Nom.
Min.
Max. Min.
0.185
Max.
4.70
7
39
0.020
0.51
1
A
2
A
b
b
c
0.145 0.150
0.026 0.028
3.68 3.81
3.94
0.81
0.56
0.36
0.155
1
0.032 0.66
0.71
0.022
0.016 0.018
0.41 0.46
E
H
E
G
E
0.008 0.010 0.014 0.20 0.25
16.46 16.59 16.71
0.648 0.653 0.658
D
16.59
0.653
16.46
16.71
0.648
0.658
BSC
0.630
E
e
1.27 BSC
0.050
0.590
0.590
0.680
0.680
0.090
14.99
16.00
16.00
15.49
0.610
D
G
G
H
HE
L
y
17
29
14.99 15.49
0.610 0.630
0.690 0.700
E
17.27 17.53 17.78
17.27 17.53 17.78
D
18
28
c
0.690 0.700
0.100
2.54
2.79
0.10
0.110 2.29
0.004
L
Notes:
2
A
1. Dimensions D & E do not include interlead
flash.
A
2. Dimension b1 does not include dambar
protrusion/intrusion
3. Controlling dimension: Inches
4. General appearance spec. should be based
on final visual inspection spec.
1
e
b
A
y
b1
Seating Plane
G D
15
© 1998 STANDARD MICROSYSTEMS CORPORATION (SMSC)
Circuit diagrams utilizing SMSC products are included as a means of illustrating typical applications; consequently complete
information sufficient for construction purposes is not necessarily given. The information has been carefully checked and is believed
to be entirely reliable. However, no responsibility is assumed for inaccuracies. Furthermore, such information does not convey to the
purchaser of the semiconductor devices described any licenses under the patent rights of SMSC or others. SMSC reserves the right
to make changes at any time in order to improve design and supply the best product possible. SMSC products are not designed,
intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to
personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further
testing and/or modification will be fully at the risk of the customer.
KBD42W11 Rev. 10/20/98
相关型号：
KBE00D002M-F4070
Memory Circuit, 16MX16, CMOS, PBGA137, 10.50 X 13 MM, 0.80 MM PITCH, FBGA-137
SAMSUNG
KBE00F005A-D4110
Memory Circuit, Flash+SDRAM, 8MX32, CMOS, PBGA137, 10.50 X 13 MM, 0.80 MM PITCH, LEAD FREE, FBGA-137
SAMSUNG
©2020 ICPDF网 联系我们和版权申明