USB3613-1080XY [SMSC]
USB 2.0 Hi-Speed 3-Port Hub Controller Optimized for Portable Applications; USB 2.0高速3端口集线器控制器经过优化，用于便携式应用
| 型号： | USB3613-1080XY |
| 厂家： | 
SMSC CORPORATION |
| 描述： | USB 2.0 Hi-Speed 3-Port Hub Controller Optimized for Portable Applications |
| 文件： | 总68页 (文件大小：878K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
USB3613
USB 2.0 Hi-Speed 3-Port Hub Controller
Optimized for Portable Applications
Datasheet
PRODUCT FEATURES
Highlights
Additional Features
Hub Controller IC with 3 downstream ports
High-Speed Inter-Chip (HSIC) support
MultiTRAKTM
—
Dedicated Transaction Translator per port
PortMap
—
HSIC upstream port
—
1 downstream HSIC port
—
Configurable port mapping and disable sequencing
USB-IF Battery Charger revision 1.2 support on up &
downstream ports (DCP, CDP, SDP)
PortSwap
—
Configurable differential intra-pair signal swapping
®
PHYBoostTM
Battery charging support for Apple devices
—
Programmable USB transceiver drive strength for
FlexConnect: Downstream port 1 able to swap with
upstream port, allowing master capable devices to
control other devices on the hub
USB to I2CTM/SPI bridge endpoint support
USB Link Power Management (LPM) support
SUSPEND pin for remote wakeup indication to host
Vendor Specific Messaging (VSM) support
recovering signal integrity
VariSenseTM
—
Programmable USB receiver sensitivity
Low power operation
Full Power Management with individual or ganged
power control of each downstream port
Built-in Self-Powered or Bus-Powered internal default
settings provide flexibility in the quantity of USB
expansion ports utilized without redesign
Enhanced OEM configuration options available
through OTP or SMBus Slave Port
Flexible power rail support
Supports “Quad Page” configuration OTP flash
—
—
—
—
VBUS or VBAT only operation
3.3V only operation
VBAT + 1.8V operation
3.3V + 1.8V operation
—
Four consecutive 200 byte configuration pages
Fully integrated USB termination and Pull-up/Pull-
down resistors
On-chip Power On Reset (POR)
30-ball (2.9x2.5mm) WLCSP, RoHS compliant
package
Internal 3.3V and 1.2V voltage regulators
On Board 24MHz Crystal Driver, Resonator, or
External 24MHz clock input
Target Applications
Environmental
Mobile phones
—
Commercial temperature range support (0ºC to 70ºC)
Tablets
—
Industrial temperature range support (-40ºC to 85ºC)
Ultrabooks
Digital still cameras
Digital video camcorders
Gaming consoles
PDAs
Portable media players
GPS personal navigation devices
Media players/viewers
SMSC USB3613
Revision 1.0 (06-17-13)
DATASHEET
USB 2.0 Hi-Speed 3-Port Hub Controller Optimized for Portable Applications
Datasheet
Order Number(s):
ORDER NUMBER
USB3613-1080XY
TEMPERATURE RANGE
0°C to +70°C
PACKAGE TYPE
30-ball WLCSP
30-ball WLCSP
(Tape & Reel)
USB3613-1080XY-TR
USB3613i-1080XY
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
30-ball WLCSP
30-ball WLCSP
(Tape & Reel)
USB3613i-1080XY-TR
This product meets the halogen maximum concentration values per IEC61249-2-21
For RoHS compliance and environmental information, please visit www.smsc.com/rohs
Please contact your SMSC sales representative for additional documentation related to this product
such as application notes, anomaly sheets, and design guidelines.
The table above represents valid part numbers at the time of printing and may not represent parts that are currently
available. For the latest list of valid ordering numbers for this product, please contact the nearest sales office.
Copyright © 2013 SMSC or its subsidiaries. All rights reserved.
Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for
construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC
reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications
before placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent
rights or other intellectual property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated
version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors
known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not
designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property
damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of
this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com. SMSC is a registered
trademark of Standard Microsystems Corporation (“SMSC”). Product names and company names are the trademarks of their respective holders.
The Microchip name and logo, and the Microchip logo are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.
SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE
OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL
DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT;
TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD
TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
Revision 1.0 (06-17-13)
2
SMSC USB3613
DATASHEET
USB 2.0 Hi-Speed 3-Port Hub Controller Optimized for Portable Applications
Datasheet
Table of Contents
Chapter 1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Chapter 2 Acronyms and Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1 Acronyms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2 Reference Documents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Chapter 3 Ball Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1 Ball Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.2 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.3 Buffer Type Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Chapter 4 Power Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1 Integrated Power Regulators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1.1 3.3V Regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1.2 1.2V Regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.2 Power Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.2.1 Single Supply Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.2.2 Dual Supply Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.3 Power Connection Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Chapter 5 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.1 Boot Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.1.1 Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.1.2 Hardware Initialization Stage (HW_INIT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.1.3 Battery Charging Initialization Stage (BC_INIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.1.4 Wait REFCLK Stage (WAITREF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.1.5 Software Initialization Stage (SW_INIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.1.6 SOC Configuration Stage (SOC_CFG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.1.7 Configuration Stage (CONFIG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.1.8 Battery Charger Detection Stage (CHGDET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.1.9 Hub Connect Stage (Hub.Connect). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.1.10 Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Chapter 6 Device Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.1 Configuration Method Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.2 Customer Accessible Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.2.1 USB Accessible Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.2.2 SMBus Accessible Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.3 Device Configuration Straps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.3.1 SPI Speed Select (SPI_SPD_SEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Chapter 7 Device Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.1 SPI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.1.1 Operation of the Hi-Speed Read Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.1.2 Operation of the Dual High Speed Read Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.1.3 32 Byte Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.1.4 Interface Operation to the SPI Port When Not Performing Fast Reads. . . . . . . . . . . . . . . . . 29
SMSC USB3613
3
Revision 1.0 (06-17-13)
DATASHEET
USB 2.0 Hi-Speed 3-Port Hub Controller Optimized for Portable Applications
Datasheet
7.1.5 Erase Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.1.6 Byte Program Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.1.7 Command Only Program Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.1.8 JEDEC-ID Read Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.2 I2C Master Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.2.1 I2C Message Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.2.2 Pull-Up Resistors for I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.3 SMBus Slave Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.3.1 SMBus Run Time Accessible Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.3.2 Run Time SMBus Page Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Chapter 8 Functional Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
8.1 Battery Charger Detection & Charging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
8.1.1 Upstream Battery Charger Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
8.1.2 Downstream Battery Charging. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
8.2 Flex Connect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
8.2.1 Port Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
8.3 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
8.3.1 Power-On Reset (POR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
8.3.2 External Chip Reset (RESET_N). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
8.3.3 USB Bus Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
8.4 Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
8.5 Hub Connect (HUB_CONN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
8.6 Link Power Management (LPM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
8.7 Suspend (SUSPEND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
8.8 Interrupt Requests (IRQ_N). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
8.9 Interrupt Output (INT_N) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Chapter 9 Operational Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
9.1 Absolute Maximum Ratings* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
9.2 Operating Conditions** . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
9.3 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
9.3.1 Operational / Unconfigured . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
9.3.2 Suspend / Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
9.4 DC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
9.5 AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
9.5.1 Power-On Configuration Strap Valid Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
9.5.2 Reset and Configuration Strap Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
9.5.3 USB Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
9.5.4 HSIC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
9.5.5 SMBus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
9.5.6 I2C Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
9.5.7 SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
9.6 Clock Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
9.6.1 External Reference Clock (REFCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Chapter 10 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Chapter 11 Datasheet Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Revision 1.0 (06-17-13)
4
SMSC USB3613
DATASHEET
USB 2.0 Hi-Speed 3-Port Hub Controller Optimized for Portable Applications
Datasheet
List of Figures
Figure 1.1 System Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 3.1 30-WLCSP Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 4.1 Power Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 5.1 Hub Operational Mode Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 7.1 SPI Hi-Speed Read Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 7.2 SPI Dual Hi-Speed Read Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 7.3 SPI Erase Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 7.4 SPI Byte Program Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 7.5 SPI Command Only Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 7.6 SPI JEDEC-ID Read Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 7.7 I2C Sequential Access Write Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 7.8 I2C Sequential Access Read Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 8.1 Battery Charging External Power Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 9.1 Single/Dual Supply Rise Time Models. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 9.2 Power-On Configuration Strap Valid Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 9.3 RESET_N Configuration Strap Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 9.4 SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 10.1 30-WLCSP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 10.2 30-WLCSP Recommended Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
SMSC USB3613
5
Revision 1.0 (06-17-13)
DATASHEET
USB 2.0 Hi-Speed 3-Port Hub Controller Optimized for Portable Applications
Datasheet
List of Tables
Table 3.1 Ball Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 3.2 30-WLCSP Package Ball Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 3.3 Buffer Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 6.1 SPI_SPD_SEL Configuration Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 7.1 SMBus Accessible Run Time Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 7.2 Upstream Battery Charging Detection Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 7.3 Upstream Custom Battery Charger Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 7.4 Upstream Custom Battery Charger Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 7.5 Port Power Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 7.6 OCS Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 7.7 Serial Port Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 7.8 Serial Port Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 7.9 Upstream Battery Charger Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 7.10 Charge Detect Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 7.11 Configure Portable Hub Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 7.12 Port Select and Low-Power Suspend Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 7.13 Connect Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 7.14 Upstream (Port 0) Battery Charging Control 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 7.15 Upstream (Port 0) Battery Charging Control 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 7.16 Upstream (Port 0) Battery Charging Run Time Control Register. . . . . . . . . . . . . . . . . . . . . . . 47
Table 7.17 Upstream (Port 0) Battery Charging Detect Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 7.18 SMBus Page Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 8.1 Chargers Compatible with Upstream Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 8.2 CHRGDET[1:0] Configuration Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 8.3 Downstream Port Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 8.4 Default Reference Clock Frequencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 8.5 LPM State Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 9.1 Operational/Unconfigured Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 9.2 Single Supply Suspend/Standby Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 9.3 Dual Supply Suspend/Standby Power Consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 9.4 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 9.5 Power-On Configuration Strap Valid Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 9.6 RESET_N Configuration Strap Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 9.7 SPI Timing Values (30 MHz Operation). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 9.8 SPI Timing Values (60 MHz Operation). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 10.1 30-WLCSP Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 11.1 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Revision 1.0 (06-17-13)
6
SMSC USB3613
DATASHEET
USB 2.0 Hi-Speed 3-Port Hub Controller Optimized for Portable Applications
Datasheet
Chapter 1 General Description
The SMSC USB3613 is a low-power, OEM configurable, MTT (Multi-Transaction Translator) USB 2.0
hub controller with 3 downstream ports and advanced features for embedded USB applications. The
USB3613 is fully compliant with the USB 2.0 Specification, USB 2.0 Link Power Management
Addendum, High-Speed Inter-Chip (HSIC) USB Electrical Specification Revision 1.0, and will attach to
an upstream port as a Hi-Speed hub. The 3-port hub supports Low-Speed, Full-Speed, and Hi-Speed
downstream devices on all of the enabled downstream (non-HSIC) ports. HSIC ports support only Hi-
Speed operation.
The USB3613 has been specifically optimized for mobile embedded applications. The pin-count has
been reduced by optimizing the USB3613 for mobile battery-powered embedded systems where power
consumption, small package size, and minimal BOM are critical design requirements. Standby mode
power has been minimized and reference clock inputs can be aligned to the customer’s specific mobile
application. Flexible power rail options ease integration into energy efficient designs by allowing the
USB3613 to be powered in a single-source (VBUS, VBAT, 3.3V) or a dual-source (VBAT + 1.8, 3.3V
+ 1.8) configuration. Additionally, all required resistors on the USB ports are integrated into the hub,
including all series termination and pull-up/pull-down resistors on the D+ and D– pins.
The USB3613 supports both upstream battery charger detection and downstream battery charging.
The USB3613 integrated battery charger detection circuitry supports the USB-IF Battery Charging
(BC1.2) detection method and most Apple devices. These circuits are used to detect the attachment
and type of a USB charger and provide an interrupt output to indicate charger information is available
to be read from the device’s status registers via the serial interface. The USB3613 provides the battery
charging handshake and supports the following USB-IF BC1.2 charging profiles:
DCP: Dedicated Charging Port (Power brick with no data)
CDP: Charging Downstream Port (1.5A with data)
SDP: Standard Downstream Port (0.5A with data)
Custom profiles loaded via SMBus or OTP
The USB3613 provides an additional USB endpoint dedicated for use as a USB to I2C/SPI interface,
allowing external circuits or devices to be monitored, controlled, or configured via the USB interface.
Additionally, the USB3613 includes many powerful and unique features such as:
FlexConnect, which provides flexible connectivity options. The USB3613’s downstream port 1 can be
swapped with the upstream port, allowing master capable devices to control other devices on the hub.
MultiTRAKTM Technology, which utilizes a dedicated Transaction Translator (TT) per port to maintain
consistent full-speed data throughput regardless of the number of active downstream connections.
MultiTRAKTM outperforms conventional USB 2.0 hubs with a single TT in USB full-speed data transfers.
PortMap, which provides flexible port mapping and disable sequences. The downstream ports of a
USB3613 hub can be reordered or disabled in any sequence to support multiple platform designs with
minimum effort. For any port that is disabled, the USB3613 hub controllers automatically reorder the
remaining ports to match the USB host controller’s port numbering scheme.
PortSwap, which adds per-port programmability to USB differential-pair pin locations. PortSwap allows
direct alignment of USB signals (D+/D-) to connectors to avoid uneven trace length or crossing of the
USB differential signals on the PCB.
PHYBoost, which provides programmable levels of Hi-Speed USB
signal drive strength in the downstream port transceivers. PHYBoost
attempts to restore USB signal integrity in a compromised system
environment. The graphic on the right shows an example of Hi-
Speed USB eye diagrams before and after PHYBoost signal integrity
restoration.
SMSC USB3613
7
Revision 1.0 (06-17-13)
DATASHEET
USB 2.0 Hi-Speed 3-Port Hub Controller Optimized for Portable Applications
Datasheet
VariSense, which controls the USB receiver sensitivity enabling programmable levels of USB signal
receive sensitivity. This capability allows operation in a sub-optimal system environment, such as when
a captive USB cable is used.
The USB3613 is available in commercial (0°C to +70°C) and industrial (-40°C to +85°C) temperature
range versions.
1.1
Block Diagram
Figure 1.1 details the internal block diagram of the USB3613.
To I2C Master/Slave
or EEPROM
Up or Downstream
Sda
Scl
VBAT
VDDCOREREG
VDDCR12
HSIC
ResetN
VDD33
AddrSel
IntN
Serial
Interface
3.3V Reg
1.2V Reg
Flex
PHY
HSIC
SIE
Controller
Upstream
Hub Logic
& Repeater
Multi-
TT
Port Controller
Routing & Port Re-Ordering Logic
CPU
COMPLEX
USB
Swap
Port
JTAG
USB
Port
HSIC
Port
Upstream
Battery
Charger
Detection
PLL
RefSel
ChgDetN
RefClk
USB
Down or
Upstream
USB
Downstream
HSIC
Downstream
JTAG/
SPI/
GPIO
Figure 1.1 System Block Diagram
Revision 1.0 (06-17-13)
8
SMSC USB3613
DATASHEET
USB 2.0 Hi-Speed 3-Port Hub Controller Optimized for Portable Applications
Datasheet
Chapter 2 Acronyms and Definitions
2.1
Acronyms
EOP: End of Packet
EP:
FS:
Endpoint
Full-Speed
GPIO: General Purpose I/O (that is input/output to/from the device)
HS: Hi-Speed
HSOS: High Speed Over Sampling
HSIC: High-Speed Inter-Chip
I2C®: Inter-Integrated Circuit
LS:
Low-Speed
OTP: One Time Programmable
PCB: Printed Circuit Board
PCS: Physical Coding Sublayer
PHY: Physical Layer
SMBus: System Management Bus
UUID: Universally Unique IDentification
2.2
Reference Documents
1. UNICODE UTF-16LE For String Descriptors USB Engineering Change Notice, December 29th,
2004, http://www.usb.org
2. Universal Serial Bus Specification, Revision 2.0, April 27th, 2000, http://www.usb.org
3. Battery Charging Specification, Revision 1.2, Dec. 07, 2010, http://www.usb.org
4. High-Speed Inter-Chip USB Electrical Specification, Version 1.0, Sept. 23, 2007, http://www.usb.org
5. I2C-Bus Specification, Version 1.1, http://www.nxp.com
6. System Management Bus Specification, Version 1.0, http://smbus.org/specs
SMSC MAKES NO WARRANTIES, EXPRESS, IMPLIED, OR STATUTORY, IN REGARD TO INFRINGEMENT OR
OTHER VIOLATION OF INTELLECTUAL PROPERTY RIGHTS. SMSC DISCLAIMS AND EXCLUDES ANY AND
ALL WARRANTIES AGAINST INFRINGEMENT AND THE LIKE.
No license is granted by SMSC expressly, by implication, by estoppel or otherwise, under any patent, trademark,
copyright, mask work right, trade secret, or other intellectual property right. **To obtain this software program the
appropriate SMSC Software License Agreement must be executed and in effect. Forms of these Software License
Agreements may be obtained by contacting SMSC.
SMSC USB3613
9
Revision 1.0 (06-17-13)
DATASHEET
USB 2.0 Hi-Speed 3-Port Hub Controller Optimized for Portable Applications
Datasheet
Chapter 3 Ball Descriptions
1
2
3
4
5
6
SUSPEND/
IRQ_N/
INT_N
VDDCORE
REG
STRB0
DATA0
REFCLK
VDDCR12
A
B
C
D
E
HUB_CONN
RESET_N
GND
VDD33
VBAT
DP1
DP2
SCL/
SMBCLK
REFSEL0
RBIAS
GND
DM1
SDA/
SMBDATA
SPI_DO/
SPI_SPD_SEL
SPI_CLK
CHRGDET0
CHRGDET1
DM2
STRB3
SPI_CE_N
SPI_DI
PRTCTLA
DATA3
REFSEL1
Top of USB3613 Package
Figure 3.1 30-WLCSP Pin Assignments
Revision 1.0 (06-17-13)
10
SMSC USB3613
DATASHEET
USB 2.0 Hi-Speed 3-Port Hub Controller Optimized for Portable Applications
Datasheet
3.1
Ball Descriptions
This section provides a detailed description of each ball. The signals are arranged in functional groups
according to their associated interface.
The “_N” symbol in the signal name indicates that the active, or asserted, state occurs when the signal
is at a low voltage level. For example, RESET_N indicates that the reset signal is active low. When
“_N” is not present after the signal name, the signal is asserted when at the high voltage level.
The terms assertion and negation are used exclusively. This is done to avoid confusion when working
with a mixture of “active low” and “active high” signals. The term assert, or assertion, indicates that a
signal is active, independent of whether that level is represented by a high or low voltage. The term
negate, or negation, indicates that a signal is inactive.
Note: The buffer type for each signal is indicated in the BUFFER TYPE column of Table 3.1. A
description of the buffer types is provided in Section 3.3.
Table 3.1 Ball Descriptions
NUM
BALLS
BUFFER
TYPE
NAME
SYMBOL
DESCRIPTION
USB/HSIC INTERFACES
Upstream
HSIC Data
(Flex Port 0)
DATA0
STRB0
DP1
HSIC
HSIC
AIO
Upstream HSIC Port 0 DATA signal.
Note:
The upstream Port 0 signals can be
optionally swapped with the
downstream Port 1 signals.
1
1
1
1
Upstream
HSIC Strobe
(Flex Port 0)
Upstream HSIC Port 0 STROBE signal.
Note:
The upstream Port 0 signals can be
optionally swapped with the
downstream Port 1 signals.
Downstream
USB D+
(Swap Port 1)
Downstream USB Port 1 D+ data signal.
Note:
The downstream Port 1 signals can be
optionally swapped with the upstream
Port 0 signals.
Downstream
USB D-
(Swap Port 1)
DM1
AIO
Downstream USB Port 1 D- data signal.
Note:
The downstream Port 1 signals can be
optionally swapped with the upstream
Port 0 signals.
Downstream
USB D+
(Port 2)
DP2
DM2
AIO
AIO
Downstream USB Port 2 D+ data signal.
Downstream USB Port 2 D- data signal.
Downstream HSIC Port 3 DATA signal.
Downstream HSIC Port 3 STROBE signal.
1
1
1
Downstream
USB D-
(Port 2)
Downstream
HSIC Data
(Port 3)
DATA3
STRB3
HSIC
HSIC
Downstream
HSIC Strobe
(Port 3)
1
SMSC USB3613
11
Revision 1.0 (06-17-13)
DATASHEET
USB 2.0 Hi-Speed 3-Port Hub Controller Optimized for Portable Applications
Datasheet
Table 3.1 Ball Descriptions (continued)
NUM
BALLS
BUFFER
TYPE
NAME
SYMBOL
DESCRIPTION
I2C/SMBUS INTERFACE
I2C Serial
SCL
I_SMB
I2C serial clock input.
Clock Input
1
1
SMBus Clock
SMBCLK
SDA
I_SMB
IS/OD8
SMBus serial clock input.
I2C Serial
Data
I2C bidirectional serial data.
SMBus Serial
Data
SMBDATA
IS/OD8
SMBus bidirectional serial data.
SPI MASTER INTERFACE
SPI Chip
Enable
Output
SPI_CE_N
O12
Active-low SPI chip enable output.
1
1
Note:
If the SPI is enabled, this pin will be
driven high in powerdown states.
SPI Clock
Output
SPI_CLK
SPI_DO
O12
O12
SPI clock output
SPI Data
Output
SPI data output
SPI Speed
Select
Configuration
Strap
SPI_SPD_SEL
IS
(PD)
This strap is used to select the speed of the SPI.
0 = 30MHz (default)
1 = 60MHz
1
Note:
If the latched value on reset is 1, this pin
is tri-stated when the chip is in the
suspend state. If the latched value on
reset is 0, this pin is driven low during a
suspend state.
See Note 3.2 for more information on
configuration straps.
SPI Data
Input
SPI_DI
IS
(PD)
SPI data input
1
MISC.
Reference
Clock Input
REFCLK
ICLK
This signal is the reference clock input. The clock
input frequency is configured via REFSEL[1:0].
Refer to Section 8.4, "Reference Clock," on
page 54 for additional information.
1
1
Reference
Clock Select
0 Input
REFSEL0
IS
This signal, combined with REFSEL1, selects the
reference clock input frequency. The reference
select input must be set to correspond to the
frequency applied to the REFCLK input. Refer to
Section 8.4, "Reference Clock," on page 54 for
additional information.
Revision 1.0 (06-17-13)
12
SMSC USB3613
DATASHEET
USB 2.0 Hi-Speed 3-Port Hub Controller Optimized for Portable Applications
Datasheet
Table 3.1 Ball Descriptions (continued)
NUM
BALLS
BUFFER
TYPE
NAME
SYMBOL
DESCRIPTION
Reference
Clock Select
1 Input
REFSEL1
IS
This signal, combined with REFSEL0, selects the
reference clock input frequency. The reference
select input must be set to correspond to the
frequency applied to the REFCLK input. Refer to
Section 8.4, "Reference Clock," on page 54 for
additional information.
1
SystemReset
Input
RESET_N
I_RST
This active-low signal allows external hardware to
reset the device.
Note:
The active-low pulse must be at least
5us wide. Refer to Section 8.3.2,
"External Chip Reset (RESET_N)," on
page 53 for additional information.
1
1
External USB
Transceiver
Bias Resistor
RBIAS
AI
IS
A 12.0kΩ (+/- 1%) resistor is attached from
ground to this pin to set the transceiver’s internal
bias settings.
Hub Connect
Input
HUB_CONN
This signal is used to control the hub
communication stage. The device will transition
to the hub communications stage when this pin is
asserted high. Two methods of use may be used:
Tie to +3.3V: The hub will automatically transition
to the communications stage when configuration
is complete.
1
Transition from low to high: The hub will
transition to the communications stage after
configuration is complete and this signal
transitions from low to high.
Refer to Section 8.5, "Hub Connect
(HUB_CONN)," on page 55 for additional
information.
Charge
Detect 0
Output
CHRGDET0
CHRGDET1
O8
O8
This signal, in conjunction with CHRGDET1, can
be configured to communicate information that
can affect the level of current that the system
may draw from the upstream USB VBUS wire.
Refer to Section 8.1.1.1, "Charger Detection
(CHRGDET[1:0])," on page 50 for additional
information.
1
1
Charge
Detect 1
Output
This signal, in conjunction with CHRGDET0, can
be configured to communicate information that
can affect the level of current that the system
may draw from the upstream USB VBUS wire.
Refer to Section 8.1.1.1, "Charger Detection
(CHRGDET[1:0])," on page 50 for additional
information.
SMSC USB3613
13
Revision 1.0 (06-17-13)
DATASHEET
USB 2.0 Hi-Speed 3-Port Hub Controller Optimized for Portable Applications
Datasheet
Table 3.1 Ball Descriptions (continued)
NUM
BALLS
BUFFER
TYPE
NAME
SYMBOL
DESCRIPTION
Suspend
Output
SUSPEND
PU
This signal is used to indicate that the entire hub
has entered the USB suspend state and that
VBUS current consumption should be reduced in
accordance with the USB specification. Refer to
Section 8.7, "Suspend (SUSPEND)," on page 55
for additional information.
Note:
SUSPEND must be enabled via the
Protouch configuration tool.
1
Interrupt
Request Input
IRQ_N
INT_N
IS
This active-low signal allows external hardware to
interrupt the device. Refer to Section 8.8,
"Interrupt Requests (IRQ_N)," on page 56 for
additional information.
Interrupt
Output
OD8
This active-low signal allows the device to output
an interrupt to external hardware. Refer to
Section 8.9, "Interrupt Output (INT_N)," on
page 56 for additional information.
USB Port
Control
PRTCTLA
OD8/IS
(PU)
This pin functions as both the downstream USB
port power enable output (PRTPWRA) and the
downstream USB port over-current sense input
(OCSA_N).
1
POWER
Battery
Power Supply
Input
VBAT
P
Battery power supply input. When VBAT is
connected directly to a +3.3V supply from the
system, the internal +3.3V regulator runs in
dropout and regulator power consumption is
eliminated. A 4.7 μF (<1 Ω ESR) capacitor to
ground is required for regulator stability. The
capacitor should be placed as close as possible
to the device. Refer to Chapter 4, "Power
Connections," on page 17 for power connection
information.
1
+3.3V Power
Supply
VDD33
P
P
+3.3V power supply. A 1.0 μF (<1 Ω ESR)
capacitor to ground is required for regulator
stability. The capacitor should be placed as close
as possible to the device. Refer to Chapter 4,
"Power Connections," on page 17 for power
connection information.
1
1
1
+1.8-3.3V
Core Power
Supply Input
VDDCOREREG
+1.8-3.3V core power supply input to internal
+1.2V regulator. This pin may be connected to
VDD33 for single supply applications when VBAT
equals +3.3V. Running in a dual supply
configuration with VDDCOREREG at a lower
voltage, such as +1.8V, may reduce overall
system power consumption. Refer to Chapter 4,
"Power Connections," on page 17 for power
connection information.
+1.2V Core
Power Supply
VDDCR12
P
+1.2V core power supply. A 1.0 μF (<1 Ω ESR)
capacitor to ground is required for regulator
stability. The capacitor should be placed as close
as possible to the device. Refer to Chapter 4,
"Power Connections," on page 17 for power
connection information.
Revision 1.0 (06-17-13)
14
SMSC USB3613
DATASHEET
USB 2.0 Hi-Speed 3-Port Hub Controller Optimized for Portable Applications
Datasheet
Table 3.1 Ball Descriptions (continued)
NUM
BALLS
BUFFER
TYPE
NAME
SYMBOL
DESCRIPTION
2
Ground
GND
P
Ground
Note 3.2 Configuration strap values are latched on Power-On Reset (POR) and the rising edge of
RESET_N (external chip reset). Configuration straps are identified by an underlined
symbol name. Signals that function as configuration straps must be augmented with an
external resistor when connected to a load. Refer to Section 6.3, "Device Configuration
Straps," on page 27 for additional information.
3.2
Pin Assignments
Table 3.2 30-WLCSP Package Ball Assignments
BALL
A
1
2
3
4
5
6
VDDCOREREG
SUSPEND/
IRQ_N/INT_N
STRB0
DATA0
REFCLK
VDDCR12
B
C
D
E
HUB_CONN
RESET_N
GND
VDD33
GND
VBAT
DM1
DP1
DP2
REFSEL0
SCL/
SMBCLK
RBIAS
SDA/
SMBDATA
SPI_CLK
SPI_DO/
SPI_SPD_SEL
CHRGDET0
CHRGDET1
DM2
STRB3
REFSEL1
SPI_CE_N
SPI_DI
PRTCTLA
DATA3
SMSC USB3613
15
Revision 1.0 (06-17-13)
DATASHEET
USB 2.0 Hi-Speed 3-Port Hub Controller Optimized for Portable Applications
Datasheet
3.3
Buffer Type Descriptions
Table 3.3 Buffer Types
DESCRIPTION
BUFFER TYPE
IS
I_RST
I_SMB
O8
Schmitt-triggered input
Reset Input
I2C/SMBus Clock Input
Output with 8 mA sink and 8 mA source
OD8
O12
Open-drain output with 8 mA sink
Output with 12 mA sink and 12 mA source
HSIC
PU
High-Speed Inter-Chip (HSIC) USB Specification, Version 1.0 compliant input/output
50 µA (typical) internal pull-up. Unless otherwise noted in the pin description, internal pull-
ups are always enabled.
Note:
Internal pull-up resistors prevent unconnected inputs from floating. Do not rely on
internal resistors to drive signals external to the device. When connected to a load
that must be pulled high, an external resistor must be added.
PD
50 µA (typical) internal pull-down. Unless otherwise noted in the pin description, internal
pull-downs are always enabled.
Note:
Internal pull-down resistors prevent unconnected inputs from floating. Do not rely
on internal resistors to drive signals external to the device. When connected to a
load that must be pulled low, an external resistor must be added.
AIO
ICLK
P
Analog bi-directional
Crystal oscillator input pin
Power pin
Revision 1.0 (06-17-13)
16
SMSC USB3613
DATASHEET
USB 2.0 Hi-Speed 3-Port Hub Controller Optimized for Portable Applications
Datasheet
Chapter 4 Power Connections
4.1
Integrated Power Regulators
The integrated 3.3V and 1.2V power regulators provide flexibility to the system in providing power the
device. Several different configurations are allowed in order to align the power structure to supplies
available in the system.
The regulators are controlled by RESET_N. When RESET_N is brought high, the 3.3V regulator will
turn on. When RESET_N is brought low the 3.3V regulator will turn off.
4.1.1
4.1.2
3.3V Regulator
The device has an integrated regulator to convert from VBAT to 3.3V.
1.2V Regulator
The device has an integrated regulator to convert from a variable voltage input on VDDCOREREG to
1.2V. The 1.2V regulator is tolerant to the presence of low voltage (~0V) on the VDDCOREREG pin
in order to support system power solutions where a supply is not always present in low power states.
The 1.2V regulator supports an input voltage range consistent with a 1.8V input in order to reduce
power consumption in systems which provide multiple power supply levels. In addition, the 1.2V
regulator supports an input voltage up to 3.3V for systems which provide only a single power supply.
The device will support operation where the 3.3V regulator output can drive the 1.2V regulator input
such that VBAT is the only required supply.
4.2
Power Configurations
The device supports operation with no back current when power is connected in each of the following
configurations. Power connection diagrams for these configurations are included in Section 4.3, "Power
Connection Diagrams," on page 18.
4.2.1
Single Supply Configurations
4.2.1.1
VBAT Only
VBAT must be tied to the VBAT system supply. VDD33 and VDDCOREREG must be tied together on
the board. In this configuration the 3.3V and 1.2V regulators will be active.
4.2.1.2
3.3V Only
VBAT must be tied to the 3.3V system supply. VDD33 and VDDCOREREG must be tied together on
the board. In this configuration the 3.3V regulator will operate in dropout mode and the 1.2V regulator
will be active.
4.2.2
Dual Supply Configurations
4.2.2.1
VBAT + 1.8V
VBAT must be tied to the VBAT system supply. VDDCOREREG must be tied to the 1.8V system
supply. In this configuration, the 3.3V regulator and the 1.2V regulator will be active.
SMSC USB3613
17
Revision 1.0 (06-17-13)
DATASHEET
USB 2.0 Hi-Speed 3-Port Hub Controller Optimized for Portable Applications
Datasheet
4.2.2.2
3.3V + 1.8V
VBAT must be tied to the 3.3V system supply. VDDCOREREG must be tied to the 1.8V system supply.
In this configuration the 3.3V regulator will operate in dropout mode and the 1.2V regulator will be
active.
4.3
Power Connection Diagrams
Figure 4.1 illustrates the power connections for the USB3613 with various power supply configurations.
Single Supply Application
HSIC
3.3V Internal
Logic
1.2V
Core Logic
3.3V I/O
VBAT/+3.3V
Supply
3.3V Regulator
1.2V Regulator
VBAT
(IN)
(OUT)
(IN)
(OUT)
4.7uF
USB3613
GND
VDD33
VDDCOREREG
VDDCR12
1.0uF
1.0uF
Dual Supply Application (3.3V & 1.8V)
HSIC
3.3V Internal
Logic
1.2V
Core Logic
3.3V I/O
+3.3V
Supply
3.3V Regulator
1.2V Regulator
VBAT
(IN)
(OUT)
(IN)
(OUT)
4.7uF
USB3613
GND
VDD33
VDDCOREREG
VDDCR12
1.0uF
+1.8V
Supply
1.0uF
Figure 4.1 Power Connections
Revision 1.0 (06-17-13)
18
SMSC USB3613
DATASHEET
USB 2.0 Hi-Speed 3-Port Hub Controller Optimized for Portable Applications
Datasheet
Chapter 5 Modes of Operation
The device provides two main modes of operation: Standby Mode and Hub Mode. The operating mode
of the device is selected by setting values on primary inputs according to the table below.
Table 5.1 Controlling Modes of Operation
RESET_N
INPUT
RESULTING
MODE
SUMMARY
0
Standby
Lowest Power Mode: No functions are active other than monitoring the
RESET_N input. All port interfaces are high impedance. All regulators are
powered off.
1
Hub
Full Feature Mode: Device operates as a configurable USB hub with battery
charger detection. Power consumption is based on the number of active ports,
their speed, and amount of data transferred.
Note: Refer to Section 8.3.2, "External Chip Reset (RESET_N)," on page 53 for additional information
on RESET_N.
The flowchart in Figure 5.1 shows the modes of operation. It also shows how the device traverses
through the Hub mode stages (shown in bold.) The flow of control is dictated by control register bits
shown in italics as well as other events such as availability of a reference clock. The remaining sections
in this chapter provide more detail on each stage and mode of operation.
SMSC USB3613
19
Revision 1.0 (06-17-13)
DATASHEET
USB 2.0 Hi-Speed 3-Port Hub Controller Optimized for Portable Applications
Datasheet
(HW_INIT)
YES
REFCLK
Present
NO
(SW_INIT)
Dead Battery
Bond Option
YES
External
SPI ROM
present?
YES
NO
NO
Load BC registers
On RO
(BC_INIT)
Run from
Internal ROM
Run From
External SPI ROM
Run BC Detect
On RO
YES
SMBus or I2C
Present?
NO
YES
NO
REFCLK
Present
Config Load
From Internal ROM
Do SMBus or I2C
Initialization
(WAITREF)
NO
SOC Done?
YES
Combine OTP
Config Data
(CONFIG)
(SOC_CFG)
SW Upstream
BC detection
(CHGDET)
Hub Connect
(Hub.Connect)
Normal
operation
Figure 5.1 Hub Operational Mode Flowchart
Revision 1.0 (06-17-13)
20
SMSC USB3613
DATASHEET
USB 2.0 Hi-Speed 3-Port Hub Controller Optimized for Portable Applications
Datasheet
5.1
Boot Sequence
5.1.1
Standby Mode
If the external hardware reset is asserted, the hub will be in Standby Mode. This mode provides a very
low power state for maximum power efficiency when no signaling is required. This is the lowest power
state. In Standby Mode all internal regulators are powered off, the PLL is not running, and core logic
is powered down in order to minimize power consumption. Because core logic is powered off, no
configuration settings are retained in this mode and must be re-initialized after RESET_N is negated
high.
5.1.2
Hardware Initialization Stage (HW_INIT)
The first stage is the initialization stage and occurs on the negation of RESET_N. In this stage the
1.2V regulator is enabled and stabilizes, internal logic is reset, and the PLL locks if a valid REFCLK
is supplied. Configuration registers are initialized to their default state and strap input values are
latched. The device will complete initialization and automatically enter the next stage. Because the
digital logic within the device is not yet stable, no communication with the device using the SMBus is
possible. Configuration registers are initialized to their default state.
If there is no REFCLK present, the next state is BC_INIT. If there is a REFCLK present, the next state
is SW_INIT.
5.1.3
Battery Charging Initialization Stage (BC_INIT)
This state is entered to deal with the dead battery condition. The processor Ring Oscillator (RO) is
enabled. The processor is woken up for a short period. In that period, the processor reads the OTP
to determine what type(s) of upstream battery charging detection will be done. Based on the settings,
the firmware will program the upstream battery charging registers appropriately.
The processor loads the battery charging registers with the values out of OTP memory. Once the
processor has initialized the BC registers, it turns off the ring oscillator. If the hardware detects the
presence of REFCLK, it switches over to regular operation of the PLL.
5.1.4
Wait REFCLK Stage (WAITREF)
In this stage, the reference clock is checked for activity. If the reference clock is active, the device will
continue to the Hub configuration stage. If the reference clock is not active but battery charger
detection is enabled, the detection sequence will begin while operating on an internal ring oscillator.
If the PLL locks while battery charger detection is still in progress, the sequence will be aborted until
the battery charger detection stage. If aborted, no results are captured. If battery charger detection
completes, the results of the battery charger detection may be communicated through the INT_N pin
function, CHRGDET pin function or neither based on the default ROM settings.
If the reference clock is provided before entering hub mode, the device will transition to the Software
Initialization stage (SW_INIT) without pausing in the WAITREF stage. Otherwise, the device will
transition to the SW_INIT stage once a valid reference clock is supplied and the PLL has locked. If
the hardware detects the presence of REFCLK, it switches over to regular operation of the PLL.
Note: During this stage the SMbus is not functional.
5.1.5
Software Initialization Stage (SW_INIT)
Once the hardware is initialized, the firmware can begin to execute. The internal firmware checks for
an external SPI ROM. The firmware looks for an external SPI flash device that contains a valid
SMSC USB3613
21
Revision 1.0 (06-17-13)
DATASHEET
USB 2.0 Hi-Speed 3-Port Hub Controller Optimized for Portable Applications
Datasheet
signature of “2DFU” (device firmware upgrade) beginning at address 0xFFFA. If a valid signature is
found, then the external ROM is enabled and the code execution begins at address 0x0000 in the
external SPI device. If a valid signature is not found, then execution continues from internal ROM. SPI
ROMs used with the device must be 1 Mbit and support either 30 MHz or 60 MHz. The frequency
used is set using the SPI_SPD_SEL configuration strap. Both 1- and 2-bit SPI operation is supported.
For optimum throughput, a 2-bit SPI ROM is recommended. Both mode 0 and mode 3 SPI ROMS are
also supported. Refer to Section 6.3.1, "SPI Speed Select (SPI_SPD_SEL)," on page 27 for additional
information on selection of the SPI speed.For all other configurations, the firmware checks for the
presence of an external I2C/SMBus. It does this by asserting two pull down resistors on the data and
clock lines of the bus. The pull downs are typically 50Kohm. If there are 10Kohm pull-ups present, the
device becomes aware of the presence of an external SMBus/I2C bus. If a bus is detected, the
firmware transitions to the SOC_CFG state.
5.1.6
5.1.7
SOC Configuration Stage (SOC_CFG)
In this stage, the SOC may modify any of the default configuration settings specified in the integrated
ROM such as USB device descriptors, or port electrical settings, and control features such as
upstream battery charging detection.
There is no time limit. In this stage the firmware will wait indefinitely for the SMBus/I2C configuration.
When the SOC has completed configuring the device, it must write to register 0xFF to end the
configuration.
Configuration Stage (CONFIG)
Once the SOC has indicated that it is done with configuration, then all the configuration data is
combined. The default data, the SOC configuration data, the OTP data are all combined in the firmware
and device is programmed.
After the device is fully configured, it will go idle and then into suspend if there is no VBUS or
Hub.Connect present. Once VBUS is present, and upstream battery charging is enabled, the device
will transition to the Battery Charger Detection Stage (CHGDET). If VBUS is present, and upstream
battery charging is not enabled, the device will transitions to the Connect (Hub.Connect) stage.
5.1.8
Battery Charger Detection Stage (CHGDET)
After configuration, if enabled, the device enters the Battery Charger Detection Stage. If the battery
charger detection feature was disabled during the CONFIG stage, or the HUB_CONN pin is asserted,
the device will immediately transition to the Hub Connect (Hub.Connect) stage. If the battery charger
detection feature remains enabled, the battery charger detection sequence is started automatically.
If a charger is detected during this stage, the device asserts the CHRGDET[1:0] output pin function if
the charger type identified is not masked. If the charger detection remains enabled, the device will
transition to the Hub.Connect stage if using the hardware detection mechanism.
5.1.9
Hub Connect Stage (Hub.Connect)
Once the CHGDET stage is completed, the device enters the Hub.Connect stage. USB connect can
be initiated by asserting the HUB_CONN pin high. The device will remain in the Hub.Connect stage
indefinitely until the HUB_CONN pin is deasserted.
5.1.10
Normal Mode
Lastly the SOC enters the Normal Mode of operation. In this stage, full USB operation is supported
under control of the USB Host on the upstream port. The device will remain in the normal mode until
Revision 1.0 (06-17-13)
22
SMSC USB3613
DATASHEET
USB 2.0 Hi-Speed 3-Port Hub Controller Optimized for Portable Applications
Datasheet
the operating mode is changed by the system. The only device registers accessible to the SOC are
the run time registers described in Section 7.3.1, "SMBus Run Time Accessible Registers," on page 35.
If RESET_N is asserted low, then Standby Mode is entered. The device may then be placed into any
of the designated Hub stages. Asserting the soft disconnect on the upstream port will cause the Hub
to return to the Hub.Connect stage until the soft disconnect is negated. If the HUB_CONN pin
transitions from asserted to negated, the device will return to the Hub.Connect stage.
To save power, communication over the SMBus is not supported while in USB Suspend. The system
can, however, command the device to wake up by the asserting the IRQ_N pin. The system can
prevent the device from going to sleep by asserting the ClkSusp control bit of the Configure Portable
Hub Register anytime before entering USB Suspend. While the device is kept awake during USB
Suspend, it will provide the SMBus functionality at the expense of not meeting USB requirements for
average suspend current consumption.
SMSC USB3613
23
Revision 1.0 (06-17-13)
DATASHEET
USB 2.0 Hi-Speed 3-Port Hub Controller Optimized for Portable Applications
Datasheet
Chapter 6 Device Configuration
The device supports a large number of features (some mutually exclusive), and must be configured in
order to correctly function when attached to a USB host controller. The hub can be configured either
internally or externally depending on the implemented interface.
SMSC provides a comprehensive software programming tool, Pro-Touch, for configuring the USB3613
functions, registers and OTP memory. All configuration is to be performed via the Pro-Touch
programming tool. For additional information on the Pro-Touch programming tool, contact your local
SMSC sales representative.
6.1
Configuration Method Selection
The hub will interface to external memory depending on the configuration of the device pins associated
with each interface type. The device will first check whether an external SPI ROM is present. If present,
the device will operate entirely from the external ROM. When an external SPI ROM is not present, the
device will check whether the SMBus is configured. When the SMBus is enabled, it can be used to
configure the internal device registers via the XDATA address space, or to program the internal OTP
memory. If no external options are detected, the device will operate using the internal default and
configuration strap settings. The order in which device configuration is attempted is summarized below:
1. SPI (Reading the configuration from an SPI ROM)
2. SMBus (either writing the configuration registers in the XDATA address space, or to OTP)
3. Internal default settings (with or without configuration strap over-rides)
Note: Refer to Chapter 7, "Device Interfaces," on page 28 for detailed information on each device
configuration interface.
6.2
Customer Accessible Functions
The following USB or SMBus accessible functions are available to the customer via the SMSC Pro-
Touch Programming Tool.
Note: For additional programming details, refer to the SMSC Pro-Touch Programming Tool User
Manual.
6.2.1
USB Accessible Functions
6.2.1.1
VSM commands over USB
By default, Vendor Specific Messaging (VSM) commands to the hub are enabled. The supported
commands are:
Enable Embedded Controller
Disable Embedded Controller
Enable Special Resume
Disable Special Resume
Reset Hub
Revision 1.0 (06-17-13)
24
SMSC USB3613
DATASHEET
USB 2.0 Hi-Speed 3-Port Hub Controller Optimized for Portable Applications
Datasheet
2
6.2.1.2
6.2.1.3
6.2.1.4
6.2.1.5
I C Master Access over USB
Access to I2C devices is performed as a pass-through operation from the USB Host. The device
firmware has no knowledge of the operation of the attached I2C device. The supported commands are:
Enable I2C pass through mode
Disable I2C pass through mode
I2C write
I2C read
Send I2C start
Send I2C stop
SPI Access over USB
Access to an attached SPI device is performed as a pass-through operation from the USB Host. The
device firmware has no knowledge of the operation of the attached SPI device. The supported
commands are:
Enable SPI pass through mode
Disable SPI pass through mode
SPI write
SPI read
Note: Refer to Section 7.1, "SPI Interface," on page 28 for additional information on the SPI interface.
OTP Access over USB
The OTP ROM in the device is accessible via the USB bus. All OTP parameters can modified via the
USB Host. The OTP operates in Single Ended mode. The supported commands are:
Enable OTP reset
Set OTP operating mode
Set OTP read mode
Program OTP
Get OTP status
Program OTP control parameters
Battery Charging Access over USB
The Battery charging behavior of the device can be dynamically changed by the USB Host when
something other than the preprogrammed or OTP programmed behavior is desired. The supported
commands are:
Enable/Disable battery charging
Upstream battery charging mode control
Downstream battery charging mode control
Battery charging timing parameters
Download custom battery charging algorithm
SMSC USB3613
25
Revision 1.0 (06-17-13)
DATASHEET
USB 2.0 Hi-Speed 3-Port Hub Controller Optimized for Portable Applications
Datasheet
6.2.1.6
Other Embedded Controller functions over USB
The following miscellaneous functions may be configured via USB:
Enable/Disable Embedded controller enumeration
Program Configuration parameters.
Program descriptor fields:
—Language ID
—Manufacturer string
—Product string
—idVendor
—idProduct
—bcdDevice
6.2.2
SMBus Accessible Functions
6.2.2.1
OTP Access over SMBus
The device’s OTP ROM is accessible over SMBus. All OTP parameters can modified via the SMbus
Host. The OTP can be programmed to operate in Single-Ended, Differential, Redundant, or Differential
Redundant mode, depending on the level of reliability required. The supported commands are:
Enable OTP reset
Set OTP operating mode
Set OTP read mode
Program OTP
Get OTP Status
Program OTP control parameters
6.2.2.2
Configuration Access over SMBus
The following functions are available over SMBus prior to the hub attaching to the USB host:
Program Configuration parameters.
Program descriptor fields:
—Language ID
—Manufacturer string
—Product string
—idVendor
—idProduct
—bcdDevice
Program Control Register
6.2.2.3
Run time Access over SMBus
There is a limited number of registers that are accessible via the SMBus during run time operation of
the device. Refer to Section 7.3.1, "SMBus Run Time Accessible Registers," on page 35 for details.
Revision 1.0 (06-17-13)
26
SMSC USB3613
DATASHEET
USB 2.0 Hi-Speed 3-Port Hub Controller Optimized for Portable Applications
Datasheet
6.3
Device Configuration Straps
Configuration straps are multi-function pins that are driven as outputs during normal operation. During
a Power-On Reset (POR) or an External Chip Reset (RESET_N), these outputs are tri-stated. The high
or low state of the signal is latched following de-assertion of the reset and is used to determine the
default configuration of a particular feature. Configuration straps are latched as a result of a Power-On
Reset (POR) or a External Chip Reset (RESET_N). Configuration strap signals are noted in Chapter 3,
"Ball Descriptions," on page 10 and are identified by an underlined symbol name. The following sub-
sections detail the various configuration straps.
Configuration straps include internal resistors in order to prevent the signal from floating when
unconnected. If a particular configuration strap is connected to a load, an external pull-up or pull-down
should be used to augment the internal resistor to ensure that it reaches the required voltage level
prior to latching. The internal resistor can also be overridden by the addition of an external resistor.
Note: The system designer must guarantee that configuration straps meet the timing requirements
specified in Section 9.5.2, "Reset and Configuration Strap Timing," on page 63 and Section
9.5.1, "Power-On Configuration Strap Valid Timing," on page 62. If configuration straps are not
at the correct voltage level prior to being latched, the device may capture incorrect strap
values.
Note: Configuration straps must never be driven as inputs. If required, configuration straps can be
augmented, or overridden with external resistors.
6.3.1
SPI Speed Select (SPI_SPD_SEL)
This strap is used to select the speed of the SPI as follows:
Table 6.1 SPI_SPD_SEL Configuration Definitions
SPI_SPD_SEL
DEFINITION
‘0’
‘1’
30 MHz SPI Operation (Default)
60 MHz SPI Operation
Note: If the latched value on reset is 1, this pin is tri-stated when the chip is in the suspend state. If
the latched value on reset is 0, this pin is driven low during a suspend state.
SMSC USB3613
27
Revision 1.0 (06-17-13)
DATASHEET
USB 2.0 Hi-Speed 3-Port Hub Controller Optimized for Portable Applications
Datasheet
Chapter 7 Device Interfaces
The USB3613 provides multiple interfaces for configuration and external memory access. This chapter
details the various device interfaces and their usage.
Note: For information on device configuration, refer to Chapter 6, "Device Configuration," on page 24.
7.1
SPI Interface
The device is capable of code execution from an external SPI ROM. On power up, the firmware looks
for an external SPI flash device that contains a valid signature of 2DFU (device firmware upgrade)
beginning at address 0xFFFA. If a valid signature is found, then the external ROM is enabled and the
code execution begins at address 0x0000 in the external SPI device. If a valid signature is not found,
then execution continues from internal ROM. The following sections describe the interface options to
the external SPI ROM.
The SPI interface is always enabled after reset. It can be disabled by setting the SPI_DISABLE bit in
the UTIL_CONFIG1 register.
Note: For SPI timing information, refer to Section 9.5.7, "SPI Timing," on page 64.
7.1.1
Operation of the Hi-Speed Read Sequence
The SPI controller will automatically handle code reads going out to the SPI ROM address. When the
controller detects a read, the controller drives SPI_CE_N low, and outputs 0x0B, followed by the 24-
bit address. The SPI controller outputs a DUMMY byte. The next eight clocks will clock-in the first byte.
When the first byte is clocked-in, a ready signal is sent back to the processor, and the processor gets
one byte.
After the processor gets the first byte, its address will change. If the address is one more than the last
address, the SPI controller will clock out one more byte. If the address is anything other than one more
than the last address, the SPI controller will terminate the transaction by driving SPI_CE_N high. As
long as the addresses are sequential, the SPI Controller will continue clocking data in.
SPI_CE_N
80
55 56
63 64
71 72
0
4
5
6
7 8
15 16
23 24
31 32
39 40
47 48
1
2
3
SPI_CLK
SPI_DO
X
ADD.
ADD.
ADD.
0B
MSB
MSB
N
N+1
N+2
N+3
N+4
HIGH IMPEDANCE
DOUT
DOUT
DOUT
DOUT
DOUT
SPI_DI
MSB
Figure 7.1 SPI Hi-Speed Read Sequence
Revision 1.0 (06-17-13)
28
SMSC USB3613
DATASHEET
USB 2.0 Hi-Speed 3-Port Hub Controller Optimized for Portable Applications
Datasheet
7.1.2
Operation of the Dual High Speed Read Sequence
The SPI controller also supports dual data mode. When configured in dual mode, the SPI controller
will automatically handle XDATA reads going out to the SPI ROM. When the controller detects a read,
the controller drives SPI_CE_N low and outputs 0x3B (the value must be programmed into the SPI_
FR_OPCODE Register) followed by the 24 bit address. Bits 23 through Bit 17 are forced to zero, and
address bits 16 through 0 are directly from the XDATA address bus. Because it is in fast read mode,
the SPI controller then outputs a DUMMY byte. The next four clocks will clock-in the first byte. The
data appears two bits at a time on SPI_DO and SPI_DI. When the first byte is clocked in, a ready
signal is sent back to the processor, and the processor gets one byte.
After the processor gets the first byte, its address will change. If the address is one more than the last
address, the SPI controller will clock out one more byte. If the address in anything other than one more
than the last address, the SPI controller will terminate the transaction by driving SPI_CE_N high. As
long as the addresses are sequential, the SPI Controller will continue clocking data in.
SPI_CE_N
SPI_CLK
59
47 48
51 52
55 56
0
4
5
6
7 8
15 16
23 24
31 32
39 40
43 44
1
2
3
N
N+1
N+2
N+3
N+4
D1
Bits-6,4,2,0
D2
D3
D4
Bits-6,4,2,0
D5
Bits-6,4,2,0
X
ADD.
ADD.
ADD.
0B
SPI_DO
SPI_DI
Bits-6,4,2,0 Bits-6,4,2,0
MSB
MSB
MSB
N
N+1
N+2
N+3
N+4
D1
D2
D3
D4
D5
Bits-7,5,3,1
HIGH IMPEDANCE
Bits-7,5,3,1 Bits-7,5,3,1 Bits-7,5,3,1 Bits-7,5,3,1
MSB
Figure 7.2 SPI Dual Hi-Speed Read Sequence
7.1.3
7.1.4
32 Byte Cache
There is a 32-byte pipeline cache with an associated base address pointer and length pointer. Once
the SPI controller detects a jump, the base address pointer is initialized to that address. As each new
sequential data byte is fetched, the data is written into the cache and the length is incremented. If the
sequential run exceeds 32 bytes, the base address pointer is incremented to indicate the last 32 bytes
fetched. If the firmware performs a jump, and the jump is in the cache address range, the fetch is done
in 1 clock from the internal cache instead of an external access.
Interface Operation to the SPI Port When Not Performing Fast Reads
There is a 8-byte command buffer (SPI_CMD_BUF[7:0]), an 8-byte response buffer
(SPI_RESP_BUF[7:0]), and a length register that counts out the number of bytes (SPI_CMD_LEN).
Additionally, there is a self-clearing GO bit in the SPI_CTL register. Once the GO bit is set, device
drives SPI_CE_N low and starts clocking. It will then output SPI_CMD_LEN x 8 number of clocks. After
the first COMMAND byte has been sent out, the SPI_DI input is stored in the SPI_RESP buffer. If the
SPI_CMD_LEN is longer than the SPI_CMD_BUF, don’t cares are sent out on the SPI_DO output.
This mode is used for program execution out of internal RAM or ROM.
SMSC USB3613
29
Revision 1.0 (06-17-13)
DATASHEET
USB 2.0 Hi-Speed 3-Port Hub Controller Optimized for Portable Applications
Datasheet
Automatic reads and writes happen when there is an external XDATA read or write, using the serial
stream that has been previously discussed.
7.1.5
Erase Example
To perform a SCTR_ERASE, 32BLK_ERASE, or 64BLK_ERASE, the device writes 0x20, 0x52, or
0xD8, respectively to the first byte of the command buffer, followed by a 3-byte address. The length
of the transfer is set to 4 bytes. To perform this, the device drives SPI_CE_N low, then counts out 8
clocks. It then outputs on SPI_DO the 8 bits of command, followed by 24 bits of address of the location
to be erased. When the transfer is complete, SPI_CE_N goes high, while the SPI_DI line is ignored
in this example.
SPI_CE_N
0
4 5 6
7 8
1
2 3
1516
23 24
31
SPI_CLK
ADD.
ADD.
ADD.
Command
SPI_DO
SPI_DI
MSB
MSB
HIGH IMPEDANCE
Figure 7.3 SPI Erase Sequence
Revision 1.0 (06-17-13)
30
SMSC USB3613
DATASHEET
USB 2.0 Hi-Speed 3-Port Hub Controller Optimized for Portable Applications
Datasheet
7.1.6
Byte Program Example
To perform a Byte Program, the device writes 0x02 to the first byte of the command buffer, followed
by a 3-byte address of the location that will be written to, and one data byte. The length of the transfer
is set to 5 bytes. The device first drives SPI_CE_N low, then SPI_DO outputs 8 bits of command,
followed by 24 bits of address, and one byte of data. SPI_DI is not used in this example.
SPI_CE_N
SPI_CLK
0
4 5 6
7 8
1
2 3
15
16
23
24
3132
39
0xFE
/0xFF
0x00
0xBF
Data
0xDB
SPI_DO
SPI_DI
MSB
MSB
MSB LSB
HIGH IMPEDANCE
Figure 7.4 SPI Byte Program Sequence
SMSC USB3613
31
Revision 1.0 (06-17-13)
DATASHEET
USB 2.0 Hi-Speed 3-Port Hub Controller Optimized for Portable Applications
Datasheet
7.1.7
Command Only Program Example
To perform a single byte command such as the following:
- WRDI
- WREN
- EWSR
- CHIP_ERASE
- EBSY
- DBSY
The device writes the opcode into the first byte of the SPI_CMD_BUF and the SPI_CMD_LEN is set
to one. The device first drives SPI_CE_N low, then 8 bits of the command are clocked out on SPI_DO.
SPI_DI is not used in this example.
SPI_CE_N
0 1 2 3 4 5 6 7
SPI_CLK
SPI_DO
SPI_DI
Command
MSB
HIGH IMPEDANCE
Figure 7.5 SPI Command Only Sequence
Revision 1.0 (06-17-13)
32
SMSC USB3613
DATASHEET
USB 2.0 Hi-Speed 3-Port Hub Controller Optimized for Portable Applications
Datasheet
7.1.8
JEDEC-ID Read Example
To perform a JEDEC-ID command, the device writes 0x9F into the first byte of the SPI_CMD_BUF.
The length of the transfer is 4 bytes. The device first drives SPI_CE_N low, then SPI_DO is output
with 8 bits of the command, followed by the 24 bits of dummy bytes (due to the length being set to 4).
When the transfer is complete, SPI_CE_N goes high. After the first byte, the data on SPI_DI is clocked
into the SPI_RSP_BUF. At the end of the command, there are three valid bytes in the SPI_RSP_BUF.
In this example, 0xBF, 0x25, 0x8E.
SPI_CE_N
SPI_CLK
0
4
5 6
9 10 1112 1314 15 16 17 18 19 20 2122 2324 25 26 272829 30 31 32 33 34
1
2
3
7
8
SPI_DO
SPI_DI
9F
MSB
HIGH IMPEDANCE
8E
BF
25
MSB
MSB
Figure 7.6 SPI JEDEC-ID Read Sequence
7.2
I2C Master Interface
The I2C master interface implements a subset of the I2C Master Specification (Please refer to the
Philips Semiconductor Standard I2C-Bus Specification for details on I2C bus protocols). The device’s
I2C master interface conforms to the Standard-Mode I2C Specification (100 kbit/s transfer rate and 7-
bit addressing) for protocol and electrical compatibility. The device acts as the master and generates
the serial clock SCL, controls the bus access (determines which device acts as the transmitter and
which device acts as the receiver), and generates the START and STOP conditions.
Note: Extensions to the I2C Specification are not supported.
Note: All device configuration must be performed via the SMSC Pro-Touch Programming Tool. For
additional information on the Pro-Touch programming tool, contact your local SMSC sales
representative.
2
7.2.1
I C Message Format
7.2.1.1
Sequential Access Writes
The I2C interface supports sequential writing of the device’s register address space. This mode is
useful for configuring contiguous blocks of registers. Figure 7.7 shows the format of the sequential
SMSC USB3613
33
Revision 1.0 (06-17-13)
DATASHEET
USB 2.0 Hi-Speed 3-Port Hub Controller Optimized for Portable Applications
Datasheet
write operation. Where color is visible in the figure, blue indicates signaling from the I2C master, and
gray indicates signaling from the slave.
S
7-Bit Slave Address
0
A
xxxxxxxx
A
nnnnnnnn
A
...
nnnnnnnn
A
P
Register
Address
(bits 7-0)
Data value for
XXXXXX
Data value for
XXXXXX + y
Figure 7.7 I2C Sequential Access Write Format
In this operation, following the 7-bit slave address, the 8-bit register address is written indicating the
start address for sequential write operation. Every subsequent access is a data write to a data register,
where the register address increments after each access and an ACK from the slave occurs.
Sequential write access is terminated by a Stop condition.
7.2.1.2
Sequential Access Reads
The I2C interface supports direct reading of the device registers. In order to read one or more register
addresses, the starting address must be set by using a write sequence followed by a read. The read
register interface supports auto-increment mode. The master must send a NACK instead of an ACK
when the last byte has been transferred.
In this operation, following the 7-bit slave address, the 8-bit register address is written indicating the
start address for the subsequent sequential read operation. In the read sequence, every data access
is a data read from a data register where the register address increments after each access. The write
sequence can end with optional Stop (P). If so, the read sequence must begin with a Start (S).
Otherwise, the read sequence must start with a Repeated Start (Sr).
Figure 7.8 shows the format of the read operation. Where color is visible in the figure, blue and gold
indicate signaling from the I2C master, and gray indicates signaling from the slave.
Optional. If present, Next
access must have Start(S),
otherwise Repeat Start (Sr)
S
7-Bit Slave Address
0
A
xxxxxxxx
A
P
Register
Address
(bits 7-0)
If previous write setting up
Register address ended with a
Stop (P), otherwise it will be
Repeated Start (Sr)
S
7-Bit Slave Address
1
ACK n n n n n n n n ACK n n n n n n n n ACK
...
n n n n n n n n NACK
P
Register value
for xxxxxxxx
Register value
for xxxxxxxx + 1
Register value
for xxxxxxxx + y
Figure 7.8 I2C Sequential Access Read Format
Revision 1.0 (06-17-13)
34
SMSC USB3613
DATASHEET
USB 2.0 Hi-Speed 3-Port Hub Controller Optimized for Portable Applications
Datasheet
2
7.2.2
Pull-Up Resistors for I C
The circuit board designer is required to place external pull-up resistors (10 kΩ recommended) on the
SDA & SCL signals (per SMBus 1.0 Specification) to Vcc in order to assure proper operation.
7.3
SMBus Slave Interface
The USB3613 includes an integrated SMBus slave interface, which can be used to access internal
device run time registers or program the internal OTP memory. SMBus detection is accomplished by
detection of pull-up resistors (10 KΩ recommended) on both the SMBDATA and SMBCLK signals. To
disable the SMBus, a pull-down resistor of 10 KΩ must be applied to SMBDATA. The SMBus interface
can be used to configure the device as detailed in Section 6.1, "Configuration Method Selection," on
page 24.
Note: All device configuration must be performed via the SMSC Pro-Touch Programming Tool. For
additional information on the Pro-Touch programming tool, contact your local SMSC sales
representative.
7.3.1
SMBus Run Time Accessible Registers
Table 7.1 provides a summary of the SMBus accessible run time registers. Each register is detailed in
the subsequent tables.
Note: The SMBus page register must be configured to allow the SOC to access the proper register
space. Refer to Section 7.3.2, "Run Time SMBus Page Register," on page 48 for details.
Table 7.1 SMBus Accessible Run Time Registers
XDATA
ADDR
NAME
UP_BC_DET
0x30E2
0x30E3
0x30E4
0x30E5
0x30E6
0x30E8
0x30E9
0x30EC
0x30ED
0x30EE
0x318B
0x318E
0x6100
0x6101
Table 7.2, "Upstream Battery Charging Detection Control Register"
Table 7.3, "Upstream Custom Battery Charger Control Register"
Table 7.4, "Upstream Custom Battery Charger Status Register"
Table 7.5, "Port Power Status Register"
UP_CUST_BC_CTL
UP_CUST_BC_STAT
PORT_PWR_STAT
OCS_STAT
Table 7.6, "OCS Status Register"
INT_STATUS
Table 7.7, "Serial Port Interrupt Status Register"
INT_MASK
Table 7.8, "Serial Port Interrupt Mask Register"
BC_CHG_MODE
CHG_DET_MSK
CFGP
Table 7.9, "Upstream Battery Charger Mode Register"
Table 7.10, "Charge Detect Mask Register"
Table 7.11, "Configure Portable Hub Register"
PSELSUSP
Table 7.12, "Port Select and Low-Power Suspend Register"
Table 7.13, "Connect Configuration Register"
CONNECT_CFG
BC_CTL_1 (Upstream)
Table 7.14, "Upstream (Port 0) Battery Charging Control 1 Register"
Table 7.15, "Upstream (Port 0) Battery Charging Control 2 Register"
BC_CTL_2
(Upstream)
SMSC USB3613
35
Revision 1.0 (06-17-13)
DATASHEET
USB 2.0 Hi-Speed 3-Port Hub Controller Optimized for Portable Applications
Datasheet
Table 7.1 SMBus Accessible Run Time Registers (continued)
XDATA
ADDR
NAME
BC_CTL_RUN_TIME
(Upstream)
0x6102
0x6103
Table 7.16, "Upstream (Port 0) Battery Charging Run Time Control
Register"
BC_CTL_DET
(Upstream)
Table 7.17, "Upstream (Port 0) Battery Charging Detect Register"
Table 7.2 Upstream Battery Charging Detection Control Register
UPSTREAM BATTERY CHARGING REGISTER
UP_BC_DET
(0x30E2 - RESET= 0x02)
BIT
NAME
R/W
DESCRIPTION
7:5
CHARGER_TYPE
R/W
Read Only.
This field indicates the result of the automatic charger detection. Values
reported depend on EnhancedChrgDet bit setting in Upstream Battery
Charger Mode Register.
If EnhancedChrgDet = 1
000 = Charger Detection is not complete.
001 = DCP - Dedicated Charger Port
010 = CDP – Charging Downstream Port
011 = SDP – Standard Downstream Port
100 = Apple Low Current Charger
101 = Apple High Current Charger
110 = Apple Super High Current Charger
111 = Charger Detection Disabled
If EnhancedChrgDet = 0
000 = Charger Detection is not complete.
001 = DCP/CDP – Dedicated Charger or Charging Downstream Port
010 = Reserved
011 = SDP – Standard Downstream Port
100 = Apple Low Current Charger
101 = Apple High Current Charger
110 = Apple Super High Current Charger
111 = Charger Detection Disabled
4
CHGDET_COMPLETE
R
Indicates Charger Detection has been run and is completed. This bit is
negated when START_CHG_DET is asserted high.
3
Reserved
R/W
R
Reserved for debugging
2:1
CHG_DET[1:0]
Indicates encoded status of what chargers or status has been detected
according to the settings in the Charge Detect Mask Register. It can be
used to determine what current can be drawn from the upstream USB
port.
00 = No selected Chargers or Status identified
01 = 100ma (VBUS detect without enumeration)
10 = 500ma (Device enumerated, Set Config seen)
11 = 1000+ma (Charger detected)
The actual current amount for the charger will be system dependent
Revision 1.0 (06-17-13)
36
SMSC USB3613
DATASHEET
USB 2.0 Hi-Speed 3-Port Hub Controller Optimized for Portable Applications
Datasheet
Table 7.2 Upstream Battery Charging Detection Control Register (continued)
UP_BC_DET
(0x30E2 - RESET= 0x02)
UPSTREAM BATTERY CHARGING REGISTER
DESCRIPTION
BIT
NAME
R/W
0
START_CHG_DET
R/W
Manually Initiates a USB battery charger detection sequence at the time
of assertion. This bit must not be set while hub is in operation. This bit
is cleared automatically when the manual battery charger detection
sequence is completed.
0 = Write: No Effect / Read: Battery Charger Detection Sequence
Completed or not run.
1 = Write: Start Battery Charger Detection / Read: Battery Charger
Detection Sequence is running
Table 7.3 Upstream Custom Battery Charger Control Register
UPSTREAM CUSTOM BATTERY CHARGING CONTROL
UP_CUST_BC_CTL
(0x30E3 - RESET= 0x00)
BIT
NAME
R/W
DESCRIPTION
7
I2CControl
R/W
I2C control
0: I2C control disabled
1: I2C control enabled
6
5
4
3
DmPulldownEn
DpPulldownEn
IdatSinkEn
R/W
R/W
R/W
R/W
DM 15K pull down resistor control
0: DM 15K pull down resistor disabled
1: DM 15K pull down resistor enabled
DP 15K pull down resistor control
0: DP 15K pull down resistor disabled
1: DP 15K pull down resistor enabled
Idat current sink control
0: Idat current sink disabled
1: Idat current sink enabled
HostChrgEn
Host charger detection swap control
0: Charger detection connections of DP and DM are not swapped
(standard)
1: Charger detection connections of DP and DM are swapped. The USB
signal path is not reversed.
2
1
VdatSrcEn
R/W
R/W
Vdat voltage source control
0: Vdat voltage source disabled
1: Vdat voltage source enabled
ContactDetectEn
Contact detect current source control
0: Contact detect current source disabled
1: Contact detect current source enabled
SMSC USB3613
37
Revision 1.0 (06-17-13)
DATASHEET
USB 2.0 Hi-Speed 3-Port Hub Controller Optimized for Portable Applications
Datasheet
Table 7.3 Upstream Custom Battery Charger Control Register (continued)
UP_CUST_BC_CTL
(0x30E3 - RESET= 0x00)
UPSTREAM CUSTOM BATTERY CHARGING CONTROL
BIT
NAME
R/W
DESCRIPTION
0
SeRxEn
R/W
Single-ended receiver control
0: Single-ended receiver disabled
1: Single-ended receiver enabled
Table 7.4 Upstream Custom Battery Charger Status Register
UPSTREAM CUSTOM BATTERY CHARGING STATUS
UP_CUST_BC_STAT
(0x30E4 - RESET= 0x00)
BIT
NAME
R/W
DESCRIPTION
7:4
3
Reserved
RxHiCurr
R
R
Reserved
DM high current Apple charger output
0: DM signal is not above the VSE_RXH threshold
1: DM signal is above the VSE_RXH threshold
2
1
0
DmSeRx
DpSeRx
VdatDet
R
R
R
DM Single Ended Receiver Status
DP Single Ended Receiver Status
Vdat detect
0: Vdat not detected
1: Vdat detect comparator output
Table 7.5 Port Power Status Register
PORT POWER STATUS
PORT_PWR_STAT
(0x30E5 - RESET= 0x00)
BIT
NAME
R/W
DESCRIPTION
7:5
4:1
Reserved
R
R
Reserved
PRTPWR[4:1]
Optional status to SOC indicating that power to the corresponding
downstream port was enabled by the USB Host for the specified port. Not
required for an embedded application.
This is a read-only status bit. Actual control over port power is
implemented by the USB Host, OCS Status Register and Downstream
Battery Charging logic, if enabled.
0: USB Host has not enabled port to be powered or in downstream battery
charging and corresponding OCS bit has been set
1: USB Host has enabled port to be powered
0
Reserved
R
Reserved
Revision 1.0 (06-17-13)
38
SMSC USB3613
DATASHEET
USB 2.0 Hi-Speed 3-Port Hub Controller Optimized for Portable Applications
Datasheet
Table 7.6 OCS Status Register
OCS_STAT
(0x30E6 - RESET= 0x00)
PORT POWER STATUS
BIT
NAME
R/W
DESCRIPTION
7:5
4:1
Reserved
OCS[4:1]
R
R
Reserved
Optional control from SOC that indicates an over-current condition on the
corresponding port for HUB status reporting to USB host. Also resets
corresponding PRTPWR status bit in the Port Power Status Register. Not
required for an embedded application.
0: No Over Current Condition
1: Over Current Condition
0
Reserved
R
Reserved
Table 7.7 Serial Port Interrupt Status Register
SERIAL PORT INTERRUPT STATUS
SP_INT_STATUS
(0x30E8 - RESET= 0x00)
BIT
NAME
R/W
DESCRIPTION
7
Interrupt
R/W
Read:
0: INT_N pin has not been asserted low due to unmasked interrupt
1: INT_N pin has been asserted low due to unmasked interrupt
Write:
0: Negate INT_N pin high
1: No Effect – INT_N pin and register retains its current value
6:5
4
Reserved
R
Reserved
HubSuspInt
R/W
Read:
0: Hub has not entered USB suspend since last HubSuspInt reset
1: Hub has entered USB suspend
Write:
0: Negate HubSuspInt status low
1: No Effect
3
HubCfgInt
R/W
Read:
0: Hub has not been configured by the USB Host since last HubConfInt
reset
1: Hub has been configured by the USB host
Write:
0: Negate HubConfInt status low
1: No Effect
SMSC USB3613
39
Revision 1.0 (06-17-13)
DATASHEET
USB 2.0 Hi-Speed 3-Port Hub Controller Optimized for Portable Applications
Datasheet
Table 7.7 Serial Port Interrupt Status Register (continued)
SP_INT_STATUS
(0x30E8 - RESET= 0x00)
SERIAL PORT INTERRUPT STATUS
DESCRIPTION
BIT
NAME
R/W
2
PrtPwrInt
R/W
Read:
0: Port Power Status Register has not been updated since last PrtPwrInt
reset
1: Port Power Status Register has been updated
Write:
0: Negate PrtPwrInt status low
1: No Effect
1
0
ChrgDetInt
R/W
R/W
Read:
0: Charge detect has not been updated since last ChrgDetInt reset
1: Charge detect as been updated
Write:
0: Negate ChrgDetInt status low
1: No Effect
ChrgDetCompInt
Read:
0: Charge detection not completed since last ChrgDetCompInt reset
1: Charge detection completed
Write:
0: Negate ChrgDetCompInt status low
1: No Effect
Note: Refer to Section 8.9, "Interrupt Output (INT_N)," on page 56 for additional information on the
INT_N interrupt.
Table 7.8 Serial Port Interrupt Mask Register
SP_INT_MSK
(0x30E9 - RESET= 0x02)
SERIAL PORT INTERRUPT MASK
BIT
NAME
R/W
DESCRIPTION
7:5
4
Reserved
R
Reserved
HubSuspMask
R/W
0 = INT_N pin is not affected by Hub entering suspend
1 = INT_N pin is asserted when Hub enters suspend
3
2
HubCfgMask
PrtPwrMask
R/W
R/W
0 = INT_N pin is not affected by Hub configuration event
1 = INT_N pin is asserted when Hub configured by USB Host
0 = INT_N pin is not affected by Port Power register
1 = INT_N pin is asserted when Port Power register has been updated by
USB Host
1
0
ChrgDetMask
R/W
R/W
0 = INT_N pin is not affected by CHG_DET_N
1 = INT_N pin is asserted when CHG_DET bit in Charger Detect Register
is asserted
ChgDetCompMask
0 = INT_N pin is not affected by ChrgDetComplete
1 = INT_N pin is asserted when ChrgDetComplete bit in Charger Detect
Register is asserted high
Revision 1.0 (06-17-13)
40
SMSC USB3613
DATASHEET
USB 2.0 Hi-Speed 3-Port Hub Controller Optimized for Portable Applications
Datasheet
Note: Refer to Section 8.9, "Interrupt Output (INT_N)," on page 56 for additional information on the
INT_N interrupt.
Table 7.9 Upstream Battery Charger Mode Register
BC_CHG_MODE
(0x30EC - RESET= 0x14
UPSTREAM BATTERY CHARGER MODE
DESCRIPTION
BIT
NAME
R/W
7:6
5
Reserved
HoldVdat
R
Reserved
R/W
Dead Battery Vdat Detect voltage source enable
0: The charger detection state machine will turn off the Vdat Source at the
end of the charger detection routine.
1: The charger detection state machine leave Vdat Source on during
Hub.Connect stage when a SDP has been detected.
4
3
Reserved
R
Reserved
SE1ChrgDet
R/W
Apple type charger detection control
0: The charger detection routine will not look for the attachment of an
Apple type charger.
1: The charger detection routine will look for the attachment of an Apple
type charger.
2
EnhancedChrgDet
Reserved
R/W
Enhanced charge detect control
0: The charger detection routine will not reverse Vdat SRC to differentiate
between a CDP and a DCP.
1: The charger detection routine will reverse Vdat SRC to differentiate
between a CDP and a DCP.
1:0
R
Reserved
SMSC USB3613
41
Revision 1.0 (06-17-13)
DATASHEET
USB 2.0 Hi-Speed 3-Port Hub Controller Optimized for Portable Applications
Datasheet
Table 7.10 Charge Detect Mask Register
CHG_DET_MSK
(0x30ED - RESET= 0x1F)
CHARGE DETECT MASK
DESCRIPTION
BIT
NAME
R/W
7
CONFIGURED
R/W
0: battChg.chgDet is not affected for this mask set when Hub is in a
session and has been configured by the USB Host
1: battChg.chgDet indicates status for this mask set met when Hub is in a
session and has been configured by the USB Host
6
5
4
3
2
1
CONNECTED
SUSPENDED
SE1SMask
SE1HMask
SE1LMask
CDPMask
R/W
R/W
R/W
R/W
R/W
R/W
0: battChg.chgDet is not affected for this mask set when Hub has
successfully connected with an upstream Host
1: battChg.chgDet indicates status for this mask set met when Hub has
successfully connected with an upstream host.
0: battChg.chgDet is not affected for this mask set when Hub is in a
session and has been suspended by the USB Host
1: battChg.chgDet indicates status for this mask set met when Hub is in a
session and has been suspended by the USB Host
0: battChg.chgDet is not affected for this mask set by detection of a Apple
Super High Current Charger
1: battChg.chgDet indicates status for this mask set met when a SE1
(Apple) Super High Current Charger is detected
0: battChg.chgDet is not affected for this mask set by detection of a Apple
High Current Charger
1: battChg.chgDet indicates status for this mask set met when a Apple
High Current Charger is detected
0: battChg.chgDet is not affected for this mask set by detection of a Apple
Low Current Charger
1: battChg.chgDet indicates status for this mask set met when a Apple
Low Current Charger is detected
0: battChg.chgDet is not affected for this mask set by detection of a CDP
Charger
1: battChg.chgDet indicates status for this mask set met when a CDP
Charger is detected
This mask bit should only be enabled if EnhancedChrgDet is asserted in
the Upstream Battery Charger Mode Register. Without it, the charger
detection is unable to identify a CDP.
0
DCPMask
R/W
0: battChg.chgDet is not affected for this mask set by detection of a DCP
Charger
1: battChg.chgDet indicates status for this mask set met when a DCP
Charger is detected
Revision 1.0 (06-17-13)
42
SMSC USB3613
DATASHEET
USB 2.0 Hi-Speed 3-Port Hub Controller Optimized for Portable Applications
Datasheet
Table 7.11 Configure Portable Hub Register
CFGP
PORTABLE HUB CONFIGURATION REGISTER
DESCRIPTION
(0x30EE - RESET= 0x10)
BIT
NAME
R/W
7
ClkSusp
R/W
0: Allow device to gate-off its internal clocks during suspend mode in order
to meet USB suspend current requirements.
1: Force device to run internal clock even during USB suspend (will cause
device to violate USB suspend current limit - intended for test or self-
powered applications which require use of SMBus during USB session.)
6
IntSusp
R/W
0: INT_N pin function retains event sensitive role of a general serial port
interrupt.
1: INT_N pin function is a level sensitive USB suspend interrupt indication.
Allows system to adjust current consumption to comply with USB
specification limits when hub is in the USB suspend state.
Note:
5:1
DIS_CHP_PHY_CL
K[5:1]
R/W
A ‘1’ disables the PHY clock of the corresponding port:
Bit 5 - Downstream port 5
Bit 4 - Downstream port 4
Bit 3 - Downstream port 3
Bit 2 - Downstream port 2
Bit 1 - Downstream port 1
0
Reserved
R
Always read ‘0’
Table 7.12 Port Select and Low-Power Suspend Register
PORT SELECT AND LOW POWER SUSPEND REGISTER
DESCRIPTION
PSELSUSP
(0x318B- RESET=0x00)
BIT
7:6
NAME
R/W
APortSel
R/W
Specifies which downstream USB port is associated with the
PRTPWRA pin function.
‘00’ - Port 1
‘01’ - Port 2
‘10’ - Port 3
‘11’ - Port 4
5:0
Note:
Reserved
R
Always read ‘0’
This register should be assigned during the Hub.Config or Hub.Connect stages, and should not be
dynamically updated during Hub.Communication stage or undefined behavior may result.
SMSC USB3613
43
Revision 1.0 (06-17-13)
DATASHEET
USB 2.0 Hi-Speed 3-Port Hub Controller Optimized for Portable Applications
Datasheet
Table 7.13 Connect Configuration Register
CONNECT_CFG
(0x318E- RESET=0x00)
CONNECT CONFIGURATION REGISTER
DESCRIPTION
BIT
NAME
R/W
7:2
1
Reserved
R
Reserved
EN_FLEX_MODE
R/W
Flex Connect mode enable
0: Flex Connect mode is disabled. (Normal hub operation)
1: Flex Connect mode is enabled
0
FLEXCONNECT
R/W
FlexConnect Control. When asserted the device changes its hub
connections so that the Swap port (Physical Port 1) changes from it’s
default behavior of a downstream port to an upstream port. The Flex
Port (Physical port 0) transitions from an upstream port to a
downstream port.
‘0’ -
Flex Port = Upstream (Port 0)
Swap Port= Downstream (Port 1)
‘1’ -
Flex Port= Downstream (Port 1)
Swap Port= Upstream (Port 0)
This setting can be used to select whether the Flex Port is an upstream
or downstream port.
Another application for this setting is to allow a dual-role device on the
Swap Port to assume a host role and communicate directly with other
downstream hub ports, or to communicate through the Flex Port to a
exposed connector to an external device.
If a “private” communication channel is desired between embedded
devices, any externally exposed ports should be disabled.
Note: All port-specific settings such as VSNS, prtSp, sDiscon are
specific to the logic port 0, 1, 2, 3. When FLEXCONNECT is asserted,
these settings affect the newly assigned physical pins and PHY. Any
settings which are specific to the physical Flex Port and Swap Port
such as battery charger detection do not change with the setting of
FLEXCONNECT.
Revision 1.0 (06-17-13)
44
SMSC USB3613
DATASHEET
USB 2.0 Hi-Speed 3-Port Hub Controller Optimized for Portable Applications
Datasheet
Table 7.14 Upstream (Port 0) Battery Charging Control 1 Register
BC_CTL_1
(0x6100- RESET=0x00)
UPSTREAM (PORT 0) BATTERY CHARGING CONTROL 1
REGISTER
BIT
NAME
R/W
DESCRIPTION
7
USB2_IDP_SRC_EN
R/W
AFE 10uA IDP_SRC current source Enable
0: Disabled (Hi Z)
1: Enabled
6
5
USB2_VDAT_SRC_EN
R/W
AFE 0.6V VDATA_SRC voltage source Enable
0: Disabled (Hi Z)
1: Enabled
USB2_HOST_CHRG_EN R/W
Enable charging host port mode
0: Portable Device
1: Charging Host port.
When the charging host port is bit is set, the connections of
V
DATA_SRC, IDAT_SINK, IDP_SRC, VDAT_DET are reversed
between DP and DM
4
3
USB2_IDAT_SINK_EN
USB2_VDAT_DET
R/W
R
AFE 100uA current sink and the VDAT_DET comparator Enable
0: Disabled (Hi Z)
1: Enabled
V
DAT_DET comparator output
0: No voltage detected
1: Voltage detected (a possible charger or a
device)
2
1
0
USB2_BC_DP_RDIV_EN R/W
AFE Battery Charging Resistor Divider Enable – DP.
0: Disables resistor divider on DP.
1: Enables 2.7V voltage reference on DP through use of
9.7K/48.5K resistor divider.
USB2_BC_DM_RDIV_E
N
R/W
AFE Battery Charging Resistor Divider Enable – DM.
0: Disables resistor divider on DM.
1: Enables 2.0V voltage reference on DM through use of
29.1K/48.5K resistor divider.
USB2_DP_DM_SHORT_ R/W
EN
Sets the port into China battery charger mode.
SMSC USB3613
45
Revision 1.0 (06-17-13)
DATASHEET
USB 2.0 Hi-Speed 3-Port Hub Controller Optimized for Portable Applications
Datasheet
Table 7.15 Upstream (Port 0) Battery Charging Control 2 Register
BC_CTL_2
(0x6101- RESET=0x00)
UPSTREAM (PORT 0) BATTERY CHARGING CONTROL 2
REGISTER
BIT
NAME
R/W
DESCRIPTION
7
BC_10_125K_PU_DP
R/W
Setting this bit enables a 125K pull-up to VDD33 on DP. This
is used for USB battery charging in 1.0 mode detection only.
6
5
BC_10_125K_PU_DM
LINESTATE_DP
R/W
R
Setting this bit enables a 125K pull-up to VDD33 on DM. This
is used for USB battery charging in 1.0 mode detection only.
This is the direct value of the Full-Speed USB line state Data
Plus. It is used for battery charging detection. This line is not
valid in HS mode and should only be used in battery charging
detection.
4
LINESTATE_DM
R
This is the direct value of the Full-Speed USB line state Data
Minus. It is used for battery charging detection. This line is not
valid in HS mode and should only be used for battery charging
detection.
3
USB2_FS_DP
USB2_FS_DM
Reserved
R
R
R
This is the raw Full-Speed single ended receiver output for
Data Plus
2
This is the raw Full-Speed single ended receiver output for
Data Minus
1:0
Always read ‘0’
Revision 1.0 (06-17-13)
46
SMSC USB3613
DATASHEET
USB 2.0 Hi-Speed 3-Port Hub Controller Optimized for Portable Applications
Datasheet
Table 7.16 Upstream (Port 0) Battery Charging Run Time Control Register
BC_CTL_RUN_TIME
(0x6102- RESET=0x00)
UPSTREAM (PORT 0) BATTERY CHARGING RUN TIME
CONTROL REGISTER
BIT
NAME
R/W
DESCRIPTION
7
6
Reserved
R
Always read ‘0
SUSPENDN
R/W
Suspend enable. Forces upstream port into suspend
0: Suspend disabled
1: Suspend enabled
5
RESET
R/W
R/W
R/W
R/W
R/W
Reset enable. Forces upstream port into reset
0: Reset disabled
1: Reset enabled
4
USB2_FS_OEB
RPD_DP_EN
RPD_DM_EN
XCVRSELECT
Output Enable (OE). Forces upstream port into output enable
0: OE disabled
1: OE enabled
3
Data plus resistor pull-down enable
0: Data plus pull-down disabled
1: Data plus pull-down enabled
2
Data minus resistor pull-down enable
0: Data minus pull-down disabled
1: Data minus pull-down enabled
1:0
Transceiver Select. This field selects between the LS, FS and
HS transceivers.
2'b00: HS mode
2'b01: FS mode
2'b10: LS mode
2'b11: LS data-rate with FS rise/fall times (and EOP/IDLE)
Note:
Note: XCVRSELECT must change state only when
the device is not actively transmitting or receiving
Table 7.17 Upstream (Port 0) Battery Charging Detect Register
UPSTREAM (PORT 0) BATTERY CHARGING DETECT
BC_CTL_DET
(0x6103- RESET=0x00)
REGISTER
BIT
NAME
R/W
DESCRIPTION
7:3
2
Reserved
R
Always read ‘0
USB2_BC_RXHI_EN
R/W
Enable pin for the Apple high current battery charger
detection.
1
0
USB2_BC_RXHI_DET
USB2_BC_BIAS_EN
R
Output pin for the Apple high current battery charger detection.
When disabled this output will be low.
R/W
When enabling USB2_IDAT_SINK_EN or
USB2_VDAT_SRC_EN of the Upstream (Port 0) Battery
Charging Control 1 Register, this register bit must be set to
enable the required current source.
SMSC USB3613
47
Revision 1.0 (06-17-13)
DATASHEET
USB 2.0 Hi-Speed 3-Port Hub Controller Optimized for Portable Applications
Datasheet
7.3.2
Run Time SMBus Page Register
The following run time SMBus page register is located at 0xFF and must be programmed to allow the
SOC to page through different pages of the register space.
Table 7.18 SMBus Page Register
SMBUS_PAGE
(0xFF(I2C) - RESET= 0x00)
SMBUS PAGE REGISTER
BIT
NAME
R/W
DESCRIPTION
7:5
PAGE_SEL
R/W
From the I2C side, this field allows the I2C to select the accessible address
space:
000 = Select registers in the 3000 space (0x30e2 - 0x30ee)
010 = Select registers in the 3100 space (0x318b,0x318e)
110 = Select register in the 6100 space (0x6100,0x6101,0x6102)
5:0
Reserved
R
Reserved.
Note:
Software must never write a ‘1’ to these bits
Revision 1.0 (06-17-13)
48
SMSC USB3613
DATASHEET
USB 2.0 Hi-Speed 3-Port Hub Controller Optimized for Portable Applications
Datasheet
Chapter 8 Functional Descriptions
This chapter provides additional functional descriptions of key device features.
8.1
Battery Charger Detection & Charging
The USB3613 supports both upstream battery charger detection and downstream battery charging.
The integrated battery charger detection circuitry supports the USB-IF Battery Charging (BC1.2)
detection method and most Apple devices. These circuits are used to detect the attachment and type
of a USB charger and provide an interrupt output to indicate charger information is available to be read
from the device’s status registers via the serial interface. The USB3613 provides the battery charging
handshake and supports the following USB-IF BC1.2 charging profiles:
DCP: Dedicated Charging Port (Power brick with no data)
CDP: Charging Downstream Port (1.5A with data)
SDP: Standard Downstream Port (0.5A with data)
Custom profiles loaded via SMBus or OTP
The following sub-sections detail the upstream battery charger detection and downstream battery
charging features.
8.1.1
Upstream Battery Charger Detection
Battery charger detection is available on the upstream facing port. The detection sequence is intended
to identify chargers which conform to the Chinese battery charger specification, chargers which
conform to the USB-IF Battery Charger Specification 1.2, and most Apple devices.
In order to detect the charger, the device applies and monitors voltages on the upstream DP and DM
balls. If a voltage within the specified range is detected, the CHRGDET[1:0] signals will be asserted
and the will be updated to reflect the proper status.
The device includes the circuitry required to implement battery charging detection using the Battery
Charging Specification. When enabled, the device will automatically perform charger detection upon
entering the Hub.ChgDet stage in Hub Mode. The device includes a state machine to provide the
detection of the USB chargers listed in the table below. The type of charger detected is returned in the
CHARGER_TYPE field of the .
Table 8.1 Chargers Compatible with Upstream Detection
USB ATTACH TYPE
DP/DM PROFILE
CHARGERTYPE
DCP (Dedicated Charging Port)
CDP (Charging Downstream Port)
Shorted < 200ohm
001
VDP reflected to VDM
010
(EnhancedChrgDet = 1)
SDP
15Kohm pull-down on DP and DM
011
(Standard Downstream Port)
USB Host or downstream hub port
Apple Low Current Charger
Apple High Current Charger
Apple
Apple
100
101
SMSC USB3613
49
Revision 1.0 (06-17-13)
DATASHEET
USB 2.0 Hi-Speed 3-Port Hub Controller Optimized for Portable Applications
Datasheet
Table 8.1 Chargers Compatible with Upstream Detection (continued)
USB ATTACH TYPE
DP/DM PROFILE
CHARGERTYPE
Apple Super High Current Charger
DP=2.7V
DM=2.0V
110
Apple Charger Low Current Charger (500mA)
Apple Charger High Current Charger (1000mA)
DP=2.0V
DM=2.0V
100
101
DP=2.0V
DM=2.7V
If a custom charger detection algorithm is desired, the SMBus registers can also be used to control
the charger detection block to implement a custom charger detection algorithm. In order to avoid
negative interactions with automatic battery charger detection or normal hub operation, the user should
only attempt Custom battery charger detection during the Hub.Config stage or Hub.Connect stage. No
logic is implemented to disable custom detection at other times - it is up to the user software to observe
this restriction.
The SMBus registers and associated general purpose interrupts are primarily intended for
communication with the SOC. To facilitate operation when the SOC is not in a mode which can service
the SMBus, additional output signals dedicated specifically to charger detection (CHRGDET[1:0]) are
provided. This output can be used to communicate with a second device such as a PMIC. The type
of charger which affects the CHRGDET[1:0] state can be selected in the Charge Detect Mask Register.
There is a possibility that the system is not running the reference clock when battery charger detection
is required (for example if the battery is dead or missing). During the Hub.WaitRefClk stage the battery
charger detection sequence can be configured to be followed regardless of the activity of REFCLK by
relying on the operation of the internal oscillator.
Note: Battery charger detection is not available when utilizing HSIC on the upstream port.
8.1.1.1
Charger Detection (CHRGDET[1:0])
The CHRGDET[1:0] output function can be programmed to communicate information that can affect
the level of current that the system may draw from the upstream USB VBUS wire. CHRGDET[1:0] can
be set to identify that a specific type of charger was discovered or that an event on the device occurred
such as USB Device Suspend or the USB Device has been configured. Either bit of the function can
be enabled on a single pin if the resolution of two pins is not required. The output function tracks the
CHG_DET[1:0] bits of the .
The charger detect output can be used to communicate directly to a PMIC GPIO that a charger has
been identified. In this way, there is no communication required over the SMBus by the SOC. This
facilitates a dead battery case where there is insufficient battery power to activate the SOC or its
SMBus to query the cause of an interrupt. The encoding of CHRGDET[1:0] can be seen in Table 8.2.
Table 8.2 CHRGDET[1:0] Configuration Definitions
CHRGDET[1:0]
DEFINITION
‘00’
No selected chargers or status identified.
Draw no current from VBUS.
‘01’
‘10’
VBUS detect without enumeration.
Draw unconfigured current from VBUS (100mA max).
Device enumerated, Set Config seen.
Draw configured current from VBUS (500mA max).
Revision 1.0 (06-17-13)
50
SMSC USB3613
DATASHEET
USB 2.0 Hi-Speed 3-Port Hub Controller Optimized for Portable Applications
Datasheet
Table 8.2 CHRGDET[1:0] Configuration Definitions (continued)
CHRGDET[1:0]
DEFINITION
‘11’
Charger detected.
Draw battery charger current from VBUS (1.0A+).
Note:
The actual current amount for the charger will be
system dependant.
8.1.2
Downstream Battery Charging
The device can be configured by an OEM to have the downstream ports to support battery charging.
The Hub's role in battery charging is to provide an acknowledge to a device's query as to if the hub
system supports USB battery charging. The hub silicon does not provide any current or power FETs
or any additional circuitry to actually charge the device. Those components must be provided as
externally by the OEM.
DC Power
SMSC
Hub
PRTPWRA
VBUS[n]
Figure 8.1 Battery Charging External Power Supply
If the OEM provides an external supply capable of supplying current per the battery charging
specification, the hub can be configured to indicate the presence of such a supply to the device.This
indication, per the PRTCTLA output, is for all downstream ports.
Note: Battery charging is not available on downstream HSIC ports.
8.1.2.1
Downstream Battery Charging Modes
In the terminology of the USB Battery Charging Specification, if a port is configured to support battery
charging, the downstream port is a considered a CDP (Charging Downstream Port) if connected to a
USB host, or a DCP (Dedicated Charging Port) if not connected to a USB host. If the port is not
configured to support battery charging, the port is considered an SDP (Standard Downstream Port).
All charging ports have electrical characteristics different from standard non-charging ports.
SMSC USB3613
51
Revision 1.0 (06-17-13)
DATASHEET
USB 2.0 Hi-Speed 3-Port Hub Controller Optimized for Portable Applications
Datasheet
A downstream port will behave as a CDP, DCP, or SDP depending on the port’s configuration and
mode of operation. The port will not switch between a CDP/DCP or SDP at any time after initial power-
up and configuration. A downstream port can be in one of three modes shown in the table below.
Table 8.3 Downstream Port Types
USB ATTACH TYPE
DP/DM PROFILE
DCP
Apple charging mode or
China Mode (Shorted < 200ohm) or
SMSC custom mode
(Dedicated Charging Port)
CDP
VDP reflected to VDM
(Charging Downstream Port)
SDP
15Kohm pull-down on DP and DM
(Standard Downstream Port)
USB Host or downstream hub port
8.1.2.2
8.1.2.3
Downstream Battery Charging Configuration
Configuration of ports to support battery charging is performed via USB configuration, SMBus
configuration, or OTP. The Battery Charging Enable Register provides per port battery charging
configuration. Starting from bit 1, this register enables battery charging for each down stream port when
asserted. Bit 1 represents port 1 and so on. Each port with battery charging enabled asserts the
corresponding PRTPWR register bit.
Downstream Over-Current Management
It is the devices responsibility to manage over-current conditions. Over-Current Sense (OCS) is
handled according to the USB specification. For battery charging ports, PRTPWRA is driven high
(asserted) after hardware initialization. If an OCS event occurs, the PRTPWRA is negated.
If there is an over-current event in DCP mode, the port is turned off for one second and is then re-
enabled. If the OCS event persists, the cycle is repeated for a total or three times. If after three
attempts, the OCS still persists, the cycle is still repeated, but with a retry interval of ten seconds. This
retry persists for indefinitely. The indefinite retry prevents a defective device from permanently disabling
the port.
In CDP or SDP mode, the port power and over-current events are controlled by the USB host. The
OCS event does not have to be registered. When and if the hub is connected to a host, the host will
initialize the hub and enable its port power. If the over current still exists, it will be notified at that point.
Revision 1.0 (06-17-13)
52
SMSC USB3613
DATASHEET
USB 2.0 Hi-Speed 3-Port Hub Controller Optimized for Portable Applications
Datasheet
8.2
Flex Connect
This feature allows the upstream port to be swapped with downstream physical port 1. Only
downstream port 1 can be swapped physically. Using port remapping, any logical port (number
assignment) can be swapped with the upstream port (non-physical).
Flex Connect is enabled/disabled via two control bits in the Connect Configuration Register. The
FLEXCONNECT configuration bit switches the port, and EN_FLEX_MODE enables the mode.
8.2.1
Port Control
Once EN_FLEX_MODE bit is set, the functions of certain pins change, as outlined below.
If EN_FLEX_MODE is set and FLEXCONNECT is not set:
1. SUSPEND outputs ‘0’ to keep any upstream power controller off
If EN_FLEX_MODE is set and FLEXCONNECT is set:
1. The normal upstream VBUS pin becomes a don’t care
2. SUSPEND becomes PRTPWR1/OCS1_N for the port power controller for the connector port
8.3
Resets
The device has the following chip level reset sources:
Power-On Reset (POR)
External Chip Reset (RESET_N)
USB Bus Reset
8.3.1
8.3.2
Power-On Reset (POR)
A power-on reset occurs whenever power is initially supplied to the device, or if power is removed and
reapplied to the device. A timer within the device will assert the internal reset per the specifications
listed in Section 9.5.1, "Power-On Configuration Strap Valid Timing," on page 62.
External Chip Reset (RESET_N)
A valid hardware reset is defined as assertion of RESET_N, after all power supplies are within
operating range, per the specifications in Section 9.5.2, "Reset and Configuration Strap Timing," on
page 63. While reset is asserted, the device (and its associated external circuitry) enters Standby Mode
and consumes minimal current.
Assertion of RESET_N causes the following:
1. The PHY is disabled and the differential pairs will be in a high-impedance state.
2. All transactions immediately terminate; no states are saved.
3. All internal registers return to the default state.
4. The external crystal oscillator is halted.
5. The PLL is halted.
6. The HSIC Strobe and Data pins are driven low.
SMSC USB3613
53
Revision 1.0 (06-17-13)
DATASHEET
USB 2.0 Hi-Speed 3-Port Hub Controller Optimized for Portable Applications
Datasheet
Note: All power supplies must have reached the operating levels mandated in Section 9.2, "Operating
Conditions**," on page 58, prior to (or coincident with) the assertion of RESET_N.
8.3.3
USB Bus Reset
In response to the upstream port signaling a reset to the device, the device performs the following:
Note: The device does not propagate the upstream USB reset to downstream devices.
1. Sets default address to 0.
2. Sets configuration to: Unconfigured.
3. Moves device from suspended to active (if suspended).
4. Complies with Section 11.10 of the USB 2.0 Specification for behavior after completion of the
reset sequence.
The host then configures the device in accordance with the USB Specification.
8.4
Reference Clock
The device’s reference clock (REFCLK) input can be driven with a square wave from 0V to VDD33
and is compatible with several different reference frequencies as shown in Table 8.4. The REFSEL[1:0]
inputs must be configured to select the default input reference clock frequency that matches the clock
frequency applied to REFCLK. The REFSEL[1:0] inputs are latched upon entering the HUB.config
stage and are ignored afterward. REFSEL[1:0] settings are provided in Table 8.4.
Note: The frequencies shown for each REFSEL[1:0] combination in Table 8.4 are the default values.
The frequencies associated with each specific REFSEL[1:0] value can be customized to
support other frequencies. Refer to the SMSC Pro-Touch Configuration Tool documentation for
additional information.
Table 8.4 Default Reference Clock Frequencies
REFSEL[1:0]
FREQUENCY (MHz)
‘00’
‘01’
‘10’
‘11’
38.4
26.0
19.2
12.0
Revision 1.0 (06-17-13)
54
SMSC USB3613
DATASHEET
USB 2.0 Hi-Speed 3-Port Hub Controller Optimized for Portable Applications
Datasheet
8.5
8.6
Hub Connect (HUB_CONN)
HUB_CONN is the equivalent of VBUS. The device will connect to the upstream host when either of
the following conditions are met:
If there is no I2C master present, the device will attach when HUB_CONN is high.
If there is an I2C master present, the device will wait until the master has configured the device
and signalled completion by setting USB_ATTACH in the STCD register. Once the USB_ATTACH
bit it set, the device will connect once HUB_CONN is high.
Refer to Section 5.1.9, "Hub Connect Stage (Hub.Connect)," on page 22 for additional information.
Link Power Management (LPM)
The device supports the L0 (On), L1 (Sleep), and L2 (Suspend) link power management states per
the USB 2.0 Link Power Management Addendum. These supported LPM states offer low transitional
latencies in the tens of microseconds versus the much longer latencies of the traditional USB
suspend/resume in the tens of milliseconds. The supported LPM states are detailed in Table 8.5. For
additional information, refer to the USB 2.0 Link Power Management Addendum.
Table 8.5 LPM State Definitions
STATE
L2
DESCRIPTION
ENTRY/EXIT TIME TO L0
Entry: ~3 ms
Suspend
Sleep
Exit: ~2 ms
L1
L0
Entry: ~65 us
Exit: ~100 us
Fully Enabled (On)
-
Note: State change timing is approximate and is measured by change in power consumption.
Note: System clocks are stopped only in suspend mode or when power is removed from the device.
8.7
Suspend (SUSPEND)
When enabled, the SUSPEND signal can be used to indicate that the entire hub has entered the USB
suspend state and that VBUS current consumption should be reduced in accordance with the USB
specification. Selective suspend set by the host on downstream hub ports have no effect on this signal
because there is no requirement to reduce current consumption from the upstream VBUS. Suspend
can be used by the system to monitor and dynamically adjust how much current the PMIC draws from
VBUS to charge the battery in the system during a USB session. Because it is a level indication, it will
assert or negate to reflect the current status of suspend without any interaction through the SMBus.
A negation of this signal indicates no level suspend interrupt and device has been configured by the
USB Host. The full configured current can be drawn from the USB VBUS pin on the USB connector
for charging - up to 500mA - depending on descriptor settings. When asserted, this signal indicates a
suspend interrupt or that the device has not yet been configured by USB Host. The current draw can
be limited by the system according to the USB specification. The USB specification limits current to
100mA before configuration, and up to 12.5mA in USB suspend mode.
SMSC USB3613
55
Revision 1.0 (06-17-13)
DATASHEET
USB 2.0 Hi-Speed 3-Port Hub Controller Optimized for Portable Applications
Datasheet
8.8
Interrupt Requests (IRQ_N)
The IRQ_N I2C request input pin may be used by the SOC when it desires to communicate with the
device during the HUB.Communication stage, assuring the device’s SMBus is active and ready to
respond - even during USB suspend. In order to meet USB suspend current limits, most blocks in the
device, including the SMBus controller, are in a low power state and are not capable of operation.
When the device observes the assertion of IRQ_N, if the device is in suspend mode, it will enable to
PLL and allow serial communication to be achieved. When the IRQ_N pin is negated the device will
return to its normal suspend current consumption. The IRQ_N alternate function can be implemented
at the same time as the INT_N interrupt output, on the same physical pin.
Note: Asserting the IRQ_N input while the device is in suspend mode will increase the instantaneous
current consumption above the average suspend current requirement. Therefore, this feature
should be used briefly and sparingly.
8.9
Interrupt Output (INT_N)
INT_N is a general interrupt pin intended to communicate select condition changes within the device.
The conditions which may cause an interrupt are detailed in the . The conditions which cause the
interrupt to assert can be controlled through use of the Serial Port Interrupt Mask Register.
The general interrupt and all interrupt conditions are functionally latched and event driven. Once the
interrupt or any of the conditions have asserted, the status bit will remain asserted until the SOC
negates the bit using the SMBus. The bits will then remain negated until a new event condition occurs.
The latching nature of the register causes the status to remain even if the condition that caused the
interrupt ceases to be active. The event driven nature of the register causes the interrupt to only occur
when a new event occurs - when a condition is removed and then is applied again. For example, if
the battery charger detection routine has completed and the SOC negates the interrupt status, it will
not cause an interrupt just because the charger detection is still completed. A new charger detection
routine must run before the associated interrupt will assert again.
Revision 1.0 (06-17-13)
56
SMSC USB3613
DATASHEET
USB 2.0 Hi-Speed 3-Port Hub Controller Optimized for Portable Applications
Datasheet
Chapter 9 Operational Characteristics
9.1
Absolute Maximum Ratings*
VBAT Supply Voltage (Note 9.1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to +5.5 V
VDDCOREREG Supply Voltage (Note 9.1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to +3.6 V
Positive voltage on input signal pins, with respect to ground (Note 9.2) . . . . . . . . . . . . . . . . . . . . 3.6 V
Negative voltage on input signal pins, with respect to ground (Note 9.3). . . . . . . . . . . . . . . . . . . -0.5 V
Positive voltage on REFCLK, with respect to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDDCR12
Positive voltage on HSIC signals, with respect to ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.32 V
Positive voltage on USB DP/DM signals, with respect to ground (Note 9.4) . . . . . . . . . . . . . . . . . 5.5 V
Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55oC to +150oC
Lead Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Refer to JEDEC Spec. J-STD-020
HBM ESD Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..JEDEC Class 3A
Note 9.1 When powering this device from laboratory or system power supplies, it is important that
the absolute maximum ratings not be exceeded or device failure can result. Some power
supplies exhibit voltage spikes on their outputs when AC power is switched on or off. In
addition, voltage transients on the AC power line may appear on the DC output. If this
possibility exists, it is suggested to use a clamp circuit.
Note 9.2 This rating does not apply to the following signals: All USB DM/DP pins, REFCLK, and all
HSIC signals.
Note 9.3 This rating does not apply to the HSIC signals.
Note 9.4 This rating applies only when VDD33 is powered.
*Stresses exceeding those listed in this section could cause permanent damage to the device. This is
a stress rating only. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability. Functional operation of the device at any condition exceeding those indicated in
Section 9.2, "Operating Conditions**", Section 9.4, "DC Specifications", or any other applicable section
of this specification is not implied. Note, device signals are NOT 5 volt tolerant unless specified
otherwise.
SMSC USB3613
57
Revision 1.0 (06-17-13)
DATASHEET
USB 2.0 Hi-Speed 3-Port Hub Controller Optimized for Portable Applications
Datasheet
9.2
Operating Conditions**
VBAT Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+2.9 V to +5.5 V
VDDCOREREG Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Note 9.5
Power Supply Rise Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Note 9.6
Ambient Operating Temperature in Still Air (TA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Note 9.7
Note 9.5 +1.6 V to +2.0 V when VDDCOREREG is connected to an external +1.8V power supply,
+3.0 V to +3.6 V when VDDCOREREG is connected to VDD33.
Note 9.6 The power supply rise time requirements vary dependent on the usage of the external
reset (RESET_N). If RESET_N is asserted at power-on, the power supply rise time must
be 10mS or less (tRT(max) = 10mS). If RESET_N is not used at power-on (tied high), the
power supply rise time must be 1mS or less (tRT(max) = 1mS). Higher voltage supplies must
always be at an equal or higher voltage than lower voltage supplies. Figure 9.1 illustrates
the supply rise time requirements.
Note 9.7 0oC to +70oC for commercial version, -40oC to +85oC for industrial version.
**Proper operation of the device is guaranteed only within the ranges specified in this section.
Voltage
VBAT
Voltage
tRT
tRT
3.3V/VBAT
3.3V
1.8V
100%
100%
100%
VBAT
90%
90%
90%
VDDCOREREG
10%
10%
VSS
VSS
t90%
t10%
Single Supply Rise Time Model
t90%
t10%
Dual Supply Rise Time Model
Time
Time
Figure 9.1 Single/Dual Supply Rise Time Models
Revision 1.0 (06-17-13)
58
SMSC USB3613
DATASHEET
USB 2.0 Hi-Speed 3-Port Hub Controller Optimized for Portable Applications
Datasheet
9.3
Power Consumption
This section details the power consumption of the device as measured during various modes of
operation. Power dissipation is determined by temperature, supply voltage, and external source/sink
requirements.
9.3.1
Operational / Unconfigured
Table 9.1 Operational/Unconfigured Power Consumption
TYPICAL (mA)
MAXIMUM (mA)
VBAT
VDDCOREREG
VBAT
VDDCOREREG
HS Host / 1 HSIC Device
HS Host / 1 HS Devices
HS Host / 2 HS Devices
HS Host / 1 HSIC, 2 HS Devices
HS Host / 1 FS Device
HS Host / 2 FS Devices
HS Host / 1HSIC, 2 FS Devices
Unconfigured
10
20
45
45
10
20
15
10
25
30
40
45
25
25
30
20
10
25
50
55
15
25
20
-
30
35
45
55
30
35
40
-
9.3.2
Suspend / Standby
9.3.2.1
Single Supply
The following table details the device power consumption when configured with a single VBAT supply
For additional information on power connections, refer to Chapter 4, "Power Connections," on page 17.
Table 9.2 Single Supply Suspend/Standby Power Consumption
MODE
SYMBOL
TYPICAL @ 25oC
COMMERCIAL
MAX
INDUSTRIAL
MAX
UNIT
Suspend
Standby
IVBAT
IVBAT
300
0.2
1200
1.9
1550
2.2
uA
uA
Note: Typical values measured with VBAT = 4.2V. Maximum values measured with VBAT = 5.5V.
SMSC USB3613
59
Revision 1.0 (06-17-13)
DATASHEET
USB 2.0 Hi-Speed 3-Port Hub Controller Optimized for Portable Applications
Datasheet
9.3.2.2
Dual Supply
The following table details the device power consumption when configured with a dual supply (VBAT
and 1.8V VDDCOREREG) For additional information on power connections, refer to Chapter 4, "Power
Connections," on page 17.
Table 9.3 Dual Supply Suspend/Standby Power Consumption
MODE
SYMBOL
TYPICAL @ 25oC
COMMERCIAL
MAX
INDUSTRIAL
MAX
UNIT
IVDDCOREREG
IVBAT
IVDDCOREREG
IVBAT
90
30
850
1350
1.2
1300
1350
2.0
uA
uA
uA
uA
Suspend
Standby
0.1
0.2
2.1
2.5
Note: Typical values measured with VBAT = 4.2V, VDDCOREREG = 1.8V. Maximum values
measured with VBAT = 5.5V, VDDCOREREG = 2.0V.
Revision 1.0 (06-17-13)
60
SMSC USB3613
DATASHEET
USB 2.0 Hi-Speed 3-Port Hub Controller Optimized for Portable Applications
Datasheet
9.4
DC Specifications
Table 9.4 DC Electrical Characteristics
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
IS Type Input Buffer
Low Input Level
VIL
VIH
-0.3
2.0
0.8
3.6
V
V
High Input Level
I_RST Type Input Buffer
Low Input Level
VIL
VIH
-0.3
0.4
3.6
V
V
High Input Level
1.25
I_SMB Type Input Buffer
Low Input Level
VIL
VIH
-0.3
0.35
3.6
V
V
High Input Level
1.25
O8 Type Buffers
Low Output Level
High Output Level
OD8 Type Buffer
Low Output Level
O12 Type Buffers
Low Output Level
High Output Level
HSIC Type Buffers
Low Input Level
VOL
VOH
0.4
V
V
IOL = 8 mA
IOH = -8 mA
VDD33 - 0.4
VOL
0.4
0.4
V
IOL = 8 mA
VOL
VOH
V
V
IOL = 12 mA
IOH = -12 mA
VDD33 - 0.4
0.35*VDDCR12
VDDCR12+0.3
0.25*VDDCR12
VIL
VIH
-0.3
V
V
V
V
High Input Level
0.65*VDDCR12
Low Output Level
High Output Level
VOL
VOH
0.75*VDDCR12
ICLK Type Buffer
(REFCLK Input)
Low Input Level
High Input Level
VIL
VIH
-0.3
0.8
0.35
V
V
VDDCR12
SMSC USB3613
61
Revision 1.0 (06-17-13)
DATASHEET
USB 2.0 Hi-Speed 3-Port Hub Controller Optimized for Portable Applications
Datasheet
9.5
AC Specifications
This section details the various AC timing specifications of the device.
9.5.1
Power-On Configuration Strap Valid Timing
Figure 9.2 illustrates the configuration strap timing requirements, in relation to power-on, for
applications where RESET_N is not used at power-on. The operational levels (Vopp) for the external
power supplies are detailed in Section 9.2, "Operating Conditions**," on page 58.
Note: For RESET_N configuration strap timing requirements, refer to Section 9.5.2, "Reset and
Configuration Strap Timing," on page 63.
All External
Power Supplies
Vopp
tcsh
Configuration
Straps
Figure 9.2 Power-On Configuration Strap Valid Timing
Table 9.5 Power-On Configuration Strap Valid Timing
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
tcsh
Configuration strap hold after external power supplies at
operational levels
1
ms
Revision 1.0 (06-17-13)
62
SMSC USB3613
DATASHEET
USB 2.0 Hi-Speed 3-Port Hub Controller Optimized for Portable Applications
Datasheet
9.5.2
Reset and Configuration Strap Timing
Figure 9.3 illustrates the RESET_N timing requirements and its relation to the configuration strap
signals. Assertion of RESET_N is not a requirement. However, if used, it must be asserted for the
minimum period specified.
Refer to Section 8.3, "Resets," on page 53 for additional information on resets. Refer to Section 6.3,
"Device Configuration Straps," on page 27 for additional information on configuration straps.
trstia
RESET_N
tcsh
Configuration
Straps
Figure 9.3 RESET_N Configuration Strap Timing
Table 9.6 RESET_N Configuration Strap Timing
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
trstia
tcsh
RESET_N input assertion time
5
1
us
Configuration strap hold after RESET_N deassertion
ms
9.5.3
USB Timing
All device USB signals conform to the voltage, power, and timing characteristics/specifications as set
forth in the Universal Serial Bus Specification. Please refer to the Universal Serial Bus Specification,
Revision 2.0, available at http://www.usb.org.
9.5.4
9.5.5
9.5.6
HSIC Timing
All device HSIC signals conform to the voltage, power, and timing characteristics/specifications as set
forth in the High-Speed Inter-Chip USB Electrical Specification. Please refer to the High-Speed Inter-
Chip USB Electrical Specification, Version 1.0, available at http://www.usb.org.
SMBus Timing
All device SMBus signals conform to the voltage, power, and timing characteristics/specifications as
set forth in the System Management Bus Specification. Please refer to the System Management Bus
Specification, Version 1.0, available at http://smbus.org/specs.
2
I C Timing
All device I2C signals conform to the 100KHz Standard Mode (Sm) voltage, power, and timing
characteristics/specifications as set forth in the I2C-Bus Specification. Please refer to the I2C-Bus
Specification, available at http://www.nxp.com.
SMSC USB3613
63
Revision 1.0 (06-17-13)
DATASHEET
USB 2.0 Hi-Speed 3-Port Hub Controller Optimized for Portable Applications
Datasheet
9.5.7
SPI Timing
The following specifies the SPI timing requirements for the device.
tceh
SPI_CE_N
tfc
tcel
SPI_CLK
SPI_DI
tclq
tdh
tos toh
tov
toh
SPI_DO
Figure 9.4 SPI Timing
Note: The SPI can be configured for 30 MHz or 60 MHz operation via the SPI_SPD_SEL
configuration strap. 30 MHz operation timing values are shown in Table 9.7. 60 MHz operation
timing values are shown in Table 9.8.
Table 9.7 SPI Timing Values (30 MHz Operation)
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
tfc
tceh
tclq
tdh
Clock frequency
30
MHz
ns
Chip enable (SPI_CE_EN) high time
Clock to input data
100
13
ns
Input data hold time
0
5
ns
tos
Output setup time
ns
toh
tov
tcel
tceh
Output hold time
5
ns
Clock to output valid
4
ns
Chip enable (SPI_CE_EN) low to first clock
Last clock to chip enable (SPI_CE_EN) high
12
12
ns
ns
Revision 1.0 (06-17-13)
64
SMSC USB3613
DATASHEET
USB 2.0 Hi-Speed 3-Port Hub Controller Optimized for Portable Applications
Datasheet
Table 9.8 SPI Timing Values (60 MHz Operation)
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
tfc
tceh
tclq
tdh
Clock frequency
60
MHz
ns
Chip enable (SPI_CE_EN) high time
Clock to input data
50
9
ns
Input data hold time
0
5
ns
tos
Output setup time
ns
toh
tov
tcel
tceh
Output hold time
5
ns
Clock to output valid
4
ns
Chip enable (SPI_CE_EN) low to first clock
Last clock to chip enable (SPI_CE_EN) high
12
12
ns
ns
9.6
Clock Specifications
The device can accept a 24 MHz single-ended clock oscillator input. REFCLK should be driven with a
clock that adheres to the specifications outlined in Section 9.6.1, "External Reference Clock
(REFCLK)".
9.6.1
External Reference Clock (REFCLK)
The following input clock specifications are suggested:
50% duty cycle 10%
350 PPM
The input frequency of REFCLK is user configurable. Refer to Section 8.4, "Reference Clock" for
additional information on configuring a reference clock input.
Note: The external clock is recommended to conform to the signalling levels designated in the
JEDEC specification on 1.2V CMOS Logic.
SMSC USB3613
65
Revision 1.0 (06-17-13)
DATASHEET
USB 2.0 Hi-Speed 3-Port Hub Controller Optimized for Portable Applications
Datasheet
Chapter 10 Package Outline
Figure 10.1 30-WLCSP Package
Table 10.1 30-WLCSP Dimensions
MIN
NOMINAL
MAX
REMARKS
A
A1
A2
D
-
0.56
0.20
-
2.90
2.50
0.62
0.24
0.38
2.93
2.53
Overall Package Height
Standoff
Package Thickness
X Die Size
0.16
-
2.87
2.47
E
Y Die Size
D1
E1
b
e
ccc
2.00 BSC
1.60 BSC
0.25
0.40 BSC
-
X End Balls Distance
Y End Balls Distance
Ball Diameter
0.20
0
0.30
0.05
Ball Pitch
Coplanarity
Notes:
1. All dimensions are in millimeters unless otherwise noted.
2. Dimension “b” is measured at the maximum ball diameter parallel to primary datum “C”.
3. The ball A1 identifier may vary, but is always located within the zone indicated.
Revision 1.0 (06-17-13)
66
SMSC USB3613
DATASHEET
USB 2.0 Hi-Speed 3-Port Hub Controller Optimized for Portable Applications
Datasheet
4. Primary datum “C” and the seating plane are defined by the spherical crowns of the contact solder balls.
5. Dimension “A” does not include attached external features, such as a heat sink or chip capacitors. Dimension
“A(max)” is given for the extremely thin variation of the package profile height.
6. Dimension “A2” includes a die coating thickness.
Figure 10.2 30-WLCSP Recommended Land Pattern
SMSC USB3613
67
Revision 1.0 (06-17-13)
DATASHEET
USB 2.0 Hi-Speed 3-Port Hub Controller Optimized for Portable Applications
Datasheet
Chapter 11 Datasheet Revision History
Table 11.1 Revision History
REVISION LEVEL
& DATE
SECTION/FIGURE/ENTRY
Initial Release
CORRECTION
Rev. 1.0
(06-17-13)
Revision 1.0 (06-17-13)
68
SMSC USB3613
DATASHEET
相关型号：
©2020 ICPDF网 联系我们和版权申明