CXD1947Q [SONY]
IEEE1394 LINK Layer / PCI Bridge LSI; IEEE1394链路层/ PCI桥接LSI
| 型号： | CXD1947Q |
| 厂家： | 
SONY CORPORATION |
| 描述： | IEEE1394 LINK Layer / PCI Bridge LSI |
| 文件： | 总4页 (文件大小：66K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
CXD1947Q
IEEE1394 LINK Layer / PCI Bridge LSI
Overview
160 pin QFP
The CXD1947Q is a single-chip implementation of the
link layer protocol of the 1394 Serial Bus, with additional
features to support the transaction and bus management
layers.
The CXD1947Q includes a PCI bus interface and mul-
tiple DMA engines to enable high performance bus
transfers.
Features
• Includes interfaces to
• 1394 Link Layer/PCI Bridge
— 1394 PHY interface (CXD1944 or equivalent)
— ROM (64K x 8)
• Conforms to IEEE1394 high speed Serial Bus
• Supports 100Mb/s and 200Mb/s 1394 bus speeds
• Conforms to PCI version 2.1 specification
• Supports 6 independent programmable DMA channels
— Asynchronous transmit (1)
— Silicon Serial ROM
• Supports big and little Endian data formats
Device Structure
— Asynchronous receive (1)
Silicon gate CMOS IC
— Isochronous transmit (2)
— Isochronous receive (2)
Recommended Operating Conditions
• Three 128-word-deep FIFOs
• Supply voltage
VDD 3.0 to 3.6
V
— Asynchronous transmit
• Operating temperature range Topr –20 to +75 °C
— Isochronous transmit
— Receive
Block Diagram
ITDMA
ITF
ALIGN
ALIGN
ATF
ATDMA
MBIU
PCI INF
PCI BUS
PHY
RF
RDMA
IRDMA
LINK
CORE
ALIGN
ROM INF
CNTL REG
SSN INF
MBIU: Master Bus Interface
ITDMA: Isochronous Transmit DMA
ATDMA: Asynchronous Transmit DMA
RDMA: Receive DMA
ALIGN:
ITF:
ATF:
RF:
Data Aligner
PHY:
ROM INF:
Link Layer/Physical Layer
1394 Interface
ROM Interface
Isochronous Transmit FIFO
Asynchronous Transmit FIFO
Receive FIFO
CNTL REG: Control Registers
IRDMA: Isochronous Receive DMA
SSN INF: Silicon Serial Number
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication
or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony
cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
10/18/96
Preliminary
CXD1947Q
Pin Configuration
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
VSS
VDD
121
PHYDATA3
122
PHYDATA2
123
PHYDATA1
124
ROMDT3
ROMDT2
VSS
VDD
NC
ROMDT1
ROMDT0
NC
NC
VSS
VDD
VST
TDO
TENA1
TDI
TCK
BCI
VSS
VDD
PCIAD0
PCIAD1
PCIAD2
PCIAD3
VSS
VDD
NC
INT
PCIAD4
PCIAD5
PCIAD6
PCIAD7
VSS
PHYDATA0
125
PCTL1
126
VSS
127
VDD
128
LPSTAT
129
PCTL0
130
LREQ
131
DIRECT
132
SCLK
133
VSS
134
VDD
135
NC
136
RESET
137
PCICLK
138
PCIGNT
139
PCIREQ
140
160 PIN QFP
VSS
141
VDD
142
NC
143
PCIAD31
144
PCIAD30
145
PCIAD29
146
PCIAD28
147
VSS
148
VDD
149
NC
150
PCIAD27
151
PCIAD26
152
PCIAD25
153
PCIAD24
154
VDD
NC
VDD
155
VSS
156
PCIAD8
PCIAD9
PCIAD10
PCIAD11
VDD
NC
157
PCI_BE3
158
PCIIDSEL
159
VSS
160
–2–
Preliminary
CXD1947Q
Functions
addresses. The DMA unit is made up of three controller
modules which support these various DMA functions.
Each module has access to the PCI Interface to perform
move operations, and is capable of sequencing through
buffer descriptor lists stored in main memory in order to
find the next buffer address after a channel exhausts the
previous buffer. This frees the system from stringent
interrupt response requirements after buffer completions.
Each DMA controller stores the current channel pro-
gram pointers and the current context for each of its
DMA channels. A 32-bit incrementer updates both the
Channel Program Pointers and the current buffer point-
ers. A 16-bit decrementer is used to adjust the count val-
ues for the channels. These incrementers and
decrementers will be shared if a Controller unit has multi-
ple channels.
1. Asynchronous Function
The CXD1947Q can transmit and receive all of the
defined 1394 packet formats. Packets to be transmitted
are read out of host memory and received packets are
written into host memory, both using DMA. CXD1947Q
can be programmed to act as a bus bridge between PCI
and 1394 by directly executing 1394 read and write
requests to the first 4GB of node offset address as read
and writes to PCI memory space. The CXD1947Q can
also be programmed to automatically place the data from
read response packets in the proper location in host
memory, then optionally interrupt the host processor to
indicate that the transaction is complete.
2. Isochronous Function
The CXD1947Q is capable of performing the cycle
master function as defined by 1394. This means it con-
tains a cycle timer and counter, and can transmit a spe-
cial packet called a “cycle start” after every rising edge of
the 8KHz cycle clock. The CXD1947Q can either gener-
ate the cycle clock from the 49.152MHz clock it receives
from the PHY, or use the “CycleIn” pin directly. When not
the cycle master, the CXD1947Q keeps its internal cycle
timer synchronized with the cycle master node by cor-
recting its own cycle timer with the reload value from the
cycle start packet. The CXD1947Q supports two isochro-
nous transmit channels and two isochronous receive
channels. The CXD1947Q can regulate the rate of trans-
mit to emulate data rates which are synchronous with,
but not even multiples of, the 8KHz cycle clock.
5. Miscelleneous Functions
Upon detecting a bus reset, the CXD1947Q automati-
cally turns off the asynchronous transmitter. The receiver
remains on so that the CXD1947Q can receive PHY self-
ID packets during the self-ID process which immediately
follows the 1394 bus reset.
Following the bus reset operation, the CXD1947Q
receives the new node ID from the PHY and updates its
node ID register. Host system software must explicitly
restart the transmitter, presumably after it has corrected
the node addresses of any queued-up packets.
The CXD1947Q has an interface to a Dallas
Semiconductor Silicon Serial Number™ chip. This inter-
face retrieves a unique serial number which manage-
ment software then uses to uniquely identify the node for
which the CXD1947Q is attached on the 1394 interface.
3. PCI Interface
This block acts both as a master and a slave on the
PCI bus. As a slave, it decodes and responds to access-
es to registers within CXD1947Q. As a master, it acts on
behalf of the DMA units to generate transactions on the
PCI bus. These transactions are used to move streams
of data between system memory and the devices, as
well as to read and write the DMA command lists.
6. Brief Hardware Description
The block diagram shows the CXD1947Q and its con-
nections in a host system. The CXD1947Q attaches to
the host via PCI bus. PCI provides an inexpensive and
moderatly high performance point for the connection of
I/O devices. PCI is a 32-bit, multiplexed address/data
bus, capable of performing 32-bit transfers at a rate of
33MHz.
4. DMA
The CXD1947Q supports six independent DMA chan-
nels: one Asynchronous Transmit channel, one
Asynchronous Receive channel, and four Isochronous
channels. The CXD1947Q also has Physical DMA capa-
bility to respond to incoming requests to physical
–3–
Preliminary
CXD1947Q
Package Outline
Unit: mm
160 pin QFP (Plastic)
31.2 ±0.2
+0.1
–0.05
28.0 ±0.2
0.15
0.1
120
81
121
80
160
41
1
40
M
3.45 ±0.25
0.3 ±0.1
0.65
±0.13
0.15 ±0.1
0°-10°
–4–
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