CXD2452R [SONY]
Timing Generator for Progressive Scan CCD Image Sensor; 时序发生器逐行扫描CCD图像传感器
| 型号： | CXD2452R |
| 厂家： | 
SONY CORPORATION |
| 描述： | Timing Generator for Progressive Scan CCD Image Sensor |
| 文件： | 总28页 (文件大小：357K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CXD2452R
Timing Generator for Progressive Scan CCD Image Sensor
Description
48 pin LQFP (Plastic)
The CXD2452R is a timing generator which generates
the timing pulses for performing progressive scan
readout for digital still cameras and personal
computer image input applications using the
ICX098AK CCD image sensor.
Features
• Base oscillation frequency 36.81MHz (2340fH)
• Monitoring readout allowed
Absolute Maximum Ratings
• High-speed/low-speed electronic shutter function
• Horizontal driver for CCD image sensor
• Signal processor IC system clock generation 1170fH,
780fH
• Supply voltage VDD
• Input voltage
Vss – 0.5 to +7.0
Vss – 0.5 to VDD + 0.5
Vss – 0.5 to VDD + 0.5
V
V
V
VI
• Output voltage VO
• Operating temperature
Topr
• Vertical/horizontal sync (SSG) timing generation
–20 to +75
°C
°C
• Storage temperature
Tstg
Applications
–55 to +150
• Digital still cameras
• Personal computer image input
Recommended Operating Conditions
• Supply voltage
Structure
VDDa, VDDb, VDDc, VDDd 3.0 to 3.6
• Operating temperature
V
Silicon gate CMOS IC
Topr
–20 to +75
°C
Pin Configuration
Applicable CCD Image Sensors
ICX098AK (Type 1/4 CCD)
35
32
31 30 29 28 27 26 25
36
34 33
37
38
DSGAT
MCK
24 VDD5
23
3/2MCK
VSS6 39
40
22 1/2MCK
21
XSUB
PBLK
XV3 41
20 VSS4
19 XRS
XSG2 42
43
44
45
46
18
17
16
15
XSG1
XV2
XSHD
XSHP
VDD7
XV1
VDD4
XCLPDM
OSCO 47
48
14 VDD3
13
OSCI
H2
1
2
3
4
5
6
7
8
9
10 11 12
*Groups of pins enclosed in the fingure indicate sections for which power supply separationis possible.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E96830C9X
CXD2452R
Block Diagram
13
18 19
46
44 41 43 42
12
9
17
OSCI
48
OSCO
47
40
XSUB
PBLK
XCLPDM
XCLPOB
ID
21
15
7
3MCK
1
1/3
Pulse Generator
1/2
23
22
3/2MCK
1/2MCK
4
3
WEN
1/2
CLD 35
HRI
differential
MCK
38
6
8
Latch
Latch
14
16
24
26
45
VDD
SSG
SSI
27
28 SSK
SEN
Register
1/390
29
2
1/2
10
11
20
36
39
VSS
1/525
31
32
33
34
5
37 30
25
– 2 –
CXD2452R
Pin Description
Pin
Symbol
No.
I/O
Description
1
2
3MCK
Vss1
I
Internal main clock. (2340fH)
GND
—
Memory write timing.
Stop control possible using the serial interface data.
3
4
WEN
ID
O
O
Vertical direction line identification pulse output.
Stop control possible using the serial interface data.
5
6
TEST
I
IC test pin; normally fixed to GND. (With pull-down resistor)
3.3V power supply. (Power supply for common logic block)
VDD1
—
CCD optical black signal clamp pulse output.
Stop control possible using the serial interface data.
7
XCLPOB
O
8
VDD2
RG
—
O
3.3V power supply. (Power supply for RG)
CCD reset gate pulse output. (780fH)
GND
9
10
11
12
13
14
15
16
17
18
19
20
21
Vss2
Vss3
H1
—
—
O
GND
CCD horizontal register drive clock output. (780fH)
CCD horizontal register drive clock output. (780fH)
3.3V power supply. (Power supply for H1/H2)
Pulse output for dummy bit block clamp .
3.3V power supply. (Power supply for CDS system)
Precharge level sample-and-hold pulse output. (780fH)
Data level sample-and-hold pulse output. (780fH)
H2
O
VDD3
XCLPDM
VDD4
XSHP
XSHD
XRS
—
O
—
O
O
O
Sample-and-hold pulse output for analog/digital conversion phase alignment. (780fH)
GND
Vss4
PBLK
—
O
Pulse output for horizontal and vertical blanking interval pulse cleaning.
Horizontal direction pixel identification pulse output.
Stop control possible using the serial interface data.
22
1/2MCK
O
System clock output for signal processing IC (1170fH).
Stop control possible using the serial interface data.
23
24
25
3/2MCK
VDD5
—
—
I
3.3V power supply. (Power supply for common logic block)
Internal system reset input. High: Normal status, Low: Reset status
Always input one reset pulse after power-on.
RST
26
27
28
29
VDD6
SSI
—
3.3V power supply. (Power supply for common logic block)
Serial interface data input for internal mode settings.
Serial interface clock input for internal mode settings.
Serial interface strobe input for internal mode settings.
I
I
I
SSK
SEN
CHKSUM enable. (With pull-down resistor)
High: Sum check invalid, Low: Sum check valid
30
31
EBCKSM
FRO
I
Vertical sync signal output.
Stop control possible using the serial interface data.
O
– 3 –
CXD2452R
Pin
No.
Symbol
HRO
I/O
O
Description
Horizontal sync signal output.
32
Stop control possible using the serial interface data.
33
34
HRI
FRI
I
I
Horizontal sync signal input.
Vertical sync signal input.
Clock output for analog/digital conversion IC. (780fH)
Phase adjustment in 60° units possible using the serial interface data.
35
36
CLD
O
VSS5
—
GND
Control input used to stop pulse generation for CCD image sensor, sample-and-
hold IC and analog/digital conversion IC. High: Normal status, Low: Stop status
Controlled pulse can be changed using the serial interface data.
37
DSGAT
I
38
39
40
41
42
43
44
45
46
47
48
MCK
Vss6
XSUB
XV3
O
—
O
O
O
O
O
—
O
O
I
System clock output for signal processor IC. (780fH)
GND
Pulse output for electronic shutter.
CCD vertical register drive pulse output.
CCD sensor readout pulse output.
CCD sensor readout pulse output.
CCD vertical register drive pulse output.
3.3V power supply. (Power supply for common logic block)
CCD vertical register drive pulse output.
Inverter output for oscillation.
XSG2
XSG1
XV2
VDD7
XV1
OSCO
OSCI
Inverter input for oscillation.
– 4 –
CXD2452R
Electrical Characteristics
DC Characteristics
(Within the recommended operating conditions)
Item
Pins
Symbol
VDDa
VDDb
VDDc
Conditions
Min.
3.0
3.0
3.0
Typ. Max.
Unit
V
Supply voltage 1 VDD2
Supply voltage 2 VDD3
Supply voltage 3 VDD4
3.3
3.3
3.3
3.6
3.6
3.6
V
V
VDD1, VDD5,
VDD6, VDD7
Supply voltage 4
3.0
3.3
3.6
VDDd
VIH1
V
V
RST, DSGAT,
SSI, SSK, SEN,
FRI, HRI
0.8VDDd
1
Input voltage 1
0.2VDDd
0.2VDDd
0.3VDDd
0.4
VIL1
V
V
V
V
V
V
V
V
V
V
0.8VDDd
0.7VDDd
VIH2
VIL2
Input
voltage 2
EBCKSM
TEST
1
2
2
VIH3
VIL3
Input
voltage 3
VDDa – 0.8
VOH1
VOL1
VOH2
VOL2
VOH3
Feed current where IOH = –3.3mA
Pull-in current where IOL = 2.4mA
Feed current where IOH = –10.4mA
Pull-in current where IOL = 7.2mA
Feed current where IOH = –3.3mA
Output
voltage 1
RG
VDDb – 0.8
Output
voltage 2
H1, H2
0.4
XSHP, XSHD,
XRS, PBLK,
XCLPDM
VDDc
– 0.8
Output
voltage 3
VOL3
VOH4
VOL4
VOH5
VOL5
Pull-in current where IOL = 2.4mA
0.4
0.4
0.4
V
V
V
V
V
VDD
d
d
– 0.8
– 0.8
Feed current where IOH = –10.4mA
Pull-in current where IOL = 7.2mA
Feed current where IOH = –3.3mA
Pull-in current where IOL = 2.4mA
Output
voltage 4
3/2MCK, MCK,
CLD
VDD
Output
voltage 5
1/2MCK
XV1, XV2, XV3,
XSUB, XSG1,
XSG2, XCLPOB,
ID, WEN
VOH6
VOL6
Feed current where IOH = –2.4mA
Pull-in current where IOL = 4.8mA
VDD
d
d
– 0.8
– 0.8
V
V
Output
voltage 6
0.4
0.4
VDD
VOH7
VOL7
Feed current where IOH = –3.6mA
Pull-in current where IOL = 7.2mA
V
V
Output
voltage 7
FRO, HRO
1
These input pins do not have protective diodes on the internal power supply side.
These input pins have internal pull-down resistors.
2
3
The above table indicates the condition for 3.3V drive.
– 5 –
CXD2452R
(Within the recommended operating conditions)
Inverter I/O Characteristics for Oscillation
Item
Pins
Symbol
LVth
VIH
Conditions
Min.
Typ.
Max.
0.3VDDd
VDDd/2
Unit
V
Logical Vth
VDDd/2
OSCI
OSCI
0.7VDDd
V
Input voltage
VIL
V
Feed current where
IOH = –6.0mA
VOH
VOL
VDDd/2
V
V
OSCO
Output voltage
Pull-in current where
IOL = 6.0mA
Feedback resistor
RFB
f
500k
20
2M
Ω
VIN = VDDd or Vss
5M
50
OSCI, OSCO
OSCI, OSCO
Oscillation frequency
MHz
Inverter Input Characteristics for Base Oscillation Clock Duty Adjustment
(Within the recommended operating conditions)
Item
Pins
Symbol
LVth
VIH
Conditions
Min.
Typ.
Max.
Unit
V
Logical Vth
VDDd/2
V
0.7VDDd
Input voltage
3MCK
V
VIL
0.3VDDd
fmax 50MHz sine
wave
Vp-p
Input amplitude
VIN
0.3
1
Input voltage is the input voltage characteristics for direct input from an external source. Input amplitude is
the input amplitude characteristics in the case of input through capacitor.
– 6 –
CXD2452R
AC Characteristics
1) AC characteristics between the serial interface clocks
0.8VDDd
SSI
0.2VDDd
0.8VDDd
ts1
SSK
0.2VDDd
th1
ts2
SEN
SEN
0.2VDDd
ts3
0.8VDDd
th2
(Within the recommended operating conditions)
Symbol
ts1
Definition
Min.
20
Typ.
Max. Unit
ns
ns
ns
ns
ns
SSI setup time, activated by the rising edge of SSK
SSI hold time, activated by the rising edge of SSK
SSK setup time, activated by the rising edge of SEN
SSK hold time, activated by the rising edge of SEN
SEN setup time, activated by the rising edge of SSK
20
th1
20
ts2
20
th2
20
ts3
2) Serial interface clock internal loading characteristics
Example: During recording drive mode
FRI
HRI
XSG1
Enlarged view
HRI
0.2VDDd
XSG1
SEN
ts4
th4
0.8VDDd
0.2VDDd
Note) Be sure to maintain a constantly high SEN logic level near the HRI fall immediately before XSG1
generation.
(Within the recommended operating conditions)
Symbol
ts4
Definition
Min.
0
Typ.
Max. Unit
ns
ns
SEN setup time, activated by the falling edge of HRI
SEN hold time, activated by the falling edge of HRI
0
th4
– 7 –
CXD2452R
3) Serial interface clock output variation characteristics
Normally, the serial interface data is loaded to the CXD2452R at the timing shown in 2) above. However, one
exception to this is when the data such as SSGSEL and STB is loaded to the CXD2452R and controlled at the
rising edge of SEN. For STB, see control data D62 to D63 STB in “Description of Operation”.
0.8VDDd
SEN
Output signal
tpdPULSE
(Within the recommended operating conditions)
Symbol
Definition
Min.
5
Typ.
Max. Unit
100
ns
tpdPULSE
Output signal delay, activated by the rising edge of SEN
4) RST loading characteristics
0.8VDDd
RST
0.2VDDd
tw1
(Within the recommended operating conditions)
Symbol
Definition
Min.
35
Typ.
Max. Unit
ns
tw1
RST pulse width
5) Phase identification characteristics using FRI and HRI input
When the HRI logic level is low tpd1 after the
falling edge of FRI
When the HRI logic level is high tpd1 after the
falling edge of FRI
FRI
FRI
0.2VDDd
0.2VDDd
tpd1
HRI
tpd1
HRI
The field is identified as an ODD field .
The field is identified as an EVEN field .
(Within the recommended operating conditions)
Symbol
tpd1
Definition
Min.
Typ.
Max. Unit
ns
1300
Field identification clock phase, activated by the falling edge of FRI
1100
– 8 –
CXD2452R
6) FRI and HRI loading characteristics
0.8VDDd
0.8VDDd
FRI, HRI
ts5
0.8VDDd
th5
MCK
MCK load capacitance = 10pF
(Within the recommended operating conditions)
Symbol
ts5
th5
Definition
Miin.
Typ.
Min.
Unit
ns
FRI and HRI setup time, activated by the rising edge of MCK
FRI and HRI hold time, activated by the rising edge of MCK
10
0
ns
7) Output timing characteristics using DSGAT
DSGAT
0.2VDDd
H1, H2, RG, XV1, XV2, XV3, XSUB, XSG1, XSG2,
XSHP, XSHD, XRS, PBLK, XCLPDM, XCLPOB, CLD
0.2VDDd
tpDSGAT
H1 and H2 load capacitance = 100pF, RG load capacitance = 20pF, XV1, XV2, XV3, XSG1, XSG2, XSUB,
XSHP, XSHD, XRS, PBLK, XCLPDM, XCLPOB and CLD load capacitance = 10pF
(Within the recommended operating conditions)
Symbol
Definition
Min.
Typ.
Max. Unit
ns
tpDSGAT
Time until the above outputs go low after the fall of DSGAT
100
8) Output variation characteristics
0.8VDDd
MCK
WEN, ID
tpd2
WEN and ID load capacitance = 10pF
Symbol
(Within the recommended operating conditions)
Definition
Miin.
20
Typ.
Min.
40
Unit
ns
tpd2
Time until the above outputs change after the rise of MCK
– 9 –
CXD2452R
9) H1 and RG waveform characteristics
0.9VDDb
0.9VDDb
H1
0.1VDDb
0.9VDDa
0.1VDDb
trH1
tfH1
0.9VDDa
RG
0.1VDDa
trRG
0.1VDDa
tfRG
VDDb = 3.3V, Topr = 25°C, H1 and H2 load capacitance = 100pF, RG load capacitance = 20pF
(Within the recommended operating conditions)
Symbol
trH1
Definition
Min.
Typ.
10
10
3
Max. Unit
H1 rise time
H1 fall time
RG rise time
RG fall time
ns
ns
ns
ns
tfH1
trRG
tfRG
3
(Within the recommended operating conditions)
Min. Typ. Max. Unit
10) I/O pin capacitance
Symbol
Definition
CIN
Input pin capacitance
9
pF
pF
pF
COUT
CI/O
Output pin capacitance
I/O pin capacitance
11
11
– 10 –
CXD2452R
Description of Operation
All pulses output from the CXD2452R are controlled by the RST and DSGAT pins and by the serial interface
data shown below. The details of control by the serial interface data and a description of operation are as
follows.
SSI
SSK
SEN
00 01 02 03 04 05 06 07 08 09 10 11
58 59 60 61 62 63 64 65 66 67 68 69 70 71
The CXD2452R basically loads and reflects the serial interface data sent in the above format in the readout
portion at the falling edge of HRI. Here, readout portion specifies the horizontal interval during which XSG1
rises.
There are two types of serial interface data: drive control data and phase adjustment data. Hereafter, these
data are distinguished by referring to the former as control data and the latter as adjustment data.
An example of the initialization data for the CXD2452R control data is shown below. This data is based on the
Application Circuit Block Diagram, so care should be taken as there are some differences from the RST pin
initialization data. Concretely, the internal SSG operates, the XCLPOB and ID pulses are generated, and the
3/2 MCK pulse is stopped. This data shows the values when the EBCKSM pin is low and D64 to D71
CHKSUM is valid.
MSB
LSB
D71 D70 D69 D68 D67 D66 D65 D64 D63 D62 D61 D60 D59 D58 D57 D56
1
0
1
0
1
1
0
1
0
0
0
0
0
0
1
0
MSB
LSB
D55 D54 D53 D52 D51 D50 D49 D48 D47 D46 D45 D44 D43 D42 D41 D40
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
MSB
LSB
D39 D38 D37 D36 D35 D34 D33 D32 D31 D30 D29 D28 D27 D26 D25 D24
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MSB
LSB
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D09 D08
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MSB
LSB
D07 D06 D05 D04 D03 D02 D01 D00
1
0
0
0
0
0
0
1
The adjustment data does not normally need to be set. However, when adjustment is difficult due to the
system configuration or for other reasons, the data considered most appropriate at that time should be set as
the initialization data.
– 11 –
CXD2452R
Control Data
Data
Symbol
Function
Chip switching
Data = 0
Data = 1
When a reset
All 0
D00
to
D07
CHIP
See D00 to D07 CHIP.
See D08 to D15 CTGRY.
D08
to
D15
CTGRY
SMD
Category switching
All 0
All 0
All 0
All 0
D16
to
D17
See D16 to D35
Electronic shutter mode.
Electronic shutter mode setting
D18
to
D25
Electronic shutter vertical interval
setting
See D16 to D35
Electronic shutter mode.
Shut.FRM
Shut.HD
—
D26
to
D35
Electronic shutter horizontal interval
setting
See D16 to D35
Electronic shutter mode.
D36
to
D47
—
OFF
—
—
ON
—
—
All 0
0
D48 EXPOSE
Recording exposure setting switching
—
D49
to
—
All 0
D50
Recording
ON
D51 PSMT
Drive mode switching
0
0
0
0
0
0
0
0
0
Monitoring
OFF
D52 SSGSEL
D53 WENSEL
D54 CLPSEL
D55 IDSEL
Internal SSG operation switching
WEN pulse operation switching
XCLPOB pulse operation switching
ID pulse operation switching
ON
OFF
ON
OFF
OFF
ON
D56 HMCKSEL
D57 TMCKSEL
D58 HMCKREV
D59 TMCKREV
D60
1/2MCK pulse operation switching
3/2MCK pulse operation switching
1/2MCK pulse reset polarity switching
2/3MCK pulse reset polarity switching
OFF
ON
ON
OFF
Positive polarity Negative polarity
Negative polarity Positive polarity
to
D61
DSG
Pulse generation control
IC pin status control
Check sum bit
All 0
All 0
All 0
See D60 to D61 DSG table.
See D62 to D63 STB table.
See D64 to D71 CHKSUM.
D62
to
D63
STB
D64
to
D71
CHKSUM
– 12 –
CXD2452R
Detailed Description of Each Data
D00 to D07 CHIP
The serial interface data is loaded to the CXD2452R when D00 and D07 are 1. However, this assumes that
either the EBCKSM pin is low and D64 to D71 CHKSUM is satisfied or the EBCKSM pin is high.
MSB
LSB
Function
Loading to the CXD2452R
D07 D06 D05 D04 D03 D02 D01 D00
1
0
0
0
0
0
0
1
Note that when SEN is shared with other ICs and indentification is performed using CHIP-ID, the CXD2452R
data must be positioned immeditately before the load timing, that is to say at the very end.
D08 to D15 CTGRY
Of the data provided to the CXD2452R by the serial interface, the CXD2452R loads D16 and subsequent data
to the control register side when D08 is 0, and to the adjustment register side when D08 is 1. However, this
assumes that the CXD2452R is selected by CHIP and that either the EBCKSM pin is low and D64 to D71
CHKSUM is satisfied or the EBCKSM pin is high.
MSB
LSB
Function
D15 D14 D13 D12 D11 D10 D09 D08
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Loading to the control register side
Loading to the adjustment register side
Note that the CXD2452R cannot apply both categories simultaneously during the same vertical interval. Also,
care should be taken as the data is overwritten even if the same category is applied.
D16 to D35 Electronic shutter mode
The CXD2452R's electronic shutter mode can be switched as follows by SMD D16 to D17 . Handling of the
data from D18 to D35 differs according to the mode, and is explained in detail below.
D17
X
D16
0
Description of operation
XSUB stopped mode
0
1
High-speed/low-speed shutter mode
HTSG control mode
1
1
The electronic shutter data is expressed as shown in the table below using Shut.HD as an example.
MSB
LSB
D35 D34 D33 D32 D31 D30 D29 D28 D27 D26
0
1
1
1
0
0
0
0
1
1
↓
↓
↓
1
C
3
Shut.HD is expressed as 1C3h .
[XSUB stopped mode]
During this mode, the data from D18 to D35 is invalid. The shutter speed is 1/60s during monitoring drive
mode, and 1/30s during recording drive mode.
– 13 –
CXD2452R
[High-speed/low-speed shutter mode]
During this mode, the data has the following meanings.
Symbol
Shut.FRM
Shut.HD
Data
Description
D18 to D25 Shutter speed data (number of vertical intervals) specification
D26 to D35 Shutter speed data (number of horizontal intervals) specification
The CXD2452R does not distinguish between the high-speed shutter and low-speed shutter modes. The
interval during which Shut.FRM and Shut.HD are specified together is the shutter speed. At this time,
Shut.FRM controls the XSG1, XSG2 output, and Shut.HD controls the XSUB output. Concretely, when
specifying high-speed shutter, Shut.FRM is set to 00h. (See the figure.) During low-speed shutter, or in other
words when Shut.FRM is set to 01h or higher, the serial interface data is not loaded until this interval is
finished.
However, care should be taken as the vertical interval indicated here is set in 1/60s units when the drive mode
is monitoring drive mode and 1/30s units during recording drive mode.
For monitoring drive mode, care should be taken that shut.HD value is offset. This is because the same
exposure time can be obtained for the same shut.HD data without depending on drive mode basically for high-
speed shutter.
Formula for calculating the electronic shutter speed: [Shut.FRM/Shut.HD] (unit: µs)
Monitoring drive mode:
T = Shut.FRM 1.66834 104 + {(20Ch – Shut.HD) 780 + 447} 81.5 10–3 (107h ≤ Shut.HD ≤ 20Ch)
FRI
XSG1
XSUB
Shut.HD-106h
01
Shut.FRM
SMD
Shut. FRM
Shut. HD
WEN
01
01
00h
01h
00h
1A6h
1DDh
1A6h
During monitoring drive mode/low-speed shutter mode
Recording drive mode:
T = Shut.FRM 3.33667 104 + {(20Ch – Shut.HD) 780 + 447} 81.5 10–3 (000h ≤ Shut.HD ≤ 20Ch)
FRI
XSG1
XSUB
Shut.HD
Shut.FRM
SMD
Shut. FRM
Shut. HD
WEN
01
01
01h
00h
1DDh
1A6h
During recording drive mode/low-speed shutter mode
– 14 –
CXD2452R
Electronic shutter speed table [Shut.FRM/Shut.HD]
Calculation
results (s)
Shutter speed
(s)
Calculation
Shutter speed
(s)
Shut.HD
Shut.FRM Shut.HD
Shut.FRM
results (s)
1/60
1/60
1/50
1/30
1/8
1
00h
00h
00h
00h
00h
00h
00h
00h
00h
20Ch
20Bh
209h
205h
1FDh
1EDh
1CEh
18Fh
16Fh
1/27450
1/10000
1/4403
1/2077
1/1010
1/498
00h
01h
01h
02h
07h
09h
00h
00h
00h
107h
1/60
1/27000
1/10000
1/4500
1/2000
1/1000
1/500
2
20Ch
1D8h
20Ch
18Bh
109h
0D2h
083h
000h
1/60
2
1/50
2
1/30
2
1/8
2
1/6
1/6
3
1/251
1/50
1/250
1/50
1/40
1/30
3
1/125
1/40
1/125
3
1/100
1/30
1/100
1
2
3
One XSUB pulse is generated for odd fields and two for even fields.
These are the settings during monitoring drive mode.
These can only be specified during recording drive mode.
Note) Input prohibited data:
Monitoring drive mode
000h to 106h
20Dh to 3FFh
Recording drive mode and monitoring drive mode
[HTSG control mode]
During this mode, the data from D18 to D35 is invalid. The shutter speed is the value obtained by adding
the shutter speed specified in the preceding vertical interval to the vertical period during which XSG1 (and
XSG2) is stopped as shown in the figure.
FRI
XSG1
XSUB
Vck
SMD
WEN
01
11
01
During HTSG control mode
– 15 –
CXD2452R
D48 EXPOSE
0: No operation
1: XSUB for recording exposure is generated.
This control specification is such that one XSUB pulse is always generated during the horizontal interval
immediately following the readout portion even if the electronic shutter speed is set to 1/60s (SMD = 00). This
mode is closely related to D51 PSMT, so see D51 regarding the control.
D51 PSMT
0: Driving is controlled in accordance with monitoring drive mode under the assumption that vertical/horizontal sync
signals are input.
1: Driving is controlled in accordance with recording drive mode under the assumption that vertical/horizontal sync
signals are input.
See the timing charts for the vertical/horizontal sync signals in accordance with each mode.
Note that when switching from monitoring drive to recording drive mode, the pixels decimated thus far must be
cleaned.
Concretely, this operation is supported by generating XSUB, but the CXD2452R facilitates this control by
using D48 EXPOSE. (See the figure.)
FRI
XSG1
XSUB
Exposure time
WEN
SMD
EXPOSE
PSMT
00
00
00
0
00
0
0
1
0
0
1
0
Mode
Recording
Monitoring
Monitoring
Monitoring
Image of switching from monitoring drive mode to recording drive mode
D52 SSGSEL
0: Internal SSG functions are stopped.
1: Internal SSG functions operate, and FRO and HRO are generated.
When generation is stopped, these pulses are fixed low.
D53 WENSEL
0: WEN is generated.
1: WEN generation is stopped.
When generation is stopped, operation is the same as for D52 SSGSEL.
– 16 –
CXD2452R
D54 CLPSEL
0: XCPOB generation is stopped.
1: XCPOB is generated.
When generation is stopped, operation is the same as for D52 SSGSEL.
D55 IDSEL
0: ID generation is stopped.
1: ID is generated.
When generation is stopped, operation is the same as for D52 SSGSEL.
D56 HMCKSEL
0: 1/2MCK generation is stopped.
1: 1/2MCK is generated.
When generation is stopped, operation is the same as for D52 SSGSEL.
D57 TMCKSEL
0: 3/2MCK is generated.
1: 3/2MCK generation is stopped.
When generation is stopped, operation is the same as for D52 SSGSEL.
D58 HMCKREV
0: 1/2MCK reset when positive polarity.
1: 1/2MCK reset when negative polarity.
D59 HMCKREV
0: 3/2MCK reset when negative polarity.
1: 3/2MCK reset when positive polarity.
D60 to D61 DSG
The CXD2452R can stop control to the CCD pulses and pulses for the sample-and-hold and analog/digital
conversion ICs by setting the DSGAT pin low. Conversely, when the DSGAT pin is set high, the controlled
pulses can be switched as follows using the serial interface data.
D61
0
D60
0
Operating mode
No control performed
CCD pulse control
0
1
1
0
Sample-and-hold and analog/digital conversion IC pulse control
1
1
CCD pulse and sample-and-hold and analog/digital conversion IC pulse control
Here, CCD pulses refer to the H1, H2, RG, XV1, XV2, XV3, XSUB, XSG1 and XSG2 pulses. Sample-and-hold
and analog/digital conversion IC pulses refer to the XSHP, XSHD, XRS, PBLK, XCLPOB, XCLPDM and CLD
pulses.
See 7) Output timing characteristics using DSGAT of "AC Characteristics" for the stop control status of each
pulse.
– 17 –
CXD2452R
D62 to D63 STB
This switches the operating mode as shown below. However, the IC pin status control bit is loaded to the
CXD2452R and controlled immediately at the rise of the SEN input.
Operating mode
D63
X
D62
0
Symbol
CAMERA
SLEEP
Normal operation mode
1
0
1
Sleep mode
1
1
Standby mode
STNBY
1
Mode for the status which does not require CCD drive when playing back recorded data within the system.
The pin status during each mode is shown in the table below.
Pin
1
Symbol
3MCK
Vss1
Pin
CAMERA
ACT
CAMERA SLEEP
STNBY
ACT
Symbol
SLEEP
ACT
—
STNBY
ACT
25 RST
26 VDD6
27 SSI
ACT
ACT
—
L
2
WEN
ID
3
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
L
ACT
ACT
ACT
ACT
L
L
L
28 SSK
29 SEN
30 EBCKSM
31 FRO
32 HRO
33 HRI
4
L
TEST
VDD1
5
—
—
L
6
XCLPOB
VDD2
7
ACT
ACT
L
L
8
L
—
L
RG
9
ACT
ACT
L
Vss2
34 FRI
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
—
—
L
Vss3
35 CLD
36 VSS5
37 DSGAT
38 MCK
39 Vss6
H1
ACT
ACT
—
L
L
H2
ACT
ACT
ACT
ACT
—
ACT
L
L
VDD3
—
L
XCLPDM
VDD4
ACT
L
XSUB
40
ACT
ACT
ACT
ACT
ACT
L
L
L
L
L
L
—
L
XSHP
XSHD
XRS
41 XV3
ACT
ACT
ACT
L
L
L
L
42 XSG2
43 XSG1
44 XV2
L
L
L
L
Vss4
L
—
L
PBLK
1/2MCK
3/2MCK
VDD5
45 VDD7
46 XV1
ACT
ACT
ACT
—
L
L
L
ACT
ACT
ACT
L
L
L
47 OSCO
48 OSCI
ACT
ACT
ACT
ACT
ACT
—
Note) ACT means that the circuit is operating. L indicates a low output level in the controlled status.
– 18 –
CXD2452R
D64 to D71 CHKSUM
This is the check sum bit. Apply the data shown below.
MSB
LSB
D07 D06 D05 D04 D03 D02 D01 D00
D15 D14 D13 D12 D11 D10 D09 D08
D23 D22 D21 D20 D19 D18 D17 D16
D31 D30 D29 D28 D27 D26 D25 D24
D39 D38 D37 D36 D35 D34 D33 D32
D47 D46 D45 D44 D43 D42 D41 D40
D55 D54 D53 D52 D51 D50 D49 D48
D63 D62 D61 D60 D59 D58 D57 D56
D71 D70 D69 D68 D67 D66 D65 D64
+)
→ CHKSUM
0
0
0
0
0
0
0
0
→ Reflected when the total is 0.
– 19 –
CXD2452R
– 20 –
CXD2452R
– 21 –
CXD2452R
– 22 –
CXD2452R
– 23 –
CXD2452R
– 24 –
CXD2452R
– 25 –
CXD2452R
– 26 –
CXD2452R
Application Circuit Block Diagram
DRV OUT
VRT
10
D0 to 9
CCD
CCD OUT
S/H
A/D
ICX098AK
CXA2006Q
CXD2311AR
VRB
18 19
7
35
17
21 15
H1
H2
12
13
9
3/2MCK
1/2MCK
23
22
RG
ID
4
WEN
3
XV1
XV2
46
44
41
43
42
40
TG
CXD2452R
MCK
38
FRI
34
XV3
V-Dr
CXD1267AN
HRI
XSG1
XSG2
XSUB
33
HRO
32
SSG
37
5
25
30 27 28 29
FRO
31
1
48
47
Controller
Note) When the CXD2311AR is used as A/D converter, CLD must be inversed.
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 27 –
CXD2452R
Package Outline
Unit: mm
48PIN LQFP (PLASTIC)
9.0 ± 0.2
7.0 ± 0.1
S
36
25
24
13
37
B
A
48
(0.22)
0.13
12
1
+ 0.05
0.127 – 0.02
0.5
+ 0.2
1.5 – 0.1
+ 0.08
0.18 – 0.03
M
0.1
S
0.1 ± 0.1
+ 0.08
0.18 – 0.03
(0.18)
0.18 ± 0.03
0° to 10°
DETAIL B:SOLDER
DETAIL B:PALLADIUM
DETAIL A
NOTE: Dimension “ ” does not include mold protrusion.
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
EPOXY RESIN
SOLDER/PALLADIUM
LQFP-48P-L01
LQFP048-P-0707
SONY CODE
EIAJ CODE
PLATING
42/COPPER ALLOY
0.2g
JEDEC CODE
PACKAGE MASS
– 28 –
相关型号：
©2020 ICPDF网 联系我们和版权申明