概述
规格参数
数据手册CXD2931GA-9 概述
1 chip GPS LSI 1 GPS芯片LSI 其他电信集成电路
CXD2931GA-9 规格参数
| 是否无铅： | 不含铅 | 是否Rohs认证： | 符合 |
| 生命周期： | Obsolete | 零件包装代码： | LGA |
| 包装说明： | LFBGA, LGA144,15X15,32 | 针数： | 144 |
| Reach Compliance Code： | unknown | HTS代码： | 8542.39.00.01 |
| 风险等级： | 5.83 | Is Samacsys： | N |
| JESD-30 代码： | S-PBGA-BU144 | JESD-609代码： | e4 |
| 长度： | 13 mm | 功能数量： | 1 |
| 端子数量： | 144 | 最高工作温度： | 85 °C |
| 最低工作温度： | -40 °C | 封装主体材料： | PLASTIC/EPOXY |
| 封装代码： | LFBGA | 封装等效代码： | LGA144,15X15,32 |
| 封装形状： | SQUARE | 封装形式： | GRID ARRAY, LOW PROFILE, FINE PITCH |
| 峰值回流温度（摄氏度）： | 260 | 电源： | 3.3 V |
| 认证状态： | Not Qualified | 座面最大高度： | 1.4 mm |
| 子类别： | Other Telecom ICs | 标称供电电压： | 3.3 V |
| 表面贴装： | YES | 技术： | CMOS |
| 电信集成电路类型： | TELECOM CIRCUIT | 温度等级： | INDUSTRIAL |
| 端子面层： | Gold (Au) | 端子形式： | BUTT |
| 端子节距： | 0.8 mm | 端子位置： | BOTTOM |
| 处于峰值回流温度下的最长时间： | 10 | 宽度： | 13 mm |
| Base Number Matches： | 1 |
CXD2931GA-9 数据手册
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PDF下载CXD2931R-9/GA-9
1 chip GPS LSI
Description
CXD2931R-9
CXD2931GA-9
The CXD2931R-9/GA-9 is a dedicated LSI for the
GPS (Global Positioning System) satellite-based
position measurement system.
144 pin LQFP (Plastic) 144 pin LFLGA (Plastic)
This LSI contains a 32-bit RISC CPU, 2M-bit MASK
ROM, RAM, UART, timer, and others.
This LSI, used together with the RF LSI (CXA1951AQ),
enables the configuration of a 2-chip system capable
of measuring its position anywhere on the globe.
Absolute Maximum Ratings
Features
• Supply voltage
• Input voltage
• Output voltage
VDD
VSS – 0.5 to 4.6
V
• 16-channel GPS receiver capable of
simultaneously receiving 16 satellites
• Supports differential GPS
—Comforms to RTCM SC-104 Ver. 2.1
—Supports DARC
VI
VSS – 0.5 to VDD + 0.5 V
VO VSS – 0.5 to VDD + 0.5 V
• Operating temperature
Topr
• Storage temperature
Tstg
–40 to +85
°C
°C
• All-in-view measurement
–50 to +150
• 2-satellite measurement
• Timer supporting GPS time
• High performance 32-bit RISC CPU
• 256K-byte program ROM
• 36K-byte RAM
Recommended Operating Conditions
• Supply voltage
VDD
3.0 to 3.6
V
• Operating temperature
Topr
–40 to +85
°C
• 3-channel UART
—Baud rate generator
Input/Output Pin Capacitance
—Supports 1.2K, 2.4K, 4.8K, 9.6K, 19.2K and
38.4K baud
• Input capacitance
• Output capacitance COUT
• I/O capacitance
CIN
9 (Max.)
11 (Max.)
11 (Max.)
pF
pF
pF
—Supports 1/2/4-byte buffer mode
• 23-bit general-purpose I/O port capable of defining
input/output independently for each bit
• 8-bit successive approximation system A/D
converter
CI/O
Structure
Silicon gate CMOS IC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E01Z12A22-PS
CXD2931R-9/GA-9
Performance
• 16-channel GPS receiver
• High performance 32-bit RISC CPU
• Receiver frequency: 1575.42MHz (L1 band, CA code)
• Reception sensitivity
Tracking sensitivity: –145dBm (typ.) when using the antenna of 25dBi, NF = 2dB and the RF amplifier
with the 25dB gain
Reference data using the Sony's reference board.
This value is not guaranteed, depending on the conditions.
• Time to First Fix (time until initial measurement after power-on)
Cold Start (without both ephemeris and almanac): 27 to 58s
Warm Start (without ephemeris with almanac):
Hot Start (with both ephemeris and almanac):
23 to 45s
6 to 17s
Reference data with elevation angle of 5° or more and no interception environment on Nov., 2001.
Positioning time with 90% possibility.
These values are not guaranteed, depending on the conditions.
• Positioning accuracy
2DRMS: approx. 12m
Reference data with elevation angle of 5° or more and no interception environment.
This value is not guaranteed, depending on the conditions.
• Measurement data update time
1s
• Interfece format
NMEA0183 (4800bps)
• Communication method
Start-stop synchronization
• All-in-view
1575.42MHz
LNA
CXA1951AQ
RF Converter
18.414MHz
IF
TCXO
1.023MHz
TXD
CXD2931R-9
16ch GPS Processor
RXD
GPS receiver system block diagram using the CXD2931R-9
– 2 –
CXD2931R-9/GA-9
Block Diagram
TEST0, 1
ICST0, 1
XROMW
BIU
RUN
HOLD
NMI
CLKS
CLKI
PMI
32-bit RISC
CLKO
IODBK
CLKOUT
TCXOS
HOLDA
SINT/PORT (22)
EXRS
256K-byte ROM
36K-byte SRAM
PWRST
VDD × 10
VSS × 10
TXD0 to TXD2
RXD0 to RXD2
UART (Baud Rate Generator) × 3
TIMER × 3
AVD
AVS
VRT
VRB
8-bit
ADC
16ch GPS DSP
– 3 –
CXD2931R-9/GA-9
Pin Configuration (CXD2931R-9)
108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
72 IB8
71 IB7
DB6 109
DB7 110
70
VSS
SINT/PORT22 111
DCS0/PORT21 112
69 IB6
68 IB5
67 IB4
66 IB3
65 IB2
64 IB1
VDD 113
DCS1/PORT20 114
DCS2/PORT19 115
DCS3/PORT18 116
DCS4/PORT17 117
DCS5/PORT16 118
PORT15 119
63
VDD
62 IB0
61 IADR18
60 IADR17
59 IADR16
58 IADR15
57 IADR14
56 IADR13
PORT14 120
VSS 121
PORT13 122
PORT12 123
PORT11 124
PORT10 125
PORT9 126
PORT8 127
PORT7 128
55
VSS
54 IADR12
53 IADR11
52 IADR10
51 IADR9
50 IADR8
49 IADR7
48 IADR6
VDD 129
PORT6 130
PORT5 131
PORT4 132
PORT3 133
47
VDD
134
135
136
137
138
139
140
141
142
143
144
PORT2
PORT1
PORT0
46 IADR5
45 IADR4
44 IADR3
43 IADR2
42 IADR1
41 XROMW
40 ICS1
VSS
TXD2
RXD2
TXD1
RXD1
TXD0
RXD0
39
38 ICS0
37
VSS
IRD
VDD
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
– 4 –
CXD2931R-9/GA-9
Pin Configuration (CXD2931GA-9)
34
R
P
N
M
L
64
62
59
58
55
54
51
50
47
45
42
39
70
67
VSS
IB4
IB1
IB0
IADR16 IADR15
VSS
IADR12 IADR9 IADR8
V
DD
IADR4 IADR1
VSS
VDD
31
68
66
63
60
56
53
49
46
43
41
38
35
75
71
VDD
IB7
IB5
IB3
VDD
IADR17 IADR13 IADR11 IADR7 IADR5 IADR2 XROMW ICS0
RUN
CLKO
28
72
69
65
61
57
52
48
44
40
37
36
32
78
74
IB13
IB10
IB8
IB6
IB2
IADR18 IADR14 IADR10 IADR6 IADR3
ICS1
IRD
IWR
CLKS PWRST
26
30
73
33
81
77
DRD
IB12
IB9
CLKOUT CLKI IODBK
23
76
29
27
83
79
XCS0
IB14
IB11
VSS
EXRS
NMI
22
K
J
80
25
24
86
82
VSS
DWR
IB15
HOLDA
PMI
HOLD
19
84
21
20
87
85
DADR2 DADR1 DADR0
VDD
TCXOS IF0O
18
17
H
G
F
88
DADR5 DADR4 DADR3
16
90
89
ICST0 ICST1
IF0
15
93
DADR6 DADR7 DADR8
12
13
91
92
TEST1 CCKI
VSS
14
97
DADR9 DADR10 DADR11
8
10
94
96
XTCXO OTCXO CCKO
11
E
D
C
B
A
101
DADR13 DADR15
4
7
95
99
VDD
VRB
TCXO TEST0
9
5
105
1
98
102
DADR12 DB0
DB2
AVD
AVS
VDD
6
108
109
112
116
120
124
129
133
137
141
144
2
100
104
SS
DCS0/
PORT21 PORT18
DCS3/
DADR14
V
DB5
DB6
PORT14 PORT11
VDD
PORT3
VSS
RXD1
VDD
AVIN
VSS
3
110
113
115
118
121
SS
125
128
132
135
138
140
143
103
107
DCS2/
PORT19 PORT16
DCS5/
DB1
DB4
DB7
VDD
V
PORT10 PORT7 PORT4 PORT1 TXD2
TXD1
RXD0
VRT
142
114
117
119 122
123
126
127
130
131
134
136
139
106
111
SINT/
DCS1/
DCS4/
DB3
PORT15 PORT13 PORT12 PORT9 PORT8 PORT6 PORT5 PORT2 PORT0 RXD2 TXD0
PORT22 PORT20 PORT17
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
– 5 –
CXD2931R-9/GA-9
Pin Configuration
Pin
Symbol
No.
I/O
Description
1
2
3
4
5
6
7
8
9
AVD
—
I
A/D converter power supply.
Analog input.
AVIN
VRT
I
Reference input.
VRB
AVS
I
—
—
I
A/D converter GND.
GND
Vss
TCXO
XTCXO
VDD
TCXO binary conversion circuit/crystal oscillator.
O
—
O
I
Power supply.
10 OTCXO
11 TEST0
12 TEST1
13 CCKI
14 CCKO
15 Vss
TCXO clock output.
Test. (Low level fixed)
I
I
Timer oscillation. (32.768kHz ± 100ppm)
O
—
I
GND
16 ICST0
17 ICST1
18 IF0
Test. (Low level fixed)
I
I
IF signal binary conversion circuit.
19 IF0O
20 TCXOS
21 VDD
O
I
TCXO select. (Low: TCXO/2, High: TCXO through)
Power supply.
—
I
22 HOLD
23 NMI
Hold input signal. (High: Hold)
Non maskable interrupt.
I
24 PMI
I
Program maskable interrupt.
Hold acknowledge signal.
25 HOLDA
26 IODBK
27 EXRS
28 PWRST
29 Vss
O
O
I
Break signal for debugging.
Reset input signal.
I
Connect to main power supply. Leave open during backup.
GND
—
I
30 CLKI
31 CLKO
32 CLKS
33 CLKOUT
34 VDD
CPU clock oscillation circuit.
O
I
CPU clock select signal. (Low: TCXO, High: CLKI)
CPU clock output.
O
—
O
O
O
Power supply.
35 RUN
36 IWR
Signal indicating CPU operating status.
Write signal for external expansion memory.
37 IRD
Read signal for external expansion memory.
– 6 –
CXD2931R-9/GA-9
Pin
No.
Symbol
I/O
Description
38 ICS0
39 Vss
O
—
O
I
Chip select 0 for external expansion memory.
GND
40 ICS1
41 XROMW
42 IADR1
43 IADR2
44 IADR3
45 IADR4
46 IADR5
47 VDD
Chip select 1 for external expansion memory.
Wait signal for external expansion memory. (High: Wait)
I/O (LSB)
I/O
I/O Address signal for external expansion memory.
I/O
I/O
—
Power supply.
48 IADR6
49 IADR7
50 IADR8
51 IADR9
52 IADR10
53 IADR11
54 IADR12
55 Vss
I/O
I/O
I/O
I/O Address signal for external expansion memory.
I/O
I/O
I/O
—
GND
56 IADR13
57 IADR14
58 IADR15
59 IADR16
60 IADR17
61 IADR18
62 IB0
I/O
I/O
I/O
I/O
I/O
Address signal for external expansion memory.
I/O (MSB)
I/O (LSB) Data bus I/O for external expansion memory.
63 VDD
—
Power supply.
64 IB1
I/O
I/O
I/O
I/O
I/O
I/O
—
65 IB2
66 IB3
Data bus I/O for external expansion memory.
67 IB4
68 IB5
69 IB6
70 Vss
GND
71 IB7
I/O
I/O
I/O
I/O
72 IB8
Data bus I/O for external expansion memory.
73 IB9
74 IB10
– 7 –
CXD2931R-9/GA-9
Pin
No.
Symbol
I/O
Description
75 VDD
—
I/O
I/O
Power supply.
76 IB11
77 IB12
78 IB13
I/O Data bus I/O for external expansion memory.
79 IB14
I/O
80 IB15
I/O (MSB)
81 DRD
O
O
O
Read signal for external expansion data memory.
Write signal for external expansion data memory.
Chip select signal for external expansion data memory.
82 DWR
83 XCS0
84 DADR0
85 DADR1
86 Vss
I/O (LSB)
Address signal for external expansion data memory.
I/O
—
GND
87 DADR2
88 DADR3
89 DADR4
90 DADR5
91 DADR6
92 DADR7
93 DADR8
94 DADR9
95 VDD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
—
Address signal for external expansion data memory.
Power supply.
96 DADR10
97 DADR11
98 DADR12
99 DADR13
100 DADR14
101 DADR15
102 DB0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
—
Address signal for external expansion data memory.
(MSB)
(LSB)
Data bus I/O for external expansion data memory.
103 DB1
104 Vss
GND
105 DB2
I/O
I/O
I/O
I/O
I/O
I/O
106 DB3
107 DB4
Data bus I/O for external expansion data memory.
(MSB)
108 DB5
109 DB6
110 DB7
– 8 –
CXD2931R-9/GA-9
Pin
No.
Symbol
I/O
Description
External interrupt input signal/general-purpose I/O port.
111 SINT/PORT22
I/O This pin can be used as a general-purpose I/O port according to the internal
registers.
Chip select for external expansion data memory/general-purpose I/O port.
112 DCS0/PORT21 I/O This pin can be used as a general-purpose I/O port according to the internal
registers.
113 VDD
—
Power supply.
114 DCS1/PORT20 I/O
115 DCS2/PORT19 I/O
Chip select for external expansion data memory/general-purpose I/O port.
116 DCS3/PORT18 I/O These pins can be used as a general-purpose I/O port according to the
internal registers.
117 DCS4/PORT17 I/O
118 DCS5/PORT16 I/O
119 PORT15
120 PORT14
121 Vss
I/O
I/O
—
General-purpose I/O port.
GND
122 PORT13
123 PORT12
124 PORT11
125 PORT10
126 PORT9
127 PORT8
128 PORT7
129 VDD
I/O
I/O
I/O
I/O General-purpose I/O port.
I/O
I/O
I/O
—
Power supply.
130 PORT6
131 PORT5
132 PORT4
133 PORT3
134 PORT2
135 PORT1
136 PORT0
137 Vss
I/O
I/O
I/O
I/O General-purpose I/O port.
I/O
I/O
I/O
—
O
I
GND
138 TXD2
139 RXD2
140 TXD1
141 RXD1
142 TXD0
143 RXD0
144 VDD
UART transmission data output. (channel 2)
UART reception data input. (channel 2)
UART transmission data output. (channel 1)
UART reception data input. (channel 1)
UART transmission data output. (channel 0)
UART reception data input. (channel 0)
Power supply.
O
I
O
I
—
– 9 –
CXD2931R-9/GA-9
A/D Converter Characteristics
(0 < VRB < VIN < VRT < AVD = 3.0 to 3.6V, Topr = –40 to +85°C)
Item
Pin
Condition
Min.
Typ.
Max.
8
Unit
Bit
Resolution
Differential linearity error (DLE)
Integral linearity error (ILE)
Sampling time
–0.5
–2.5
648
864
+0.5
+2.5
LSB
LSB
ns
AVD = 3.0V
f = 18.414MHz
AVD = 3.0V
Conversion time
ns
Current consumption
2.0
mA
Electrical Characteristics
DC Characteristics
(VDD = 3.0 to 3.6V, Topr = –40 to +85°C)
Applicable
Pins
Item
Symbol
Condition
Min.
Typ.
Max.
Unit
High level
VIH (1)
VIL (1)
VIH (2)
VIL (2)
0.7 × VDD
0.7 × VDD
VDD
0.2 × VDD
5.5
V
V
V
V
V
V
V
V
V
V
Input voltage (1)
(CMOS level)
1
2
3
4
5
Low level
High level
Low level
High level
Low level
High level
Low level
High level
Low level
Input voltage (2)
(5V interface)
0.2 × VDD
VOH (1) IOH = –4.0mA VDD – 0.4
VOL (1) IOL = 4.0mA
Output voltage (1)
Output voltage (2)
Output voltage (3)
0.4
0.4
VOH (2) IOH = –2.0mA VDD – 0.8
VOL (2) IOL = 4.0mA
VOH (3) IOH = –2.0mA VDD – 0.8
VOL (3) IOL = 8.0mA
0.4
70
50
VDD = 3.0V
ISTB
20
4
Current consumption in standby mode
(Using external timer, +85°C)
µA
—
—
VDD = 1.8V
Supply current
IDD
f = 18.414MHz
55
mA
Applicable pins
1
Pins 11, 12, 16, 17, 20, 28, 32, 41
2
Pins 22 to 24, 27, 62, 64 to 69, 71 to 74, 76 to 80, 84, 85, 87 to 94, 96 to 103, 105 to 112, 114 to 120,
122, 128, 130 to 136, 139, 141, 143
3
4
5
Pins 10, 25, 26, 33, 35
Pins 38, 40, 82, 83, 138, 140, 142
Pins 36, 37, 42 to 46, 48 to 54, 56 to 62, 64 to 69, 71 to 74, 76 to 81, 84, 85, 87 to 94, 96 to 103,
105 to 112, 114 to 120, 122 to 128, 130 to 136
– 10 –
CXD2931R-9/GA-9
Battery Backup Mode
The battery backup mode is activated when the power for the GPS receiver is turned off and power-on reset
goes to low level. The timer clock continues to operate even when power-on reset goes low, but all other clock
are fixed high and the LSI is set to the low power consumption mode. At this time, the RAM data is held and
the registers are initialized.
Battery backup mode is canceled by setting power-on reset to high.
10 clocks
Power-on reset
EXRS
PWRST
100ms or more
Timer clocks
CCKI, CCKO
Other clocks
TCXO, XTCXO, CLKI, CLKO
Normal outputs
Fixed low
TXD0 to 2, OTCXO, HOLDA
Tri-state outputs
Fixed low
IODBK, RUN, CLKOUT
Tri-state outputs
ICS0, ICS1, IADR[18:1],
Hi-Z
IRD, IWR, DRD, DWR, XCS0
Fixed low
Hi-Z
Bidirectional
SINT, IB[15:0], DCS0 to DCS5,
DADR[15:0], DB[7:0], PORT[22:0]
(Input)
(Outut)
Inputs
RXD0 to RXD2, IF0,
HOLD, NMI, PMI
Fixed low
– 11 –
CXD2931R-9/GA-9
CXD2931R-9/GA-9 Initialization
CXD2931R-9/GA-9 initialization is started by setting the reset input signal EXRS (Pin 27) to low level. The
timing should satisfy the conditions noted below.
1. During power-on (power-on reset) (VDD = 3.0 to 3.6V, Topr = –40 to +85°C)
V
DD
Power supply,
PWRST
(Pin 28)
EXRS (Pin 27)
V
DD [V]
100ms or more
V
DD/2
GND
The PWRST (Pin 28) signal should rise simultaneously with the power supply. The EXRS (Pin 27) signal
should rise 100ms or more after the power supply and the PWRST signal have risen. Note that the PWRST
signal should be left open during battery backup.
2. Initialization during operation (VDD = 3.0 to 3.6V, Topr = –40 to +85°C)
Power supply,
PWRST
(Pin 28)
VDD
EXRS (Pin 27)
VDD [V]
100µs or more
VDD/2
GND
The internal registers can be initialized during operation by setting the EXRS (Pin 27) signal to low level for
100µs or more. Keep the PWRST (Pin 28) signal at high level at this time.
– 12 –
CXD2931R-9/GA-9
• External Command Fetch Timing (XROMW = 0)
CLKOUT
(a)
(b)
IADR
(c)
(d)
(f)
ICS0, ICS1
(e)
IRD
IB
(g)
(h)
(16)
No.
(a)
(b)
(c)
(d)
(e)
(f)
Item
Read cycle time (Fex: @20MHz)
Address delay time
Min.
—
—
2
Typ.
100
—
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
—
12
10
10
3
Chip select fall delay time
Chip select rise delay time
Read signal fall delay time
Read signal rise delay time
Read data setup time
—
2
—
0
—
0
—
5
(g)
(h)
11
0
—
—
—
Read data hold time
—
The load capacitance = 30pF.
• External Command Fetch Timing (XROMW = 1)
CLKOUT
IADR
ICS0, ICS1
IRD
IB
(16)
– 13 –
CXD2931R-9/GA-9
• External Data Access Timing (ICS0, ICS1/XROMW = 0)
(1) Read (half-word access/XROMW = 0)
CLKOUT
(a)
(b)
IADR
(c)
(d)
(f)
ICS0, ICS1
(e)
IRD
(g)
(16)
(h)
IB
(2) Write (half-word access/XROMW = 0)
CLKOUT
(a)
(b)
IADR
(c)
(d)
(j)
ICS0, ICS1
(i)
IWR
IB
(k)
(l)
(16)
No.
Item
Min.
—
—
2
Typ.
100
—
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(a) Read/write cycle time (Fex: @20MHz)
(b) Address delay time
—
12
10
10
3
(c)
Chip select fall delay time
—
(d) Chip select rise delay time
(e) Read signal fall delay time
2
—
0
—
(f)
Read signal rise delay time
0
—
5
(g) Read data setup time
(h) Read data hold time
11
0
—
—
—
1
—
(i)
(j)
Write signal fall delay time
Write signal rise delay time
Write data established time
Write data hold time
0
—
0
—
2
(k)
(l)
—
5
—
5
—
—
The load capacitance = 30pF.
– 14 –
CXD2931R-9/GA-9
(3) Read (word access/XROMW = 0)
CLKOUT
IADR
ICS0, ICS1
IRD
IB
H (16)
L (16)
(4) Write (word access/XROMW = 0)
CLKOUT
IADR
ICS0, ICS1
IWR
IB
L (16)
H (16)
– 15 –
CXD2931R-9/GA-9
• External Data Access Timing (ICS0, ICS1/XROMW = 1)
(1) Read (half-word access/XROMW = 1)
CLKOUT
IADR
ICS0, ICS1
IRD
IB
(16)
(2) Write (half-word access/XROMW = 1)
CLKOUT
IADR
ICS0, ICS1
IWR
IB
(16)
(3) Read (word access/XROMW = 1)
CLKOUT
IADR
ICS0, ICS1
IRD
IB
H (16)
L (16)
(4) Write (word access/XROMW = 1)
CLKOUT
IADR
ICS0, ICS1
IWR
IB
L (16)
H (16)
– 16 –
CXD2931R-9/GA-9
• External Data Access Timing (XCS0, DCS0 to DCS5/no data wait)
(1) Read (byte access/no data wait)
CLKOUT
(a)
(b)
DADR
(c)
(d)
(f)
XCS0, DCS0 to DCS5
(e)
DRD
DB
(h)
(g)
(8)
(2) Write (byte access/no data wait)
CLKOUT
(a)
(b)
DADR
(c)
(d)
(j)
XCS0, DCS0 to DCS5
(i)
DWR
(l)
(k)
(8)
DB
No.
Item
Min.
—
—
3
Typ.
100
—
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(a) Read/write cycle time (Fex: @20MHz)
(b) Address delay time
—
12
13
13
8
(c)
Chip select fall delay time
—
(d) Chip select rise delay time
(e) Read signal fall delay time
3
—
2
—
(f)
Read signal rise delay time
2
—
10
—
—
2
(g) Read data setup time
(h) Read data hold time
16
0
—
—
(i)
(j)
Write signal fall delay time
Write signal rise delay time
Write data established time
Write data hold time
0
—
0
—
3
(k)
(l)
—
5
—
12
—
—
The load capacitance = 30pF.
– 17 –
CXD2931R-9/GA-9
(3) Read (half-word access/no data wait)
CLKOUT
DADR
XCS0, DCS0 to DCS5
DRD
DB
H (8)
H (8)
(4) Write (half-word access/no data wait)
CLKOUT
DADR
XCS0, DCS0 to DCS5
DWR
DB
L (8)
H (8)
(5) Read (word access/no data wait)
CLKOUT
DADR
XCS0, DCS0 to DCS5
DRD
HH (8)
HL (8)
LH (8)
LL (8)
DB
(6) Write (word access/no data wait)
CLKOUT
DADR
XCS0, DCS0 to DCS5
DWR
DB
LL (8)
LH (8)
HL (8)
HH (8)
– 18 –
CXD2931R-9/GA-9
• External Data Access Timing (XCS0, DCS0 to DCS5/data wait = 1)
(1) Read (byte access/data wait = 1)
CLKOUT
DADR
XCS0, DCS0 to DCS5
DRD
(8)
DB
(2) Write (byte access/data wait = 1)
CLKOUT
DADR
XCS0, DCS0 to DCS5
DWR
DB
(8)
(3) Read (half-word access/data wait = 1)
CLKOUT
DADR
XCS0, DCS0 to DCS5
DRD
DB
H (8)
L (8)
(4) Write (half-word access/data wait = 1)
CLKOUT
DADR
XCS0, DCS0 to DCS5
DWR
DB
L (8)
H (8)
– 19 –
CXD2931R-9/GA-9
(5) Read (word access/data wait = 1)
CLKOUT
DADR
XCS0, DCS0 to DCS5
DRD
DB
HH (8)
HL (8)
LH (8)
LL (8)
(6) Write (word access/data wait = 1)
CLKOUT
DADR
XCS0, DCS0 to DCS5
DWR
DB
LL (8)
LH (8)
HL (8)
HH (8)
• External Data Access Timing (XCS0, DCS0 to DCS5/data wait = 2)
(1) Read (byte access/data wait = 2)
CLKOUT
DADR
XCS0, DCS0 to DCS5
DRD
(8)
DB
(2) Write (byte access/data wait = 2)
CLKOUT
DADR
XCS0, DCS0 to DCS5
DWR
DB
(8)
– 20 –
CXD2931R-9/GA-9
(3) Read (half-word access/data wait = 2)
CLKOUT
DADR
XCS0, DCS0 to DCS5
DRD
DB
H (8)
L (8)
(4) Write (half-word access/data wait = 2)
CLKOUT
DADR
XCS0, DCS0 to DCS5
DWR
DB
L (8)
H (8)
(5) Read (word access/data wait = 2)
CLKOUT
DADR
XCS0, DCS0 to DCS5
DRD
HH (16)
HL (16)
LH (16)
LL (16)
DB
(6) Write (word access/data wait = 2)
CLKOUT
DADR
XCS0, DCS0 to DCS5
DWR
DB
LL (16)
LH (16)
HL (16)
HH (16)
– 21 –
CXD2931R-9/GA-9
Application Notes
The constants shown in the circuits below are the examples, and do not quarantee the circuit operation.
1. TCXO input
(1) When inputting the binary-converted signal
The TCXO (Pin 7) input signal should be 18.414MHz ± 3ppm.
7
8
Input
Open
(2) When performing the self-oscillation with the TCXO and XTCXO pins (Pins 7 and 8)
The TCXO (Pin 7) input signal should be 18.414MHz ± 3ppm.
0.01µF
7
8
TCXO
1MΩ
2. CPU clock generation
Pin 32 is used to select that TCXO is used or that the self-oscillation is performed with the MCKI and
MCKO pins (Pins 30 and 31).
(1) TCXO solution (TCXO is used for CPU clock)
Set Pin 32 to low.
Pin 30: Low
Pin 31: Open
(2) When performing the self-oscillation with the MCKI and MCKO pins (Pins 30 and 31)
Set Pin 32 to high.
The crystal frequency should be less than 20MHz.
The following circuit is just a reference, and is not guaranteed.
20pF
30
20MHz max.
20pF
10MΩ
31
– 22 –
CXD2931R-9/GA-9
(3) Using internal clock
Set PORT5 (Pin 131) to high.
Connect the external parts as follows when performing the self-oscillation with the CCKI and CCKO pins
(Pins 13 and 14).
220pF
13
32.768kHz
±100ppm
10MΩ
14
220pF
(4) Input IF signal
0.01µF
18
1MΩ
19
– 23 –
CXD2931R-9/GA-9
Description of Application Circuit
See the Application Circuit when using the CXD2931R-9/GA-9 to configure a GPS receiver.
Points for caution are as follows.
1. Unused pins
Software processing is performed to prevent undesired current from flowing to unused pins in the circuit
diagram, so leave these pins open.
2. TCXO input
The TCXO frequency is 18.414MHz ± 3ppm. Signals that have not been binary-converted should be input
via a DC filter capacitor (C19 in the circuit diagram). Input binary-converted signals directly to Pin 7 (TCXO)
without passing through C19 or R1 in the circuit diagram.
Make sure the input level at this time satisfies the Electrical Characteristics.
3. IF input
The CXD2931R-9/GA-9 interface is 1.023MHz, and does not accept other frequencies. Signals that have
not been binary-converted should be input via a DC filter capacitor (C20). Input binary-converted signals
directly to Pin 18 (IF0) without passing through C20 or R3 in the circuit diagram.
Make sure the input level at this time satisfies the Electrical Characteristics.
4. TXD (SIO output)
The TXD amplitude low level is 0.4V or less, and the high level is VDD – 0.4V (VDD = 3.0 to 3.6V) or more.
When the LSI, etc., connected to TXD operates at 5V and has a CMOS input level, perform 3 to 5V
conversion before inputting the signal.
5. Real-time clock
The current software version uses an external real-time clock. Consult your Sony representative
beforehand when using the internal real-time clock. When using an external real-time clock, connect Pin 13
(CCKI) to GND.
– 24 –
CXD2931R-9/GA-9
S S V
D D V
I B 9
I B 1 0
D D V
I W R
R U
N
D D V
O U T C L K
C L K S
C L K
C L K I
S S V
I B 1 1
I B 1 2
I B 1 3
I B 1 4
I B 1 5
D R D
D W
O
P W R S T
E X R S
I O D B K
H O L D
P M I
R
X C S 0
A D R 0
A D R 1
A
S S V
N M I
A D R 2
A D R 3
A D R 4
A D R 5
A D R 6
A D R 7
A D R 8
A D R 9
H O L D
D D V
T C X O S
I F 0 O
I F 0
I C S T 1
I C S T 0
S S V
D D V
O
C C K
A D R 1 0
A D R 1 1
A D R 1 2
A D R 1 3
A D R 1 4
A D R 1 5
C C K I
T E S T 1
T E S T 0
T C O X O
D D V
X T C X O
T C X O
S S V
D B 0
D B 1
S S V
S
A V
D B 2
D B 3
D B 4
D B 5
V R B
V R
T
N I A V
A V
D
D D V
S S V
D D V
S S V
G N D
V I N
S S V
D D V
N C
N C
O V U T
– 25 –
CXD2931R-9/GA-9
Package Outline
Unit: mm
CXD2931R-9
144PIN LQFP (PLASTIC)
22.0 ± 0.2
20.0 ± 0.1
1.7 MAX
1.4 ± 0.1
73
108
109
72
B
A
37
144
36
0.08
1
0.5
0.1
S
b
S
M
S
0.1 ± 0.05
b = 0.20 ± 0.03
0˚ to 10˚
DETAIL B
DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
EPOXY RESIN
SONY CODE
EIAJ CODE
PALLADIUM PLATING
COPPER ALLOY
1.3 g
LQFP-144P-L01
LQFP144-P-2020
JEDEC CODE
PACKAGE MASS
– 26 –
CXD2931R-9/GA-9
Package Outline
Unit: mm
CXD2931GA-9
144PIN LFLGA
0.2
S
A
13.0
1.4MAX
0.01
X
PIN 1 INDEX
x4
0.15
S
3 – φ0.50
A
0.55
DETAIL X
144 – φ0.40 ± 0.05
R
P
N
M
L
M
φ0.08
S A B
K
B
J
H
G
F
E
D
C
B
A
2
1
3 4 5 6 7 8 9 101112131415
0.5
0.55
0.8
0.9
PACKAGE STRUCTURE
ORGANIC SUBSTRATE
PACKAGE MATERIAL
TERMINAL TREATMENT
TERMINAL MATERIAL
PACKAGE MASS
SONY CODE
EIAJ CODE
LFLGA-144P-01
NICKEL & GOLD PLATING
P-LFLGA144-13x13-0.8
COPPER
0.5g
JEDEC CODE
Sony Corporation
– 27 –
CXD2931GA-9 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| CXD2931R | SONY | 1 chip GPS LSI | 获取价格 |
|
| CXD2931R-9 | SONY | 1 chip GPS LSI | 获取价格 |
|
| CXD2931R-9-TL | SONY | Telecom Circuit, 1-Func, CMOS, PQFP144, 20 X 20 MM, PLASTIC, LQFP-144 | 获取价格 |
|
| CXD2931R-9/GA-9 | ETC | 1 chip GPS LSI | 获取价格 |
|
| CXD2932AGA-2 | SONY | GPS Base Band LSI | 获取价格 |
|
| CXD2932AR-2 | ETC | GPS Base Band LSI | 获取价格 |
|
| CXD2951GA | SONY | Telecom Circuit, 1-Func, CMOS, PBGA176, 12 X 12 MM, 0.50 MM PITCH, PLASTIC, LFLGA-176 | 获取价格 |
|
| CXD2951GA-1 | SONY | Telecom Circuit, 1-Func, CMOS, PBGA176, 12 X 12 MM, 0.50 MM PITCH, PLASTIC, LFLGA-176 | 获取价格 |
|
| CXD2951GA-2 | SONY | Single Chip GPS LSI | 获取价格 |
|
| CXD2951GA-4 | SONY | Single Chip GPS LSI | 获取价格 |
|
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