CXD3513 [SONY]
Interface and Driver IC for LCD; 接口和驱动器IC LCD型号: | CXD3513 |
厂家: | SONY CORPORATION |
描述: | Interface and Driver IC for LCD |
文件: | 总24页 (文件大小:202K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
CXD3513GG
Interface and Driver IC for LCD
Description
128 pin TFBGA (Plastic)
The CXD3513GG is an interface and driver IC for
the color LCD module ACX706AKM/AKN.
Features
• Generates the color LCD module ACX706AKM/AKN
drive pulse.
• Supports standby mode
• Built-in 9-channel reference voltage driver
• Built-in common voltage driver
• Built-in 2 channels of LED driver for ACX706AKN
(4-light of LED front light for ACX706AKM is not
supported.)
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage 1 VDD1
• Supply voltage 2 VDD2
VSS – 0.3 to +4.6
VSS – 0.3 to +6.0
V
V
• Input voltage
VI
VSS – 0.3 to VDD + 0.3 V
VSS – 0.3 to VDD + 0.3 V
• Output voltage
VO
Applications
• Storage temperature
Tstg
PDA, compact LCD monitor, etc.
–55 to +125
°C
Structure
Recommended Operating Conditions
Silicon gate CMOS IC
• Supply voltage 1 VDD1
• Supply voltage 2 VDD2
• Operating temperature
Topr
3.0 to 3.6
4.7 to 5.3
V
V
–25 to +75
°C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E01407B1Z
CXD3513GG
Block Diagram
C10, J6,
L11, M1
V
V
DD1 (3.3V)
Serial/Parallel Transform Block
M11, L10, M10, M9
J7, M6, L6, K6
R31, R21, R11, R01
XR31, XR21, XR11, XR01
B11, G9,
L2
SS1 (GND)
F12, F11, E12, E11 R32, R22, R12, R02
R3
H12
H11
H10
H9
R2
R1
R0
D10, A9, B9, C9
L9, M8, L8, K8
M5, L5, K5, J5
XR32, XR22, XR12, XR02
G31, G21, G11, G01
XG31, XG21, XG11, XG01
G3
G2
G1
G0
J12
J11
J10
J9
B12, C12, D12, A11 G32, G22, G12, G02
D9, A8, B8, C8
J8, M7, L7, K7
M4, L4, M3, L3
XG32, XG22, XG12, XG02
B31, B21, B11, B01
B3
B2
B1
B0
K12
K11
K10
K9
XB31, XB21, XB11, XB01
C11, D11, A10, B10 B32, B22, B12, B02
D8, A7, B7, C7
XB32, XB22, XB12, XB02
MCK
PCI
L12
G11
G12
E10
M12
A12
G11
E9
PCO
Power CTR.
H Counter
HST1, XHST1
HST2, XHST2
H4, H3
H2, H1
Delay
Delay
Hsync/DENB
SLIN
HCK1, XHCK1
HCK2, XHCK2
K2, K1
J2, J1
TESTP
TEST
H Timing Pulse GEN.
V Counter
G4, G3,
G2, G1
OE1, XOE1,
OE2, XOE2
Vsync
VST, XVST
VCK, XVCK
ENB, XENB
M2, L1
J4, J3
K4, K3
CLR
F9
V Timing Pulse GEN.
Timing Generator Block
F10 TESTO
B2, D2,
D7
V
V
DD2 (5.0V)
SS1 (GND)
F3 V0
B4, D3,
F4
E2 V1
E4 V2
D1 V3
C1 V4
D4 V5
C3 V6
VH1
F2
F1
VL1
VH2
VL2
E1
E3
Resistor
Array
Block
VRFSTB
A1
VH6
VL6
C2
B1
B3 V7
VH8
VL8
A2
C4
D5 V8
A3 VCOM
LEDC1
LEDC0
A5
C6
D6
B5
B6
Reference Voltage Driver Block
LED Driver Block
LEDSTB
LEDVRF
LEDVRS
A4 LEDIO1
C5 LEDIO2
A6 LEDIRF
– 2 –
CXD3513GG
Pin Configuration (Top View)
1
2
3
4
5
6
7
8
9
10
11
12
A
B
C
D
E
F
VRFSTB
VL6
VH8
VCOM
V7
LEDIO1
LEDC1
LEDIRF
XB22
XB12
XB02
XG22
XG12
XG02
XB32
XR22
XR12
XR02
XG32
PCO
CLR
B12
B02
G02
TEST
G32
G22
G12
R12
R32
VDD2
VSS2
LEDVRF LEDVRS
VSS1
V4
VH6
V6
VL8
V5
LEDIO2
V8
LEDC0
V
DD1
XR32
SLIN
TESTO
PCI
B32
B22
R02
R22
Vsync
R2
V3
VDD2
VSS2
LEDSTB
VDD2
VH2
V1
VL2
V0
V2
VL1
VH1
VSS2
G
H
J
Hsync/
DENB
XOE2
XHST2
XHCK2
XHCK1
XVST
OE2
XOE1
XHST1
XVCK
XENB
XB01
XB11
OE1
HST1
VCK
VSS1
HST2
HCK2
HCK1
R0
G0
R1
R3
G3
XG01
XG11
XG21
XG31
VDD1
XR31
B01
B31
G01
G11
G21
G1
G2
K
L
ENB
XR01
XR11
XR21
B0
B1
B2
B3
V
SS1
XB21
XB31
B11
G31
R01
R21
R11
VDD1
MCK
TESTP
M
VDD1
VST
B21
R31
– 3 –
CXD3513GG
Pin Description
Input pin for
open status
Pin
No.
Symbol
I/O
Description
B11 VSS1
—
—
—
—
—
—
—
I
GND (Logic)
—
—
—
—
—
—
—
UP
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
G9
L2
VSS1
VSS1
GND (Logic)
GND (Logic)
C10 VDD1
VDD1
Power supply (3.3V)
Power supply (3.3V)
Power supply (3.3V)
Power supply (3.3V)
J6
L11 VDD1
M1 VDD1
F9 CLR
H12 R3
System reset (Cleared at 0V)
Red signal input (MSB)
Red signal input
I
H11 R2
I
H10 R1
I
Red signal input
H9 R0
I
Red signal input (LSB)
Green signal input (MSB)
Green signal input
J12 G3
I
J11 G2
I
J10 G1
I
Green signal input
J9 G0
I
Green signal input (LSB)
Blue signal input (MSB)
Blue signal input
K12 B3
I
K11 B2
I
K10 B1
I
Blue signal input
K9 B0
I
Blue pulse input (LSB)
Hsync pulse input/Data enable signal input
Vsync pulse input
G12 Hsync/DENB
G11 Vsync
L12 MCK
G10 PCI
E10 SLIN
F10 TESTO
E9 PCO
M11 R31
L10 R21
M10 R11
M9 R01
L9 G31
M8 G21
L8 G11
K8 G01
J8 B31
I
I
I
Dot clock input
I
Power control signal input
Sync input signal mode selector switch
Test output (Leave it open.)
Power control signal output
Red signal output
I
O
O
O
O
O
O
O
O
O
O
O
Red signal output
Red signal output
Red signal output
Green signal output
Green signal output
Green signal output
Green signal output
Blue signal output
UP: Pull-up (typ. 160kΩ)
– 4 –
CXD3513GG
Input pin for
open status
Pin
No.
Symbol
I/O
Description
M7 B21
L7 B11
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
Blue signal output
Blue signal output
Blue signal output
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DWN
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
K7 B01
J7 XR31
M6 XR21
L6 XR11
K6 XR01
M5 XG31
L5 XG21
K5 XG11
J5 XG01
M4 XB31
L4 XB21
M3 XB11
L3 XB01
M12 TESTP
A12 TEST
M2 VST
R31 signal inversion output
R21 signal inversion output
R11 signal inversion output
R01 signal inversion output
G31 signal inversion output
G21 signal inversion output
G11 signal inversion output
G01 signal inversion output
B31 signal inversion output
B21 signal inversion output
B11 signal inversion output
B01 signal inversion output
Test input (Connect to GND.)
Test input (Connect to GND.)
VST pulse output
I
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
L1 XVST
K4 ENB
VST pulse inversion output
ENB pulse output
K3 XENB
J4 VCK
ENB pulse inversion output
VCK pulse output
J3 XVCK
K2 HCK1
K1 XHCK1
J2 HCK2
J1 XHCK2
H4 HST1
H3 XHST1
H2 HST2
H1 XHST2
G4 OE1
VCK pulse inversion output
HCK1 pulse output
HCK1 pulse inversion output
HCK2 pulse output
HCK2 pulse inversion output
HST1 pulse output
HST1 pulse inversion output
HST2 pulse output
HST2 pulse inversion output
OE1 pulse output
G3 XOE1
G2 OE2
OE1 pulse inversion output
OE2 pulse output
G1 XOE2
D8 XB32
A7 XB22
OE2 pulse inversion output
B32 signal inversion output
B22 signal inversion output
DWN: Pull-down (typ. 180kΩ)
– 5 –
CXD3513GG
Input pin for
open status
Pin
No.
Symbol
I/O
Description
B12 signal inversion output
B7 XB12
C7 XB02
D9 XG32
A8 XG22
B8 XG12
C8 XG02
D10 XR32
A9 XR22
B9 XR12
C9 XR02
C11 B32
D11 B22
A10 B12
B10 B02
B12 G32
C12 G22
D12 G12
A11 G02
F12 R32
F11 R22
E12 R12
E11 R02
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
—
—
—
—
—
—
O
O
I
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DWN
—
—
—
—
—
—
B02 signal inversion output
G32 signal inversion output
G22 signal inversion output
G12 signal inversion output
G02 signal inversion output
R32 signal inversion output
R22 signal inversion output
R12 signal inversion output
R02 signal inversion output
Blue signal output
Blue signal output
Blue signal output
Blue signal output
Green signal output
Green signal output
Green signal output
Green signal output
Red signal output
Red signal output
Red signal output
Red signal output
B4
D3
F4
B2
D2
D7
VSS2
VSS2
VSS2
VDD2
VDD2
VDD2
GND (Analog)
GND (Analog)
GND (Analog)
Power supply (5.0V)
Power supply (5.0V)
Power supply (5.0V)
A4 LEDIO1
C5 LEDIO2
D6 LEDSTB
B6 LEDVRS
A6 LEDIRF
A5 LEDC1
C6 LEDC0
B5 LEDVRF
F3 V0
LED driver output 1
LED driver output 2
LED driver on/off switch
Reference voltage switch for LED
Reference resistor connection
Output current setting (MSB)
Output current setting (LSB)
External reference voltage input for LED
V0 output
I
O
I
I
I
O
DWN: Pull-down (typ. 180kΩ)
– 6 –
CXD3513GG
Input pin for
open status
Pin
No.
Symbol
I/O
Description
E2 V1
E4 V2
D1 V3
C1 V4
D4 V5
C3 V6
B3 V7
D5 V8
O
O
O
O
O
O
O
O
O
I
V1 output
V2 output
V3 output
V4 output
V5 output
V6 output
V7 output
V8 output
VCOM output
—
—
—
—
—
—
—
—
A3 VCOM
A1 VRFSTB
F2 VH1
F1 VL1
—
Reference voltage driver on/off selector switch
DWN
—
I
VH1 input
VL1 input
VH2 input
VL2 input
VH6 input
VL6 input
VH8 input
VL8 input
I
—
E1 VH2
E3 VL2
C2 VH6
B1 VL6
A2 VH8
C4 VL8
I
—
I
—
I
—
I
—
I
—
I
—
DWN: Pull-down (typ. 180kΩ)
– 7 –
CXD3513GG
Electrical Characteristics (Serial/parallel conversion block, timing generator block)
DC Characteristics (VDD1 = 3.0 to 3.6V, Ta = –25 to +75°C)
Typ.
3.3
Item
Symbol
Applicable pins
Conditions
Min.
3.0
Max.
3.6
Unit
V
Supply voltage
VDD1
VDD1
VDD1
—
No load, Ta = 25°C
VDD1 = 3.3V,
MCK: 5.62MHz
Current
consumption
IDD1
—
1.5
—
mA
V
MCK, LEDVRS,
LEDC0, LEDC1,
LEDSTB, VRFSTB
0.7VDD1
—
—
—
VIH1
VIL1
Input voltage 1
Input voltage 2
CMOS input cell
—
0.2VDD1
All input pins excluding
MCK, LEDVRS, LEDC0,
LEDC1, LEDSTB,
VRFSTB
—
0.15VDD1
—
—
—
—
—
0.75VDD1
—
Vt+
CMOS
Schmitt trigger
input cell
V
Vt–
R0, R1, R2, R3, G0, G1,
G2, G3, B0, B1, B2, B3,
Hsync/DENB, Vsync,
MCK, PCI
VI = 0V
1.0
| IIL1 |
| IIH1 |
Input current 1
µA
VI = VDD
—
1.0
| IIL2 |
| IIH2 |
VI = 0V
VI = VDD
VI = 0V
VI = VDD
10
—
—
10
—
—
—
—
100
3.0
3.0
100
Input current 2
Input current 3
CLR
µA
µA
| IIL3 |
| IIH3 |
TEST, TESTP, SLIN
R01, R11, R21, R31,
R02, R12, R22, R32,
XR01, XR11, XR21, XR31,
XR02, XR12, XR22, XR32,
G01, G11, G21, G31,
G02, G12, G22, G32,
XG01, XG11, XG21, XG31,
XG02, XG12, XG22, XG32,
B01, B11, B21, B31,
B02, B12, B22, B32,
XB01, XB11, XB21, XB31,
XB02, XB12, XB22, XB32,
VST, XVST, ENB, XENB,
OE1, XOE1, OE2, XOE2,
TESTO
VOL1
IOL1 = 4.0mA
—
—
—
0.2
Output voltage 1
V
VOH1
IOH1 = –4.0mA VDD – 0.8
—
HST1, XHST1, HST2,
XHST2, VCK, XVCK,
PCO
VOL2
VOH2
IOL2 = 6.0mA
—
—
—
0.2
Output voltage 2
Output voltage 3
V
V
IOH2 = –6.0mA VDD – 0.8
IOL3 = 10.0mA
IOH3 = –10.0mA VDD – 0.8
—
VOL3
VOH3
—
—
—
0.4
HCK1, XHCK1,
HCK2, XHCK2
—
– 8 –
CXD3513GG
AC Characteristics
(VDD = 3.0 to 3.6V, Ta = –25 to +75°C)
1
Item
Symbol
Applicable pins
Conditions
Min.
Typ.
Max.
Unit
ns
HCK1, HCK2, XHCK1,
XHCK2, HST1, HST2,
XHST1, XHST2
HCK/HST time
difference
∆tHST-HCKU
∆tHST-HCKD
2
—
—
—
15
R01, R11, R21, R31,
R02, R12, R22, R32,
XR01, XR11, XR21, XR31,
XR02, XR12, XR22, XR32,
G01, G11, G21, G31,
G02, G12, G22, G32,
XG01, XG11, XG21, XG31,
XG02, XG12, XG22, XG32,
B01, B11, B21, B31,
Data output
rise time
GND – VDD
(0 – 90%)
—
—
—
—
35
35
t
t
RD
ns
Data output
fall time
VDD – GND
(100 – 10%)
FD
B02, B12, B22, B32,
XB01, XB11, XB21, XB31,
XB02, XB12, XB22, XB32
Horizontal pulse
output rise time
GND – VDD
(0 – 90%)
HCK1, HCK2,
XHCK1, XHCK2,
HST1, HST2,
—
—
—
—
—
—
—
—
35
35
50
50
t
t
t
t
RHP
FHP
RVP
FVP
ns
ns
Horizontal pulse
output fall time
VDD – GND
(100 – 10%)
XHST1, XHST2
Vertical pulse
output rise time
GND – VDD
(0 – 90%)
VCK, XVCK, VST, XVST,
ENB, XENB, OE1, OE2,
XOE1, XOE2, PCO,
TESTO
Vertical pulse
output fall time
VDD – GND
(100 – 10%)
HCK1, HCK2,
XHCK1, XHCK2,
R01, R11, R21, R31,
R02, R12, R22, R32,
XR01, XR11, XR21, XR31,
XR02, XR12, XR22, XR32,
G01, G11, G21, G31,
G02, G12, G22, G32,
XG01, XG11, XG21, XG31,
XG02, XG12, XG22, XG32,
B01, B11, B21, B31,
B02, B12, B22, B32,
XB01, XB11, XB21, XB31,
XB02, XB12, XB22, XB32
HCK1, HCK2,
XHCK1, XHCK2/
DATA setup time
3
35
55
100
ns
t
STP
dHCK
dVCK
HCK1, HCK2, XHCK1,
XHCK2, VCK, XVCK
4
HCK, VCK duty
48
50
52
%
1
Load capacitance CL of each output pin is shown below.
• R01, R11, R21, R31, R02, R12, R22, R32, XR01, XR11, XR21, XR31, XR02, XR12, XR22, XR32, G01,
G11, G21, G31, G02, G12, G22, G32, XG01, XG11, XG21, XG31, XG02, XG12, XG22, XG32, B01,
B11, B21, B31, B02, B12, B22, B32, XB01, XB11, XB21, XB31, XB02, XB12, XB22, XB32, OE1, XOE1,
OE2, XOE2, TESTO, ENB, XENB
• HCK1, HCK2, XHCK1, XHCK2
• VCK, XVCK
: CL = 70pF
: CL = 180pF
: CL = 150pF
• HST1, HST2, XHST1, XHST2, VST, XVST, PCO : CL = 100pF
Absolute value of the time difference of the change point at HST1, XHST1, HCK1 and XHCK1 (50%) is
within 15ns.
2
Similarly, absolute value of the time difference of the change point at HST2, XHST2, HCK2 and XHCK2
(50%) is within 15ns.
3
4
t
STP: tST1D, tST1U, tST2D, tST2U
dHCK = (tHH/(tHH + tHL)) × 100, dVCK = (tVH/(tVH + tVL)) × 100
– 9 –
CXD3513GG
Timing Definition
Horizontal System
t
HL
t
HH
VDD1
50%
HCK1
50%
50%
GND
VDD1
50%
50%
XHCK1
GND
∆t
H
∆tH
VDD1
HCK2
50%
50%
GND
VDD1
50%
50%
XHCK2
GND
∆t
H
∆t
H
VDD1
50%
HST1
(HST2)
GND
VDD1
50%
XHST1
(XHST2)
GND
VDD1
HCK1
50%
(HCK2)
GND
VDD1
50%
XHCK1
(XHCK2)
GND
∆tHST-HCKU
∆tHST-HCKD
– 10 –
CXD3513GG
Vertical System
t
VL
t
VH
V
DD1
50%
VCK
50%
50%
GND
V
DD1
50%
50%
XVCK
GND
∆t
V
∆tV
DATA
VDD1
50%
HCK1
50%
GND
VDD1
50%
50%
XHCK1
GND
VDD1
50%
HCK2
50%
GND
VDD1
50%
50%
XHCK2
GND
VDD1
DATA
GND
tST1D
tST2D
tST1U
tST2U
tSTX1U
tSTX2U
tSTX1D
tSTX2D
– 11 –
CXD3513GG
PCI, PCO
These pins control to turn power on/off of the ACX706AKM/AKN when the LCD is turned on/off. Connect PCO
to DC-DC converter that can control power on/off of the ACX706AKM/AKN.
Power-on Sequence
• Raise and fall VDD1 and VDD2 simultaneously (within 10ms)
• Input the input signal 1 for 1 field (Min.), and then raise PCI.
• After PCI becomes high, latch is performed twice at Vsync. When both of them are high, PCO output is
changed from low to high.
(Turn the power on of the ACX706AKM/AKN at this timing.)
Also, effective screen is displayed after two fields of entire white display from this timing.
±10ms
V
DD1
DD2
DD1
V
V
DD1
DD2
0
V
0
V
CLR
0
3
Low
Low
Low
Low
PCI
PCO
2
1
2
High
High
Pulse
Active
White Data
Valid
DATA (out)
Vsync
DENB
Low
Low
MCK
Hsync
DATA (in)
Low
Active
1 field (min.)
1 field (min.)
2 fields
1
Hsync, Vsync, DENB, MCK, DATA
2
HST1, XHST1, HST2, XHST2, HCK1, XHCK1, HCK2, XHCK2, VST, XVST, VCK, XVCK, ENB, XENB,
OE1, XOE1, OE2, XOE2, TESTO, (FRP)
3
Do not change PCI from low to high on the following timing.
Hsync + Vsync mode (SLIN: Low) Period between 330 to 332 lines (See Vertical Direction Input Signal
Timing Chart on page 15.)
DENB only mode (SLIN: High) Period between 240 to 245 clocks (See Horizontal Direction Input Signal
Timing Chart on page 14.)
– 12 –
CXD3513GG
Power-off Sequence (Standby)
• When LCD is off, LCD is turned off after entire white display.
±10ms
Standby Mode
High
Low
PCI
High
Low
PCO
V
0
DD1
DD2
V
DD1
DD2
V
0
V
Low
Low
Valid
DATA
All Data: High (XDATA: Low)
1
Active
Pulse
Vsync
DENB
Low
Low
3 fields
10 fields
MCK
Hsync
Low
Active
DATA (in)
1
HST1, XHST1, HST2, XHST2, HCK1, XHCK1, HCK2, XHCK2, VST, XVST, VCK, XVCK, ENB, XENB,
OE1, XOE1, OE2, XOE2, TESTO, (FRP)
SLIN
This is a selector switch for sync input signal mode.
SLIN: Low → Hsync + Vsync Mode.
SLIN: High → DENB ONLY Mode. (Vsync is invalid.)
– 13 –
Horizontal Direction Input Signal Timing Chart
272 dots
230
235
240
245
250
255
260
265
270
0
5
MCK
1
Hsync
16 dots
16 dots
1
DENB
32 dots
DATA
227 228 229 230 231 232 233 234 235 236 237 238 239 240
1
2
3
4
5
6
7
8
9 10 11
tch
tcl
PCI prohibited period (Low → High)
MCK
tclk
thss
1
Hsync
thsw
1
DENB
tdes
tdeh
DATA
1
2
240
tds tdh
1 Input either Hsync + Vsync or DENB as sync input signal.
Input Signal AC Characteristics (VDD1 = 3.0 to 3.6V, Ta = –25 to +75°C)
Item
Symbol
ftch
Min.
Typ.
Max.
MCK frequency
4MHz 5.62MHz 8MHz
MCK low, high pulse width tch, tcl
—
5
—
—
0.5tclk
—
DATA setup time
DATA hold time
tds
tdh
10
5
—
—
DENB setup time
DENB hold time
Hsync setup time
Hsync low pulse width
tdes
tdeh
thss
thsw
—
—
10
5
—
—
—
—
9tclk
—
16tclk
Vertical Direction Input Signal Timing Chart
344 lines
315
320
325
330
335
340
0
5
10
15
1
1
1
Hsync
Vsync
DENB
10 lines
14 lines
PCI prohibited period (Low → High)
(1)
(2)
(14)
(15)
1
1
Hsync
Vsync
tvhde
tvsw
1
DENB
DATA
1 Input either Hsync + Vsync or DENB as sync input signal.
Input Signal AC Characteristics (VDD1 = 3.0 to 3.6V, Ta = –25 to +75°C)
Item
Symbol
tvhde
tvsw
Min.
3tclk
Typ.
Max.
Hsync rising edge
→ Vsync rising edge
—
272tclk
20 lines
Vsync low pulse width
—
2 lines
Horizontal Direction Timing Chart
272 dots
200
210
220
230
240
250
260
0
10
20
MCK
Hsync
DENB
DATA
16 dots
16 dots
32 dots
1
2
3
4
5
6 7 8 9
R/G/B
01 to 31
189 191 193 195 197 199 201 203 205 207 209 211 213 215 217 219 221 223 225 227 229 231 233 235 237 239
190 192 194 196 198 200 202 204 206 208 210 212 214 216 218 220 222 224 226 228 230 232 234 236 238 240
1
3
5
6
7
8
9
11 13 15 17 19 21 23
R/G/B
02 to 32
2
4
10 12 14 16 18 20 22 24
262
266
HST1
4 dots
XHST1
HCK1
XHCK1
264
268
HST2
4 dots
XHST2
HCK2
XHCK2
OE1
248
260
XOE1
240
0
OE2
XOE2
224
0
ENB
XENB
270
VST
XVST
VCK
254
254
254
XVCK
(FRP)
Vertical Direction Timing Chart
344 lines
320
325
330
335
340
0
5
10
15
20
Hsync
10 lines
Vsync
DENB
14 lines
VST
XVST
VCK
XVCK
ENB
XENB
OE1
XOE1
OE2
XOE2
1
(FRPO)
1
(FRPE)
1
FRPO: FRP pulse at odd field. FRPE: FRP pulse at even field.
CXD3513GG
Reference Voltage Driver Block
Block Diagram
VDD2 (5.0V)
VDD2
VH0
VL0
VH1
VL1
VH2
VL2
VH3
VL3
VH4
VL4
VH5
VL5
VH6
VL6
VH7
VL7
VH8
VL8
V0
V1
V2
V3
V4
V5
V6
V7
V8
VCOM
VSS2
Resistor array
VRFSTB
Level Shift
Level Shift
1
FRP
V
SS2
1 Internal pulse of the logic block
Electrical Characteristics (Reference voltage driver block)
Resistor array output voltage
(VDD1 = 3.3V, VDD2 = 5.0V, Ta = 25°C)
Item
VH0
VH1
VH2
VH3
VH4
VH5
VH6
VH7
VH8
Min.
—
—
—
—
—
—
—
—
—
Typ.
Max.
—
Unit
Item
VL0
VL1
VL2
VL3
VL4
VL5
VL6
VL7
VL8
Min.
—
—
—
—
—
—
—
—
—
Typ.
Max.
—
Unit
5.000
4.200
3.625
3.250
2.900
2.550
2.025
1.650
0.800
0.000
0.800
1.375
1.750
2.100
2.450
2.975
3.350
4.200
—
—
—
—
—
—
—
—
V
V
—
—
—
—
—
—
—
—
– 18 –
CXD3513GG
AC, DC Characteristics
(VDD1 = 3.3V, VDD2 = 5.0V, Ta = –25 to +75°C)
Min.
4.7
Typ.
5.0
Max.
5.3
Item
Symbol
Conditions
Unit
V
Supply voltage
VDD2
—
Input voltage = 2.5V,
During no load
Current consumption
IDD2
—
3.4
6.0
mA
VH, VL input current high IIH
Input voltage = 4.8V
Input voltage = 0.2V
Input voltage = 0.2 to 4.8V
ISOURCE = 10mA
ISINK = 10mA
–0.15
–0.15
0.985
VDD2 – 1.0
—
—
—
—
—
—
—
—
—
0.15
µA
µA
V/V
V
VH, VL input current low
Voltage gain
IIL
0.15
AV
VOH
VOL
—
Output voltage high
Output voltage low
—
GND + 1.0
—
V
COM output voltage high VCOH
ISOURCE = 10mA
ISINK = 10mA
VDD2 – 0.1
—
V
COM output voltage low
Offset voltage
VCOL
VOFF
GND + 0.1
20
V
Rs = 10kΩ
—
mV
Input voltage = 0.2 to 4.8V
ISOURCE = 10mA
Load regulation
∆VO
—
±5
±10
mV
ISINK = 10mA
Output impedance
Settling time 1
Settling time 2
Settling time 3
Settling time 4
RIMP
ts1
V1 to V8
—
—
—
—
—
15
—
—
—
—
—
10
10
6
Ω
Measurement circuit 1
Measurement circuit 1
Measurement circuit 2
Measurement circuit 2
µs
µs
µs
µs
ts2
ts3
ts4
6
– 19 –
CXD3513GG
Measurement Circuit
Measurement circuit 1
15Ω
VH
4.8V
Measuring point
V1 to V8
0.2V
VL
30nF
Measurement circuit 2
5.0V
0V
Measuring point
V0, VCOM
30nF
FRP (internal pulse)
Output (V0 to V8)
50%
50%
ts1
ts2
90%
10%
90%
ts4
Output (VCOM)
10%
ts3
VRFSTB
This is a selector switch for reference voltage driver output on/off.
VRFSTB: Low → V0 to V8 and VCOM are GND level.
VRFSTB: High → V0 to V8 and VCOM are active.
– 20 –
CXD3513GG
LED Driver (ACX706AKN, 2-light of LED front light supported)
Block Diagram
Level Shift
Level Shift
Level Shift
LEDSTB
LEDC0
LEDC1
IOUT1
IOUT2
IREF
LEDIO1
LEDIO2
LEDVRF
LEDVRS
VREF
LEDIRF
Level Shift
Reference
Voltage Circuit
1.0mA
1.2kΩ
Note: Not supported for 4-light of LED front light of ACX706AKM.
Prepare LED driver separately for ACX706AKM.
Reference resistor
(external)
Electrical Characteristics (LED driver block)
DC Characteristics
(VDD1 = 3.3V, VDD2 = 5.0V, Ta = 25°C)
Min.
Typ.
Max.
10
Item
Symbol
Iref
Conditions
LEDIO1, LEDIO2
Unit
%
Constant-current accuracy
–10
—
(10, 15, 20, 25mA)
Internal reference voltage
source accuracy
Vref
LEDVRF
1.05
1.2
1.35
V
Current consumption
(excluding constant-current)
Total current consumption =
output current + Idd
Idd
—
—
1.5
—
mA
V
Maximum output voltage
Vmax
LEDIO1, LEDIO2
—
4.0
– 21 –
CXD3513GG
LEDC0, 1
These are constant-current source setting pins.
(Always fix to low or high, and do not leave open.)
LEDC0 LEDC1 LEDIO1 LEDIO2
0
1
0
1
0
0
1
1
20
15
10
25
20
15
10
25
mA
LEDVRS
This is an LED reference voltage source selector switch pin.
(Always fix to low or high, and do not leave open.)
LEDVRS: Low → Internal reference voltage
LEDVRS: High → External reference voltage (Input voltage: 1.2V)
LEDSTB
This is a selector switch for LED driver on/off.
LEDSTB: Low → LEDIO1 and LEDIO2 are inactive (Hi-Z).
LEDSTB: High → LEDIO1 and LEDIO2 are active.
– 22 –
CXD3513GG
Application Circuit
INPUT
To ACX706AKN
Front Light
1.2V (Reference voltage input)
To ACX706AKM/AKN
1.2kΩ
VDD2
VDD1
A2 A3 B3 C4 D5 A4 C5 B4 B5 B6 D6 A5 C6 A6 D7 C7 B7 A7 D8 C8 B8 A8 D9 C9 B9 A9 D10 B10 A10 D11 C11 C10
A1 VRFSTB
B1 VL7
TEST A12
VSS1 B11
B2
C1
C2
C3
D1
D2
D3
D4
E1
E2
E3
E4
F1
F2
F3
F4
G1
G2
G3
G4
H1
H2
H3
H4
J1
A11
D12
C12
B12
E11
E12
F11
F12
E9
V
DD2
G02
V4
G12
G22
VH7
V6
G32
V3
R02
V
DD2
SS2
R12
V
R22
V5
R32
VH2
V1
PCO
SLIN
CLR
TESTO
E10
F9
VL2
V2
F10
G9
VL0
VH0
V0
VSS1
G10
G11
G12
H9
PCI
Vsync
VSS2
Hsync/DENB
XOE2
OE2
R0
R1
H10
H11
H12
J9
XOE1
OE1
R2
R3
XHST2
HST2
XHST1
HST1
XHCK2
HCK2
XVCK
VCK
G0
G1
G2
G3
B0
J10
J11
J12
K9
J2
K10
K11
K12
L12
L11
B1
J3
B2
J4
B3
K1
K2
XHCK1
HCK1
MCK
VDD1
VDD1
M1 L2 M2 L1 K4 K3 L3 M3 L4 M4 J5 K5 L5 M5 K6 L6 M6 J7 J6 K7 L7 M7 J8 K8 L8 M8 L9 M9 M10 L10 M11 M12
To ACX706AKM/AKN
VDD1
1
Connect PCO to DC-DC converter that can control power on/off of the ACX706AKM/AKN.
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 23 –
CXD3513GG
Package Outline
Unit: mm
128PIN TFBGA (PLASTIC)
11.0
0.3
A
S
x4
0.20
0.2
S
10.6 ± 0.1
S
0.1
S
0.8
1.1
A
M
L
K
J
H
G
B
F
E
D
C
B
A
1 2 3 4 5 6 7 8 9 10 11 12
128 - φ 0.5 ± 0.05
M
φ 0.08
S
A
B
PACKAGE STRUCTURE
ORGANIC SUBSTRATE
PACKAGE MATERIAL
TERMINAL TREATMENT
SONY CODE
TFBGA-128P-061
TERMINAL MATERIAL
PACKAGE MASS
EIAJ CODE
P-TFBGA128-11x11-0.8
SOLDER
0.22g
JEDEC CODE
Sony Corporation
– 24 –
相关型号:
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