CXG1092N [SONY]
SP5T GSM Triple-Band Antenna Switch; SP5T GSM三频天线开关
| 型号： | CXG1092N |
| 厂家： | 
SONY CORPORATION |
| 描述： | SP5T GSM Triple-Band Antenna Switch |
| 文件： | 总6页 (文件大小：70K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CXG1092N
SP5T GSM Triple-Band Antenna Switch
For the availability of this product, please contact the sales office.
Description
20 pin SSOP (Plastic)
The CXG1092N is a high power antenna MMIC
switch for use in triple-band GSM handsets.
One antenna can be routed to either of the 2 Tx or
3 Rx ports.
Features
• 4 CMOS compatible control lines
• Standby control
• 34.5dBm power handling at 5.0V (GSM900)
• Low second harmonic < –36dBm at 34.5dBm
• Small package size: 20-pin SSOP (6.4 × 5.0 × 1.25mm)
Applications
Triple-band handsets using combinations of GSM900/DCS1800/PCS1900 and DECT
Structure
GaAs J-FET MMIC (The Sony JFET process is used for low insertion loss.)
Absolute Maximum Ratings (Ta = 25°C)
• Bias voltage
VDD
7
5
V
V
• Control voltage
Vctl
• Operating temperature Topr
–35 to +85 °C
–65 to +150 °C
• Storage temperature
Tstg
Note on Handling
GaAs MMICs are ESD sensitive devices. Special handling precautions are required.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E99Z07-PS
CXG1092N
Truth Table
On Pass
GSM900 DCS1800 PCS1900
Rx ON
STDBY
Ant.-Tx1 GSM900
H
L
L
H
L
L
L
L
L
H
H
H
H
H
L
Ant.-Tx2 GSM1800
Ant.-Rx1 GSM900/1800/1900
Ant.-Rx2 GSM900/1800/1900
Ant.-Rx3 GSM900/1800/1900
OFF
H
L
L
H
H
H
—
H
L
L
L
H
—
—
—
CMOS logic values
(Ta = 25°C)
Logic
High
Low
Min.
2.4
Typ.
2.8
Max.
3.2
Unit
V
0.0
0.4
V
– 2 –
CXG1092N
Electrical Characteristics
(Ta = 25°C)
Item
Symbol
Port
Condition
Min.
Typ.
0.6
Max.
Unit
dB
dB
dB
dB
dB
dB
dB
dB
dB
1
2
3
4
5
3
Ant-Tx1, Tx2
0.9
1.0
0.7
Insertion loss
IL
Ant-Rx1, Rx2, Rx3
0.6
0.9
0.85
0.9
1.1
1.15
Ant-Tx1, Tx2
15
14
18
17
4,
1
5
Isolation
ISO.
Ant-Rx1, Rx2, Rx3
2
VSWR
VSWR
2fo
1.2
1,
1,
2
2
–36
–30
dBm
dBm
HarmonicsNote)
Ant-Tx1, Tx2
3fo
Ant-Tx1
Ant-Tx2
36
P1dB compression
input power
P1dB
dBm
35.5
Control current
Ictl
170
1
µA
Supply current
Tx mode
STBY = H
TxON = L
ITX
mA
Supply current
Rx mode
STBY = H
RxON = H
IRX
IIK
1
mA
µA
Leakage current
STBY = L
100
1
Pin 1 = 34.5dBm, 880 to 915MHz, VDD = 5.0V
(GSM Tx)
2
3
4
5
Pin 2 = 32dBm, 1710 to 1910MHz, VDD = 5.0V (DCS & PCS Tx)
Pin 3 = 10dBm, 925 to 960MHz
Pin 4 = 10dBm, 1805 to 1880MHz
Pin 5 = 10dBm, 1930 to 1990MHz
(GSM Rx)
(DCS Rx)
(PCS Rx)
Note) Harmonics measured with Tx inputs harmonically matched.
Sony recommends the use of harmonic matching to ensure optimum device performance
Application Note (1).
– 3 –
CXG1092N
Recommended Circuit
(RRF)
(RRF)
(
1)
11 ANT
12 GND
10
9
8
7
6
5
4
3
2
1
Tx1
GND
Tx2
13
14
15
16
17
18
19
20
GND
(RRF)
VDD
GND
Rx1
GND
GSM900 CTL
DCS1800 CTL
PCS1900 CTL
RX ON
GND
Rx2
GND
Rx3
GND
STDBY
Recommended PCB Layout
As indicated in the diagram AC coupling capacitors are necessary to the Ant, Tx1, Tx2, Rx1, Rx2 and Rx3
pins, and decoupling capacitors are necessary to the VDD, STDBY and CTL lines.
The ground plane should be included under the device and all ground pins connected to this.
RRF (200kΩ) is used to stabilize the electrical characteristics at the high power signal input.
These resistors are required to ensure correct operation of the switch.
1
See Application Note (1).
– 4 –
CXG1092N
Application Note (1)
Impedance matching for harmonic minimization
To achieve the 2nd harmonic levels lower than –36dBm for GSM900
Design of 1.8GHz harmonic matching network and the 900MHz trap network is dependent on the board design
and components.
1800MHz Matching
Network
900MHz Trap
LPF
ANT 11
12
10
9
8
7
6
5
4
3
2
1
Tx1
GND
GND
GND 13
VDD 14
Tx2
GND
Rx1
GND 15
GSM900 CTL 16
GND
Rx2
DCS1800 CTL
PCS1900 CTL
RX ON
17
18
19
20
GND
Rx3
GND
STDBY
Application Note (2)
Operating the CXG1092 from a 3V supply
Technique
Logic lines
Allows use of the CXG1092N (SP5T) in handsets
with 3V min. battery voltage (2.7V SW supply).
The CXG1092N is for 5V nominal battery voltage
but work well down to 4V.
200k
200k
Tx1
Tx2
Rx1
Rx2
Rx3
Fundamentally, the 577µs time slot waveform is
used to increase the 2.7V supply to over 4V.
200k
ANT
This waveform may be taken from the PA
ramping input (or drain supply in case of drain
power control) or via the TX ON/OFF logic.
CXG1092N
C
D
≈ 4.0V D.C. Out
VDD
C
R
Additional Components
C: 0603 CAPS, few µF
R: 200R
VDD @2.7V
D: Low Turn-on voltage diode
577µs
– 5 –
CXG1092N
Package Outline
Unit: mm
20PIN SSOP(PLASTIC)
5.0 ± 0.05
1.25MAX
S
A
20
11
A
10
1
b
0.5
A
0.1
S
0.1
S
M
B
b = 0.22 ± 0.05
b = 0.2 ± 0.03
0.25
(0.2)
0.1 ± 0.1
DETAIL B : SOLDER
DETAIL B : PALLADIUM
0° to 10°
NOTE: Dimension “ ” does not include mold protrusion.
A
DETAIL
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
EPOXY RESIN
SOLDER/PALLADIUM
PLATING
SONY CODE
EIAJ CODE
SSOP-20P-L03
LEAD MATERIAL
PACKAGE MASS
COPPER ALLOY
SSOP020-P-0044
JEDEC CODE
0.1g
– 6 –
Sony Corporation
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