CXK5T8512TM_技术文档

CXK5T8512TM/TN-10LLX/12LLX

65536-word × 8-bit High Speed CMOS Static RAM

Preliminary

For the availability of this product, please contact the sales office.

Description

CXK5T8512TN

CXK5T8512TM

The CXK5T8512TM/TN is a high speed CMOS

static RAM organized as 65536-words by 8-bits.

Special feature are low power consumption and

high speed.

32 pin TSOP (Plastic)

The CXK5T8512TM/TN is a suitable RAM for

portable equipment with battery back up.

Features

• Extended operating temperature range:

–25 to +85°C

Block Diagram

• Wide supply voltage range operation: 2.7 to 3.6V

A15

A13

A8

A11

A9

• Fast access time:

(Access time)

3.0V operation

VCC

Memory

Matrix

CXK5T8512TM/TN-10LLX 100ns (Max.)

CXK5T8512TM/TN-12LLX 120ns (Max.)

3.3V operation

Row

Decoder

Buffer

A7

A6

A5

1024 × 512

GND

A14

A12

CXK5T8512TM/TN-10LLX 85ns (Max.)

CXK5T8512TM/TN-12LLX 100ns (Max.)

• Low standby current:

14µA (Max.)

A4

A3

A10

A0

A2

A1

• Low data retention current: 12µA (Max.)

• Low power data retention: 2.0V (Min.)

• Package line-up

I/O Gate

Column

Decoder

Buffer

CXK5T8512TM

8mm × 20mm 32 pin TSOP package

CXK5T8512TN

8mm × 13.4mm 32 pin TSOP package

OE

Buffer

WE

I/O Buffer

CE1

CE2

Function

I/O1 I/O8

65536-word × 8-bit static RAM

Structure

Silicon gate CMOS IC

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by

any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the

operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

– 1 –

PE96727-PS

CXK5T8512TM/TN

Pin Configuration (Top View)

Pin Description

Symbol

Description

1

32

31

30

29

28

27

OE

A11

A9

A8

A13

2

A10

CE1

I/O8

I/O7

I/O6

I/O5

I/O4

GND

I/O3

I/O2

I/O1

A0

A0 to A15

Address input

3

4

I/O1 to I/O8 Data input output

5

WE

CE2

A15

Vcc

NC

6

CE1, CE2

WE

Chip enable 1, 2 input

Write enable input

Output enable input

Power supply

7

8

26

25

24

23

22

21

20

19

18

17

CXK5T8512TM

(Standard Pinout)

9

NC 10

A14

OE

11

A12 12

A7 13

VCC

A1

A2

A3

A6

14

GND

NC

Ground

A5 15

16

A4

No connection

1

32

31

30

29

28

27

OE

A11

A9

A8

A13

WE

CE2

A15

Vcc

NC

2

3

4

5

A10

CE1

I/O8

I/O7

I/O6

I/O5

I/O4

GND

I/O3

I/O2

I/O1

A0

6

7

8

26

25

24

23

22

21

20

19

18

17

CXK5T8512TN

(Standard Pinout)

9

NC 10

A14

11

A12 12

A7 13

A1

A2

A3

A6

14

A5 15

16

A4

Absolute Maximum Ratings

(Ta = 25°C, GND = 0V)

Item

Symbol

VCC

Rating

–0.5 to +4.6

–0.5 ¹to VCC + 0.5

0.7

Unit

V

Supply voltage

Input voltage

VIN

V

Input and output voltage

Allowable power dissipation

Operating temperature

Storage temperature

VI/O

V

PD

W

Topr

Tstg

–25 to +85

°C

°C · s

–55 to +150

235 · 10

Soldering temperature · time Tsolder

1

VIN, VI/O = –3.0V Min. for pulse width less than 50ns.

Truth Table

Mode

Not selected

Output disable

Read

I/O pin

High Z

VCC Current

CE1 CE2 OE WE

H

×

L

×

L

×

H

L

×

ISB1, ISB2

High Z

Data out

Data in

ISB1, ISB2

H

L

ICC1, ICC2, ICC3

Write

×: “H” or “L”

– 2 –

CXK5T8512TM/TN

DC Recommended Operating Conditions

(Ta = –25 to +85°C, GND = 0V)

VCC = 2.7 to 3.6V

Typ.

VCC = 3.3V ± 0.3V

Unit

Item

Symbol

Min.

3.0

Typ.

3.3

—

Max.

Min.

2.7

Max.

3.6

Supply voltage

VCC

VIH

VIL

3.6

3.3

Input high voltage

Input low voltage

V

VCC + 0.3

0.6

—

VCC + 0.3

0.4

2.2

2.4

1

—

–0.3

¹VIL = –3.0V Min. for pulse width less than 50ns.

Electrical Characteristics

• DC Characteristics

(VCC = 2.7 to 3.6V, GND = 0V, Ta = –25 to +85°C)

1

Item

Symbol

I^LI

Test conditions

Min.

–1

Typ.

—

Max. Unit

Input leakage current

VIN = GND to VCC

+1

µA

CE1 = VIH or CE2 = VIL or

OE = V^IHor WE = VIL

VI/O = GND to VCC

Output leakage current

ILO

–1

—

1

+1

µA

CE1 = VIL, CE2 = VIH

VIN = VIH or VIL

IOUT = 0mA

Operating power supply

current

ICC1

ICC2

3

mA

2

3

Min. cycle

duty = 100%

IOUT = 0mA

10LLX

12LLX

—

25

35

Cycle time 1µs

duty = 100%

IOUT = 0mA

Average operating current

—

5

10

CE1 ≤ 0.2V

mA

ICC3

CE2 ≥ Vcc – 0.2V

VIL ≤ 0.2V

VIH ≥ Vcc – 0.2V

–25 to +85°C

–25 to +70°C

+25°C

—

14

7

CE2 ≤ 0.2V

ISB1

CE1 ≥ Vcc – 0.2V

CE2 ≥ Vcc – 0.2V

µA

or

{

Standby current

—

0.24

0.12

—

1.4

—

0.4

ISB2

VOH

VOL

mA

V

CE1 = VIH or CE2 = VIL

I^OH= –2.0mA

—

Output high voltage

Output low voltage

2.4

—

IOL = 2.0mA

—

V

1

VCC = 3.3V, Ta = 25°C

2

3

ICC2 = 30mA for 3.3V operation (VCC = 3.3V ± 0.3V)

ICC2 = 40mA for 3.3V operation (VCC = 3.3V ± 0.3V)

– 3 –

CXK5T8512TM/TN

I/O capacitance

Item

(Ta = 25°C, f = 1MHz)

Symbol Test conditions Min.

Typ.

—

Max. Unit

CIN

VIN = 0V

VI/O = 0V

—

pF

Input capacitance

I/O capacitance

8

CI/O

—

10

Note) This parameter is sampled and is not 100% tested.

AC Characteristics

• AC test conditions

(Ta = –25 to +85°C)

Conditions

• Test circuit

Item

V^CC= 2.7 to 3.6V

VIH = 2.4V

VCC = 3.3V ± 0.3V

VIH = 2.2V

TTL

Input pulse high level

Input pulse low level

Input rise time

V^IL= 0.6V

VIL = 0.4V

tr = 5ns

CL

tf = 5ns

Input fall time

tf = 5ns

1.4V

Input and output reference level

1.4V

CL ¹= 30pF, 1TTL

CL ¹= 100pF, 1TTL

-10LLX

Output load conditions

-12LLX

¹CL includes scope and jig capacitances.

– 4 –

CXK5T8512TM/TN

• Read cycle (WE = “H”)

VCC = 2.7 to 3.6V

-10LLX -12LLX

Min. Max. Min. Max.

VCC = 3.3V ± 0.3V

-10LLX -12LLX

Min. Max. Min. Max.

Item

Symbol

Unit

Read cycle time

100

—

100

50

120

—

120

60

ns

t

RC

85

—

10

—

85

40

—

100

—

100

50

Address access time

AA

Chip enable access time (CE1)

Chip enable access time (CE2)

Output enable to output valid

Output hold from address change

—

CO1

CO2

OE

—

10

—

10

—

OH

10

—

Chip enable to output in low Z

(CE1, CE2)

t

LZ1

LZ2

10

5

—

40

35

10

5

—

40

35

ns

10

5

—

35

30

10

5

—

40

35

t

Output enable to output in low Z (OE)

tOLZ

1

Chip disable to output in high Z

(CE1, CE2)

t

HZ1

HZ2

—

t

1

Output disable to output in high Z (OE)

tOHZ

¹tHZ1, tHZ2 and tOHZ are defined as the time required for outputs to turn to high impedance state and are not

referred to as output voltage levels.

• Write cycle

VCC = 2.7 to 3.6V

-10LLX -12LLX

Min. Max. Min. Max.

VCC = 3.3V ± 0.3V

-10LLX -12LLX

Min. Max. Min. Max.

Item

Symbol

Unit

120

100

50

0

—

40

—

40

ns

100

80

40

0

85

70

35

0

—

35

100

80

40

0

—

40

Write cycle time

t

WC

AW

CW

DW

DH

Address valid to end of write

Chip enable to end of write

Data to write time overlap

Data hold from write time

Write pulse width

70

0

70

0

60

0

70

0

WP

AS

Address setup time

5

Write recovery time (WE)

Write recovery time (CE1, CE2)

Output active from end of write

Write to output in high Z

2

WR

WR1

OW

WHZ

5

2

—

tWHZ is defined as the time required for outputs to turn to high impedance state and is not referred to as

output voltage level.

– 5 –

CXK5T8512TM/TN

Timing Waveform

• Read cycle (1) : CE1 = OE = VIL, CE2 = VIH, WE = VIH

tRC

Address

tAA

tOH

Previous data valid

Data valid

Data out

• Read cycle (2) : WE = VIH

tRC

Address

CE1

tAA

tCO1

tHZ

tHZ1

tLZ1

tCO2

tLZ2

CE2

tHZ2

OE

tOHZ

tOE

tOLZ

Data out

Data valid

High impedance

– 6 –

CXK5T8512TM/TN

• Write cycle (1) : WE control

tWC

tAW

Address

tWR

OE

tCW

CE1

CE2

(

1)

tAS

tWP

WE

tDW

tDH

Data in

Data valid

tWHZ

tOW

Data out

High impedance

(

2)

(

2)

• Write cycle (2) : CE1 control

tWC

Address

OE

tAW

tAS

tCW

( 3)

tWR1

CE1

CE2

tWP

WE

tDW

tDH

Data in

Data out

Data valid

High impedance

– 7 –

CXK5T8512TM/TN

• Write cycle (3) : CE2 control

tWC

tAW

Address

OE

tCW

CE1

CE2

tWR1

tAS

(

3)

tWP

WE

tDW

tDH

Data valid

Data in

Data out

High impedance

1

Write is executed when both CE1 and WE are at low and CE2 is at high simultaneously.

2

3

Do not apply the data input voltage of the opposite phase to the output while I/O pin is in output condition.

WR1 is tested from either the rising edge of CE1 or the falling edge of CE2, whichever comes earlier, until

the end of the write cycle.

t

– 8 –

CXK5T8512TM/TN

Data retention waveform

• Low supply voltage data retention waveform (1) (CE1 contol)

tCDRS

Data retention mode

tR

VCC

2.7V

VIH

VDR

CE1

CE1 ≥ VCC – 0.2V

GND

• Low supply voltage data retention waveform (2) (CE2 contol)

Data retention mode

VCC

2.7V

tCDRS

tR

CE2

VDR

VIL

CE2 ≤ 0.2V

GND

Data Retention Characteristics

(Ta = –25 to +85°C)

Item

Symbol

V^DR

Test conditions

Min.

2.0

—

0

Typ.

Max. Unit

1

—

3.6

12

6

V

Data retention voltage

–25 to +85°C

–25 to +70°C

+25°C

1

VCC = 3.0V

ICCDR1

—

µA

Data retention current

0.2

0.24

—

14

—

1

2

ICCDR2

tCDRS

tR

VCC = 2.0 to 3.6V

µA

ns

Chip disable to data retention mode

Data retention setup time

Recovery time

5

—

ms

1

CE1 ≥ Vcc – 0.2V, CE2 ≥ Vcc – 0.2V (CE1 control) or CE2 ≤ 0.2V (CE2 control)

2

Vcc = 3.3V, Ta = 25°C

– 9 –

CXK5T8512TM/TN

Package Outline

Unit: mm

CXK5T8512TM

32PIN TSOP (PLASTIC)

+ 0.2

1.07 – 0.1

8.0 ± 0.2

0.1

17

32

A

1

16

+ 0.08

0.2 – 0.03

M

0.08

0.5

0.1 ± 0.1

0° to 10°

DETAIL

PACKAGE STRUCTURE

NOTE :

“ ” Dimensions do not include mold protrusion.

A

PACKAGE MATERIAL

LEAD TREATMENT

LEAD MATERIAL

EPOXY RESIN

TSOP-32P-L01

SOLDER PLATING

42 ALLOY

0.3g

SONY CODE

EIAJ CODE

TSOP032-P-0820

JEDEC CODE

PACKAGE WEIGHT

CXK5T8512TN

32PIN TSOP (PLASTIC)

1.2 MAX

0.1

8.0 ± 0.1

32

17

A

1

16

0.5

0.2

M

+ 0.1

0.05 – 0.05

0.08

0° to 10°

DETAIL

A

NOTE: Dimension “ ” does not include mold protrusion.

PACKAGE STRUCTURE

PACKAGE MATERIAL

LEAD TREATMENT

LEAD MATERIAL

EPOXY RESIN

SOLDER PLATING

42 ALLOY

TSOP-32P-L02

SONY CODE

EIAJ CODE

TSOP032-P-0813.4-C

JEDEC CODE

PACKAGE MASS

0.2g

– 10 –


型号：	CXK5T8512TM
厂家：	SONY CORPORATION
描述：	65536-word X 8-bit High Speed CMOS Static RAM 65536字×8位高速CMOS静态RAM
文件：	总10页 (文件大小：218K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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