CXL1506M [SONY]
CMOS-CCD 1H/2H Delay Line for PAL; 对于PAL CMOS ， CCD 1H / 2H延时线
| 型号： | CXL1506M |
| 厂家： | 
SONY CORPORATION |
| 描述： | CMOS-CCD 1H/2H Delay Line for PAL |
| 文件： | 总12页 (文件大小：172K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CXL1506M/N
CMOS-CCD 1H/2H Delay Line for PAL
For the availability of this product, please contact the sales office.
Description
CXL1506M
16 pin SOP (Plastic)
CXL1506N
20 pin SSOP (Plastic)
The CXL1506M/N is a CMOS-CCD delay line
developed for video signal processing. Usage in
conjunction with an external low pass filter provides
1H and 2H delay signals simultaneously (For PAL
signals).
Features
• Single power supply (5V)
• Low power consumption
• Built-in peripheral circuits
• Built-in tripling PLL circuit
• For PAL signals
Blook Diagram
CXL1506N
CXL1506M
• 1 input and 2 outputs
(Outputs for both 1H and 2H delays)
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage
• Operating temperature Topr
• Storage temperature Tstg
• Allowable power dissipation
VDD
6
V
°C
°C
–10 to +60
–55 to +150
PD CXL1506M 400 mW
CXL1506N 300 mW
Recommended Operating Voltage (Ta = 25°C)
VDD
5 ± 0.25
V
Recommended Clock Conditions (Ta = 25°C)
• Input clock amplitude
• Input clock frequency
• Input clock waveform
VCLK 0.2 to 1.0Vp-p (0.4Vp-p Typ.)
fCLK
4.433619 MHz
sine wave
Input Signal Amplitude
VSIG 575 (Max.) mVp-p (at internal clamp condition)
PC
OUT
VCO
IN
PC
OUT
VCO
IN
VSS
20
NC
19
AB
18
VDD
17
VSS
14
NC
13
VDD
11
CLK
12
VSS
11
VSS
16
AB
15
VDD
14
VDD
9
CLK
10
16
15
13
12
PLL
PLL
Timing
Driver
Autobias circuit
Clamp circuit
Timing
Autobias circuit
Clamp circuit
Driver
CCD (1698bits)
847bits
CCD (1698bits)
847bits
1698bits
Bias
circuit
1698bits
Bias
circuit
Output circuit
S/H 1bit
Output circuit
Output circuit
S/H 1bit
Output circuit
S/H 1bit
S/H 1bit
1
2
3
4
5
6
7
8
9
10
1
2
3
4
5
6
7
8
OUT2
(2H)
VSS
(VCO OUT)
NC
IN
VG1
VG2
VSS
NC
VSS
OUT1
(1H)
OUT1
(1H)
IN
VG2
VSS
VSS
VG1
OUT2
(2H) (VCO OUT)
VSS
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E89X22C78-PS
CXL1506M/N
Pin Description (CXL1506M)
Pin No.
Symbol
I/O
I
Description
Signal input
(Non-inverted signal)
Gate bias 1 DC output
Gate bias 2 DC input
Impedance [Ω]
1
IN
> 10kΩ (at no clamp)
2
VG1
O
I
3(Note) VG2
1H signal output
(Inverted signal)
4
5
6
OUT1
O
—
O
40 to 500Ω
40 to 500Ω
VSS
GND
2H signal output
(Inverted signal)
OUT2
7
VSS (VCO OUT)
(O)
—
—
I
GND or VCO output (3fsc)
GND
8
VSS
9
VDD
Power supply (5V)
Clock input (fsc)
GND
10
11
12
13
14
15
16
CLK
VSS
> 10kΩ
—
O
I
PC OUT
VCO IN
VDD
Phase comparator output
VCO input
—
O
—
Power supply (5V)
Autobias DC output
GND
AB
600 to 200kΩ
VSS
Note) Description of VG2
Control of input signal clamp condition
0V … Sync tip clamp condition
5V … Center bias condition
The input signal is biased to approx. 2.1V by means of the IC internal resistance (approx. 10kΩ ).
In this mode the input signal is limited to the APL 50% and the maximum input signal amplitude is
at 200mVp-p.
– 2 –
CXL1506M/N
Pin Description (CXL1506N)
Pin No.
1
Symbol
I/O
—
Description
—
Impedance [Ω]
NC
IN
Signal input
2
3
I
> 10kΩ (at no clamp)
(Non-inverted signal)
Gate bias 1 DC output
Gate bias 2 DC input
VG1
O
I
4(Note) VG2
1H signal output
(Inverted signal)
5
6
7
OUT1
O
—
O
40 to 500Ω
40 to 500Ω
VSS
GND
2H signal output
(Inverted signal)
OUT2
8
NC
—
—
9
VSS (VCO OUT)
(O) GND or VCO output (3fsc)
10
11
12
13
14
15
16
17
18
19
20
VSS
—
—
I
GND
VDD
Power supply (5V)
Clock input (fsc)
—
CLK
NC
> 10kΩ
—
—
O
I
VSS
GND
PC OUT
VCO IN
VDD
Phase comparator output
VCO input
—
O
—
—
Power supply (5V)
Autobias DC output
—
AB
600 to 200kΩ
NC
VSS
GND
Note) Description of VG2
Control of input signal clamp condition
0V … Sync tip clamp condition
5V … Center bias condition
The input signal is biased to approx. 2.1V by means of the IC internal resistance (approx. 10kΩ ).
In this mode the input signal is limited to the APL 50% and the maximum input signal amplitude is
at 200mVp-p.
– 3 –
CXL1506M/N
Electrical Characteristics
(Ta = 25°C, VDD = 5V, fCLK = 4.433619MHz, VCLK = 400mVp-p sine wave)
See Electrical Characteristics Test Circuit.
SW conditions
Test conditions
Item
Symbol
Min.
Typ.
Max. Unit Note
(Note 1)
1
2 3 4
b a a
b a b
b b b
37
2
Supply current
IDD
17
–2
–2
mA
dB
2
3
—
a
27
0
GL1
GL2
fR1
a
200kHz
500mVp-p sine wave
Low frequency
gain
2
0
a
–0.7
–0.8
7
a a b –2.7
a b b –2.8
–1.7
–1.8
5
b →← c
200kHz →← 4.434MHz
150mVp-p sine wave
Frequency
response
dB
%
4
5
5
6
7
fR2
b →← c
DG1
DG2
DP1
DP2
SN1
SN2
CP1
CP2
b a c
b b c
b a c
b b c
b a d
b b d
b a a
b b a
—
—
—
—
52
52
—
—
d
d
d
d
e
e
e
e
Differential gain
Differential phase
S/N ratio
5 staircase wave
5 staircase wave
No signal input
No signal input
7
5
7
5
degree
dB
7
5
—
—
350
350
56
56
—
—
S/H pulse coupling
mVp-p
– 4 –
CXL1506M/N
– 5 –
CXL1506M/N
Notes)
1) By switching SW2, input condition turns out as follows.
SW2 condition
Input condition
Center bias condition (approx. 2.1V)
Approx. 2.1V bias is applied internally to the input signal
a
b
Sync tip and clamp conditions
2) This is the IC supply current value during clock and signal input.
3) GL is the output gain of pin OUT when a 500mVp-p, 200kHz sine wave is fed to pin IN.
pin OUT output voltage [mVp-p]
GL = 20 log
[dB]
500 [mVp-p]
4) Indicates the dissipation at 4.434MHz in relation to 200kHz. From the output voltage at pin OUT when a
150mVp-p, 200kHz sine wave is fed to pin IN, and from the output voltage at pin OUT when a 150mVp-p,
4.434MHz sine wave is fed to same, calculation is made according to the following formula.
pin OUT output voltage (4.434MHz) [mVp-p]
fR = 20 log
[dB]
pin OUT output voltage (200kHz) [mVp-p]
5) The differential gain (DG) and the differential phase (DP), when the 5-staircase wave in the following figure
is fed, are tested with a vector scope:
150mV
275mV
500mV
150mV
1H 64µs
– 6 –
CXL1506M/N
6) The noise level of the output signal at no-input signal is tested with a video noise meter in the Sub Carrier
Trap mode at BPF 100kHz to 5MHz. (Vn [Vrms])
The signal component is determined either by testing the output voltage (the same testing system as for
noise level) at the input of 350mVp-p, 200kHz, or by utilizing values from GL to calculate according to the
following formula. (Vs [Vp-p])
(Example of Vs calculation)
GL
Vs = 0.35 × 10 20
(Example of SN ratio calculation)
Vn (noise component) [Vrms]
SN = 20 log
[dB]
Vs (signal component) [Vp-p]
7) The internal clock component to the output signal during no-signal input and the leakage of that high
harmonic component are tested.
Test value [mVp-p]
fsc (4.433619MHz) sine wave
Clock
400mVp-p
(typ.)
– 7 –
CXL1506M/N
– 8 –
CXL1506M/N
Example of Representative Characteristics
Low frequency gain (1H) vs. Ambient temperature
Supply current vs. Ambient temperature
35
2
1
25
0
–1
–2
15
–20
0
20
40
60
80
–20
0
20
40
60
80
Ambient temperature [°C]
Ambient temperature [°C]
Low frequency gain (2H) vs. Ambient temperature
2
Frequency response (1H) vs. Ambient temperature
0
1
0
–1
–2
–3
–1
–2
–20
0
20
40
60
80
–20
0
20
40
60
80
Ambient temperature [°C]
Ambient temperature [°C]
Frequency response (2H) vs. Ambient temperature
Differential gain (1H) vs. Ambient temperature
10
0
8
6
4
2
0
–1
–2
–3
–20
0
20
40
60
80
–20
0
20
40
60
80
Ambient temperature [°C]
Ambient temperature [°C]
– 9 –
CXL1506M/N
Differential gain (2H) vs. Ambient temperature
10
Supply current vs. Supply voltage
35
25
15
8
6
4
2
0
–20
0
20
40
60
80
4.75
5
5.25
Ambient temperature [°C]
Supply voltage [V]
Low frequency gain (1H) vs. Supply voltage
Low frequency gain (2H) vs. Supply voltage
2
2
1
0
1
0
–1
–1
–2
–2
4.75
5
5.25
4.75
5
5.25
Supply voltage [V]
Supply voltage [V]
Frequency response (1H) vs. Supply voltage
0
Frequency response (2H) vs. Supply voltage
0
–1
–1
–2
–2
–3
4.75
–3
4.75
5
5.25
5
5.25
Supply voltage [V]
Supply voltage [V]
– 10 –
CXL1506M/N
Differential gain (1H) vs. Supply voltage
Differential gain (2H) vs. Supply voltage
10
8
10
8
6
6
4
4
2
2
0
0
4.75
5
5.25
4.75
5
5.25
Supply voltage [V]
Supply voltage [V]
Frequency response (1H)
2
0
–2
–4
–6
10K
100K
1M
10M
Frequency [Hz]
Frequency response (2H)
2
0
–2
–4
–6
10K
100K
1M
10M
Frequency [Hz]
Note) 1H and 2H shown in brackets indicate 1H and 2H outputs.
– 11 –
CXL1506M/N
Package Outline
Unit: mm
CXL1506M
16PIN SOP (PLASTIC)
+ 0.4
1.85 – 0.15
+ 0.4
9.9 – 0.1
16
9
0.15
+ 0.2
0.1 – 0.05
1
0.45 ± 0.1
8
+ 0.1
0.2 – 0.05
1.27
0.24
M
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
EPOXY RESIN
SONY CODE
SOP-16P-L01
SOLDER PLATING
COPPER ALLOY
0.2g
SOP016-P-0300
EIAJ CODE
JEDEC CODE
PACKAGE MASS
CXL1506N
20PIN SSOP (PLASTIC)
+ 0.2
1.25 – 0.1
6.5 ± 0.1
0.1
11
20
A
1
10
+ 0.05
0.15 – 0.02
0.65
+ 0.1
0.22 – 0.05
0.13
M
0.1 ± 0.1
0° to 10°
DETAIL
A
NOTE: Dimension “ ” does not include mold protrusion.
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
EPOXY RESIN
SOLDER / PALLADIUM
SONY CODE
EIAJ CODE
SSOP-20P-L01
PLATING
SSOP020-P-0044
LEAD MATERIAL
PACKAGE MASS
42/COPPER ALLOY
JEDEC CODE
0.1g
– 12 –
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