CXL5509P [SONY]
CMOS-CCD 1H/2H Delay Line for NTSC; CMOS - CCD 1H / 2H延时线的NTSC
| 型号： | CXL5509P |
| 厂家： | 
SONY CORPORATION |
| 描述： | CMOS-CCD 1H/2H Delay Line for NTSC |
| 文件： | 总12页 (文件大小：157K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CXL5509M/P
CMOS-CCD 1H/2H Delay Line for NTSC
Description
CXL5509M
16 pin SOP (Plastic)
CXL5509P
16 pin DIP (Plastic)
The CXL5509M/P is a CMOS-CCD delay line
developed for video signal processing. Usage in
conjunction with an external low-pass filter provide 1H
and 2H delay signals simultaneously (For NTSC
signals).
Features
• Single power supply (5V)
• Low power consumption 130mW (Typ.)
• Built-in peripheral circuits
• Built-in quadruple PLL circuit
• For NTSC signals
• 1 input and 2 outputs
(Outputs for both 1H and 2H delays)
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage
VDD
6
V
°C
• Operating temperature Topr
• Storage temperature Tstg
• Allowable power dissipation
PD
–10 to +60
–55 to +150 °C
Functions
• 906-bit (1H) and 1816-bit (2H) CCD register
• Clock driver
CXL5509M
CXL5509P
400
800
mW
mW
• Auto-bias circuit
• Sync tip clamp circuit
• Sample-and-hold circuit
• Quadruple PLL circuit
Recommended Operating Condition (Ta = 25°C)
Supply voltage 5 ± 5%
VDD
V
Structure
CMOS-CCD
Recommended Clock Conditions (Ta = 25°C)
• Input clock amplitude VCLK 0.3 to 1.0
Vp-p
(0.5Vp-p typ.)
3.579545 MHz
• Input clock waveform sine wave
• Clock frequency
fCLK
Input Signal Amplitude
VSIG 571mVp-p (Max.) (at internal clamp condition)
Blook Diagram and Pin Configuration (Top View)
16
15
14
13
12
11
10
9
Auto-bias circuit
PLL
Driver
Timing circuit
CCD
(1816bit)
Clamp circuit
906bit
1816bit
Bias circuit
Output circuit
(S/H 1bit)
Output circuit
(S/H 1bit)
2
3
4
5
6
7
8
1
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E91401B7X-PS
CXL5509M/P
Pin Description
Pin No.
1
Symbol
Description
Signal input
(Non-inverted signal)
Gate bias 1 DC output
Gate bias 2 DC input
Impedance
I/O
I
IN
> 10kΩ (at no clamp)
VG1
VG2
O
I
2
3
1H signal output
(Inverted signal)
OUT1
VSS
O
—
O
4
5
6
40 to 500Ω
40 to 500Ω
GND
2H signal output
(Inverted signal)
OUT2
VSS (VCO OUT) (O)
7
GND or VCO output (4fsc)
GND
VSS
—
—
I
8
VDD
9
Power supply (5V)
Clock input (fsc)
GND
CLK
VSS
10
11
12
13
14
15
16
> 10kΩ
—
O
I
PC OUT
VCO IN
VDD
Phase comparator output
VCO input
—
O
—
Power supply (5V)
Autobias DC output
GND
AB
600 to 200kΩ
VSS
Description of Pin 3 (VG2)
Control of input signal clamp condition
0V ........ Sync tip clamp condition
5V ........ Center bias condition
The input signal is biased to approx. 2.1V by means of the IC internal resistance (approx. 10kΩ).
In this mode, the input signal is limited to APL 50% and the maximum input signal amplitude is at
200mVp-p.
– 2 –
CXL5509M/P
Electrical Characteristics
(Ta = 25°C, VDD = 5V, fCLK = 3.579545MHz, VCLK = 500mVp-p, sine wave)
See "Electrical Characteristics Test Circuit"
SW conditions
Test conditions
(Note 1)
Item
Symbol
Note
2
Min. Typ. Max. Unit
1
a
2
b
b
b
a
a
b
b
b
b
b
b
b
b
3
a
a
b
a
b
a
b
a
b
a
b
a
b
4
a
b
b
b
b
c
c
c
c
d
d
a
a
26
0
36
2
mA
dB
Supply current
IDD
—
16
–2
–2
200kHz,
500mVp-p,
sine wave
GL1
GL2
fR1
a
Low frequency
gain
3
a
0
2
200kHz ←→ 3.58MHz,
150mVp-p,
sine wave
b
b
←→
←→
d
c
c
–2.0 –1.0
–2.0 –1.0
0
Frequency
response
dB
%
4
5
5
6
7
0
fR2
3
3
5
DG1
DG2
DP1
DP2
SN1
SN2
CP1
CP2
—
—
—
—
52
52
—
—
Differential
gain
5-staircase wave
5-staircase wave
d
5
d
3
5
Differential
phase
degree
dB
d
3
5
e
56
56
—
—
—
—
350
350
50% white
video signal
S/N ratio
e
f
mVp-p
S/H pulse coupling
No signal input
f
– 3 –
CXL5509M/P
p 0 0 0 1
p 0 0 0 1
– 4 –
CXL5509M/P
– 5 –
CXL5509M/P
Notes
(1) By switching SW2, input condition turns out as follows.
SW2 condition
Input condition
Center bias condition (approx. 2.1V)
Approx. 2.1V bias is applied internally to the input signal
a
b
Sync tip clamp conditions
(2) This is the IC supply current value during clock and signal input.
(3) GL is the output gain of OUT pin when a 500mVp-p, 200kHz sine wave is fed to IN pin.
OUT pin output voltage [mVp-p]
GL = 20 log
[dB]
500 [mVp-p]
(4) Indicates the dissipation at 3.58MHz in relation to 200kHz.
From the output voltage at OUT pin when a 150mVp-p, 200kHz sine wave is fed to IN pin, and from the
output voltage at OUT pin when a 150mVp-p, 3.58MHz sine wave is fed to same, calculation is made
according to the following formula.
OUT pin otuput voltage (3.58MHz) [mVp-p]
fR = 20 log
[dB]
OUT pin output voltage (200kHz) [mVp-p]
(5) The differential gain (DG) and the differential phase (DP), when the 5-staircase wave in the following
figure is fed, are tested with a vector scope:
143mV
285.5mV
500mV
143mV
1H 63.56µs
(6) S/N ratio during 50% white video signal input shown in figure below is tested at video noise meter, in BPF
100kHz to 4MHz, Sub Carrier Trap mode.
178mV
321mV
143mV
1H 63.56µs
– 6 –
CXL5509M/P
(7) The internal clock component to the output signal during no-signal input and the leakage of that high
harmonic component are tested.
Test value (mVp-p)
Clock
fsc (3.579545MHz) sine wave
500mVp-p
(Typ.)
– 7 –
CXL5509M/P
Example of Representative Characteristics
Supply current vs. Supply voltage
36
26
16
4.75
5.0
5.25
Supply voltage [V]
Low frequency gain (1H) vs. Supply voltage
Low frequency gain (2H) vs. Supply voltage
2
2
1
0
1
0
–1
–2
–1
–2
4.75
5.0
5.25
4.75
5.0
5.25
Supply voltage [V]
Supply voltage [V]
Frequency response (1H) vs. Supply voltage
Frequency response (2H) vs. Supply voltage
1
1
0
–1
–2
–3
0
–1
–2
–3
4.75
5.0
5.25
4.75
5.0
5.25
Supply voltage [V]
Supply voltage [V]
– 8 –
CXL5509M/P
Differential gain (1H) vs. Supply voltage
Differential gain (2H) vs. Supply voltage
5
4
3
2
1
5
4
3
2
1
4.75
5.0
5.25
4.75
5.0
5.25
Supply voltage [V]
Supply voltage [V]
Supply current vs. Ambient temperature
36
26
16
–20
0
20
40
60
80
Ambient temperature [°C]
Low frequency gain (1H) vs. Ambient temperature
Low frequency gain (2H) vs. Ambient temperature
2
2
1
0
1
0
–1
–2
–1
–2
–20
0
20
40
60
80
–20
0
20
40
60
80
Ambient temperature [°C]
Ambient temperature [°C]
– 9 –
CXL5509M/P
Frequency response (1H) vs. Ambient temperature
Frequency response (2H) vs. Ambient temperature
1
1
0
–1
–2
–3
0
–1
–2
–3
–20
0
20
40
60
80
–20
0
20
40
60
80
Ambient temperature [°C]
Ambient temperature [°C]
Differential gain (1H) vs. Ambient temperature
Differential gain (2H) vs. Ambient temperature
8
8
6
4
2
0
6
4
2
0
–20
0
20
40
60
80
–20
0
20
40
60
80
Ambient temperature [°C]
Ambient temperature [°C]
– 10 –
CXL5509M/P
Frequency responses (1H)
2
0
–2
–4
–6
10k
100k
1M
10M
Frequency [Hz]
Frequency responses (2H)
2
0
–2
–4
–6
10k
100k
1M
10M
Frequency [Hz]
Note) 1H means 1H output; 2H means 2H output.
– 11 –
CXL5509M/P
Package Outline
CXL5509M
Unit: mm
16PIN SOP (PLASTIC)
+ 0.4
1.85 – 0.15
+ 0.4
9.9 – 0.1
16
9
0.15
+ 0.2
0.1 – 0.05
1
8
+ 0.1
0.2 – 0.05
0.45 ± 0.1
1.27
0.24
M
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
EPOXY RESIN
SONY CODE
SOP-16P-L01
SOLDER PLATING
COPPER ALLOY
0.2g
SOP016-P-0300
EIAJ CODE
JEDEC CODE
PACKAGE MASS
CXL5509P
16PIN DIP (PLASTIC)
+ 0.4
19.2 – 0.1
16
1
9
0° to 15°
8
2.54
Two kinds of package surface:
1.All mat surface type.
2.All mirror surface type.
0.5 ± 0.1
1.2 ± 0.15
PACKAGE STRUCTURE
EPOXY RESIN
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
SOLDER PLATING
COPPER ALLOY
1.0 g
SONY CODE
EIAJ CODE
DIP-16P-01
DIP016-P-0300
Similar to MO-001-AE
PACKAGE MASS
JEDEC CODE
– 12 –
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