CXP836P61Q-1-XXX [SONY]
Microcontroller, 8-Bit, OTPROM, SPC700 CPU, 10MHz, CMOS, PQFP80, 14 X 14 MM, 0.65 MM PITCH, PLASTIC, QFP-80;
| 型号： | CXP836P61Q-1-XXX |
| 厂家： | 
SONY CORPORATION |
| 描述： | Microcontroller, 8-Bit, OTPROM, SPC700 CPU, 10MHz, CMOS, PQFP80, 14 X 14 MM, 0.65 MM PITCH, PLASTIC, QFP-80 可编程只读存储器 时钟 PC 驱动 CD 微控制器 外围集成电路 |
| 文件： | 总31页 (文件大小：434K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CXP836P60
CXP836P61
CMOS 8-bit Single Chip Microcomputer
Description
CXP836P60
80 pin QFP (Plastic) 80 pin LQFP (Plastic)
The CXP836P60/836P61 is a CMOS 8-bit single
chip microcomputer integrating on a single chip an
A/D converter, serial interface, timer/counter, time-
base timer, sub timer/counter, LCD controller/driver
and remote control reception circuit besides the basic
configurations of 8-bit CPU, PROM, RAM, and I/O
port.
The CXP836P60/836P61 also provides a sleep/stop
function that enables lower power consumption.
The CXP836P60 and CXP836P61 are the PROM-
incorporated version of the CXP83508/83512/83516/
83620/83624 and CXP83509/83513/83517/83621/83625
with built-in mask ROM, and they are able to write
directly into the program. Thus, it is most suitable for
evaluation use during system development and for
small-quantity production.
CXP836P61
80 pin QFP (Plastic)
Features
• Wide-range instruction system (213 instructions) to
cover various types of data.
— 16-bit arithmetic/multiplication and division/boolean bit operation instructions
• Minimum instruction cycle
400ns at 10MHz operation (4.5 to 5.5V)
1µs at 4MHz operation (2.7 to 5.5V)
122µs at 32kHz operation (2.7 to 5.5V)
• Incorporated PROM capacity 60K bytes
• Incorporated RAM capacity
• Peripheral functions
— A/D converter
736 bytes (includes LCD display data area and serial interface RAM)
8-bit, 8-channel, successive approximation method
(Conversion time of 12.4µs/10MHz)
Incorporated buffer RAM
— Serial interface
(Auto transfer for 1 to 32 bytes), 1 channel
8-bit clock synchronized type (MSB/LSB first selectable), 1 channel
8-bit timer, 8-bit timer/counter, 19-bit time-base timer,
Sub timer/counter
— Timer
— LCD controller/driver
Maximum 128 segment display possible (during 1/4 duty)
4 common output, 32 segment output
Display method static, 1/2, 1/3, 1/4 duty
Bias method 1/2, 1/3 bias
— Remote control reception circuit
• Interruption
• Standby mode
8-bit pulse measuring counter, 6-stage FIFO
14 factors, 14 vectors, multi-interruption possible
Sleep/stop
• Package
80-pin plastic QFP/LQFP
Structure
Silicon gate CMOS IC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E98342C1Y-PS
CXP836P60, CXP836P61
P O R T B
P O R T D
P O R
P O R T I
P O R T A
P O R
P O R T F
P O R T
V p p
V s s
D D V
R S T
X T A L
E X T A L
T X
T E X
I N T 4
I N T 3
I N T 2
I N T 1
I N T 0
I N T E R R U P T C O N T R O L L E R
– 2 –
CXP836P60, CXP836P61
Pin Assignment (Top View) CXP836P60 (QFP package)
80 79 78 77 76 75 74 73 72
71 70 69 68 67
66 65
1
64
63
62
61
60
PD6/SEG22
PD5/SEG21
PD4/SEG20
PD3/SEG19
PD2/SEG18
PD1/SEG17
PD0/SEG16
SEG15
PE3/INT3
2
PE4/RMC
3
PE5/TO
4
PE6/ADJ
5
PB0
6
PB1/CS0
PB2/SCK0
PB3/SI0
PB4/SO0
PB5/SCK1
PB6/SI1
PB7/SO1
PC0
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
7
8
SEG14
9
SEG13
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
SEG12
SEG11
SEG10
SEG9
PC1
SEG8
PC2
SEG7
PC3
SEG6
PC4
SEG5
PC5
SEG4
PC6
SEG3
PC7
SEG2
PH0/INT4
PA0/AN0
PA1/AN1
PA2/AN2
SEG1
SEG0
COM3
35
36 37 38
40
39
25 26 27 28 29 30
31
32 33
34
Note) Do not make any connections to Vpp (Pin 75).
– 3 –
CXP836P60, CXP836P61
Pin Assignment (Top View) CXP836P60 (LQFP package)
80 79 78 77 76 75 74 73 72 71
70 69 68 67
66 65 64 63 62 61
PD4/SEG20
PD3/SEG19
PD2/SEG18
PD1/SEG17
PD0/SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
1
2
PE5/TO
PE6/ADJ
PB0
3
4
PB1/CS0
PB2/SCK0
PB3/SI0
PB4/SO0
PB5/SCK1
PB6/SI1
PB7/SO1
PC0
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
PC1
SEG8
PC2
SEG7
PC3
SEG6
PC4
SEG5
PC5
SEG4
PC6
SEG3
PC7
SEG2
PH0/INT4
PA0/AN0
SEG1
35
36 37 38
40
39
21 22 23 24 25 26 27 28 29 30
31
32 33
34
Note) Do not make any connections to Vpp (Pin 73).
– 4 –
CXP836P60, CXP836P61
Pin Assignment (Top View) CXP836P61 (QFP package)
80 79 78 77 76 75 74 73 72 71
70 69 68 67
66 65 64 63 62 61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
PD4/SEG20
PD3/SEG19
PD2/SEG18
PD1/SEG17
PD0/SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
1
2
PE5/TO
PE6/ADJ
PB0
3
4
PB1/CS0
PB2/SCK0
PB3/SI0
PB4/SO0
PB5/SCK1
PB6/SI1
PB7/SO1
PC0
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
PC1
SEG8
PC2
SEG7
PC3
SEG6
PC4
SEG5
PC5
SEG4
PC6
SEG3
PC7
SEG2
PH0/INT4
PA0/AN0
SEG1
35
36 37 38
40
39
21 22 23 24 25 26 27 28 29 30
31
32 33
34
Note) Do not make any connections to Vpp (Pin 73).
– 5 –
CXP836P60, CXP836P61
Pin Description
Symbol
I/O
Functions
(Port A)
8-bit I/O port. I/O can
be set in a bit unit.
Standby release input
can be set in a bit unit.
Incorporation of pull-up
resistor can be set
through the program in
a bit unit.
PA0/AN0
to
PA7/AN7
Analog inputs to A/D converter.
(8 pins)
I/O/Analog input
(8 pins)
I/O
PB0
Chip select input for serial interface (CH0).
Serial clock I/O (CH0).
I/O/Input
I/O/I/O
PB1/CS0
PB2/SCK0
PB3/SI0
PB4/SO0
PB5/SCK1
PB6/SI1
PB7/SO1
(Port B)
8-bit I/O port. I/O can
be set in a bit unit.
Incorporation of pull-up
resistor can be set
through the program in
a bit unit.
Serial data input (CH0).
I/O/Input
I/O/Output
I/O/I/O
Serial data output (CH0).
Serial clock I/O (CH1).
(8 pins)
Serial data input (CH1).
I/O/Input
I/O/Output
Serial data output (CH1).
(Port C)
8-bit I/O port. I/O can be set in a bit unit. Capable of driving 12mA sink
PC0 to PC7
I/O
current. Incorporation of pull-up resistor can be set through the program
in a bit unit.
(8 pins)
Input/Input/Input
Input/Input
External event inputs for 8-bit timer/counter.
PE0/INT0/EC
PE1/INT1
PE2/INT2
PE3/INT3
PE4/RMC
PE5/TO
External interruption request inputs.
(4 pins)
(Port E)
Input/Input
7-bit port. Lower 5 bits
are for inputs; upper 2
bits are for outputs.
(7 pins)
Input/Input
Input/Input
Remote control reception circuit input.
Output/Output
Output/Output
Output for 8-bit timer/counter rectangular wave.
Output for TEX oscillation frequency division.
PE6/ADJ
(Port H)
1-bit I/O port.
Incorporation of pull-up External interruption request input.
I/O/Input
PH0/INT4
resistor can be set
through the program.
(1 pin)
(1 pin)
(Port I)
2-bit input port.
(2 pins)
Crystal connectors for sub timer/counter clock
oscillation. For usage as event counter, input to
TEX, and leave TX open.
Input
PI0/TX
Input/Input
PI1/TEX
– 6 –
CXP836P60, CXP836P61
Symbol
I/O
Functions
PD0/SEG16
to
PD7/SEG23
(Port D)
8-bit output port.
(8 pins)
Output/Output
LCD segment signal outputs.
(16 pins)
(Port F)
8-bit output port.
(8 pins)
PF0/SEG24
to
PF7/SEG31
Output/Output
Output
Output
SEG0 to SEG15
COM0 to COM3
VLC1 to VLC3
LCD segment signal output. (16 pins)
LCD common signal output. (4 pins)
LCD bias power supply. (3 pins)
Control pin to cut off the current flowing to external LCD bias resistor
during standby.
Output
Input
VL
EXTAL
XTAL
RST
Crystal connectors for system clock oscillation. When the clock is supplied
externally, input to EXTAL; opposite phase clock should be input to XTAL.
Input
Low-level active system reset.
Positive power supply pin for writing of built-in PROM.
Do not make any connections under normal operation.
Vpp
VDD
Positive power supply.
GND.
VSS
– 7 –
CXP836P60, CXP836P61
I/O Circuit Format for Pins
Pin
After a reset
Circuit format
Port A
Pull-up resistor
"0" after a reset
Port A data
Port A direction
"0" after a reset
Internal data bus
Input protection
circuit
PA0/AN0
to
PA7/AN7
IP
Hi-Z
RD (Port A)
Port A function select
Edge detection
circuit
"0" after a reset
Standby release
Input multiplexer
A/D converter
Pull-up transistor
8 pins
approx. 100kΩ (VDD = 4.5 to 5.5V)
approx. 150kΩ (VDD = 2.7 to 3.3V)
Port B
Pull-up resistor
"0" after a reset
Port B data
PB0
Hi-Z
Port B direction
"0" after a reset
Internal data bus
IP
RD (Port B)
Pull-up transistor
approx. 100kΩ (VDD = 4.5 to 5.5V)
approx. 150kΩ (VDD = 2.7 to 3.3V)
1 pin
Port B
Pull-up resistor
"0" after a reset
Port B data
PB1/CS0
PB3/SI0
PB6/SI1
Hi-Z
Port B direction
"0" after a reset
IP
Schmitt input
Internal data bus
RD (Port B)
Pull-up transistor
approx. 100kΩ (VDD = 4.5 to 5.5V)
approx. 150kΩ (VDD = 2.7 to 3.3V)
CS0
SI0
SI1
3 pins
– 8 –
CXP836P60, CXP836P61
Pin
After a reset
Circuit format
Port B
Pull-up resistor
"0" after a reset
Output buffer capability
"0" after a reset
SCK out
Serial clock output ebable
PB2/SCK0
PB5/SCK1
Port B function select
"0" after a reset
Hi-Z
Port B data
IP
Port B direction
"0" after a reset
Schmitt input
Internal
data bus
RD (Port B)
SCK in
Pull-up transistor
approx. 100kΩ (VDD = 4.5 to 5.5V)
approx. 150kΩ (VDD = 2.7 to 3.3V)
2 pins
Port B
Pull-up resistor
"0" after a reset
Output buffer capability
"0" after a reset
SO
Serial data output ebable
PB4/SO0
PB7/SO1
Port B function select
"0" after a reset
Hi-Z
Port B data
IP
Port B direction
"0" after a reset
Internal
data bus
RD (Port B)
Pull-up transistor
2 pins
approx. 100kΩ (VDD = 4.5 to 5.5V)
approx. 150kΩ (VDD = 2.7 to 3.3V)
Port C
2
Pull-up resistor
"0" after a reset
Port C data
1
PC0 to PC7
Port C direction
"0" after a reset
Hi-Z
IP
Internal data bus
RD (Port C)
1 High current drive
12mA (VDD = 4.5 to 5.5V)
4.5mA (VDD = 2.7 to 3.3V)
2 Pull-up transistor
approx. 100kΩ (VDD = 4.5 to 5.5V)
approx. 150kΩ (VDD = 2.7 to 3.3V)
8 pins
– 9 –
CXP836P60, CXP836P61
Pin
After a reset
Circuit format
Port E
INT0/EC
INT1
INT2
INT3
RMC
PE0/INT0/EC
PE1/INT1
PE2/INT2
PE3/INT3
PE4/RMC
Schmitt input
IP
Hi-Z
Internal data bus
RD (Port E)
5 pins
Port E
TO
Port E function select
"0" after a reset
PE5/TO
1 pin
Port E data
High level
"1" after a reset
Internal data bus
RD (Port E)
Port E
Internal reset signal
2
00
MPX
Port E data
"1" after a reset
High level
High level
at ON
1
01
10
11
ADJ32K
ADJ16K
ADJ2K
PE6/ADJ
resistance
of pull-up
transistor
during a
reset.
Port E function select (upper)
Port E function select (lower)
"00" after a reset
1 ADJ signals are frequency driver
outputs for TEX oscillation frequency
adjustment.
ADJ2K provides usage as buzzer output.
2 Pull-up transistor
Internal data bus
RD (Port E)
approx. 150kΩ (VDD = 4.5 to 5.5V)
approx. 200kΩ (VDD = 2.7 to 3.3V)
1 pin
Port H
Pull-up resistor
"0" after a reset
Port H data
PH0/INT4
Hi-Z
Port H direction
"0" after a reset
IP
Schmitt input
Internal data bus
RD (Port H)
Pull-up transistor
approx. 100kΩ (VDD = 4.5 to 5.5V)
approx. 150kΩ (VDD = 2.7 to 3.3V)
1 pin
INT4
– 10 –
CXP836P60, CXP836P61
Pin
After a reset
Circuit format
Port I
TEX oscillation control circuit
"1" after a reset
Internal data bus
RD (Port I)
Internal data bus
PI0/TX
PI1/TEX
Oscillation
halted port
input
RD (Port I)
Schmitt input
IP
IP
PI1/TEX
Clock input
2 pins
PI0/TX
Port D
Port F
Port D, F data
PD0/SEG16
to
PD7/SEG23
PF0/SEG24
to
Segment
Output
(VDD level)
Port/segment output select
"0" after a reset
PF7/SEG31
Segment
driver
Segment data
16 pins
Segment
Common
VCH
VCL
SEG0 to SEG15
16 pins
VDD level
VDD
VLC1
VLC2
VLC3
COM0 to COM3
VDD level
4 pins
– 11 –
CXP836P60, CXP836P61
Pin
After a reset
Circuit format
VL
LCD control
(DSP bit)
Hi-Z
"0" after a reset
1 pin
• Diagram shows circuit
composition during
oscillation.
EXTAL
XTAL
EXTAL
XTAL
IP
IP
• Feedback resistor is
removed during stop.
XTAL becomes high
level.
Oscillation
2 pins
Pull-up resistor
RST
1 pin
Low level
(during a reset)
Mask option
OP
IP
Schmitt input
– 12 –
CXP836P60, CXP836P61
Absolute Maximum Ratings
(Vss = 0V)
Item
Symbol
Rating
Unit
V
Remarks
VDD
–0.3 to +7.0
–0.3 to +13.0
Supply voltage
Vpp
V
PROM incorporated version fixed
VLC1, VLC2,
VLC3
1
–0.3 to +7.0
V
LCD bias voltage
1
1
VIN
–0.3 to +7.0
–0.3 to +7.0
–5
V
V
Input voltage
VOUT
IOH
Output voltage
mA Output per pin
High level output current
High level total output current
ΣIOH
–50
mA Total for all output pins
Value per pin, excluding high current
output pins
IOL
15
mA
Low level output current
2
IOLC
ΣIOL
Topr
Tstg
20
100
mA Value per pin for high current output pins
mA Total for all output pins
°C
Low level total output current
Operating temperature
Storage temperature
–20 to +75
–55 to +150
600
°C
mW QFP-80P-L01
mW LQFP-80P-L01
mW QFP-80P-L03
PD
380
Allowable power dissipation
380
1
VIN and VOUT must not exceed VDD + 0.3V.
2
The high current drive transistor is the N-ch transistor of Port C (PC).
Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should
be conducted under the recommended operating conditions. Exceeding these conditions may adversely
affect the reliability of the LSI.
– 13 –
CXP836P60, CXP836P61
Recommended Operating Conditions
(Vss = 0V)
Item
Symbol
Min.
4.5
Max.
5.5
Unit
V
Remarks
Guaranteed operation range
during 1/2 and 1/4 frequency
dividing mode
fc = 10MHz or less
fc = 4MHz or less
2.7
5.5
Guaranteed operation range during 1/16
frequency dividing mode or sleep mode
Supply voltage
VDD
2.7
5.5
2.7
2.5
5.5
5.5
Guaranteed operation range with TEX clock
Guaranteed data hold range during stop
VLC1
VLC2
VLC3
VIH
4
LCD bias voltage
Vss
VDD
V
LCD power supply range
1
0.7VDD
0.8VDD
VDD
VDD
V
V
High level
input voltage
2
VIHS
VIHEX
VIL
Hysteresis input
3
5
VDD – 0.4 VDD + 0.3
V
EXTAL , TEX
1
0
0
0.3VDD
0.2VDD
0.4
V
Low level
input voltage
2
VILS
VILEX
Topr
V
Hysteresis input
3
5
–0.3
–20
V
EXTAL , TEX
Operating temperature
+75
°C
1
Value for each pin of normal input ports (PA, PB0, PB4, PB7, PC and PI).
2
3
4
5
Value of the following pins; RST, CS0, SI0, SI1, SCK0, SCK1, EC/INT0, INT1, INT2, INT3, INT4 and RMC.
Specifies only during external clock input.
Optimal values are determined by LCD used.
Specifies only during external event count input.
– 14 –
CXP836P60, CXP836P61
Electrical Characteristics
DC Characteristics (VDD = 4.5 to 5.5V)
(Ta = –20 to +75°C, Vss = 0V)
Item
Symbol
Pins
Conditions
VDD = 4.5V, IOH = –1.0mA
VDD = 4.5V, IOH = –2.4mA
VDD = 4.5V, IOH = –0.5mA
VDD = 4.5V, IOH = –1.2mA
VDD = 4.5V, IOL = 1.8mA
VDD = 4.5V, IOL = 3.6mA
VDD = 4.5V, IOL = 12.0mA
VDD = 5.5V, VIH = 5.5V
VDD = 5.5V, VIL = 0.4V
VDD = 5.5V, VIH = 5.5V
Min.
4.0
3.5
4.0
3.5
Typ. Max. Unit
V
V
V
V
SCK0 1, SO0
SCK1 1, SO1
1
1
High level
output voltage
VOH
PA, PB, PC,
2
PD , PE5,
PE6,
2
0.4
0.6
1.5
40
V
V
PF , PH0,
Low level
output voltage
VL (VOL only)
VOL
V
PC
0.5
–0.5
0.1
V
IIHE
IILE
IIHT
EXTAL
TEX
–40
10
µA
µA
µA
–0.1
–1.5
–10
Input current IILT
VDD = 5.5V
VIL = 0.4V
3
–400 µA
RST
IILR
IIL
–45
µA
µA
4
PA to PC ,
–2.78
VDD = 4.5V, VIH = 4.0V
PE0 to PE4,
IIH
4
PH , PI,
VDD = 5.5V
VI = 0, 5.5V
I/O leakage
IIZ
3
±10
5
µA
RST
current
Common
output
impedance
COM0 to
COM3
3
5
kΩ
RCOM
VDD = 5V
VLC1 = 3.75V
VLC2 = 2.5V
VLC3 = 1.25V
SEG0 to
SEG15,
SEG16 to
Segment
output
impedance
15
45
kΩ
RSEG
2
SEG31
High-speed mode operation
(1/2 frequency dividing clock)
IDD1
mA
14
VDD = 5.5V, 10MHz crystal oscillation
(C1 = C2 = 15pF)
Sleep mode
Supply
current
VDD
5
2.8
9
mA
µA
IDDS1
VDD = 5.5V, 10MHz crystal oscillation
(C1 = C2 = 15pF)
Stop mode
10
IDDS3
VDD = 5.5V, 10MHz and termination
of TEX oscillation
– 15 –
CXP836P60, CXP836P61
Item
Symbol
Pins
Conditions
Clock 1MHz
0V for all pins excluding
measured pins
Min.
Typ.
10
Max.
20
Unit
pF
PA to PC,
PE0 to PE4, PH,
PI, EXTAL, RST
Input capacity CIN
1
Specifies when Port B output buffer capability switching register (BUFB: 01F4h) selects the buffer capability
to high.
2
3
4
5
Common pins of PD0/SEG16 to PD7/SEG23, PF0/SEG24 to PF7/SEG31, PD and PF is the case when the
common pin is selected as port; SEG16 to SEG31 is when the common pin is selected as segment output.
RST specifies the input current when pull-up resistor has been selected; leakage current when no resistor
has been selected.
Pins PA to PC, and PH0 specifies the input current when pull-up resistor has been selected; leakage
current when no resistor has been selected.
When all output pins are left open.
– 16 –
CXP836P60, CXP836P61
Electrical Characteristics
DC Characteristics (VDD = 2.7 to 3.3V)
(Ta = –20 to +75°C, Vss = 0V)
Item
Symbol
Pins
Conditions
Min.
2.5
2.1
2.5
2.1
Typ. Max. Unit
V
V
V
V
VDD = 2.7V, IOH = –0.24mA
VDD = 2.7V, IOH = –0.9mA
VDD = 2.7V, IOH = –0.12mA
VDD = 2.7V, IOH = –0.45mA
VDD = 2.7V, IOL = 1.0mA
VDD = 2.7V, IOL = 1.4mA
VDD = 2.7V, IOL = 4.5mA
VDD = 3.3V, VIH = 3.3V
VDD = 3.3V, VIL = 0.3V
SCK0 1, SO0
SCK1 1, SO1
1
1
High level
output voltage
VOH
PA, PB, PC,
2
PD , PE5,
PE6,
2
0.25
0.4
0.9
20
V
V
PF , PH0,
Low level
output voltage
VL (VOL only)
VOL
PC
V
IIHE
IILE
IIHT
IILT
IILR
IIL
0.3
–0.3
0.1
V
EXTAL
TEX
–20
10
µA
µA
µA
VDD = 3.3V, VIH = 3.3V
–0.1
–0.9
–10
Input current
VDD = 3.3V
VIL = 0.3V
3
RST
–200 µA
–20
µA
µA
4
PA to PC ,
VDD = 2.7V, VIH = 2.4V
IIH
PE0 to PE4,
0.9
4
PH , PI,
VDD = 3.3V
VI = 0, 3.3V
I/O leakage
current
3
RST
±10
7.5
µA
IIZ
Common
output
impedance
COM0 to
COM3
4.5
10
kΩ
RCOM
VDD = 3V
VLC1 = 2.25V
VLC2 = 1.5V
VLC3 = 0.75V
SEG0 to
SEG15,
SEG16 to
Segment
output
impedance
30
9
kΩ
RSEG
2
SEG31
High-speed mode operation
(1/2 frequency dividing clock)
IDD1
3
mA
VDD = 3.3V, 4MHz crystal oscillation
(C1 = C2 = 15pF)
VDD = 3.3V, TEX 6 crystal oscillation
(C1 = C2 = 47pF)
IDD2
34
0.65
16
100
2.5
30
µA
mA
µA
µA
Sleep mode
Supply
current
VDD
5
IDDS1
VDD = 3.3V, 4MHz crystal oscillation
(C1 = C2 = 15pF)
VDD = 3.3V, TEX 6 crystal oscillation
(C1 = C2 = 47pF)
IDDS2
Stop mode
IDDS3
10
VDD = 3.3V, 4MHz and termination of
TEX oscillation
– 17 –
CXP836P60, CXP836P61
Item
Symbol
Pins
Conditions
Clock 1MHz
0V for all pins excluding
measured pins
Min.
Typ.
10
Max.
20
Unit
pF
PA to PC,
PE0 to PE4, PH,
PI, EXTAL, RST
Input capacity CIN
1
Specifies when Port B output buffer capability switching register (BUFB: 01F4h) selects the buffer capability
to high.
2
3
4
Common pins of PD0/SEG16 to PD7/SEG23, PF0/SEG24 to PF7/SEG31, PD and PF is the case when the
common pin is selected as port; SEG16 to SEG31 is when the common pin is selected as segment output.
RST specifies the input current when pull-up resistor has been selected; leakage current when no resistor
has been selected.
Pins PA to PC, and PH0 specifies the input current when pull-up resistor has been selected; leakage
current when no resistor has been selected.
5
6
When all output pins are left open.
The value when 32.768kHz oscillator is connected to TEX.
– 18 –
CXP836P60, CXP836P61
AC Characteristics
(1) Clock timing
(Ta = –20 to +75°C, VDD = 2.7 to 5.5V, Vss = 0V)
Item
Symbol
Pin
Conditions
Min.
1
Typ. Max. Unit
10
V
DD = 4.5 to 5.5V
XTAL
EXTAL
MHz
5
Fig. 1, Fig. 2
System clock frequency
fC
1
37.5
77.5
V
DD = 4.5 to 5.5V
Fig. 1, Fig. 2
System clock input pulse
width
t
t
XL,
XH
ns
EXTAL
external clock drive
Fig. 1, Fig. 2
external clock drive
System clock input rise and
fall time
t
t
CR,
CF
ns
ns
200
20
EXTAL
EC
Event count input clock pulse
width
t
t
EH,
EL
1
tsys + 50
Fig. 3
Fig. 3
Event count input clock rise
and fall time
t
t
ER,
EF
ms
EC
VDD = 2.7 to 5.5V
Fig. 2 (32kHz clock
applied condition)
TEX
TX
kHz
32.768
System clock frequency
fC
Event count input clock input
pulse width
t
t
TL,
TH
µs
10
Fig. 3
Fig. 3
TEX
TEX
Event count input clock rise
and fall time
t
t
TR,
TF
ms
20
1
tsys indicates the three values below according to the upper two bits (CPU clock selection) of the clock
control register (CLC: 00FEh).
tsys [ns] = 2000/fc (upper two bits = “00”), 4000/fc (upper two bits = “01”), 16000/fc (upper two bits = “11”).
1/fc
VDD – 0.4V
EXTAL
0.4V
tCF
tXH
tXL
tCR
Fig. 1. Clock timing
Crystal oscillation
Ceramic oscillation
TEX clock applied condition
Crystal oscillation
External clock
EXTAL
XTAL
EXTAL
XTAL
TEX
TX
C1
C2
74HC04
C1
C2
Fig. 2. Clock applied conditions
0.8VDD
0.2VDD
TEX
EC
tEH
tTH
tEF
tTF
tEL
tTL
tER
tTR
Fig. 3. Event count clock timing
– 19 –
CXP836P60, CXP836P61
(2) Serial transfer (CH0)
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)
Item
Symbol
Pin
Conditions
Min.
Max.
Unit
ns
Chip select transfer mode
(SCK = output mode)
CS ↓ → SCK
delay time
t
t
t
DCSK
DCSKF
DCSO
SCK0
tsys + 200
Chip select transfer mode
(SCK = output mode)
CS ↑ → SCK
float delay time
ns
ns
ns
SCK0
SO0
tsys + 200
tsys + 200
tsys + 200
CS ↓ → SO
delay time
Chip select transfer mode
Chip select transfer mode
CS ↓ → SO
float delay time
t
t
DCSOF
WHCS
SO0
CS0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip select transfer mode
Input mode
tsys + 200
2tsys + 200
16000/fc
CS high level width
SCK cycle time
t
KCY
SCK0
SCK0
SI0
Output mode
Input mode
tsys + 100
8000/fc – 100
–tsys + 100
200
SCK high and low
level widths
t
t
KH
KL
Output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
SI input setup time
(for SCK ↑)
t
t
t
SIK
2tsys + 100
100
SI input hold time
(for SCK ↑)
KSI
SI0
2tsys + 200
100
SCK ↓ → SO
delay time
KSO
SO0
Note 1) tsys indicates the three values below according to the upper two bits (CPU clock selection) of the
clock control register (CLC: 00FEh).
tsys [ns] = 2000/fc (upper two bits = “00”), 4000/fc (upper two bits = “01”), 16000/fc (upper two bits = “11”)
Note 2) CS, SCK, SI and SO indicates CS0, SCK0, SI0 and SO0, respectively.
Note 3) The load condition for the SCK output mode, SO output delay time is 50pF + 1TTL.
Note 4) The value when Port B output buffer capability switching register (BUFB: 01F4h) selects buffer
capability to normal.
– 20 –
CXP836P60, CXP836P61
Serial transfer (CH0)
(Ta = –20 to +75°C, VDD = 2.7 to 3.3V, Vss = 0V)
Item
Symbol
Pin
Conditions
Min.
Max.
Unit
ns
CS ↓ → SCK
delay time
Chip select transfer mode
(SCK = output mode)
t
t
t
DCSK
DCSKF
DCSO
SCK0
tsys + 250
CS ↑ → SCK
float delay time
Chip select transfer mode
(SCK = output mode)
ns
ns
ns
SCK0
SO0
tsys + 200
tsys + 250
tsys + 200
CS ↓ → SO
delay time
Chip select transfer mode
Chip select transfer mode
CS ↓ → SO
float delay time
t
t
DCSOF SO0
Chip select transfer mode
Input mode
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WHCS
CS0
CS high level width
tsys + 200
2tsys + 200
16000/fc
SCK0
SCK cycle time
t
KCY
Output mode
Input mode
tsys + 100
8000/fc – 150
–tsys + 100
200
SCK high and low
level widths
t
t
KH
KL
SCK0
SI0
Output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
SI input setup time
(for SCK ↑)
t
t
t
SIK
2tsys + 100
100
SI input hold time
(for SCK ↑)
KSI
SI0
2tsys + 250
125
SCK ↓ → SO
delay time
KSO
SO0
Note 1) tsys indicates the three values below according to the upper two bits (CPU clock selection) of the
clock control register (CLC: 00FEh).
tsys [ns] = 2000/fc (upper two bits = “00”), 4000/fc (upper two bits = “01”), 16000/fc (upper two bits = “11”)
Note 2) CS, SCK, SI and SO indicates CS0, SCK0, SI0 and SO0, respectively.
Note 3) The load condition for the SCK output mode, SO output delay time is 50pF.
Note 4) The value when Port B output buffer capability switching register (BUFB: 01F4h) selects buffer
capability to high.
– 21 –
CXP836P60, CXP836P61
tWHCS
CS0
0.8VDD
0.2VDD
tKCY
tDCSK
tDCSKF
tKL
tKH
0.8VDD
0.8VDD
0.2VDD
SCK0
tSIK tKSI
0.8VDD
0.2VDD
SI0
Input data
tDCSO
tKSO
tDCSOF
0.8VDD
0.2VDD
SO0
Output data
Fig. 4. Serial transfer CH0 timing
– 22 –
CXP836P60, CXP836P61
Serial Transfer (CH1)
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)
Item
Symbol
Pin
Conditions
Input mode
Min.
1000
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
KCY
SCK1
SCK cycle time
Output mode
8000/fc
400
Input mode
SCK high and low level
widths
t
t
KH
KL
SCK1
SI1
Output mode
4000/fc – 50
100
SCK input mode
SCK output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
SI input setup time
(for SCK ↑)
t
SIK
200
200
SI input hold time
(for SCK ↑)
SI1
t
KSI
100
200
100
SO1
t
KSO
SCK ↓ → SO delay time
Note 1) tsys indicates the three values below according to the upper two bits (CPU clock selection) of the
clock control register (CLC: 00FEh).
tsys [ns] = 2000/fc (upper two bits = “00”), 4000/fc (upper two bits = “01”), 16000/fc (upper two bits = “11”)
Note 2) SCK, SI and SO indicates SCK1, SI1 and SO1, respectively.
Note 3) The load condition for the SCK1 output mode, SO1 output delay time is 50pF + 1TTL.
Note 4) The value when Port B output buffer capability switching register (BUFB: 01F4h) selects buffer
capability to normal.
Serial Transfer (CH1)
(Ta = –20 to +75°C, VDD = 2.7 to 3.3V, Vss = 0V)
Item
Symbol
Pin
Conditions
Input mode
Min.
1000
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCK1
SCK cycle time
t
KCY
Output mode
8000/fc
400
Input mode
SCK high and low level
widths
t
t
KH
KL
SCK1
SI1
Output mode
4000/fc – 100
100
SCK input mode
SCK output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
SI input setup time
(for SCK ↑)
t
t
t
SIK
200
200
SI input hold time
(for SCK ↑)
SI1
KSI
100
250
125
SO1
SCK ↓ → SO delay time
KSO
Note 1) tsys indicates the three values below according to the upper two bits (CPU clock selection) of the
clock control register (CLC: 00FEh).
tsys [ns] = 2000/fc (upper two bits = “00”), 4000/fc (upper two bits = “01”), 16000/fc (upper two bits = “11”)
Note 2) SCK, SI and SO indicates SCK1, SI1 and SO1, respectively.
Note 3) The load condition for the SCK1 output mode, SO1 output delay time is 50pF.
Note 4) The value when Port B output buffer capability switching register (BUFB: 01F4h) selects buffer
capability to high.
– 23 –
CXP836P60, CXP836P61
tKCY
tKL
tKH
0.8VDD
SCK1
0.2VDD
tSIK
tKSI
0.8VDD
0.2VDD
SI1
Input data
tKSO
0.8VDD
SO1
Output data
0.2VDD
Fig. 5. Serial transfer CH1 timing
– 24 –
CXP836P60, CXP836P61
(3) A/D converter characteristics
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)
Item
Resolution
Symbol
Pin
Conditions
Min.
Typ.
Max.
8
Unit
Bits
LSB
±3
Linearity error
Ta = 25°C
VDD = 5.0V
VSS = 0V
Zero transition
voltage
1
VZT
–10
10
70
mV
mV
Full-scale transition
voltage
2
VFT
4910
4970
5030
3
3
Conversion time
Sampling time
31/fADC
10/fADC
0
µs
µs
V
t
CONV
SAMP
t
Analog input voltage
VDD
AN0 to AN7
VIAN
(Ta = –20 to +75°C, VDD = 2.7 to 3.3V, Vss = 0V)
Item
Resolution
Symbol
Pin
Conditions
Min.
Typ.
Max.
8
Unit
Bits
LSB
±3
Linearity error
Ta = 25°C
VDD = 2.7V
VSS = 0V
Zero transition
voltage
1
–10
11
40
mV
mV
VZT
Full-scale transition
voltage
2
2651
2688
2716
VFT
3
3
Conversion time
Sampling time
31/fADC
10/fADC
0
µs
µs
V
t
CONV
SAMP
t
Analog input voltage
VDD
AN0 to AN7
VIAN
FFh
FEh
1
VZT: Value at which the digital conversion value changes
from 00h to 01h and vice versa.
2
3
VFT: Value at which the digital conversion value changes
from FEh to FFh and vice versa.
fADC = fc/4
Linearity error
01h
00h
VZT
VFT
Analog input
Fig. 6. Definition of A/D converter terms
– 25 –
CXP836P60, CXP836P61
(4) Interruption, reset input
(Ta = –20 to +75°C, VDD = 2.7 to 5.5V, Vss = 0V)
Pin Conditions Min. Max. Unit
INT0
Item
Symbol
INT1
INT2
INT3
INT4
External interruption
high and low level widths
t
t
IH
IL
1
µs
32/fc
µs
RST
Reset input low level width
t
RSL
tIH
tIL
0.8VDD
INT0
INT1
INT2
INT3
INT4
0.2VDD
tIL
tIH
Fig. 7. Interruption input timing
tRSL
RST
0.2VDD
Fig. 8. RST input timing
– 26 –
CXP836P60, CXP836P61
Appendix
(i) Main clock
EXTAL
(ii) Main clock
(iii) Sub clock
XTAL
Rd
C2
EXTAL
XTAL
Rd
TEX
TX
Rd
C1
C1
C2
C1 C2
Fig. 9. SPC700 series recommended oscillation circuit
Circuit
example
Remarks
Rd (Ω)
Manufacturer
Model
fc (MHz)
C1 (pF)
C2 (pF)
CSA4.19MG
CSA8.00MG
CSA10.0MT
CST4.19MGW
CST8.00MTW
4.19
8.00
100
30
30
100
30
30
22
15
10
33
18
15
100
30
30
100
30
30
22
15
10
33
18
15
0
0
(i)
0
10.00
MURATA MFG
CO., LTD.
1
0
4.19
8.00
1
0
(ii)
1
0
CST10.00MTW
10.00
4.19
1.0k
100
100
2.2k
0
RIVER
ELETEC
CO., LTD.
HC-49/U03
8.00
10.00
4.19
(i)
CL = 12.0pF
CL = 12.0pF
CL = 12.0pF
CX-5F
8.00
KINSEKI LTD.
10.00
4.19
0
1
FCR4.19MC5
30 ( ± 20%) 30 ( ± 20%)
20 ( ± 20%) 20 ( ± 20%)
20 ( ± 20%) 20 ( ± 20%)
36 ( ± 20%) 36 ( ± 20%)
20 ( ± 20%) 20 ( ± 20%)
20 ( ± 20%) 20 ( ± 20%)
1
8.00
FCR8.0MC5
FCR10.0MC5
CCR4.19MC3
1
10.00
4.19
TDK
Corporation
0
(ii)
1
1
8.00
CCR8.0MC5
CCR10.0MC5
1
10.00
32.768
75.00
CL = 12.5pF
CL = 6.0pF
18
4
18
4
330k
100k
Seiko
VTC-200
Instruments Inc. SP-T
(iii)
1
Those marked with an 1 signify types with
built-in ground capacitance (C1, C2).
FCR : Lead-type ceramic oscillator
CCR : Surface mounted-type ceramic oscillator
CL
: Load Capacitor
Product List
Products
Mask
PROM
Item
CXP CXP
83516 83620
CXP CXP CXP
CXP CXP
CXP836P60Q CXP836P60R
-1-
CXP836P61Q
-1-
CXP CXP
83508 83512
CXP
83624
83509 83513 83517 83621 83625 -1-
80-pin plastic 80-pin plastic
QFP LQFP
80-pin plastic
QFP (0.65mm pitch)
80-pin plastic
QFP/LQFP
0.65mm pitch
80-pin plastic QFP
Package
20K 24K 8K
bytes bytes bytes bytes
12K
20K 24K
bytes bytes
8K
12K 16K
16K
bytes
ROM
PROM 60K bytes
Existent
bytes bytes bytes
capacity
RST pin pull-up
resistor
Existent/Non-existent
– 27 –
CXP836P60, CXP836P61
Characteristics Curve
IDD vs. VDD
(fc = 10MHz, Ta = 25°C, typical)
1/2 frequency dividing mode
1/4 frequency dividing mode
10.0
5.0
1/16 frequency dividing mode
Sleep mode
1.0
0.5
0.1
(100µA)
32kHz mode
(instruction)
0.05
(50µA)
32kHz
Sleep mode
0.01
(10µA)
4
1
2
3
5
6
7
VDD – Supply voltage [V]
IDD vs. fc
(VDD = 5V, Ta = 25°C, typical)
15
10
5
1/2 frequency dividing mode
1/4 frequency dividing mode
1/16 frequency dividing mode
Sleep mode
0
0
5
10
fc – System clock [MHz]
– 28 –
CXP836P60, CXP836P61
Package Outline
CXP836P60
Unit: mm
80PIN QFP (PLASTIC)
23.9 ± 0.4
+ 0.1
0.15 – 0.05
+ 0.4
20.0 – 0.1
0.15
64
41
65
40
A
+ 0.2
0.1 – 0.05
80
25
1
24
+ 0.15
+ 0.35
2.75 – 0.15
0.8
0.35 – 0.1
M
0.2
0˚ to 10˚
DETAIL
A
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
EPOXY RESIN
SOLDER PLATING
SONY CODE
EIAJ CODE
QFP-80P-L01
QFP080-P-1420
42/COPPER ALLOY
1.6g
JEDEC CODE
PACKAGE MASS
80PIN QFP (PLASTIC)
CXP836P60
23.9 ± 0.4
+ 0.1
0.15 – 0.05
+ 0.4
20.0 – 0.1
0.15
64
41
65
40
A
+ 0.2
0.1 – 0.05
80
25
1
24
+ 0.15
+ 0.35
2.75 – 0.15
0.8
0.35 – 0.1
M
0.2
0˚ to 10˚
DETAIL
A
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
EPOXY RESIN
SOLDER PLATING
SONY CODE
EIAJ CODE
QFP-80P-L01
QFP080-P-1420
42/COPPER ALLOY
1.6g
JEDEC CODE
PACKAGE MASS
LEAD PLATING SPECIFICATIONS
ITEM
SPEC.
LEAD MATERIAL
42 ALLOY
SOLDER COMPOSITION
PLATING THICKNESS
Sn-Bi Bi:1-4wt%
5-18µm
– 29 –
CXP836P60, CXP836P61
Package Outline
CXP836P61
Unit: mm
80PIN QFP (PLASTIC)
+ 0.35
1.5 – 0.15
16.0 ± 0.4
+ 0.4
14.0 – 0.1
0.1
60
41
61
40
A
+ 0.15
0.1 – 0.1
80
21
1
20
0.24
0.65
b
M
0˚ to 10˚
+ 0.15
b = 0.3 – 0.1
( 0.3 )
PACKAGE STRUCTURE
DETAIL A : SOLDER
EPOXY RESIN
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
SOLDER PLATING
42 / COPPER ALLOY
0.6g
SONY CODE
EIAJ CODE
QFP-80P-L03
P-QFP80-14x14-0.65
JEDEC CODE
PACKAGE MASS
80PIN QFP (PLASTIC)
CXP836P61
+ 0.35
1.5 – 0.15
16.0 ± 0.4
+ 0.4
14.0 – 0.1
0.1
60
41
61
40
A
+ 0.15
0.1 – 0.1
80
21
1
20
0.24
0.65
b
M
0˚ to 10˚
+ 0.15
b = 0.3 – 0.1
( 0.3 )
PACKAGE STRUCTURE
DETAIL A : SOLDER
EPOXY RESIN
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
SOLDER PLATING
42 / COPPER ALLOY
0.6g
SONY CODE
EIAJ CODE
QFP-80P-L03
P-QFP80-14x14-0.65
JEDEC CODE
PACKAGE MASS
LEAD PLATING SPECIFICATIONS
ITEM
SPEC.
42 ALLOY
LEAD MATERIAL
SOLDER COMPOSITION
PLATING THICKNESS
Sn-Bi Bi:1-4wt%
5-18µm
– 30 –
CXP836P60, CXP836P61
Package Outline
CXP836P60
Unit: mm
80PIN LQFP (PLASTIC)
14.0 ± 0.2
12.0 ± 0.1
60
41
40
61
B
A
21
(0.22)
80
1
20
0.5
b
0.13
+ 0.2
1.5 – 0.1
M
0.1
0.1 ± 0.1
+ 0.08
b = 0.18 – 0.03
( 0.18 )
DETAIL B : SOLDER
0˚ to 10˚
NOTE: Dimension " " does not include mold protrusion.
DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
EPOXY RESIN
SONY CODE
SOLDER PLATING
42 / COPPER ALLOY
0.5g
LQFP-80P-L01
EIAJ CODE
P-LQFP80-12x12-0.5
PACKAGE MASS
JEDEC CODE
80PIN LQFP (PLASTIC)
CXP836P60
14.0 ± 0.2
12.0 ± 0.1
60
41
40
61
B
A
21
(0.22)
80
1
20
0.5
b
0.13
+ 0.2
1.5 – 0.1
M
0.1
0.1 ± 0.1
+ 0.08
b = 0.18 – 0.03
( 0.18 )
DETAIL B : SOLDER
0˚ to 10˚
NOTE: Dimension " " does not include mold protrusion.
DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
EPOXY RESIN
SOLDER PLATING
42 / COPPER ALLOY
0.5g
SONY CODE
LQFP-80P-L01
EIAJ CODE
P-LQFP80-12x12-0.5
PACKAGE MASS
JEDEC CODE
LEAD PLATING SPECIFICATIONS
ITEM
SPEC.
42 ALLOY
LEAD MATERIAL
SOLDER COMPOSITION
PLATING THICKNESS
Sn-Bi Bi:1-4wt%
5-18µm
Sony Corporation
– 31 –
相关型号：
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