CXP84716 [SONY]
CMOS 8-bit Single Chip Microcomputer; CMOS 8位单片机
| 型号： | CXP84716 |
| 厂家： | 
SONY CORPORATION |
| 描述： | CMOS 8-bit Single Chip Microcomputer |
| 文件： | 总29页 (文件大小：406K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CXP84716/84720/84724
CMOS 8-bit Single Chip Microcomputer
Description
100 pin QFP (Plastic)
100 pin LQFP (Plastic)
The CXP84716/84720/84724 is a CMOS 8-bit micro-
computer integrating on a single chip an A/D converter,
serial interface, timer/counter, time base timer, capture
timer/counter, FRC capture unit, high-precision timing
pattern generation circuit, PWM output, and the like
besides the basic configurations of 8-bit CPU, ROM,
RAM, and I/O port.
The CXP84716/84720/84724 also provides the
sleep/stop functions that enable to execute the power-
on reset function and lower the power consumption.
Structure
Silicon gate CMOS IC
Features
• A wide instruction set (213 instructions) which covers various types of data.
— 16-bit arithmetic/multiplication and division/Boolean bit operation instructions
• Minimum instruction cycle
250ns at 16MHz operation (4.5 to 5.5V)
333ns at 12MHz operation (3.0 to 5.5V)
16K bytes (CXP84716)
• Incorporated ROM capacity
20K bytes (CXP84720)
24K bytes (CXP84724)
• Incorporated RAM capacity
• Peripheral functions
— A/D converter
1120 bytes
8 bits, 8 channels, successive approximation method
(Conversion time 1.6µs at 16MHz)
— Serial interface
Srart-stop synchronization (UART), 1 channel
Incorporated buffer RAM (Auto transfer for 1 to 32 bytes), 2 channels
8-bit clock syncronization (MSB/LSB first selectable), 1 channel
8-bit timer, 8-bit timer/counter, 19-bit time base timer,
16-bit capture timer/counter
— Timer
— FRC capture unit
Incorporated 24-bit and 6-stage FIFO
— High-precision timing pattern generation circuit
PPG: maximum of 11 pins, 16 stages programmable, 2 channels
— PWM output
• Interruption
8 bits, 8 channels
19 factors, 15 vectors, multi-interruption possible
Sleep/stop
• Standby mode
• Package
100-pin plastic QFP/LQFP
CXP84700
• Piggyback/evaluator
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E96Z13-PS
CXP84716/84720/84724
P O R T A P R T B P O R T C P O R T D P R T E P O R T F P R T P O R T H P O R T I P O R T J
E X I 3
t o
E X I 0
S S V
D D V
R S T
X T A L
E X T A L
P P O 2 1
t o
P P O 1 1
P P O 1 0
t o
P P O 0
I N T 4
I N T 3
I N T 2
I N T 1
I N T 0
N M I
I N T E R R U P T C O N T R O L L E R
R E F A V
R E F A V
S S A V
– 2 –
CXP84716/84720/84724
Pin Assignment (Top View) 100-pin QFP package
100
99 98
96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
97
1
2
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
PF3
PF4
PI1/INT1
PI0/INT0
PE7/TO
PE6
3
PF5
4
PF6/TxD
PF7/RxD
PD0/PPO0
PD1/PPO1
PD2/PPO2
PD3/PPO3
PD4/PPO4
PD5/PPO5
PD6/PPO6
PD7/PPO7
PC0
5
PE5
6
PE4
7
PE3/NMI
PE2
8
9
PE1/EC1
PE0/EC0
PB7/SO1
PB6/SI1
PB5/SCK1
PB4/CS1
PB3
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
PC1
PC2
PB2
PC3
PB1
PC4
PB0/CINT
SO0
PC5
PC6
SI0
PC7
SCK0
PH0/PPO8
PH1/PPO9
PH2/PPO10
PH3/PPO11
PH4/PPO12
PH5/PPO13
PH6/PPO14
PH7/PPO15
PJ0/PPO16
CS0
PA7
PA6
PA5
PA4
PA3/AN7
PA2/AN6
PA1/AN5
PA0/AN4
31
32 33
34
35
36 37 38 39 40
41 42 43 44 45 46 47 48 49 50
Note) 1. NC (Pin 90) is left open.
2. VSS (Pins 41 and 88) are both connected to GND.
– 3 –
CXP84716/84720/84724
Pin Assignment (Top View) 100-pin LQFP package
100
99 98
96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
80 79 78 77 76
97
1
2
PF5
PF6/TxD
PF7/RxD
PD0/PPO0
PD1/PPO1
PD2/PPO2
PD3/PPO3
PD4/PPO4
PD5/PPO5
PD6/PPO6
PD7/PPO7
PC0
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
PE6
PE5
3
PE4
4
PE3/NMI
PE2
5
6
PE1/EC1
PE0/EC0
PB7/SO1
PB6/SI1
PB5/SCK1
PB4/CS1
PB3
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
PC1
PB2
PC2
PB1
PC3
PB0/CINT
SO0
PC4
PC5
SI0
PC6
SCK0
CS0
PC7
PH0/PPO8
PH1/PPO9
PH2/PPO10
PH3/PPO11
PH4/PPO12
PH5/PPO13
PA7
PA6
PA5
PA4
PA3/AN7
PA2/AN6
26 27 28 29 30
31
32 33
34
35
36 37 38 39 40
41 42 43 44 45 46 47 48 49 50
Note) 1. NC (Pin 88) is left open.
2. VSS (Pins 39 and 86) are both connected to GND.
– 4 –
CXP84716/84720/84724
Pin Description
Symbol
AN0
to
AN3
I/O
Description
Analog inputs to A/D converter.
(4 pins)
Input
(Port A)
PA0/AN4
to
PA3/AN7
8-bit I/O port. I/O can be set in
a unit of single bits.
Incorporation of pull-up
resistor can be set through the
software in a unit of 4 bits.
(8 pins)
Analog inputs to A/D converter.
(4 pins)
I/O/Input
PA4 to PA7
PB0/CINT
PB1 to PB3
PB4/CS1
I/O
External capture input to 16-bit
timer/counter.
I/O/Input
I/O
(Port B)
8-bit I/O port. I/O can be set in
a unit of single bits.
Incorporation of pull-up resistor
can be set through the
software in a unit of 4 bits.
(8 pins)
Chip select input for serial interface
(CH1).
I/O/Input
Serial clock I/O (CH1).
Serial data input (CH1).
Serial data output (CH1).
PB5/SCK1
PB6/SI1
I/O/I/O
I/O/Input
I/O/Output
PB7/SO1
(Port C)
8-bit I/O port. I/O can be set in a unit of single bits. Can drive 12mA sink
PC0 to PC7
I/O
current. Incorporation of pull-up resistor can be set through the software in
a unit of 4 bits.
(8 pins)
(Port D)
8-bit I/O port. I/O can be set in
a unit of single bits.
Incorporation of pull-up resistor
can be set through the software
in a unit of 4 bits.
Data is gated with PPO contents
by OR-gate and they are output.
(8 pins)
PPO0 to PPO7 outputs for programmable
pattern generator (PPG0). Functions as
high-precision real-time pulse output port.
(PPG0: 11 pins; PPG1: 11 pins)
PD0/PPO0
to
PD7/PPO7
I/O/Real-time
output
PE0/EC0
PE1/EC1
PE2
Input/Input
Input/Input
Input
External event inputs for timer/counter.
(2 pins)
(Port E)
8-bit port. Lower 5 bits are for
input; upper 2 bits are for
output.
Non-maskable interruption request.
PE3/NMI
PE4 to PE5
PE6
Input/Input
Input
(8 pins)
Output
Rectangular wave output for 16-bit
timer/counter.
PE7/TO
Output/Output
– 5 –
CXP84716/84720/84724
Symbol
I/O
Description
(Port F)
Lower 6 bits are for I/O. I/O can be set in a unit of single bits.
Incorporation of pull-up resistor can be set through the software in a unit
of 4 bits (PF0 to PF3) or 2 bits (PF4,PF5)
PF6 is for output; PF7 is for input.
PF0 to PF5
I/O
(8 pins)
PF6/TxD
PF7/RxD
Output/Output
Input/Input
UART transmission data output.
UART reception data input.
(Port G)
8-bit I/O port. I/O can be set in
a unit of single bits.
Incorporation of pull-up
PG0/PWM0
to
PG7/PWM7
PWM outputs.
(8 pins)
I/O/Output
resistor can be set through the
software in a unit of 4 bits.
(8 pins)
(Port H)
8-bit I/O port. I/O can be set in
PPO8 to PPO11 (PPG0) outputs and
a unit of single bits.
PPO12 to PPO15 (PPG1) outputs for
Incorporation of pull-up resistor
PH0/PPO8
to
PH7/PPO15
I/O/Real-time
output
programmable pattern generator (PPG0,
can be set through the software
in a unit of 4 bits.
Data is gated with PPO contents
PPG1).
Functions as high-precision real-time pulse
output port.
by OR-gate and they are output.
(8 pins)
PI0/INT0
to
PI4/INT4
(Port I)
External interruption request inputs.
8-bit I/O port. I/O can be set in
(5 pins)
I/O/Input
a unit of single bits.
Incorporation of pull-up resistor
can be set through the software
in a unit of 4 bits.
(8 pins)
Serial clock I/O (CH2).
PI5/SCK2
PI6/SI2
I/O/I/O
Serial data input (CH2).
Serial data output (CH2).
I/O/Input
I/O/Output
PI7/SO2
(Port I)
8-bit I/O port. I/O can be set in
a unit of single bits.
Incorporation of pull-up resistor
can be set through the software
in a unit of 4 bits.
PPO16 to PPO21 outputs for
programmable pattern generator (PPG1).
Functions as high-precision real-time
pulse output port.
PJ0/PPO16
to
PJ5/PPO21
I/O/Real-time
output
Data is gated with PPO contents
by OR-gate and they are output.
(8 pins)
PJ6/EXI0
PJ7/EXI1
I/O/Input
I/O/Input
External inputs to FRC capture unit.
(2 Pins)
External inputs to FRC capture unit.
(2 pins)
EXI2 to EXI3 Input
Chip select input for serial interface (CH0).
Serial clock I/O (CH0).
CS0
SCK0
SI0
Input
I/O
Serial data input (CH0).
Input
Serial data I/O (CH0).
SO1
I/O/Output
– 6 –
CXP84716/84720/84724
Symbol
EXTAL
I/O
Description
Connects a crystal for system clock oscillation. When a clock is supplied
externally, input it to EXTAL pin and input a reversed phase clock to XTAL
pin.
Input
XTAL
Output
System reset; active at Low level. This pin is I/O pin, and outputs Low
level at the power on with the power-on reset function is executed. (Mask
option)
RST
I/O
Not connected.
Leave this pin open for normal operation.
NC
AVDD
AVREF
AVSS
VDD
Positive power supply of A/D converter.
Reference voltage input of A/D converter.
GND of A/D converter.
Input
Positive power supply.
VSS
GND.
– 7 –
CXP84716/84720/84724
I/O Circuit Format for Pins
Pin
When reset
Circuit format
Port A
Pull-up resistor
"0" when reset
Port A data
PA0/AN4
to
PA3/AN7
Port A direction
"0" when reset
IP Input
protection
circuit
Hi-Z
Data bus
RD (Port A)
Port A function
selection
Input multiplexer
"0" when reset
A/D converter
Pull-up transistors
approx. 100kΩ (VDD = 4.5 to 5.5V)
approx. 300kΩ (VDD = 3.0 to 3.6V)
4 pins
Port A
Port B
Port F
Pull-up resistor
"0" when reset
Ports A, B, F data
PA4 to PA7
PB1 to PB3
PF0 to PF5
Ports A, B, F direction
"0" when reset
Hi-Z
IP
Data bus
RD (Ports A, B, F)
Pull-up transistors
13 pins
approx. 100kΩ (VDD = 4.5 to 5.5V)
approx. 300kΩ (VDD = 3.0 to 3.6V)
Port B
Pull-up resistor
"0" when reset
Port I
Port J
Ports B, I, J data
PB0/CINT
PB4/CS1
PB6/SI1
PI6/SI2
PJ6/EXI0
PJ7/EXI1
Ports B, I, J direction
"0" when reset
IP
Hi-Z
Schmitt input
Data bus
RD (Ports B, I, J)
CINT
CS1
SI1
EXI0
EXI1
Pull-up transistors
approx. 100kΩ (VDD = 4.5 to 5.5V)
approx. 300kΩ (VDD = 3.0 to 3.6V)
6 pins
– 8 –
CXP84716/84720/84724
Pin
When reset
Circuit format
Port B
Port I
Pull-up resistor
"0" when reset
SCK OUT
Serial clock output enable
Ports B, I function
selection
"0" when reset
PB5/SCK1
PI5/SCK2
IP
Ports B, I data
Hi-Z
Ports B, I direction
"0" when reset
Schmitt input
Data bus
RD (Ports B, I)
Pull-up transistors
SCK in
approx. 100kΩ (VDD = 4.5 to 5.5V)
approx. 300kΩ (VDD = 3.0 to 3.6V)
2 pins
Port B
Port I
Pull-up resistor
"0" when reset
SO
Serial data output enable
Ports B, I function
selection
"0" when reset
PB7/SO1
PI7/SO2
IP
Ports B, I data
Hi-Z
Ports B, I direction
"0" when reset
Data bus
RD (Ports B, I)
Pull-up transistors
approx. 100kΩ (VDD = 4.5 to 5.5V)
approx. 300kΩ (VDD = 3.0 to 3.6V)
2 pins
Port C
2
Pull-up resistor
"0" when reset
Port C data
1
Port C direction
"0" when reset
PC0 to PC7
IP
Hi-Z
Data bus
RD (Port C)
1 Large current
(12mA: VDD = 4.5 to 5.5V)
(5mA: VDD = 3.0 to 3.6V)
2 Pull-up transistors
approx. 100kΩ (VDD = 4.5 to 5.5V)
approx. 300kΩ (VDD = 3.0 to 3.6V)
8 pins
– 9 –
CXP84716/84720/84724
Pin
When reset
Circuit format
Port D
Port H
Port J
PD0/PPO0
to
PD7/PPO7
Pull-up resistor
"0" when reset
PPO data
Ports D, H, J data
PH0/PPO8
to
Hi-Z
PH7/PPO15
Ports D, H, J direction
IP
"0" when reset
Data bus
PJ0/PPO16
to
PJ5/PPO21
RD (Ports D, H, J)
Pull-up transistors
approx. 100kΩ (VDD = 4.5 to 5.5V)
approx. 300kΩ (VDD = 3.0 to 3.6V)
22 pins
Port E
Port F
PE0/EC0
PE1/EC1
PE2
PE3/NMI
PE4
Schmitt input (Inverter input for PE2, PE4, PE5)
EC0, EC1, NMI, RxD
Data bus
RD (Ports E, F)
IP
Hi-Z
PE5
PF7/RxD
7 pins
Port E
PE6
Port E data
High level
"1" when reset
Data bus
1 pin
RD (Port E)
Port E
Internal reset signal
Port E data
00
01
MPX
"1" when reset
High level
with the
TO
PE7/TO
resistor of pull-
up transistor
ON for reset
(
)
Port E function selection (upper)
Port E function selection (lower)
"00" when reset
Pull-up transistors
approx. 150kΩ (VDD = 4.5 to 5.5V)
approx. 400kΩ (VDD = 3.0 to 3.6V)
TO output enable
1 pin
– 10 –
CXP84716/84720/84724
Pin
When reset
Circuit format
Port F
UART transmission circuit
Transmission control/
port control
PF6/TxD
1 pin
"0" when reset
High level
Port F data
"1" when reset
Data bus
RD (Port F)
Port G
Pull-up resistor
"0" when reset
PWM
Port G function
selection
"0" when reset
PG0/PWM0
to
IP
Port G data
PG7/PWM7
Hi-Z
Port G direction
"0" when reset
Data bus
RD (Port G)
Pull-up transistors
approx. 100kΩ (VDD = 4.5 to 5.5V)
approx. 300kΩ (VDD = 3.0 to 3.6V)
8 pins
Port I
Pull-up resistor
"0" when reset
Port I data
PI0/INT0
to
PI4/INT4
Port I direction
"0" when reset
IP
Hi-Z
Schmitt input
Data bus
RD (Port I)
INT0
INT1
INT2
INT3
INT4
Pull-up transistors
approx. 100kΩ (VDD = 4.5 to 5.5V)
approx. 300kΩ (VDD = 3.0 to 3.6V)
5 pins
AN0
to
Input multiplexer
AN3
Hi-Z
IP
A/D converter
4 pins
– 11 –
CXP84716/84720/84724
When reset
Hi-Z
Pin
Circuit format
EXI2
EXI3
Schmitt input
IP
EXI2, EXI3
2 pins
CS0
SI0
Schmitt input
Hi-Z
Hi-Z
IP
SIO
2 pins
SO0
1 pin
SO0 from SIO
SO0 output enable
Internal serial clock
from SIO
SCK0
1 pin
Hi-Z
IP
SCK0 output enable
External serial clock to SIO
Schmitt input
EXTAL
XTAL
• Diagram shows the circuit
composition during oscillation.
IP
IP
EXTAL
XTAL
Oscillation
• Feedback resistor is removed
during stop mode and XTAL
becomes High level.
2 pins
Pull-up resistor
Mask option
IP
RST
1 pin
OP
Low level
Schmitt input
From power-on reset circuit
(Mask option)
– 12 –
CXP84716/84720/84724
Absolute Maximum Ratings
(Vss = 0V reference)
Item
Symbol
VDD
Rating
Unit
V
Remarks
–0.3 to +7.0
AVSS to +7.0
–0.3 to +0.3
AVSS to +7.0
1
V
AVDD
AVSS
AVREF
VIN
Supply voltage
V
V
2
–0.3 to +7.0
–0.3 to +7.0
–5
V
Input voltagte
2
V
Output voltage
VOUT
IOH
mA
mA
Output (value per pin)
Total for all output pins
High level output current
–50
∑IOH
High level total output current
Low level output current
All pins excluding large current
outputs (value per pin)
15
mA
IOL
3
20
100
mA
mA
°C
IOLC
Large current outputs (value per pin)
Total for all output pins
Low level total output current ∑IOL
–20 to +75
–55 to +150
600
Operating temperature
Storage temperature
Topr
Tstg
°C
QFP package
LQFP package
mW
Allowable power dissipation
PD
380
1
AVDD and VDD must be set to the same voltage.
VIN and VOUT must not exceed VDD + 0.3V.
The large current output pins are Port C (PC).
2
3
Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should
be conducted under the recommended operating conditions. Exceeding these conditions may adversely
affect the reliability of the LSI.
– 13 –
CXP84716/84720/84724
Recommended Operating Conditions
(Vss = 0V reference)
Item
Supply voltage
Analog voltage
Symbol
Min.
4.5
Max.
5.5
Unit
V
Remarks
Guaranteed operation
range for 1/2 and 1/4
frequency dividing clock.
fc = 16MHz or less
fc = 12MHz or less
3.0
2.7
5.5
5.5
V
VDD
Guaranteed operation range for 1/16
frequency dividing clock or sleep mode
V
V
Guaranteed data hold operation range
during stop mode
2.7
5.5
1
AVDD
V
V
V
V
V
V
V
V
V
V
V
°C
3.0
5.5
VDD
VDD
VDD
2,
2,
5
6
0.7VDD
0.8VDD
0.8VDD
VIH
High level input
voltage
3
VIHS
VIHEX
Hysteresis input
4,
5
VDD – 0.4 VDD + 0.3
VDD – 0.2 VDD + 0.2
EXTAL pin
EXTAL pin
4,
6
2,
5
0
0
0.3VDD
0.2VDD
0.2VDD
0.4
VIL
2,
6
Low level input
voltage
3
VILS
VILEX
Topr
0
Hysteresis input
4,
5
–0.3
–0.3
–20
EXTAL pin
EXTAL pin
4,
6
0.2
Operating temperature
+75
1
AVDD and VDD must be set to the same voltage.
2
3
Normal input port (PA, PB1 to PB3, PB7, PC, PD, PE2, PE4, PE5, PF0 to PF5, PG, PH, PI7, PJ0 to PJ5)
RST, CINT, CS0, CS1, SCK0, SCK1, SCK2, SI0, SI1, SI2, EC0, EC1, NMI, RxD, INT0, INT1, INT2, INT3,
INT4, EXI0, EXI1, EXI2 and EXI3
4
5
6
Specifies only when the external clock is input.
This case applies to the range of 4.5 to 5.5V supply voltage (VDD).
This case applies to the range of 3.0 to 5.5V supply voltage (VDD).
– 14 –
CXP84716/84720/84724
Electrical Characteristics
DC Characteristics (VDD = 4.5 to 5.5V)
(Ta = –20 to +75°C, VSS = 0V reference)
Item
Symbol
Pins
Conditions
Min.
4.0
Typ.
Max.
Unit
V
PA to PD,
PE6, PE7,
PF0 to PF6,
PG to PJ,
VDD = 4.5V, IOH = –0.5mA
High level
output voltage
VOH
3.5
V
V
V
VDD = 4.5V, IOH = –1.2mA
VDD = 4.5V, IOL = 1.8mA
VDD = 4.5V, IOL = 3.6mA
SCK0, SO0
PA to PD,
PE6, PE7,
PF0 to PF6,
PG to PJ,
0.4
0.6
Low level
output voltage
VOL
SCK0, SO0,
1
RST
PC
1.5
40
V
VDD = 4.5V, IOL = 12.0mA
VDD = 5.5V, VIH = 5.5V
VDD = 5.5V, VIL = 0.4V
VDD = 5.5V, VIL = 5.5V
VDD = 5.5V, VIL = 0.4V
IIHE
IILE
IIHT
0.5
–0.5
0.1
µA
µA
µA
µA
µA
µA
µA
EXTAL
–40
10
TEX
Input current IILT
–0.1
–1.5
–10
–400
–45
2
IILR
RST
VDD = 5.5V, VIL = 0.4V
VDD = 4.5V, VIL = 4.0V
3
PA to PD
PF0 to PF
PG to PJ
,
3
IIL
5
,
3
–2.78
3
PA to PD
,
PE0 to PE5,
PF0 to PF5
3
,
PF7,
PG to PJ
3
I/O leakage
IIZ
,
VDD = 5.5V
VI = 0, 5.5V
±10
µA
current
CS0, SCK0,
SI0, EXI2,
EXI3,
AN0 to AN3
2
RST
– 15 –
CXP84716/84720/84724
Item
Symbol
Pins
Conditions
Min.
Typ.
17.5
Max.
40
Unit
mA
1/2 frequency dividing clock operation
IDD
V
DD = 5.5V, 16MHz crystal oscillation
(C1 = C2 = 15pF)
Sleep mode
Supply
current
VDD
mA
µA
4
IDDS1
IDDS2
1.4
8
VDD = 5.5V, 16MHz crystal oscillation
(C1 = C2 = 15pF)
Stop mode
VDD = 5.5V, termination of 16MHz
crystal oscillation
10
PA to PD,
PE0 to PE5,
PF0 to PF5,
PF7,
PG to PJ,
CS0, SCK0,
SI0, EXI2,
EXI3,
Clock 1MHz
0V for all pins excluding measured
pins
Input
capacity
pF
20
CIN
10
AN0 to AN3,
EXTAL,
RST
1
2
RST pin specifies the output voltage only when the power-on reset circuit is selected with mask option.
RST pin specifies the input current when the pull-up resistance is selected, and specifies the leakage
current when no resistance is selected.
3
4
PA to PD, PF0 to PF5 and PG to PJ pins specify the input current when the pull-up resistance is selected,
and specify the leakage current when no resistance is selected.
When all pins are open.
– 16 –
CXP84716/84720/84724
Electrical Characteristics
DC Characteristics (VDD = 3.0 to 3.6V)
(Ta = –20 to +75°C, VSS = 0V reference)
Item
Symbol
Pins
Conditions
Min.
2.7
Typ.
Max.
Unit
V
PA to PD,
PE6, PE7,
PF0 to PF6,
PG to PJ,
VDD = 3.0V, IOH = –0.15mA
High level
output voltage
VOH
VDD = 3.0V, IOH = –0.5mA
VDD = 3.0V, IOL = 1.2mA
VDD = 3.0V, IOL = 1.6mA
2.3
V
V
V
SCK0, SO0
PA to PD,
PE6, PE7,
PF0 to PF6,
PG to PJ,
0.3
0.5
Low level
output voltage
VOL
SCK0, SO0,
1
RST
PC
VDD = 3.0V, IOL = 5.0mA
VDD = 3.6V, VIH = 3.6V
VDD = 3.6V, VIL = 0.3V
VDD = 3.6V, VIL = 3.6V
VDD = 3.6V, VIL = 0.4V
1
V
IIHE
IILE
IIHT
0.3
–0.3
0.1
20
µA
µA
µA
µA
µA
µA
µA
EXTAL
–20
10
TEX
Input current IILT
–0.1
–0.9
–10
–200
–20
2
IILR
RST
VDD = 3.6V, VIL = 0.3V
VDD = 3.0V, VIL = 2.7V
3
PA to PD
PF0 to PF
PG to PJ
,
3
IIL
5
,
3
–1.0
3
PA to PD
,
PE0 to PE5,
PF0 to PF5
3
,
PF7,
PG to PJ
3
I/O leakage
IIZ
,
VDD = 3.6V
VI = 0, 3.6V
±10
µA
current
CS0, SCK0,
SI0, EXI2,
EXI3,
AN0 to AN3
2
RST
– 17 –
CXP84716/84720/84724
Item
Symbol
Pins
Conditions
Min.
Typ.
6.5
Max.
18
Unit
mA
1/2 frequency dividing clock operation
IDD
V
DD = 3.6V, 12MHz crystal oscillation
(C1 = C2 = 15pF)
Sleep mode
Supply
current
VDD
mA
µA
4
IDDS1
IDDS2
0.5
2.0
10
VDD = 3.6V, 12MHz crystal oscillation
(C1 = C2 = 15pF)
Stop mode
VDD = 3.6V, termination of 12MHz
crystal oscillation
PA to PD,
PE0 to PE5,
PF0 to PF5,
PF7,
PG to PJ,
CS0, SCK0,
SI0, EXI2,
EXI3,
Clock 1MHz
0V for all pins excluding measured
pins
Input
capacity
pF
20
CIN
10
AN0 to AN3,
EXTAL,
RST
1
2
RST pin specifies the output voltage only when the power-on reset circuit is selected with mask option.
RST pin specifies the input current when the pull-up resistance is selected, and specifies the leakage
current when no resistance is selected.
3
4
PA to PD, PF0 to PF5 and PG to PJ pins specify the input current when the pull-up resistance is selected,
and specify the leakage current when no resistance is selected.
When all pins are open.
– 18 –
CXP84716/84720/84724
AC Characteristics
(1) Clock timing
(Ta = –20 to +75°C, VDD = 3.0 to 5.5V, Vss = 0V reference)
Item
Symbol
Pin
Conditions
Min.
1
Typ. Max. Unit
VDD = 4.5 to 5.5V
16
XTAL
EXTAL
Fig. 1, Fig. 2
System clock frequency
MHz
12
fC
1
VDD = 4.5 to 5.5V
28
Fig. 1, Fig. 2
System clock input pulse
width
t
t
XL
XTAL
EXTAL
ns
XH
External clock drive
37.5
Fig. 1, Fig. 2
System clock input
rise time, fall time
t
t
CR
CF
XTAL
EXTAL
ns
ns
200
20
External clock drive
Event count input clock
pulse width
t
t
EH
EL
EC0
EC1
1
tsys + 50
Fig. 3
Fig. 3
Event count input clock
rise time, fall time
t
t
ER
EF
EC0
EC1
ms
1
tsys indicates the three values below according to the upper two bits (CPU clock selection) of the clock
control register (CLC: 00FEh).
tsys [ns] = 2000/fc (upper two bits = “00”), 4000/fc (upper two bits = “01”), 16000/fc (Upper two bits = “11”)
Fig. 1. Clock timing
1/fc
VDD – 0.4V (VDD = 4.5 to 5.5V)
VDD – 0.3V
EXTAL
0.4V (VDD = 4.5 to 5.5V)
0.3V
tXH
tCF
tXL
tCR
Fig. 2. Clock applied conditions
Crystal oscillation
Ceramic oscillation
External clock
EXTAL
XTAL
EXTAL
XTAL
C1
C2
74HC04
Fig. 3. Event count clock timing
0.8VDD
0.2VDD
EC0
EC1
tEH
tEF
tEL
tER
– 19 –
CXP84716/84720/84724
(2) Serial transfer (CH0, CH1)
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Item
Symbol Pin
Conditions
Min.
Max.
Unit
ns
CS↓ → SCK
delay time
Chip select transfer mode
(SCK = output mode)
SCK0
SCK1
t
t
t
t
t
DCSK
1.5tsys + 200
CS↑ → SCK
floating delay time
Chip select transfer mode
(SCK = output mode)
SCK0
SCK1
DCSKF
DCSO
DCSOF
WHCS
1.5tsys + 200
1.5tsys + 200
1.5tsys + 200
ns
ns
ns
ns
SO0
SO1
CS↓ → SO delay time
Chip select transfer mode
Chip select transfer mode
Chip select transfer mode
CS↑ → SO floating
delay time
SO0
SO1
CS0
CS1
CS High level width
SCK cycle time
tsys + 200
Input mode
2tsys + 200
8000/fc
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCK0
SCK1
tKCY
Output mode
Input mode
tsys + 100
4000/fc – 50
–tsys + 100
200
SCK High and Low
level width
t
KH
KL
SCK0
SCK1
t
Output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
SI input setup time
(for SCK↑)
SI0
SI1
t
t
t
SIK
2tsys + 200
100
SI input hold time
(for SCK↑)
SI0
SI1
KSI
2tsys + 200
100
SCK↓ → SO
delay time
SO0
SO1
KSO
Note 1) tsys indicates three values according to the contents of the clock control register (CLC: 00FEh) upper
2 bits (CPU clock selection).
tsys [ns] = 2000/fc (upper 2 bits = “00”), 4000/fc (upper 2 bits = “01”), 16000/fc (upper 2 bits = “11”)
Note 2) CS, SCK, SI and SO represent CS0, SCK0, SI0 and SO0 for CH0; they represent CS1, SCK1, SI1
and SO1 for CH1, respectively.
Note 3) The load of SCK output mode and SO output delay time is 50pF + 1TTL.
– 20 –
CXP84716/84720/84724
Serial transfer (CH0, CH1)
(Ta = –20 to +75°C, VDD = 3.0 to 3.6V, Vss = 0V reference)
Item
Symbol Pin
Conditions
Min.
Max.
Unit
ns
CS↓ → SCK
delay time
Chip select transfer mode
(SCK = output mode)
SCK0
SCK1
t
t
t
t
DCSK
1.5tsys + 250
CS↑ → SCK
floating delay time
Chip select transfer mode
(SCK = output mode)
SCK0
SCK1
DCSKF
DCSO
DCSOF
1.5tsys + 200
1.5tsys + 250
1.5tsys + 200
ns
ns
ns
ns
SO0
SO1
CS↓ → SO delay time
Chip select transfer mode
Chip select transfer mode
Chip select transfer mode
CS↑ → SO floating
delay time
SO0
SO1
CS0
CS1
CS High level width tWHCS
tsys + 200
Input mode
2tsys + 200
8000/fc
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCK0
SCK1
SCK cycle time
t
KCY
Output mode
Input mode
tsys + 100
4000/fc – 100
–tsys + 100
200
SCK High and Low
level widths
t
KH
KL
SCK0
SCK1
t
Output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
SI input setup time
(for SCK↑)
SI0
SI1
t
t
t
SIK
2tsys + 200
100
SI input hold time
(for SCK↑)
SI0
SI1
KSI
2tsys + 250
125
SCK↓ → SO
delay time
SO0
SO1
KSO
Note 1) tsys indicates three values according to the contents of the clock control register (CLC: 00FEh) upper
2 bits (CPU clock selection).
tsys [ns] = 2000/fc (upper 2 bits = “00”), 4000/fc (upper 2 bits = “01”), 16000/fc (upper 2 bits = “11”)
Note 2) CS, SCK, SI and SO represent CS0, SCK0, SI0 and SO0 for CH0; they represent CS1, SCK1, SI1
and SO1 for CH1, respectively.
Note 3) The load of SCK output mode and SO output delay time is 50pF.
– 21 –
CXP84716/84720/84724
Fig. 4. Serial transfer CH0, CH1 timing
tWHCS
CS0
CS1
0.8VDD
0.2VDD
tKCY
tDCSK
tDCSKF
tKL
tKH
0.8VDD
0.8VDD
0.2VDD
SCK0
SCK1
tSIK
tKSI
0.8VDD
0.2VDD
SI0
SI1
Input data
tDCSO
tKSO
tDCSOF
0.8VDD
0.2VDD
SO0
SO1
Output data
– 22 –
CXP84716/84720/84724
Serial transfer (CH2)
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Item
Symbol Pin
Conditions
Input mode
Min.
1000
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCK2
SCK2
SI2
SCK cycle time
t
KCY
Output mode
8000/fc
400
Input mode
SCK High and Low
level widths
t
KH
KL
t
Output mode
4000/fc – 50
100
SCK input mode
SCK output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
SI input setup time
(for SCK↑)
t
t
t
SIK
200
200
SI input hold time
(for SCK↑)
SI2
KSI
100
200
100
SO2
KSO
SCK↓ → SO delay time
Note 1) tsys indicates three values according to the contents of the clock control register (CLC: 00FEh) upper 2
bits (CPU clock selection).
tsys [ns] = 2000/fc (Upper 2 bits = “00”), 4000/fc (Upper 2 bits = “01’), 16000/fc (Upper 2 bits = “11”)
Note 2) SCK, SI and SO represent SCK2, SI2 and SO2 for CH2, respectively.
Note 3) The load of SCK2 output mode and SO2 output delay time is 50pF+1TTL.
Serial transfer (CH2)
(Ta = –20 to +75°C, VDD = 3.0 to 3.6V, Vss = 0V reference)
Item
Symbol Pin
Conditions
Input mode
Min.
1000
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCK2
SCK2
SI2
SCK cycle time
t
KCY
Output mode
8000/fc
400
Input mode
SCK High and Low
level widths
t
t
KH
KL
Output mode
4000/fc – 100
100
SCK input mode
SCK output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
SI input setup time
(for SCK↑)
t
t
t
SIK
200
200
SI input hold time
(for SCK↑)
SI2
KSI
100
250
125
SO2
KSO
SCK↓ → SO delay time
Note 1) tsys indicates three values according to the contents of the clock control register (CLC: 00FEh) upper 2
bits (CPU clock selection).
tsys [ns] = 2000/fc (Upper 2 bits = “00”), 4000/fc (Upper 2 bits = “01’), 16000/fc (Upper 2 bits = “11”)
Note 2) SCK, SI and SO represent SCK2, SI2 and SO2 for CH2, respectively.
Note 3) The load of SCK2 output mode and SO2 output delay time is 50pF.
– 23 –
CXP84716/84720/84724
Fig. 5. Serial transfer CH2 timing
tKCY
tKL
tKH
0.8VDD
0.2VDD
SCK2
tSIK
tKSI
0.8VDD
0.2VDD
SI2
Input data
tKSO
0.8VDD
SO2
Output data
0.2VDD
– 24 –
CXP84716/84720/84724
(3) A/D converter characteristics (Ta = –20 to +75°C, VDD = AVDD = 3.0 to 5.5V, Vss = AVSS = 0V reference)
Item
Resolution
Symbol
Pin
Conditions
Min.
Typ.
Max. Unit
8
Bits
±3
LSB
Linearity errror
Ta = 25°C
VDD = AVDD = AVREF
= 5.0V
Zero
transition voltage
1
VZT
–10
10
70
mV
VSS = AVSS = 0V
Full-scale transition
voltage
2
VFT
4910
4970
5030
±5
mV
LSB
mV
Linearity errror
Ta = 25°C
VDD = AVDD = AVREF
= 3.3V
Zero
transition voltage
1
VZT
–10
6.5
70
Full-scale transition
voltage
VSS = AVSS = 0V
2
VFT
3215
3280
mV
3345
3
µs
µs
V
Convertion time
Sampling time
26/fADC
6/fADC
t
CONV
SAMP
3
t
VDD = AVDD = 4.5 to 5.5V
VDD = AVDD = 3.0 to 3.6V
AVDD
AVDD
AVREF
1.0
AVDD – 0.5
AVDD – 0.3
0
Reference input
voltage
AVREF
VREF
VIAN
IREF
V
AN0 to AN7
Analog input voltage
V
VDD = 5.5V
Operation
mA
0.6
0.4
mode
mA
µA
VDD = 3.6V
0.7
10
AVREF current
AVREF
Sleep mode
Stop mode
IREFS
Fig.6. Definition of A/D converter terms
1
VZT: Value at which the digital conversion value changes
from 00h to 01h and vice versa.
FFh
FEh
2
3
VFT: Value at which the digital conversion value changes
from FEh to FFh and vice versa.
fADC indicates the below values due to the contents of bit
6 (CKS) of the A/D control register (ADC: 00F9h).
PS1 selected
PS2 selected
fADC = fc
fADC = fc/2
Linearity error
01h
00h
VZT
VFT
Analog input
– 25 –
CXP84716/84720/84724
(4) Interruption, reset input (Ta = –20 to +75°C, VDD = 3.0 to 5.5V, Vss = 0V reference)
Item
Symbol
Pin
INT0
Conditions Min.
Max.
Unit
INT1
INT2
INT3
INT4
NMI
External interruption
High, Low level width
t
t
IH
IL
1
µs
Reset input Low level width
32/fc
µs
t
RSL
RST
Fig. 7. Interruption input timing
tIH
tIL
INT0
0.8VDD
INT1
INT2
0.2VDD
INT3
tIL
tIH
INT4
NMI
(NMI is specified only for
the falling edge)
Fig. 8. RST input timing
tRSL
RST
0.2VDD
1
(5) Power-on reset
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, VSS = 0V reference)
Item
Power supply rise time
Power supply cut-off time
1
Symbol
Pin
Conditions
Power-on reset
Repetitive power-on reset
Min.
0.05
1
Max.
50
Unit
ms
t
t
R
VDD
ms
OFF
Specifies only when the power-on reset function is selected.
Power-on reset function can be selected only for the supply voltage range of 4.5 to 5.5V.
Fig. 9. Power-on reset
4.5V
0.2V
VDD
0.2V
tR
tOFF
Turn the power on smoothly.
– 26 –
CXP84716/84720/84724
Appendix
Fig. 10. Recommended oscillation circuit
(i) Main clock
EXTAL
XTAL
Rd
C2
C1
Circuit
example
Manufacture
Model
fc (MHz) C1 (pF) C2 (pF) Rd (Ω)
8.00
10.00
12.00
16.00
8.00
10
10
RIVER
ELETEC
co., LTD.
(i)
(i)
0
0
HC-49/U03
5
5
22 (15) 22 (15)
10.00
12.00
16.00
KINSEKI LTD.
HC-49/U (-S)
15
12
15
12
Mask Option Table
Item
Content
Reset pin pull-up resistor
Non-existent
Non-existent
Existent
Existent
1
Power-on-reset circuit
1
Power-on-reset circuit can not be selected when the supply voltage (VDD) ranges from 3.5 to 4.5V.
– 27 –
CXP84716/84720/84724
Characteristics Curve
IDD vs. fc
(VDD = 5V, Ta = 25°C, Typical)
IDD vs. VDD
(fc = 16MHz, Ta = 25°C, Typical)
20
15
10
5
1/2 dividing mode
20.0
10.0
1/4 dividing mode
1/2 dividing mode
5.0
1/16 dividing mode
Sleep mode
1.0
0.5
1/4 dividing mode
1/16 dividing mode
0.1
(100µA)
0.05
(50µA)
Stop mode
0.01
(10µA)
Sleep mode
16
3
4
5
6
0
5
10
fc – System clock [MHz]
VDD – Supply voltage [V]
IDD vs. VDD
(fc = 12MHz, Ta = 25°C, Typical)
IDD vs. fc
(VDD = 3.3V, Ta = 25°C, Typical)
20
15
10
5
20.0
10.0
1/2 dividing mode
1/4 dividing mode
5.0
1/16 dividing mode
Sleep mode
1.0
0.5
1/2 dividing mode
0.1
(100µA)
0.05
(50µA)
1/4 dividing mode
0.01
(10µA)
1/16 dividing mode
Sleep mode
3
4
5
6
0 1
5
10
15
fc – System clock [MHz]
VDD – Supply voltage [V]
– 28 –
CXP84716/84720/84724
Package Outline
Unit: mm
100PIN QFP (PLASTIC)
+ 0.1
0.15 – 0.05
23.9 ± 0.4
+ 0.4
20.0 – 0.1
A
0.65
+ 0.35
2.75 – 0.15
±0.12
M
0.15
0° to 15°
DETAIL
A
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
EPOXY RESIN
SOLDER PLATING
QFP-100P-L01
SONY CODE
EIAJ CODE
QFP100-P-1420-A
LEAD MATERIAL
COPPER / 42 ALLOY
1.4g
PACKAGE WEIGHT
JEDEC CODE
100PIN LQFP (PLASTIC)
16.0 ± 0.2
14.0 ± 0.1
75
51
76
50
A
26
100
(0.22)
1
25
+ 0.08
0.18 – 0.03
+ 0.05
0.127 – 0.02
0.5 ± 0.08
+ 0.2
1.5 – 0.1
0.1
0.1 ± 0.1
NOTE: Dimension “ ” does not include mold protrusion.
0° to 10°
DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY/PHENOL RESIN
SOLDER PLATING
LQFP-100P-L01
LEAD TREATMENT
LEAD MATERIAL
SONY CODE
EIAJ CODE
QFP100-P-1414-A
42 ALLOY
JEDEC CODE
PACKAGE WEIGHT
– 29 –
相关型号：
CXP847P60Q-1-XXX
Microcontroller, 8-Bit, OTPROM, SPC700 CPU, 16MHz, CMOS, PQFP100, 14 X 20 MM, PLASTIC, QFP-100
SONY
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