CXP88220 [SONY]
CMOS 8-bit Single Chip Microcomputer; CMOS 8位单片机
| 型号： | CXP88220 |
| 厂家： | 
SONY CORPORATION |
| 描述： | CMOS 8-bit Single Chip Microcomputer |
| 文件： | 总25页 (文件大小：479K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CXP88216/88220/88224
CMOS 8-bit Single Chip Microcomputer
Description
100 pin QFP (Plastic)
The CXP88216/88220/88224 is a CMOS 8-bit
microcomputer which consists of A/D converter,
serial interface, timer/counter, time base timer, vector
interruption, high precision timing pattern generation
circuits, PWM generator, PWM for tuner, VISS/VASS
circuit, 32kHz timer/event counter, remote control
receiving circuit, FDP controller/driver, VCR vertical
sync separation circuit and the measuring circuit
which measure signals of capstan FG and drum
FG/PG and other servo systems, as well as basic
configurations like 8-bit CPU, ROM, RAM and I/O
port. They are integrated into a single chip.
Structure
Silicon gate CMOS IC
Also, CXP88216/88220/88224 provides sleep/stop
function which enables to lower power consumption
and ultra-low speed instruction mode in 32kHz
operation.
Features
• A wide instruction set (213 instructions) which cover various types of data
— 16-bit arithmetic instruction/multiplication and division instructions/boolean bit operation instruction
• Minimum instruction cycle
• Incorporated ROM capacity
• Incorporated RAM capacity
• Peripheral function
During operation 250ns/16MHz, During operation 122µs/32kHz
16Kbytes (CXP88216), 20Kbytes (CXP88220), 24Kbytes (CXP88224)
880bytes
— A/D converter
8-bit, 8-channel, successive approximation system
(Conversion time: 20.0µs/16MHz)
— Serial I/O with auto transfer mode
— Timer
Incorporated 8-stage FIFO for data (1 to 8 bytes auto transfer)
8-bit timer/counter, 2-channel, 19-bit time base timer
— High precision timing pattern generation circuit PPG 8 pins 32-stage programmable circuit, RTG 5 pins 2-channel
— PWM/DA gate output
— Servo input control
12-bit, 2-channel (Repetitive frequency 62.5kHz/16MHz)
Capstan FG, Drum FG/PG, CTL input
— VSYNC separator
— FRC capture unit
— PWM output for tuner
— VISS/VASS circuit
Incorporated 26-bit and 8-stage FIFO
14-bit
Pulse duty auto detection circuit
— 32kHz timer/event counter
— Remote control receiving circuit
— FDP controller/driver
32kHz oscillation circuit, ultra-low speed instruction mode
8-bit pulse measuring counter, 6-stage FIFO
Max.148 segments can be displayed
Hardware key scanning function (Max.16 × 3 key matrix available)
PPG 1 pin, RTG 1 pin, output 8 pins
— Tri-state output
— Pseudo HSYNC output function
— High speed head switching circuit
• Interruption
22 factors, 15 vectors, multi-interruption possible
SLEEP/STOP
• Standby mode
• Package
100-pin plastic QFP
• Piggyback/evaluation chip
CXP88100
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E94626-PS
CXP88216/88220/88224
Block Diagram
PORT D
PORT F
PORT E
PORT A
PORT B
PORT C
PORT G
PORT H
PORT I
Vss
VDD
MP
S0 to S7
T8/S15
to
RST
TX
TEX
T15/S8
T0 to T7
VFDP
XTAL
EXTAL
RTO3 to RTO7
PPO0 to PPO7
PE1/INT2
PI4/INT1/NMI
PE0/INT0
INTERRUPT CONTROLLER
AVss
AVREF
AVDD
– 2 –
CXP88216/88220/88224
Pin Configuration (Top View)
100
99 98
96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
97
1
2
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
PB0
PC7/RTO7
PC6/RTO6
PC5/RTO5
PC4/RTO4
PC3/RTO3
PC2
PI6/SO0
PI7/SI0
VFDP
3
4
PD0/S0
PD1/S1
PD2/S2
PD3/S3
PD4/S4
PD5/S5
PD6/S6
PD7/S7
T15/S8
T14/S9
T13/S10
T12/S11
T11/S12
T10/S13
T9/S14
T8/S15
T7
5
6
7
PC1
8
9
PC0
PA7/PPO7
(HAMP) PA6/PPO6
(ROTA) PA5/PPO5
(RF-PLS) PA4/PPO4
PA3/PPO3
PA2/PPO2
PA1/PPO1
PA0/PPO0/HGO
PF7
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
PF6/SI1
PF5/SO1
PF4/SCK1
PF3/AN7
T6
T5
PF2/AN6
T4
PF1/AN5
T3
PF0/AN4
T2
AN3
T1
AN2
T0
AVREF
PE0/INT0 (ENV-DET)
PE1/EC0/INT2
PE2/PWM0
AVSS
AVDD
31
32 33
34
35
36 37 38 39 40
41 42 43 44 45 46
47
48 49 50
Note) 1. NC (Pin 90) is always connected to VDD.
2. Vss (Pins 41 and 88) are both connected to GND.
– 3 –
CXP88216/88220/88224
Pin Description
Symbol
I/O
Description
Pseudo HSYNC
output pin.
PA0/PPO0
/HGO
Output/Real time
output/Output
PA1/PPO1
PA2/PPO2
PA3/PPO3
PA4/PPO4
PA5/PPO5
PA6/PPO6
PA7/PPO7
(Port A)
Programable pattern generator (PPG)
output. Functions as high precision real-
time pulse output port.
8-bit I/O port. Enable to
specify I/O by bit unit.
Data is gated with PPO
content by OR-gate and
they are output.
I/O/
Real time output
(8 pins)
Head switching
output pins.
(8 pins)
Output/
Real time output
8-bit output port. Tri-state can be controlled.
(8 pins)
Output
Output
PB0 to PB7
PC0 to PC2
(Port C)
8-bit I/O port. Enable to
Real-time pulse generator (RTG) output.
Functions as high precision real-time pulse
output port.
(5 pins)
specify I/O by bit unit.
Data is gated with RTO
content by OR-gate and
they are output. (8 pins)
PC3/PPO3
to
PC7/PPO15
Output/
Real time output
Output
T0 to T7
FDP timing signal output pin.
T8/S15
to
T15/S8
Output/Output
Output pins for FDP timing signal and segment signal.
(Port D)
PD0/S0
to
PD7/S7
Output/Output
Input/Input
8-bit output port.
(8 pins)
FDP segment signal output pin.
Trigger pulse
Input pin to request
input pin for head external interruption.
switching output. Active when falling edge.
PE0/INT0
External event
input pin for
timer/counter.
Input pin to request
external interruption.
Active when falling edge.
PE1/EC0/
INT2
Input/Input/Input
(Port E)
8-bit port.
Lower 2 bits are input pins
and upper 6 bits are
output pins.
PE2/PWM0
PE3/PWM1
PE4/DAA0
PE5/DAA1
PE6/DAB0
PE7/DAB1
AN0 to AN3
Output/Output
Output/Output
Output/Output
Output/Output
Output/Output
Output/Output
Input
PWM output pins.
(2 pins)
(8 pins)
DA gate pulse output pins.
(2 pins)
Analog input pins to A/D converter. (8 pins)
PF0/AN0
to
Input/Input
PF3/AN3
(Port F)
Serial clock (CH1) I/O pin.
PF4/SCK1
PF5/SO1
PF6/SI1
PF7
8-bit I/O port. Enable
to specify I/O by bit unit.
(8 pins)
I/O/I/O
I/O/Output
I/O/Input
I/O
Serial data (CH1) output pin.
Serial data (CH1) input pin.
– 4 –
CXP88216/88220/88224
Symbol
PG0/CFG
PG1/DFG
PG2/DPG
I/O
Input/Input
Input/Input
Input/Input
Description
Capstan FG input pin.
Drum FG input pin.
Drum PG input pin.
External event
input pin for
timer/counter.
PG3/
PBCTL/EC1
Input/Input/Input
Input/Input/Input
Playback CTL input pin.
(Port G)
8-bit input port.
(8 pins)
External event
input pin for
timer/counter.
PG4/
SYNC0/EC2
Composite sync signal input pins.
Input/Input
Input/Input
Input/Input
PG5/SYNC1
PG6/EXI0
PG7/EXI1
External input pins for FRC capture unit.
PH0/KR0
to
PH2/KR2
(Port H)
3-bit I/O port.
(3 pins)
Key return input signal for key scanning at FDP
segment signal.
I/O/Input
I/O/Input
I/O/Input
PI1/RMC
PI2/PWM
Remote control receiving circuit input pin.
14-bit PWM output pin.
I/O/Output/Output/
Output
PI3/TO/
DDO/ADJ
Timer/counter, CTL duty detection, 32kHz oscillation
adjustment output pin.
(Port I)
8-bit I/O port.
Enable to
specify I/O by
bit unit.
Input pin to request external interruption,
non-maskable interruption and for serial chip select
(CH0). Active when falling edge.
PI4/INT1/
NMI/CS0
I/O/Input/
Input/Input
(8 pins)
PI5/SCK0
PI6/SO0
PI7/SI0
I/O/Input
I/O/Output
I/O/Input
Input
Serial clock (CH1) I/O pin.
Serial data (CH1) output pin.
Serial data (CH1) input pin.
Connecting pin of crystal oscillator for system clock.
When supplying the external clock, input the external clock to EXTAL
pin and input opposite phase clock to XTAL pin.
EXTAL
XTAL
TEX
TX
Output
Input
Connecting pin of crystal oscillator for 32kHz timer clock.
When used as event counter, input to TEX pin and leave TX pin open.
(Feedback resistor is not removed.)
Output
Input
RST
System reset pin of active "L" level.
MP
Microprocessor mode input pin. Always connect to GND.
Input
Input
FDP voltage supply pin when specifying internal resistor by mask
option.
VFDP
AVDD
AVREF
AVss
VDD
Positive power supply pin of A/D converter.
Reference voltage input pin of A/D converter.
GND pin of A/D converter.
Positive power supply pin.
Vss
GND pin. Connect both Vss pins to GND.
– 5 –
CXP88216/88220/88224
Input/Output Circuit Formats for Pins
Pin
When reset
Circuit format
Port A
HSEL
HOUT
PPO0
MPX
PA0/PPO0/HGO
PA0
Hi-Z
Data bus
RD (Port A)
HSEL
MPX
HOUTE
1 pin
Output becomes active from high impedance
by data writing to port register.
PPO1
PPG control status
register bit 0
Tri-state control selection
PPO1
PA1/PPO1
Hi-Z
PA0
Input
protection
circuit
IP
PA1 direction
(Every bit)
Data bus
1 pin
RD (Port A)
Port A
PPO data
PA2/PPO2
to
PA4/PPO4
Input
protection
circuit
Port A data
Hi-Z
IP
Port A direction
(Every bit)
Data bus
3 pins
RD (Port A)
Port A
PPO data
PA5/PPO5
to
Port A data
Hi-Z
PA7/PPO7
Data bus
RD (Port A)
Output becomes active from high impedance
by data writing to port register.
3 pins
– 6 –
CXP88216/88220/88224
Pin
When reset
Circuit format
Port B
Port B data
PB0
to
PB7
Data bus
Hi-Z
RD (Port B)
Port B tri-state
control
8 pins
Port C
PC0
to
Port C data
Input
protection
circuit
PC2
Hi-Z
IP
Port C direction
(Every bit)
Data bus
3 pins
RD (Port C)
Port C
RTO3
Input
protection
PC3
PC3/RTO3
circuit
PC3 direction
IP
Hi-Z
(Every bit)
Data bus
RD (Port C)
1 pin
Data bus
RD (Port C)
RTO4
RTG interruption
control register bit 7
Tri-state control selection
RTO4
PC3/RTO4
Input
protection
circuit
PC4
Hi-Z
IP
PC4 direction
(Every bit)
Data bus
Data bus
RD (Port C)
1 pin
RD (Port C)
– 7 –
CXP88216/88220/88224
Pin
When reset
Circuit format
Port C
RTO data
PC5/RTO5
to
PC7/RTO7
Input
protection
circuit
Port C data
Port C direction
Hi-Z
IP
(Every bit)
Data bus
3 pins
RD (Port C)
Port D
High voltage drive
transistor
Segment output data
Output selection control signal
("0" when reset)
PD0/S0
to
PD7/S7
Hi-Z
Port D data
Mask option
OP
Data bus
Pull-down resistor
VFDP
RD (Port D)
8 pins
High voltage drive
transistor
Timing output data
Output selection control signal
("0" when reset)
T0 to T7
Hi-Z
Mask option
OP
Pull-down resistor
VFDP
8 pins
High voltage drive
transistor
Timing output data
Output selection control signal
("0" when reset)
T8/S15
to
T15/S8
Segment output data
Hi-Z
OP Mask option
Pull-down resistor
VFDP
8 pins
– 8 –
CXP88216/88220/88224
When reset
Hi-Z
Pin
Circuit format
Port E
Port E
Schmitt input
PE0/INT0
PE1/EC0/INT2
IP
Data bus
2 pins
RD (Port E)
Port E function
select
PE2/PWM0
PE3/PWM1
PE4/DAA0
PE5/DAA1
DA gate output or
PWM output
MPX
Hi-Z
Port E data
Data bus
Hi-Z control
4 pins
RD (Port E)
Port E
Port E function
select
DA gate output
PE6/DAB0
PE7/DAB1
MPX
High level
Port E data
Data bus
Hi-Z control
2 pins
RD (Port E)
Port F
Input multiplexer
IP
PF0/AN4
to
PF3/AN7
To A/D converter
Data bus
Hi-Z
Port F function select
4 pins
RD (Port F)
SCK1 output enable
From serial interface
Port F
MPX
Port F data
PF4/SCK1
IP
Hi-Z
Port F direction
Data bus
RD (Port F)
2 pins
Schmitt input
To serial interface
– 9 –
CXP88216/88220/88224
Pin
When reset
Circuit format
Port F
Port F output selection
From serial interface
MPX
PF5/SO1
Port F data
Hi-Z
Port F direction
IP
Data bus
RD (Port F)
1 pin
To serial interface
Port F
Port F data
Port F direction
PF6/SI1
Hi-Z
Hi-Z
Hi-Z
IP
Data bus
RD (Port F)
Schmitt input
To serial interface
1 pin
Port F
Port F data
PF7
Port F direction
IP
Data bus
RD (Port F)
1 pin
To serial interface
Port G
PG0/CFG
PG1/DFG
PG2/DPG
PG3/PBCTL/
EC1
PG4/SYNC0/
EC2
PG5/SYNC1
PG6/EXI0
PG7/EXI1
Schmitt input
IP
Data bus
RD (Port G)
Note) For PG4/SYNC and PG5/SYNC1, CMOS schmitt input or TTL schmitt input can be
selected with the mask option.
8 pins
– 10 –
CXP88216/88220/88224
Pin
When reset
Circuit format
Port I
Port I function
select
PI2: From 14-bit PWM,
timer/counter
PI3: From CTL duty detection
circuit, 32kHz timer
PI2/PWM
PI3/TO/
MPX
DDO/ADJ
Hi-Z
Port I data
Port I direction
IP
Data bus
2 pins
RD (Port I)
Port I
Port I data
PI1/RMC
PI4/INT1/
NMI/CS0
PI7/SI0
Port I direction
Hi-Z
IP
Data bus
RD (Port I)
PI1: To remote control circuit
PI4: To interruption circuit
PI3: To serial CH0
3 pins
Port I
Port I function
select
From
serial CH0
MPX
PI5/SCK0
PI6/SO0
Port I data
Port I direction
Hi-Z
MPX
IP
Note)
P15 is schmitt input
Data bus
RD (Port I)
To SI0
2 pins
Schmitt input
Port H
Port H data
PH0/KR0
to
PH2/KR2
Port H direction
Hi-Z
IP
Data bus
RD (Port H)
3 pins
Key input signal
– 11 –
CXP88216/88220/88224
Pin
When reset
Circuit format
• Shows the circuit
composition during
oscillation.
EXTAL
XTAL
EXTAL
XTAL
IP
Hi-Z
• Feedback resistor is
removed during stop.
2 pins
• Shows the circuit composition
during oscillation.
TEX
TX
TEX
IP
• Feedback resistor is removed
during 32kHz oscillation circuit
stop by software. At this time
TEX pin outputs "L" level and
TX pin outputs "H" level.
Oscillation
TX
2 pins
Pull-up resistor
Schmitt input
RST
1 pin
Mask option
Hi-Z
or
Pull up
OP
IP
MP
Hi-Z
IP
CPU mode
1 pin
– 12 –
CXP88216/88220/88224
Absolute Maximum Ratings
(Vss = 0V)
Item
Symbol
Rating
Unit
V
Remarks
–0.3 to +7.0
AVss to +7.0
–0.3 to +0.3
–0.3 to +7.0
–0.3 to +7.0
VDD
1
V
Supply voltage
AVDD
AVSS
VIN
V
2
V
Input voltage
2
V
Output voltage
VOUT
As P-channel transistor is open drain,
VDD is reference.
VDD – 40 to VDD + 0.3
V
Display output voltage
VOD
All pins excluding display outputs
(value per pin)
–5
mA
mA
mA
IOH
3
–15
–35
High level output current
IODH1
IODH2
Display outputs S0 to S7 (value per pin)
Display outputs T0 to T7,
and T8/S15 to T15/S8 (value per pin)
–50
–100
mA
mA
mA
mA
°C
∑IOH
∑IODH
IOL
Total for all pins excluding display outputs
Total for all display outputs
High level total
output current
15
Low level output current
130
Low level total output current ∑IOL
Total for all outputs
–20 to +75
–55 to +150
600
Topr
Tstg
PD
Operating temperature
Storage temperature
Allowable power dissipation
1
°C
mW
AVDD and VDD should be set to a same voltage.
VIN and VOUT should not exceed VDD + 0.3V.
It specifies output current of general-purpose I/O port.
2
3
Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should
better take place under the recommended operating conditions. Exceeding those conditions may
adversely affect the reliability of the LSI.
– 13 –
CXP88216/88220/88224
Recommended Operating Conditions
(Vss = 0V)
Item
Symbol
Min.
4.5
Max.
5.5
Unit
V
Remarks
Guaranteed range during high speed mode
(1/2 dividing clock) operation
Guaranteed range during low speed mode
(1/16 dividing clock) operation
3.5
2.7
2.5
5.5
5.5
5.5
Supply voltage
VDD
Guaranteed operation range by TEX clock
Guaranteed data hold operation range
during STOP
1
AVDD
VIH
4.5
0.7VDD
0.8VDD
2.2
5.5
VDD
VDD
VDD
Analog power supply
High level input voltage
V
V
2
3
CMOS schmitt input
VIHS
VIHTS
VIHEX
VIL
V
4
TTL schmitt input
V
5
6
EXTAL pin
TEX pin
VDD – 0.4 VDD + 0.3
V
2
0
0
0.3VDD
0.2VDD
0.8
V
3
CMOS schmitt input
VILS
V
Low level input voltage
Operating temperature
4
TTL schmitt input
VILTS
VILEX
Topr
0
V
5
6
–0.3
–20
0.4
EXTAL pin
TEX pin
V
+75
°C
1
AVDD and VDD should be set to a same voltage.
2
3
Normal input port (each pin of PA1 to PA4, PC, PF0 to PF3, PF5, PF7, PH, PI2, PI3 and PI6), MP pin
Each pin of RST, PE0/INT0, PE1/EC0/INT2, PF4/SCK1, PF6/SI1, PI1/RMC, PI4/CS0/NMI/INT1, PI5/SCK0,
PI7/SI1 and PG (For PG4 and PG5, when CMOS schmitt input is selected with mask option)
Each pin of PG4 and PG5 (When TTL schmitt input is selected with mask option)
It specifies only when the external clock is input.
4
5
6
It specifies only when the external event is input.
– 14 –
CXP88216/88220/88224
DC Characteristics
(Ta = –20 to +75°C, Vss = 0V)
Item
Symbol
Pin
Condition
VDD = 4.5V, IOH = –0.5mA
VDD = 4.5V, IOH = –1.2mA
VDD = 4.5V, IOL = 1.8mA
VDD = 4.5V, IOL = 3.6mA
Typ.
Max.
Unit
V
Min.
4.0
PA to PC, PE
PF4 to PF7,
PH,
High level
output voltage
VOH
VOL
3.5
V
PI1 to PI7,
0.4
0.6
V
Low level
output voltage
1
RST
V
(VOL only)
–8
mA
S0 to S7
Display
output current
VDD = 4.5V,
VOH = VDD – 2.5V
S8/T15 to
S15/T8,
IOH
–20
mA
µA
T0 to T7
S0 to S7,
S8/T15 to
S15/T8,
Open drain
output leakage
current (P-CH
Tr OFF in
VDD = 5.5V,
VOL = VDD – 35V
VFDP = VDD – 35V
–20
270
ILOL
RL
T0 to T7
S0 to S7,
S8/T15 to
S15/T8,
VDD = 5V,
VOD – VFDP = 30V
Pull-down
60
100
kΩ
3
resistor
T0 to T7
VDD = 5.5V, VIH = 5.5V
VDD = 5.5V, VIL = 0.4V
VDD = 5.5V, VIH = 5.5V
0.5
–0.5
0.1
40
–40
10
µA
µA
µA
µA
µA
IIHE
EXTAL
TEX
Input
current
IILE
IILR
–0.1
–1.5
–10
–400
VDD = 5.5V,
VIL = 0.4V
2
RST
PA to PC,
PE to PI,
AN1 to AN3,
MP,
I/O leakage
current
IIZ
±10
µA
VDD = 5.5V, VI = 0, 5.5V
2
RST
16MHz crystal oscillation (C1 = C2 = 15pF),
VDD = 5V ± 10%
23
1.2
38
7
45
8
mA
mA
µA
µA
µA
IDD1
5
16MHz crystal oscillation (C1 = C2 = 15pF),
VDD = 5V ± 10%, SLEEP mode
IDDS1
IDD2
Supply
current
32kHz crystal oscillation (C1 = C2 = 47pF),
VDD = 3V ± 10%
100
30
10
VDD, Vss
4
32kHz crystal oscillation (C1 = C2 = 47pF),
VDD = 3V ± 10%, SLEEP mode
IDDS2
IDDS3
VDD = 5.5V, STOP mode
(32kHz, 16MHz oscillation stop)
Other than
S0 to S15,
T0 to T7,
Clock 1MHz
0V other than the measured pins
Input
capacity
PA0,
10
20
pF
CIN
PA5 to PA7
PE2 to PE7
PB, VDD, Vss
AVDD, AVss
– 15 –
CXP88216/88220/88224
1
2
RST pin is specified when evaluation mode is in use.
RST pin specifies the input current when the pull-up resistor is selected, and specifies leakage current
when non-resistor is selected.
3
4
5
When built-in pull-down resistor is selected with mask option.
When entire output pins are open.
When setting upper 2 bits (CPU clock selection) of clock control register CLC (address: 0002FEH) to "00"
and operating in high speed mode (1/2 dividing clock).
AC Characteristics
(1) Clock timing
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)
Item
Symbol
Pin
Condition
Fig. 1, Fig. 2
Min.
1
Typ.
Max. Unit
XTAL
EXTAL
MHz
ns
16
200
20
System clock frequency
fC
Fig. 1, Fig. 2
External clock drive
t
XL,
XH
XTAL
EXTAL
28
System clock input pulse width
t
Fig. 1, Fig. 2
External clock drive
System clock input rise and
fall times
XTAL
EXTAL
t
CR,
CF
ns
t
Event count clock input
pulse width
EC0, EC1,
EC2
t
EH,
EL
Fig. 3
Fig. 3
ns
tsys + 200
t
Event count clock input
rise and fall times
EC0, EC1,
EC2
t
ER,
EF
ms
t
VDD = 2.7 to 5.5V
Fig. 2 (32kHz clock
applying condition)
TEX
TX
kHz
32.768
System clock frequency
fC
Event count clock input
pulse width
t
TL,
Fig. 3
Fig. 3
µs
10
TEX
TEX
tTH
Event count clock input
rise and fall times
tTR,
TF
ms
20
t
tsys indicates three values according to the contents of the clock control register (address; 00FEH) upper
2 bits (CPU clock selection).
tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")
Fig. 1. Clock timing
1/fc
VDD – 0.4V
0.4V
EXTAL
XTAL
tXH
tCF
tXL
tCR
Fig. 2. Clock applying condition
Crystal oscillation
Ceramic oscillation
32kHz clock applying condition
Crystal oscillation
External clock
EXTAL
XTAL
EXTAL
XTAL
TEX
TX
C1
C2
C1
C2
74HC04
– 16 –
CXP88216/88220/88224
Fig. 3. Event count clock timing
TEX
EC0
EC1
EC2
0.8VDD
0.2VDD
tEH
tTH
tEF
tTF
tEL
tTL
tER
tTR
(2) Serial transfer (CH0)
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)
Item
CS0 ↓ → SCK0
Symbol
Pin
Condition
Min.
Max.
Unit
ns
Chip select transfer mode
(SCK0 = output mode)
t
t
t
t
t
DCSK
SCK0
tsys + 200
delay time
CS0 ↑ → SCK0
floating delay time
Chip select transfer mode
(SCK0 = output mode)
ns
ns
ns
ns
DCSKF SCK0
DCSO SO0
DCSOF SO0
WHCS CS0
tsys + 200
tsys + 200
tsys + 200
CS0 ↓ → SO0
delay time
Chip select transfer mode
Chip select transfer mode
Chip select transfer mode
CS0 ↑ → SO0
floating delay time
CS0
high level width
tsys + 200
Input mode
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2tsys + 200
16000/fc
tsys+100
8000/fc – 50
100
SCK0
cycle time
t
KCY
SCK0
SCK0
SI0
Output mode
Input mode
t
KH
KL
SCK0
t
high and low level widths
Output mode
SCK0 input mode
SCK0 output mode
SCK0 input mode
SCK0 output mode
SCK0 input mode
SCK0 output mode
SI0 input set-up time
(against SCK0 ↑)
t
t
t
SIK
200
tsys + 200
100
SI0 input hold time
(against SCK0 ↑)
KSI
SI0
tsys + 200
100
KSO
SCK0 ↓ → SO0 delay time
SO0
Note 1) tsys indicates three values according to the contents of the clock control register (address; 00FEH)
upper 2 bits (CPU clock selection).
tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")
Note 2) The load of SCK0 output mode and SO0 output delay time is 50pF + 1TTL.
– 17 –
CXP88216/88220/88224
Fig. 4. Serial transfer CH0 timing
tWHCS
0.8VDD
CS0
0.2VDD
tKCY
tDCSK
tDCSKF
tKL
tKH
0.8VDD
0.8VDD
0.2VDD
SCK0
tKSI
tSIK
0.8VDD
Input data
SI0
0.2VDD
tDCSO
tKSO
tDCSOF
0.8VDD
0.2VDD
Output data
SO0
– 18 –
CXP88216/88220/88224
Serial transfer (CH1)
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)
Item
Symbol
Pin
Condition
Input mode
Min.
1000
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCK1 cycle time
t
KCY
SCK1
Output mode
16000/fc
400
Input mode
SCK1 high and low
level widths
t
t
KH
KL
SCK1
SI1
Output mode
8000/fc – 50
100
SCK1 input mode
SCK1 output mode
SCK1 input mode
SCK1output mode
SCK1 input mode
SCK1 output mode
SI1 input set-up time
(against SCK1 ↑)
t
t
t
SIK
200
200
SI1 input hold time
(against SCK1 ↑)
KSI
SI1
100
200
100
SCK1 ↓ → SO1 delay time
KSO
SO1
Note) The load of SCK1 output mode and SO1 output delay time is 50pF + 1TTL.
Fig. 5. Serial transfer CH1 timing
tKCY
tKL
tKH
0.8VDD
0.2VDD
SCK1
tSIK
tKSI
0.8VDD
0.2VDD
SI1
Input data
tKSO
0.8VDD
0.2VDD
Output data
SO1
– 19 –
CXP88216/88220/88224
(3) A/D converter characteristics
(Ta = –20 to +75°C, VDD = AVDD = 4.5 to 5.5V, AVREF = 4.0 to AVDD, Vss = AVss =
Item
Resolution
Symbol
Pin
Max.
8
Unit
Bits
Typ.
Condition
Min.
Only for A/D converter
operation
Ta = 25°C
VDD = AVDD = AVREF =
5.0V
LSB
LSB
Linearity error
Absolute error
±1
±2
t
CONV
SAMP
Conversion time
Sampling time
µs
µs
V
160/fADC
12/fADC
AVDD – 0.5
0
t
VREF
VIAN
VDD = AVDD = 4.5 to 5.5V
AVREF
Reference input voltage
Analog input voltage
AVDD
AN0 to AN7
AVREF
V
Operation mode
AVREF = 4.0 to 5.5V
mA
0.6
1.0
10
AVREF current
IREF
AVREF
SLEEP mode
STOP mode
µA
32kHz operation mode
Fig. 6. Definitions of A/D converter terms
FFH
FEH
The value of fADC is as follows by selecting ADC
operation clock (MSC: Address 01FEH bit 0).
When PS2 is selected, fADC = fc/2
When PS1 is selected, fADC = fc
Linearity error
01H
00H
VZT
VFT
Analog input
– 20 –
CXP88216/88220/88224
(4) Interruption, reset input
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)
Item
Symbol
Pin
INT0
Condition Min.
Max.
Unit
External interruption high and
low level widths
t
IH
IL
INT1
INT2
NMI
1
µs
t
Reset input low level width
32/fc
µs
tRSL
RST
Fig. 7. Interruption input timing
tIH
tIL
INT0
0.8VDD
INT1
INT2
0.2VDD
NMI
(Falling edge)
Fig. 8. Reset input timing
tRSL
RST
0.2VDD
(5) Others
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)
Item
Symbol
Pin
Condition
Min.
Max.
Unit
ns
tCFH
CFL
CFG input high and
low level widths
CFG
t
FRC × 24 + 200
t
t
DFH
DFL
DFG input high and
low level widths
ns
ns
ns
DFG
DPG
DPG
t
FRC × 16 + 200
t
t
FRC × 8 + 200
tDPW
DPG minimum pulse width
DPG minimum removal time
tFRC × 16 + 200
trem
t
CTH
CTL
PBCTL input high and low
level widths
PBCTL
ns
ns
t
t
FRC × 8 + tsys + 200
FRC × 8 + tsys + 200
tsys = 2000/fc
tsys = 2000/fc
t
EXI0
EXI1
tEIH
EIL
EXI input high and low level
widths
t
Note 1) tsys indicates three values according to the contents of the clock control register (address; 00FEH)
upper 2 bits (CPU clock selection).
tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")
Note 2) tFRC = 1000/fc (ns)
– 21 –
CXP88216/88220/88224
Fig.9. Other timings
tCFH
tCFL
0.8VDD
CFG
0.2VDD
tDFH
tDFL
0.8VDD
DFG
0.2VDD
trem
tDPW
trem
0.8VDD
DPG
tCTH
tCTL
0.8VDD
PBCTL
0.2VDD
tEIH
tEIL
0.8VDD
EXI0
EXI1
0.2VDD
– 22 –
CXP88216/88220/88224
Supplement
Fig.10. Recommended oscillation circuit
(i)
(ii)
EXTAL
XTAL
Rd
TEX
TX
Rd
C2
C1
C2
C1
Circuit
example
Manufacturer
Model
fc (MHz)
C1 (pF)
10
C2 (pF)
Rd (Ω)
8.00
10.00
10
15
RIVER
ELETEC
CO., LTD.
HC-49/U03
0
(i)
12.00
15
16.00
8.00
16 (12)
16 (12)
12
16 (12)
16 (12)
12
0
10.00
(i)
HC-49/U (-S)
P3
KINSEKI LTD.
12.00
0
0
16.00
12
12
32.768kHz
30
(ii)
18
470k
Mask option table
Content
Item
Reset pin pull-up resistor
Non-existent
Non-existent
CMOS schmitt
Existent
High voltage drive output port pull-down resistor
Input circuit format
Existent
TTL schmitt
In PG4/SYNC0/EC2 pin and PG5/SYNC1 pin, the input circuit format can be selected every pin.
– 23 –
CXP88216/88220/88224
Characteristics Curve
IDD vs. fc
(VDD = 5V, Ta = 25°C, Typical)
IDD vs. VDD
(fc = 16MHz, Ta = 25°C, Typical)
1/2 dividing mode
20.0
10.0
5.0
1/2 dividing mode
1/4 dividing mode
1/16 dividing mode
20
15
10
5
SLEEP mode
1.0
0.5
1/4 dividing mode
32kHz mode
(Instruction)
0.1
(100µA)
32kHz
SLEEP mode
0.05
(50µA)
1/16 dividing mode
0.01
(10µA)
SLEEP mode
16
0
5
10
2
3
4
5
6
7
fc – System clock [MHz]
VDD – Supply voltage [V]
– 24 –
CXP88216/88220/88224
Package Outline
Unit: mm
100PIN QFP (PLASTIC)
+ 0.1
0.15 – 0.05
23.9 ± 0.4
+ 0.4
20.0 – 0.1
A
0.65
+ 0.35
2.75 – 0.15
±0.12
M
0.15
0° to 15°
DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
EPOXY RESIN
SOLDER PLATING
QFP-100P-L01
SONY CODE
QFP100-P-1420-A
EIAJ CODE
LEAD MATERIAL
COPPER / 42 ALLOY
1.4g
PACKAGE WEIGHT
JEDEC CODE
– 25 –
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