CXP88624 [SONY]
CMOS 8-bit Single Chip Microcomputer; CMOS 8位单片机
| 型号： | CXP88624 |
| 厂家： | 
SONY CORPORATION |
| 描述： | CMOS 8-bit Single Chip Microcomputer |
| 文件： | 总31页 (文件大小：404K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CXP88616/88624
CMOS 8-bit Single Chip Microcomputer
Description
The CXP88616/88624 is a CMOS 8-bit micro-
computer which consists of A/D converter, serial
interface, timer/counter, time base timer, high
precision timing pattern generation circuits, PWM
output, VISS/ VASS circuit, remote control receiving
circuit, VSYNC separator and the measurement
circuit which measure signals of capstan FG
amplifier and drum FG/PG amplifier and other servo
systems, as well as basic configurations like 8-bit
CPU, ROM, RAM and I/O port. They are integrated
into a single chip.
100 pin QFP (Plastic)
Structure
Silicon gate CMOS IC
Also, CXP88616/88624 provides sleep/stop function
which enables to lower power consumption.
Features
• A wide instruction set (213 instructions) which cover various types of data
— 16-bit arithmetic/multiplication and division/boolean bit operation instructions
• Minimum instruction cycle
• Incorporated ROM capacity
250ns at 16MHz operation
16K bytes (CXP88616)
24K bytes (CXP88624)
• Incorporated RAM capacity
• Peripheral function
— A/D converter
672 bytes (including PPG RAM)
8 bits, 14 channels, successive approximation system
(Conversion time of 20µs/16MHz)
Incorporated 8-bit, 8-stage FIFO for data
(Auto transfer for 1 to 8 bytes), 1 channel
8-bit timer/counter, 2 channels
19-bit time base timer
— Serial interface
— Timer
— High precision timing pattern generation PPG 19 pins 32-stage programmable circuit
RTG 5 pins, 1 channel
5-bit, 8-satge FIFO (RECCTL control), 1channel
12 bits, 2 channels (Repetitive frequency 62.5kHz/16MHz)
— PWM/DA gate output
DA gate pulse output, 13 bits, 2 channels
Capstan FG amplifier circuit
Drum FG amplifier circuit
— Analog signal input circuit
Drum PG amplifier circuit
PBCTL amplifier circuit
— CTL write/rewrite circuit
— Servo input control
— VSYNC separator
Recording current control circuit
Capstan FG, Drum FG/PG, CTL input
— FRC capture unit
— VISS/VASS circuit
Incorporated 26-bit and 8-stage FIFO
Pulse duty auto detection circuit
— 32kHz timer/event counter
— Remote control reception circuit
— Tri-state output
32kHz oscillation circuit, ultra-low speed instruction mode
8-bit pulse measurement counter, 6-stage FIFO
PPG 1 pin, output 8 pins
— Pseudo HSYNC output function
— High speed head switching circuit
• Interruption
20 factors, 15 vectors, multi-interruption possible
SLEEP/STOP
• Standby mode
• Package
100-pin plastic QFP
• Piggyback/evaluation chip
CXP88800 100-pin ceramic QFP
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E96108-ST
CXP88616/88624
A T R O P
B T R O P
C T R O P
D T R O P
E T R O P
F T R O P
G T R O P
H T R O P
I T R O P
s s V
D D V
P M
T S R
L A T X
L A T X E
7 O T R o t 3 O T R
8 1 O P P o t 0 O P P
2 T N I
I M N / 1 T N I
0 T N I
R E L L O R T N O C T P U R R E T N I
s s V A
S S V P M A
F E R V A
D D V A
D D V P M A
– 2 –
CXP88616/88624
Pin Assignment (Top View)
100
99 98
96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
97
PB5/PPO13
PB4/PPO12
PB3/PPO11
PB2/PPO10
PB1/PPO9
PB0/PPO8
PC7/RTO7
PC6/RTO6
PC5/RTO5
PC4/RTO4
PC3/RTO3
PC2/PPO18
PC1/PPO17
PC0/PPO16
PI7
1
2
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
PE5/EXI1
PE6/PWM0/DAA0
PE7/PWM1/DAA1
CFG
3
4
5
DFG
6
DPG
7
VREFOUT
AMPVSS
CTLSAMPI
CTLFAMPO
CTLAG
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CTLAMP (+)
CTLAMP (–)
CTLCIN (–)
CTLCIN (+)
RECCTL (+)
RECCTL (–)
AMPVDD
RECCAP
VDD
PI6
PI5
PI4
PI3
PI2
PI1/EC/INT2
PI0/INT0/ENV-DET
PD7/SI0
AN0/ANOUT
AN1
AN2
PD6/SO0
AN3
PD5/SCK0
PD4/CS0
PF0/AN4
PF1/AN5
AVDD
PD3/TO/DDO/ADJ/SRVO
PD2
AVREF
PD1/RMC
PD0/INT1/NMI
AVSS
PF2/AN6
31
32 33
34
35
36 37 38 39 40 41 42
43 44 45 46
47
48 49 50
Note) 1. NC (Pin 90) is always connected to VDD. NC (Pins 86 and 87) are left open.
2. VDD (Pins 61 and 89) are both connected to VDD
3. Vss (Pins 41 and 88) are both connected to GND.
4. MP (Pin 39) must be connected to GND.
– 3 –
CXP88616/88624
Pin Description
Symbol
I/O
Description
(Port A)
PA0/PPO0
/HGO
Output/Real-time
output/Output
Pseudo HSYNC output pin.
8-bit output port. Data is
gated with PPO contents
by OR-gate and they are
output.
PA1/PPO1
to
PA7/PPO7
Output/
Real-time output
(8 pins)
(Port B)
8-bit output port. Data is
gated with PPO contents
by OR-gate and they are
output.
Tri-state control is possible.
(8 pins)
Programmable pattern generator (PPG)
output. Functions as high precision real-
time pulse output port.
PB0/PPO8
to
PB7/PPO15
Output/
Real-time output
(19 pins)
PA0 can be tri-state controlled with PPG.
PC0/PPO16
to
PC2/PPO18
(Port C)
I/O/
8-bit output port. I/O can be
set in a unit of single bits.
Data is gated with PPO or
RT contents by OR-gate
and they are output.
(8 pins)
Real-time output
Real-time pulse generator (RTG) output.
Functions as high precision real-time
pulse output port.
PC3/RTO3
to
PC7/RTO7
I/O/
Real-time output
(5 pins)
Input pin to request external interruption
and non-maskable interruption.
PD0/INT1/
NMI
I/O/Input/Input
Remote control receiving circuit input pin.
I/O/Input
I/O
PD1/RMC
PD2
Timer/counter, CTL duty detector and
servo amplifier output pin.
I/O/Output/Output/
Output
PD3 /TO
DDO/SRVO
(Port D)
8-bit output port. I/O can be
set in a unit of single bits.
(8 pins)
Serial chip select (CH0) input pin.
Serial clock (CH0) I/O pin.
I/O/Input
I/O/I/O
PD4/CS0
PD5/SCK0
Serial data (CH0) output pin.
Serial data (CH0) input pin.
I/O/Output
I/O/Input
Output
PD6/SO0
PD7/SI0
PE0
Output
PE1
Input
PE2
(Port E)
Composite sync signal input pin.
Input/Input
Input/Input
Input/Input
PE3/SYNC
PE4/EXI0
PE5/EXI1
8-bit port. Bits 2, 3, 4 and 5
are for inputs; bits 0, 1, 6
and 7 are for outputs.
(8 pins)
External input pin for FRC capture unit.
(2 pins)
PE6/PWM0/
DAA0
Output/Output
Output/Output
DA gate pulse
PWM output pin.
output pin.
(2 pins)
PE7/PWM1/
DAA1
(2 pins)
– 4 –
CXP88616/88624
Description
Description
AN0/ANOUT
AN1 to AN3
I/O
Input/Output
Input
Analog circuit internal
waveform output pin.
PF0/AN4
to
PF3/AN7
(Port F)
Input/Input
Output/Input
Input/Input
Lower 4 bits are for inputs; upper 4 bits are for
outputs. Lower 4 bits are standby release input
pins.
(8 pins)
Analog input pin for
A/D converter.
(14 pins)
PF4/AN8
to
PF7/AN11
(Port G)
2-bit input port.
(2 pins)
PG0/AN12
PG1/AN13
(Port H)
8-bit output port; N-ch open drain output of medium drive voltage (12V)
and large current (12mA).
(8 pins)
PH0 to PH7
Output
Input pin to request
Trigger pulse input
external interruption.
Active when falling
edge.
PI0/INT0/
ENV-DET
(Port I)
pin for head
switching.
I/O/Input
8-bit I/O port. I/O can be
set in a unit of single bits.
Function as standby
release input can be set in
a unit of single bits.
(8 pins)
Input pin to request
External event input external interruption.
pin for timer/counter. Active when falling
edge.
PI1/EC/
INT2
I/O/Input/Input
PI2 to PI7
CFG
I/O
Capstan FG input pin.
Drum FG input pin.
Drum PG input pin.
Input
Input
Input
DFG
DPG
PBCTL signal input pin.
(2 pins)
RECCTL (+)
RECCTL (–)
RECCTL signal output pin.
(2 pins)
I/O
CTLCIN (+)
CTLCIN (–)
Connected to RECCTL (+) and RECCTL (–) with the internal switch for
playback. (2 pins)
Output
Input
CTLAMP (+)
CTLAMP (–)
Input PBCTL signal with capacitor coupled.
(2 pins)
CTLFAMPO
CTLSAMPI
PBCTL signal 1st amplifier output.
PBCTL signal 2nd amplifier input.
Output
Input
Capacitor connecting pin for the slope setting of the CTL writing
trapezoidal wave.
RECCAP
I/O
Capacitor connecting pin for the VREF level smoothing of DPG, DFG
and CFG.
VREFOUT
Output
Output
CTLAG
AMPVSS
AMPVDD
Capacitor connecting pin for the CTL and AGND smoothing.
Analog signal input circuit GND pin.
Analog signal input circuit power supply pin.
– 5 –
CXP88616/88624
Symbol
EXTAL
I/O
Description
Input
Connecting pin of crystal oscillator for system clock. When supplying
the external clock, input it to EXTAL pin and input the opposite phase
clock to XTAL pin.
XTAL
Output
Input
System reset pin; Low level active.
RST
NC
NC pin. Connect Pin 90 to VDD and leave Pins 86 and 87 open.
Test mode input pin. Always connect to GND.
Positive power supply pin for A/D converter.
Reference voltage input pin for A/D converter.
GND pin for A/D converter.
Input
Input
MP
AVDD
AVREF
AVSS
VDD
Positive power supply pin.
GND pin. Connect both Vss pins to GND.
VSS
– 6 –
CXP88616/88624
Input/Output Circuit Formats for Pins
Pin
When reset
Circuit format
Port A
HOUT
PPO0
MPX
PA0/PPO0/
HGO
PA0
Hi-Z
1 pin
Data bus
RD (Port A)
HSEL
MPX
HOUTE
Output becomes active from high impedance by
data writing to port.
PPO1
PPG control status register bit 0
Tri-state control selection
PPO1
PA1
PA1/PPO1
1 pin
Hi-Z
Data bus
RD (Port A)
Output becomes active from high impedance by data
writing to port.
Port A
PPO data
PA2/PPO2
to
PA7/PPO7
Port A data
Hi-Z
Data bus
RD (Port A)
Output becomes active from high impedance
by data writing to port.
6 pins
Port B
RTO data
PB0/PPO8
to
PB7/PPO15
Port B data
Data bus
Hi-Z
RD (Port B)
Port B tri-state
control
8 pins
– 7 –
CXP88616/88624
Circuit format
Pin
When reset
Port C
PPO, RTO data
Port C data
PC0/PPO16
to
PC2/PPO18
Input protection circuit
Port C direction
PC3/RTO3
to
Hi-Z
IP
PC7/RTO7
Data bus
RD (Port C)
8 pins
RD (Port C direction)
Port D
Port D data
PD0/INT1/
NMI
PD1/RMC
PD4/CS0
PD7/SI0
Port D direction
Hi-Z
IP
Data bus
RD (Port D)
Schmitt input
PD1...Remote control circuit
PD0...Interruption circuit
PD4, 7...Serial CH0
4 pins
Port D
Port D data
PD2
Hi-Z
Port D direction
IP
Data bus
1 pin
RD (Port D)
Port D
Port D function
select
PD3... Timer/counter, CTL duty
detection circuit,
32kHz timer,
amplifier circuit
PD3/TO/
DDO/SRVO
MPX
Hi-Z
Port D data
Port D direction
IP
Data bus
4 pins
RD (Port D)
– 8 –
CXP88616/88624
Circuit format
Pin
When reset
Port D
Port D function
select
PD5/SCK0
PD6/SO0
SI0
CH0
MPX
Port D data
Port D direction
Hi-Z
MPX
IP
Note)
PD5 is schmitt input
PD6 is inverter input
Data bus
RD (Port D)
2 pins
SI0 CH0
Port E
PE0
PE1
Port E data
Hi-Z
Data bus
Hi-Z control
RD (Port E)
2 pins
Port E
Schmitt input
IP
PE2
Data bus
Hi-Z
RD (Port E)
1 pin
Port E
Schmitt input
PE3
IP
PE4 Servo input
PE5
PE3/SYNC
PE4/EXI0
PE5/EXI1
Hi-Z
Data bus
RD (Port E)
Note) For PE3/SYNC, CMOS schmitt input or TTL schmitt input can be selected
with the mask option.
3 pins
– 9 –
CXP88616/88624
Pin
Circuit format
When reset
Port E
Port/DA/PWM
select
PE6/PWM0/
DAA0
PE7/PWM1/
DAA1
DA gate output or
PWM output
MPX
High level
Port E data
Data bus
Hi-Z control
2 pins
RD (Port E)
Input multiplexer
IP
A/D converter
AN0/ANOUT
Hi-Z
From amplifier circuit
Analog output control
1 pin
AN1
to
Input multiplexer
AN3
Hi-Z
Hi-Z
A/D converter
A/D converter
IP
3 pins
Port F
Input multiplexer
PF0/AN4
to
PF3/AN7
IP
Data bus
RD (Port F)
4 pins
Port F
Port F data
PF4/AN8
to
PF7/AN11
Data bus
Hi-Z
IP
RD (Port F)
Port/AD select
A/D converter
Input multiplexer
4 pins
– 10 –
CXP88616/88624
Pin
Circuit format
When reset
Port G
Input multiplexer
PG0/AN12
to
A/D converter
IP
PG1/AN13
Hi-Z
Data bus
RD (Port G)
2 pins
Port H
Medium drive
voltage12 V
PH0
to
PH7
Port H data
Hi-Z
Large current 12mA
Data bus
8 pins
RD (Port H)
Port I data
Port I
PI0/INT0/
EVN-DET
Port I direction
RD (Port I)
IP
PI1/EC/INT2
Data bus
Hi-Z
Edge detection
Standby release
Interruption circuit
Data bus
2 pins
RD (Port I direction)
Port I
Port I data
PI2
to
Port I direction
PI7
IP
Hi-Z
Data bus
RD (Port I)
Edge detection
Standby release
Data bus
6 pins
RD (Port I direction)
– 11 –
CXP88616/88624
Pin
When reset
Circuit format
CTLAMP (+)
CTLAMP (–)
CTLFAMPO
CTLAG
CTLAMP (+)
IP
1/2AMPVDD
1/2AMPVDD
1/2AMPVDD
IP
CTLFAMPO
CTLAMP (–)
3 pins
Input pin charge control
Input pin charge control
IP
CTLSAMPI
LPF circuit
CTLAG
1 pin
CFG
DFG
DPG
Input pin charge control
IP
LPF circuit
VREFOUT
3 pins
AMPVDD
CTLAG
VREFOUT
1/2AMPVDD
IP
AMPVSS VREFOUT...CFG, DFG,
DPG amplifiers
CTLAG........ CTL amplifier
2 pins
– 12 –
CXP88616/88624
Pin
Circuit format
When reset
AMPVDD
Recording current
control circuit
Write current select
RTO6
RECCTL (+)
Hi-Z
IP
RTO7
RTO3
CTLCIN (+) pin
AMPVSS
AMPVDD
RTG control permission
1 pin
Recording current
control circuit
Write current select
RTO7
RECCTL (–)
Hi-Z
IP
RTO6
RTO3
CTLCIN (–) pin
AMPVSS
1 pin
RTG control permission
From RECCTL (+) pin
IP
CTLCIN (+)
1 pin
RTO3
Hi-Z
RTG control permission
AMPVSS
From RECCTL (–) pin
IP
CTLCIN (
–)
Hi-Z
RTO3
RTG control permission
1 pin
AMPVSS
RTG control permission
RTO5
RECCAP
1 pin
Low level
IP
Recording current control circuit
– 13 –
CXP88616/88624
Pin
When reset
Circuit format
• Shows the circuit
composition during
oscillation.
EXTAL
XTAL
EXTAL
XTAL
IP
Oscillation
• Feedback resistor is
removed and XTAL
becomes High level
during stop.
2 pins
Mask option
Pull up resistor
Schmitt input
RST
1 pin
Low level
OP
IP
– 14 –
CXP88616/88624
Absolute Maximum Ratings
(Vss = 0V reference)
Remarks
Item
Symbol
VDD
Rating
–0.3 to +7.0
AVss to +7.0
–0.3 to +0.3
Unit
V
1
V
AVDD
AVSS
V
Supply voltage
2
V
AMPVDD AMPVSS to +7.0
V
AMPVSS
VIN
–0.3 to +0.3
–0.3 to +7.0
–0.3 to +7.0
3
V
Input voltage
3
V
Output voltage
VOUT
VOUTP
IOH
V
Medium drive output voltage
High level output current
High level total output current
–0.3 to +15.0
Port H
mA
mA
–5
∑IOH
–50
Total of output pins
Other than large current output
ports (value per pin)
mA
mA
IOL
15
20
Low level output current
4
Large current output port
IOLC
(value per pin)
Low level total output current
Operating temperature
∑IOL
Topr
Tstg
PD
mA
°C
130
–20 to +75
–55 to +150
600
Total of output pins
Storage temperature
°C
Allowable power dissipation
mW
QFP package type
1) AVDD and VDD must not exceed +0.3V.
2) AMPVDD and VDD must not exceed +0.3V.
3) VIN and VOUT must not exceed VDD +0.3V.
4) The large current output port is port H (PH).
Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should
better take place under the recommended operating conditions. Exceeding those conditions may
adversely affect the reliability of the LSI.
– 15 –
CXP88616/88624
Recommended Operating Conditions
(Vss = 0V reference)
Item
Symbol
Min.
4.5
Max.
5.5
Unit
V
Remarks
Guaranteed operation range for 1/2 and 1/4
frequency dividing clock
Guaranteed operation range for 1/16 frequency
dividing clock or during SLEEP mode
VDD
3.5
2.5
5.5
5.5
Supply voltage
Guaranteed data hold operation range
during STOP
1
2
3
V
V
V
V
V
V
V
V
V
V
°C
AVDD
AMPVDD
VIH
5.5
5.5
4.5
4.5
Analog power supply
High level input voltage
0.7VDD
0.8VDD
2.2
VDD
VDD
VDD
4
VIHS
CMOS schmitt input
5
VIHTS
VIHEX
VIL
TTL schmitt input
6
EXTAL pin
VDD – 0.4 VDD + 0.3
3
0
0
0.3VDD
0.2VDD
0.8
4
VILS
CMOS schmitt input
Low level input voltage
Operating temperature
5
VILTS
VILEX
Topr
TTL schmitt input
0
6
EXTAL pin
–0.3
–20
0.4
+75
1) AVDD and VDD should be set to the same voltage.
2) AMPVDD and VDD should be set to the same voltage.
3) Normal input port (each pin of PC, PD2, PD3, PD6, PF0 to PF3, PG and PI2 to PI7), MP pin
4) Each pin of RST, PD0/INT1/NMI, PD1/RMC, PD4/CS0, PD5/SCK0, PD7/SI0, PE2, PE3/SYNC, PE4/EXI0,
PE5/EXI1, PI0/INT0, PI1/EC/INT2 (For PE3/SYNC, when CMOS schmitt input is selected with mask
option.)
5) PE3/SYNC (when TTL schmitt input is selected with mask option.)
6) Specifies only during external clock input.
– 16 –
CXP88616/88624
Electrical Characteristics
DC Characteristics (VDD = 4.5 to 5.5V)
(Ta = –20 to +75°C, Vss = 0V reference)
Item
Symbol
Pins
Conditions
Min.
4.0
Typ.
Max. Unit
VDD = 4.5V, IOH = –0.5mA
PA to PD,
PE0 to PE1,
PE6 to PE7,
PF4 to PF7,
PH (VOL only)
PI
V
V
High level
output voltage
VOH
3.5
VDD = 4.5V, IOH = –1.2mA
VDD = 4.5V, IOL = 1.8mA
VDD = 4.5V, IOL = 3.6mA
VDD = 4.5V, IOL = 12.0mA
VDD = 5.5V, VIH = 5.5V
VDD = 5.5V, VIL = 0.4V
VDD = 5.5V, VIL = 0.4V
V
0.4
Low level
output voltage
V
VOL
0.6
PH
V
1.5
40
0.5
µA
µA
µA
IIHE
IILE
IILR
EXTAL
Input current
–0.5
–1.5
–40
–400
1
RST
PA to PG,
PI, MP,
VDD = 5.5V,
I/O leakage
current
µA
µA
IIZ
±10
50
AN0 to AN3, VI = 0, 5.5V
1
RST
Open drain
VDD = 5.5V
VOH = 12V
output leakage
current (N-CH
Tr off state)
PH
ILOH
IDD1
16MHz crystal oscillation (C1 = C2 = 15pF)
27
45
8
mA
mA
3
IDDS1
IDD2
VDD = 5.5V
SLEEP mode
VDD = 5.5V
Supply
current
1.8
VDD, VSS
IDDS2
2
STOP mode
(EXTAL pin oscillation stop)
IDDS3
10
µA
VDD = 5V±0.5V
PC, PD,
PE2 to PE5
PF, PG, PI,
RECCTL (+),
RECCTL (–),
CTLAMP (+),
CTLAMP (–),
CTLSAMPI,
CFG, DFG,
DPG
Clock 1MHz
0V other than the measured pins
Input capacity
CIN
10
20
pF
1) RST pin specifies the input current when the pull-up resistor is selected, and specifies leakage current
when no resistor is selected.
2) When entire output pins are open.
3) When setting upper 2 bits (CPU clock selection) of clock control register (CLC: 00FEH) to "00" and
operating in high speed mode (1/2 frequency dividing clock).
– 17 –
CXP88616/88624
AC Characteristics
(1) Clock timing
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Item
Symbol
Pin
Condition
Min.
1
Typ.
Max. Unit
XTAL
EXTAL
Fig. 1, Fig. 2
MHz
ns
16
200
20
System clock frequency
fC
Fig. 1, Fig. 2
External clock drive
t
t
XL,
XH
XTAL
EXTAL
28
System clock input pulse width
Fig. 1, Fig. 2
External clock drive
System clock input rise and
fall times
XTAL
EXTAL
t
t
CR,
CF
ns
Event count clock input
pulse width
t
t
EH,
EL
1
Fig. 3
Fig. 3
ns
tsys
+ 200
EC
EC
Event count clock input
rise and fall times
t
t
ER,
EF
ms
1) tsys indicates three values according to the contents of the clock control register (CLC; 00FEH) upper 2 bits
(CPU clock selection).
tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")
Fig. 1. Clock timing
1/fc
VDD – 0.4V
0.4V
EXTAL
XTAL
tXH
tCF
tXL
tCR
Fig. 2. Clock applied condition
Crystal oscillation
Ceramic oscillation
External clock
EXTAL
XTAL
EXTAL
XTAL
C1
C2
74HC04
Fig. 3. Event count clock timing
0.8VDD
0.2VDD
EC
tEH
tTH
tEF
tEL
tTL
tER
tTR
tTF
– 18 –
CXP88616/88624
(2) Serial transfer (CH0)
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Item
Symbol
Pin
Condition
Min.
Max.
Unit
ns
CS0 ↓ → SCK0
Chip select transfer mode
(SCK0 = output mode)
t
t
t
t
t
DCSK
SCK0
tsys + 200
delay time
CS0 ↑ → SCK0
floating delay time
Chip select transfer mode
(SCK0 = output mode)
ns
ns
ns
ns
DCSKF SCK0
DCSO SO0
DCSOF SO0
WHCS CS0
tsys + 200
tsys + 200
tsys + 200
CS0 ↓ → SO0
Chip select transfer mode
Chip select transfer mode
Chip select transfer mode
delay time
CS0 ↑ → SO0
floating delay time
CS0
tsys + 200
high level width
Input mode
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2tsys + 200
16000/fc
tsys + 100
8000/fc – 50
100
SCK0
cycle time
t
KCY
SCK0
SCK0
SI0
Output mode
Input mode
t
KH
KL
SCK0
t
high and low level widths
Output mode
SCK0 input mode
SCK0 output mode
SCK0 input mode
SCK0 output mode
SCK0 input mode
SCK0 output mode
SI0 input set-up time
(against SCK0 ↑)
t
t
t
SIK
200
tsys + 200
100
SI0 input hold time
(against SCK0 ↑)
KSI
SI0
tsys + 200
100
KSO
SCK0 ↓ → SO0 delay time
SO0
Note 1) tsys indicates three values according to the contents of the clock control register (CLC; 00FEH) upper
2 bits (CPU clock selection).
tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")
Note 2) The load of SCK0 output mode and SO0 output delay time is 50pF + 1TTL.
– 19 –
CXP88616/88624
Fig. 4. Serial transfer timing (CH0)
tWHCS
0.8VDD
CS0
0.2VDD
tKCY
tDCSK
tDCSKF
tKL
tKH
0.8VDD
0.8VDD
0.2VDD
SCK0
tSIK tKSI
0.8VDD
0.2VDD
Input data
SI0
tDCSO
tKSO
tDCSOF
0.8VDD
Output data
SO0
0.2VDD
– 20 –
CXP88616/88624
(3) A/D converter characteristics
(Ta = –20 to +75°C, VDD = AVDD = 4.5 to 5.5V, AVREF = 4.0 to AVDD, Vss = AVss = 0V reference)
Item
Resolution
Symbol
Pin
Max. Unit
Typ.
Condition
Min.
8
Bits
Only for A/D converter
operation
Ta = 25°C
VDD = AVDD = AVREF = 5.0V
VDD = AVss = 0V
Linearity error
Absolute error
LSB
±1
LSB
±2
1
µs
µs
V
Conversion time
Sampling time
160/fADC
12/fADC
t
CONV
SAMP
1
t
AVREF
AVDD
AVREF
1.0
Reference input voltage
Analog input voltage
AVDD – 0.5
0
VREF
VIAN
AN0 to AN7
V
0.6
mA
Operation mode
SLEEP mode
STOP mode
AVREF current
AVREF
IREF
µA
10
32kHz operation mode
Fig. 5. Definitions of A/D converter terms
FFH
FEH
1) fADC indicates the below values due to the contents
of bit 0 (ADCCK) of the ADC operation clock selection
register (MSC: 01FFH), bits 7 (PCK1) and 6 (PCK0) of
the clock control register (address: 00FEH).
Linearity error
01H
00H
VZT
VFT
ADCCK
Analog input
0 (φ/2 selection)
1 (φ selection)
PCK1, PCK0
fADC = fc/2
fADC = fc/4
fADC = fc/16
fADC = fc
00 (φ = fEX/2)
fADC = fc/2
fADC = fc/8
01 (φ = fEX/4)
11 (φ = fEX/16)
– 21 –
CXP88616/88624
(4) Interruption, reset input (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Item
Symbol
Pin
INT0
Condition Min.
Max.
Unit
External interruption high and
low level widths
t
IH
IL
INT1
INT2
NMI
1
µs
t
Reset input low level width
32/fc
µs
tRSL
RST
Fig. 6. Interruption input timing
tIH
tIL
INT0
0.8VDD
INT1
INT2
0.2VDD
NMI
(Falling edge)
Fig. 7. Reset input timing
tRSL
RST
0.2VDD
– 22 –
CXP88616/88624
Analog Circuit Characteristics
(1) Amplifier circuit reference voltage characteristics
(Ta = –20 to +75°C, VDD = AMPVDD = 5.0V, Vss = AMPVSS = 0V reference)
Item
Symbol
Pin
Max.
2.6
Typ.
2.4
Unit
V
Conditions
Min.
2.2
VREFOUT
CTLAG
Reference level
output voltage
VOR
V
2.15
3.50
2.35
6.5
2.55
mA
mA
mA
mA
VREFOUT = VREFOUT + 0.5V
VREFOUT
CTLAG
VREFOUT = VREFOUT
–
0.5V –0.30
2.80
–0.85
5.5
Reference level
output current
IOR
CTLAG = CTLAG + 0.5V
CTLAG = CTLAG – 0.5V
–0.30
–0.85
(2) CTL 1st amplifier characteristics
(Ta = –20 to +75°C, VDD = AMPVDD = 5.0V, Vss = AMPVSS = 0V, CTLAG reference)
Item
Voltage gain
Offset voltage
Symbol
Pin
Max.
16.5
Typ.
14.5
Unit
dB
Conditions
Gain = 16dB
RECCTL ( ) = 0V
Gain = 27dB
RECCTL ( ) = 0V
Gain = 42dB
Min.
12.5
–
dB
dB
dB
mV
kΩ
kΩ
Ω
23.5
39.0
54.5
–40
25.5
41.5
57.0
0
27.5
44.0
59.5
+40
–
1
AVCTL1
RECCTL (+)
CTLFAMPO
2
RECCTL (
Gain = 58dB
RECCTL ( ) = 0V
–) = 0V
–
CTLAMP (+) and CTLAMP (
= open
–)
VOSCTL
1
Charge switch OFF
CTLAMP (+) = +0.2V
CTLAMP (+)
CTLAMP (–)
CTLAMP (+)
CTLAMP (–)
26.0
1.20
44.5
2.0
Input resistance
RINCTL
1
Charge switch OFF
CTLAMP (–) = +0.2V
Charge switch ON
CTLAMP (+) = +0.5V
560
560
400
400
250
250
1010
1010
770
Charge switch ON
resistance
RCCTL
1
Charge switch ON
Ω
CTLAMP (–) = +0.5V
During CTL read operation,
RECCTL (+)
CTLCIN (+)
Ω
315
315
RECCTL and
CTLCIN connection
switch ON resistance
CTLCIN (+) – RECCTL (+) = 0.2V
During CTL read operation,
RREAD
RECCTL (–)
CTLCIN (–)
Ω
770
CTLCIN (–) – RECCTL (–) = 0.2V
During CTL write operation,
CTLCIN (+) = AMPVSS + 0.2V
CTLCIN (+)
CTLCIN (–)
Ω
310
CTLCIN 0V fix
switch ON resistance
RWRITE
During CTL write operation,
CTLCIN (–) = AMPVSS + 0.2V
Ω
310
1) When CTLCIN (+), CTLAMP (+) pins and CTLCIN (–), CTLAMP (–) pins are AC coupled, and then the
signal is input from RECCTL (+) pin.
2) The result after measuring the CTLFAMPO output waveform or voltage gain.
Note) The gain increases by approximately 1.5dB when the AC coupling capacitor (47µF) is connected to
CTLAMP (+) and CTLAMP (–) pins, and the signal is input from CTLAMP (+) and CTLAMP (–) pins.
– 23 –
CXP88616/88624
(3) CTL 2nd amplifier characteristics
(Ta = –20 to +75°C, VDD = AMPVDD = 5.0V, Vss = AMPVSS = 0V, CTLAG reference)
Item
Symbol
Pin
Max.
6.8
Typ.
5.8
Unit
dB
dB
dB
dB
Conditions
Gain = 5dB
Min.
4.8
Gain = 11dB
Gain = 16dB
Gain = 20dB
10.4
15.3
19.3
11.5
16.5
20.5
12.6
17.7
21.7
AVCTL2
1,
2
Voltage gain
LPF cut-off
fCCTL
fDC – 3dB
15.0
25.0
40.0
kHz
1,
2
frequency
2
Offset voltage
VOSCTL2
CTLSAMPI = open
–50
70.0
215
0
+50
130
275
430
mV
Comparator level = +100mV0-p
Comparator level = +250mV0-p
Comparator level = +400mV0-p
100
mV0-p
mV0-p
mV0-p
CTLSAMPI
245
370
400
2
Comparator level
Input resistance
VCCTL
Comparator level =
Comparator level =
Comparator level =
–
–
–
100mV0-p
250mV0-p
400mV0-p
–70.0
–220
–370
–100
–250
–400
–130 mV0-p
–280 mV0-p
–430
mV0-p
Charge switch OFF
CTLSAMPI = +0.2V
RINCTL2
RCCTL2
10.0
18.0
770
kΩ
Charge switch ON
resistance
Charge switch ON
CTLSAMPI = +0.5V
1140
Ω
1) When the signal is input with the AC coupling capacitor (47µF) connected to CTLSAMPI pin.
2) The result after measuring the output waveform of amplifier internal low-pass filter or voltage value.
(4) CTLAMP characteristics (1st amplifier + 2nd amplifier)
(Ta = –20 to +75°C, VDD = AMPVDD = 5.0V, Vss = AMPVSS = 0V reference)
Item
Symbol
Pin
Max.
38.2
Unit
dB
Typ.
35.0
Conditions
Min.
31.8
CTL 1st amplifier gain = 16dB
CTL 2nd amplifier gain = 20dB
RECCTL (–) = 0V
1
Voltage gain
AVCTL
Input amplitude
(peak value)
VPKCTL
VSCTL
RECCTL (–) = 0V
±300
0.10
mV0-p
RECCTL (+)
CTL 1st amplifier gain = 58dB
CTL 2nd amplifier gain = 20dB
Comparator level = +400mV0-p
–400mV0-p
Input sensitivity
Input dead band
0.08
0.04
mV0-p
mV0-p
VNSCTL
0.015
RECCTL (–) = 0V
1) As for other combinations of the amplifier gains, CTL 1st amplifier and CTL 2nd amplifier are added
respectively.
Note) The result when the signal is input from RECCTL (+) pin with CTL 1st amplifier + CTL 2nd amplifier after
performing AC coupling of CTLCIN (+), CTLAMP (+) pins and CTLCIN (–), CTLAMP (–) pins, and
CTLFAMPO, CTLSAMPI pins.
– 24 –
CXP88616/88624
(5) CFGAMP characteristics
(Ta = –20 to +75°C, VDD = AMPVDD = 5.0V, Vss = AMPVDD = 0V, VREFOUT reference)
Item
Voltage gain
LPF cut-off
Symbol
Pins
Max.
2.2
Unit
dB
dB
dB
dB
Typ.
0.6
Conditions
Gain = 0dB
Min.
–0.3
19.2
33.2
37.0
Gain = 20dB
Gain = 34dB
Gain = 38dB
20.8
34.8
38.7
22.4
36.4
40.4
1
2
,
AVCFG
fCCFG
fDC – 3dB
30.0
–50
260
55.0
0
80.0
+50
360
kHz
mV
1
,
2
frequency
2
Offset voltage
VOSCFG
CFG = open
Comparator schimitt width
= 320mVp-p
320
mVp-p
Comparator
VCCFG
judgment level
Comparator schimitt width
= 160mVp-p
2
width
110
155
4.20
2.10
4.10
2.00
8.3
200
5.00
2.40
mVp-p
mVp-p
mVp-p
mVp-p
mVp-p
kΩ
Gain = 38dB
Comparator level = 320mVp-p
1
Input sensitivity
VSCFG
CFG
Gain = 38dB
Comparator level = 160mVp-p
Gain = 38dB
Comparator level = 320mVp-p
3.40
1.50
5.5
1
Input dead band
Input resistance
VNSCFG
Gain = 38dB
Comparator level = 160mVp-p
Charge switch OFF
CFG = +0.2V
RINCFG
RCCFG
DTYCFG
VPKCFG
Charge switch ON
resistance
Charge switch ON
CFG = +0.5V
455
50.0
710
52.0
±2.4
Ω
Digital output
waveform duty
CFG = sine wave with 50%
duty
48.0
%
1,
3
Input amplitude
(peak value)
V0-p
1
1) When the signal is input with the AC coupling capacitor (47µF) connected to CFG pin.
2) The result after measuring the output waveform of amplifier internal low-pass filter or voltage value.
3) The result after measuring the digital signal waveform output from the amplifier circuit.
– 25 –
CXP88616/88624
(6) DFGAMP characteristics
(Ta = –20 to +75°C, VDD = AMPVDD = 5.0V, Vss = AMPVSS = 0V, VREFOUT reference)
Item
Voltage gain
LPF cut-off
Symbol
Pins
Max.
2.2
Unit
dB
dB
dB
dB
Typ.
0.6
Conditions
Gain = 0dB
Min.
–0.3
19.2
33.2
37.0
Gain = 20dB
Gain = 34dB
Gain = 38dB
20.8
34.8
38.7
22.4
36.4
40.4
1,
2
2
AVDFG
fCDFG
fDC – 3dB
30.0
–50
260
55.0
0
80.0
+50
360
kHz
mV
1,
frequency
2
VOSDFG
Offset voltage
DFG = open
Comparator schmitt width
= 320mVp-p
320
mVp-p
Comparator
VCDFG
VSDFG
VNSDFG
judgment level
width
Comparator schmitt width
= 160mVp-p
2
110
155
4.20
2.10
4.10
2.00
8.3
200
5.00
2.40
mVp-p
mVp-p
mVp-p
mVp-p
mVp-p
kΩ
Gain = 38dB
Comparator level = 320mVp-p
1
Input sensitivity
DFG
Gain = 38dB
Comparator level = 160mVp-p
Gain = 38dB
Comparator level = 320mVp-p
3.40
1.50
5.5
1
Input dead band
Input resistance
Gain = 38dB
Comparator level = 160mVp-p
Charge switch OFF
DFG = +0.2V
RINDFG
RCDFG
DTYDFG
VPKDFG
Charge switch ON
resistance
Charge switch ON
DFG = +0.5V
455
50.0
710
52.0
±2.4
Ω
Digital output
waveform duty
DFG = sine wave of 50%
duty
48.0
%
1,
3
Input amplitude
V0-p
1
(peak value)
1) When the signal is input with the AC coupling capacitor (47µF) connected to DFG pin.
2) The result after measuring the output waveform of amplifier internal low-pass filter or voltage value.
3) The result after measuring the digital signal waveform output from the amplifier circuit.
– 26 –
CXP88616/88624
(7) DPGAMP characteristics
(Ta = –20 to +75°C, VDD = AMPVDD = 5.0V, Vss = AMPVSS = 0V, VREFOUT reference)
Item
Voltage gain
LPF cut-off
Symbol
Pins
Max.
13.2
Unit
dB
Typ.
12.0
Conditions
Min.
11.1
1,
2
2
AVDPG
fCDPG
fDC – 3dB
30.0
55.0
85.0
kHz
mV
1,
frequency
2
VOSDPG
DFG = open
Offset voltage
–35
570
370
175
72
0
+35
640
Comparator level = 600mV0-p
Comparator level = 400mV0-p
Comparator level = 200mV0-p
Comparator level = 100mV0-p
Comparator level = –600mV0-p
Comparator level = –400mV0-p
Comparator level = –200mV0-p
Comparator level = –100mV0-p
605
mV0-p
400
432
mV0-p
200
220
mV0-p
100
125
mV0-p
2
VCDPG
Comparator level
–572
–368
–174
–71
–605
–400
–200
–100
–643
–438
–223
–124
mV0-p
mV0-p
mV0-p
mV0-p
Comparator level
= 600mV0-p, 200mV0-p
150
100
180
120
mV
0
-p
Comparator level
= 400mV0-p, 100mV0-p
mV0
-p
1
Input sensitivity
DPG
VSDPG
Comparator level
= –600mV0-p, –200mV0-p
–155
–109
142
–185
–130
mV
0
-p
Comparator level
= –400mV0-p, –100mV0-p
mV0
-p
Comparator level
= 600mV0-p, 200mV0-p
113
70
mV0
-p
Comparator level
= 400mV0-p, 100mV0-p
90
mV0
-p
1
VNSDPG
Input dead band
Input resistance
Comparator level
= –600mV0-p, –200mV0-p
–120
–80
24.0
–150
–103
44.5
450
mV
0
-p
Comparator level
= –400mV0-p, –100mV0-p
mV0
-p
Charge switch OFF
DPG = +0.2V
RINDPG
RCDPG
VPKDPG
kΩ
Charge switch ON
DPG = +0.5V
Charge switch ON
resistance
860
Ω
Input amplitude
±2.4
V
1
(peak value)
1) When the signal is input with the AC coupling capacitor (47µF) connected to DPG pin.
2) The result after measuring the output waveform of amplifier internal low-pass filter or voltage value.
– 27 –
CXP88616/88624
(8) CTL write circuit characteristics
(Ta = –20 to +75°C, VDD = AMPVDD = 5.0V, Vss = AMPVSS = 0V reference)
Item
Symbol
ROH
Pins
Max. Unit
Typ.
625
555
2.0
2.5
3.1
3.6
4.0
4.6
5.1
5.6
6.1
Conditions
Min.
450
410
1.3
1.7
2.1
2.6
2.9
3.3
3.7
4.0
4.4
RECCAP = AMPVDD – 0.5V
RECCAP = AMPVDD + 0.5V
Write current = 2.0mA
Write current = 2.5mA
Write current = 3.0mA
Write current = 3.5mA
Write current = 4.0mA
Write current = 4.5mA
Write current = 5.0mA
Write current = 5.5mA
Write current = 6.0mA
1005
840
2.9
3.7
4.5
5.2
5.9
6.6
7.2
8.0
8.9
Ω
Output resistance
RECCAP
ROL
Ω
mA
mA
mA
mA
mA
mA
mA
mA
mA
RECCTL (+)
RECCTL (–)
1
Output current
IOREC
1) The current value which flows when RECCTL (+) pin and RECCTL (–) pin are shorted.
(9) Amplifier operating current characteristics
(Ta = –20 to +75°C, VDD = AMPVDD = 5.0V, Vss = AMPVSS = 0V reference)
Item
Symbol
Pins
Max. Unit
Typ.
7.6
Conditions
Min.
1
mA
12.0
When the amplifier is operating
Amplifier operating
current
IAMP
AMPVDD
When the amplifier is not
operating
µA
10
1) The CTL recording current is added during CTL write.
Note) The amplifier operation and NOT-operation is controlled according to the contents of amplifier power
supply control register (ASWC: 05E2H) bits 5, 4, 1 and 0.
– 28 –
CXP88616/88624
Supplement
Fig. 8. Recommended oscillation circuit
EXTAL
XTAL
Rd
C1
C2
Manufacturer
Model
fc (MHz)
8.00
C1 (pF)
10
C2 (pF)
10
Rd (Ω)
RIVER
ELETEC
CO., LTD.
10.00
12.00
16.00
0
HC-49/U03
5
5
8.00
16 (12)
16 (12)
12
16 (12)
16 (12)
12
10.00
12.00
16.00
0
HC-49/U (-S)
KINSEKI LTD.
12
12
Mask option table
Content
Item
Reset pin pull-up resistor
Existent
TTL schmitt
Non-existent
1
Input circuit format
CMOS schmitt
1) The input circuit format can be selected for PE3/SYNC pin.
– 29 –
CXP88616/88624
Characteristics Curve
IDD vs. VDD
(fc = 16MHz, Ta = 25°C, Typical)
IDD vs. fc
(VDD = 5.0V, Ta = 25°C, Typical)
50
30
25
20
15
1/2 dividing mode
1/4 dividing mode
20
10
1/2 dividing mode
5
1/16 dividing mode
SLEEP mode
2
1
1/4 dividing mode
10
5
0.5
1/16 dividing mode
SLEEP mode
0.2
0.1
0
1
2
3
4
5
6
7
5
10
16
15
fc – System clock [MHz]
VDD – Supply voltage [V]
– 30 –
CXP88616/88624
Package Outline
Unit: mm
100PIN QFP (PLASTIC)
23.9 ± 0.4
+ 0.1
0.15 – 0.05
+ 0.4
20.0 – 0.1
80
51
50
81
A
31
100
1
30
+ 0.15
0.65
+ 0.35
2.75 – 0.15
0.3 – 0.1
0.13
0.15
M
+ 0.2
0.1 – 0.05
0° to 10°
DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
EPOXY RESIN
SOLDER PLATING
QFP-100P-L01
QFP100-P-1420
SONY CODE
EIAJ CODE
LEAD MATERIAL
PACKAGE MASS
42/COPPER ALLOY
1.7g
JEDEC CODE
– 31 –
相关型号：
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