CXP921064A [SONY]
CMOS 16-bit Single Chip Microcomputer; CMOS 16位单片机
| 型号： | CXP921064A |
| 厂家： | 
SONY CORPORATION |
| 描述： | CMOS 16-bit Single Chip Microcomputer |
| 文件： | 总33页 (文件大小：415K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CXP921064A
CMOS 16-bit Single Chip Microcomputer
Description
100 pin QFP (Plastic)
100 pin LQFP (Plastic)
The CXP921064A is a CMOS 16-bit microcomputer
integrating on a single chip an A/D converter, serial
interface, I2C bus interface, timer, real-time pulse
generator, clock prescaler, remote control receive
circuit, and as well as basic configurations like a 16-
bit CPU, ROM, RAM, and I/O port.
This LSI also provides the sleep/stop functions that
enable lower power consumption.
Features
104 pin LFLGA (Plastic)
• An efficient instruction set as a controller
— Direct addressing, numerous abbreviated forms,
multiplication and division instructions
• Instruction sets for C language and RTOS
— Highly quadratic instruction system, general-
purpose register of eigth 16-bit × 16-bank
configuration
• Minimum instruction cycle
100ns at 20MHz operation (2.7 to 3.3V)
61µs at 32kMHz operation (2.2 to 3.3V)
• Incorporated ROM capacity 256K bytes
• Incorporated RAM capacity 10K bytes
• Peripheral functions
— A/D converter
— Serial interface
— I2C bus interface
— Timers
8-bit 12 analog input, 2 channels successive approximation system,
automatic scanning function, (Conversion time: 3.4µs at 20MHz)
128 -byte buffer RAM, 3 channels
8-stage FIFO, 1 channel (supports special mode master/slave)
64-byte buffer RAM , 2 channels
(supports master/slave and automatic transfer mode)
8-bit timer/counter, 2 channels (with timing output)
16-bit timer, 3 channels
— Real-time pulse generator
— Clock prescaler
5-bit output, 1 channel (2-stage FIFO)
— Remote control receive circuit 8-bit pulse measurement counter, 8-stage FIFO
• Interruption
• Standby mode
• Package
30 factors, 30 vectors, multi-interruption and priority selection possible
Sleep/stop
100-pin plastic QFP/LQFP
104-pin plastic LFLGA
CXP921000A
• Piggy/evaluation chip
•
FLASH EEPROM incorporated version CXP921F064A
Structure
Silicon gate CMOS IC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E99707-PS
CXP921064A
A T R O P B T R O P C T R O P D T R O P E T R O P F T R O P G T R O P H T R O P I T R O P J T R O P
T U O X
S S V
D D V
T S R
L A T X
L A T X E
X T
4 O T R o t
0 O T R
X E T
3 2 N A o t
2 1 N A
D D V A
1 F E R V A
S S V A
5 1 S K o t
0 S K
0 F E R V A
7 T N I o t
0 T N I
1 1 N A o t
0 N A
R E L L O R T N O C T P U R R E T N I
I M N
– 2 –
CXP921064A
Pin Assignment 1 (Top View) 100-pin QFP package
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
PJ0/AN4/KS8
PB2/AN22
PB3/AN23
PB4/SI3
PB5/SO3
PB6/SCK3
PB7/RMC
PC0/SDA0
PC1/SCL0
PC2/SDA1
PC3/SCL1
PC4
2
AVDD
3
AVREF1
4
AVREF0
5
AVss
6
AN3
AN2
7
AN1
8
PI7/AN0
PI6/NMI
PI5/INT7
PI4/INT6
PI3/INT5
PI2/INT4
PI1/INT3
PI0/INT2
PH7/INT1
PH6/INT0
PH5/XOUT
PH4/RTO4
PH3/RTO3
PH2/RTO2
PH1/RTO1
PH0/RTO0
Vss
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
PC5
PC6
PC7
VSS
PD0/KS0
PD1/KS1
PD2/KS2
PD3/KS3
PD4/KS4
PD5/KS5
PD6/KS6
PD7/KS7
PE0
PE1
TX
PE2
TEX
PE3
VDD
PE4
PG7/SCK2
PG6/SO2
PE5
PE6
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Note) 1. NC (Pin 88) must be left open. However, use this pin for FLASH EEPROM
incorporated version.
2. Vss (Pins 15, 41, 56 and 90) must be connected to GND.
3. VDD (Pins 44, 53 and 89) must be connected to VDD.
– 3 –
CXP921064A
Pin Assignment 2 (Top View) 100-pin LQFP package
76
78 77
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79
AVREF0
AVss
1
2
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
PB4/SI3
PB5/SO3
PB6/SCK3
PB7/RMC
PC0/SDA0
PC1/SCL0
PC2/SDA1
PC3/SCL1
PC4
AN3
3
AN2
4
AN1
5
PI7/AN0
PI6/NMI
PI5/INT7
PI4/INT6
PI3/INT5
PI2/INT4
PI1/INT3
PI0/INT2
PH7/INT1
PH6/INT0
PH5/XOUT
PH4/RTO4
PH3/RTO3
PH2/RTO2
PH1/RTO1
PH0/RTO0
Vss
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
PC5
PC6
PC7
VSS
PD0/KS0
PD1/KS1
PD2/KS2
PD3/KS3
PD4/KS4
PD5/KS5
PD6/KS6
PD7/KS7
PE0
TX
PE1
TEX
PE2
VDD
PE3
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Note) 1. NC (Pin 86) must be left open. However, use this pin for FLASH EEPROM
incorporated version.
2. Vss (Pins 13, 39, 54 and 88) must be connected to GND.
3. VDD (Pins 42, 51 and 87) must be connected to VDD.
– 4 –
CXP921064A
Pin Assignment 3 (Top View) 104-pin LFLGA package
1
3
2
2
3
4
5
6
7
8
9
10
80
11
78
12
74
13
73
A
B
C
D
E
F
98
96
93
90
88
VSS
87
86
NC
85
83
A
B
C
D
E
F
PB1 PA7 PA4 PA1
99 97 94 91
PJ5 PJ2 PJ0
82 79 77
PB2 PB0 PA5 PA2 VDD PJ7 PJ4 PJ1 AVDD
95 92 89 84 81 76
PB3 PA6 PA3 PA0 PJ6 PJ3 AVREF1
100
PB6 PB5
AVSS AN3
72 71
AVREF0 AN2 AN1
5
4
1
75
PC0 PB7 PB4
8
7
6
70
PI7 PI6
67 66
PI4 PI3
64 62
69
68
PI5
65
PC3 PC2 PC1
11 10
PC6 PC5 PC4
9
PI2
G
H
J
G
H
J
13
VSS PC7 PD0
15 16 17
PD1 PD2 PD3
18 19 20
PD4 PD5 PD6
12
14
63
PI1 PH7 PI0
59 60 61
PH4 PH5 PH6
56 57 58
PH1 PH2 PH3
51 54 55
VDD VSS PH0
K
L
K
L
21
PD7 PE0 PE3
23 24
PE1 PE2
22
25
26
PE4 PF1 PF4
29 32 35
31
34
39
VSS
37
42
VDD PG2 PG7
41 44 47
45
50
52
53
TEX
TX
M
M
27
49
PE5 PE7 PF2 PF5 PF7 EXTAL PG1 PG4 PG6
N
N
28
30
33
36
38
40
43
46
48
PE6 PF0 PF3 PF6
XTAL PG0 PG3 PG5
RST
7
1
2
3
4
5
6
8
9
10
11
12
13
Note) 1. NC (Pin 86) must be left open. However, use this pin for FLASH EEPROM
incorporated version.
2. Vss (Pins 13, 39, 54 and 88) must be connected to GND.
3. VDD (Pins 42, 51 and 87) must be connected to VDD.
– 5 –
CXP921064A
Pin Functions
Symbol
I/O
Functions
(Port A)
PA0/AN12
to PA7/AN19
Output / Input 8-bit output port.
(8 pins)
Analog input for A/D converter.
(12 pins)
PB0/AN20
to PB3/AN23
Output / Input
(Port B)
8-bit output port.
(8 pins)
PB4/SI3
Output / Input
Output / Output
Output / I/O
Output / Input
I/O / I/O
Serial data (CH3) input.
Serial data (CH3) output.
Serial clock (CH3) I/O.
PB5/SO3
PB6/SCK3
PB7/RMC
PC0/SDA0
PC1/SCL0
PC2/SDA1
PC3/SCL1
PC4 to PC7
Remote control receive circuit input.
Data I/O of I2C bus interface (CH0).
Clock I/O of I2C bus interface (CH0).
Data I/O of I2C bus interface (CH1).
Clock I/O of I2C bus interface (CH1).
(Port C)
8-bit I/O port.
I/O can be specified in 1-bit units.
Pull-up resistor is present or not
through program in 1-bit units.
(8 pins)
I/O / I/O
I/O / I/O
I/O / I/O
I/O
(Port D)
8-bit I/O port.
Standby release input function can be
specified in 1-bit units.
(8 pins)
I/O can be specified in 1-bit units.
Can drive 5mA sink current
(VDD = 2.7 to 3.3V).
(8 pins)
PD0/KS0
to PD7/KS7
I/O / Input
(Port E)
8-bit I/O port.
I/O can be specified in 1-bit units.
(8 pins)
I/O
PE0 to PE7
PF0
Input
External event input for 8-bit
timer/counter.
PF1/EC
Input / Input
(Port F)
8-bit port.
Lower 4 bits are for input;
upper 4 bits are for output.
(8 pins)
Serial chip select (CH0) input.
Serial data (CH0) input.
Serial data (CH0) output.
Serial clock (CH0) I/O.
PF2/CS0
PF3/SI0
Input / Input
Input / Input
PF4/SO0
PF5/SCK0
PF6/TO
Output / Output
Output / I/O
8-bit timer/counter output.
16-bit timer (CH0) output.
Output / Output
Output / Output
PF7/TMO
– 6 –
CXP921064A
Symbol
PG0/CS1
PG1/SI1
I/O
Functions
Serial chip select (CH1) input.
I/O / Input
I/O / Input
I/O / Output
I/O / I/O
Serial data (CH1) input.
Serial data (CH1) output.
Serial clock (CH1) I/O.
PG2/SO1
PG3/SCK1
PG4/CS2
PG5/SI2
(Port G)
8-bit I/O port.
I/O can be specified in 1-bit units.
(8 pins)
Serial chip select (CH2) input.
Serial data (CH2) input.
Serial data (CH2) output.
Serial clock (CH2) output.
I/O / Input
I/O / Input
I/O / Output
I/O / Output
PG6/SO2
PG7/SCK2
Real-time pulse generator output.
(5 pins)
PH0/RTO0
to PH4/RTO4
(Port H)
8-bit port.
Lower 6 bits are for output;
upper 2 bits are for input.
(8 pins)
Output / Output
Output / Output
Input / Input
Clock output for clock prescaler buzzer.
PH5/XOUT
PH6/INT0
to PH7/INT1
External interrupt input.
(8 pins)
PI0/INT2
to PI5/INT7
Input / Input
(Port I)
8-bit input port.
(8 pins)
Non-maskable external interrupt input.
PI6/NMI
PI7/AN0
Input / Input
Input / Input
Analog input for A/D converter.
(12 pins)
AN1 to AN3
Input
(Port J)
8-bit I/O port.
I/O can be specified in 1-bit units.
(8 pins)
Standby release input
function can be specified in
1-bit units.
PJ0/AN4/
KS8
to PJ7/AN11/ Input
KS15
I/O / Input /
(8 pins)
Connects a crystal for main clock oscillation.
(When the clock is supplied externally, input it to EXTAL and input an
opposite phase clock to XTAL.)
EXTAL
XTAL
TEX
Input
Connects a crystal for sub clock oscillation.
(When the clock is supplied externally, input it to TEX and input an
opposite phase clock to TX.)
Input
Input
TX
RST
System reset. Active at "L" level.
AVDD
AVREF0
AVREF1
AVSS
Positive power supply for A/D converter.
Reference voltage input for A/D converter (CH0).
Reference voltage input for A/D converter (CH1).
GND for A/D converter.
Input
Input
Positive power supply.
(Connect all three VDD pins to positive power supply.)
VDD
VSS
NC
GND
(Connect all four Vss pins to GND.)
NC.
(NC is used for FLASH EEPROM incorporated version.)
– 7 –
CXP921064A
I/O Circuit Format for Pins
Pin
Circuit format
After a reset
PA register
"0" after a reset
PA0/AN12
to PA7/AN19
Input protection
circuit
PASL register
Hi-Z
IP
"0" after a reset
Internal data bus
A/D converter
RD
Input multiplexer
PB register
"0" after a reset
PB0/AN20
to PB3/AN23
PBSL register
Hi-Z
IP
"0" after a reset
Internal data bus
A/D converter
RD
Input multiplexer
PB register
"0" after a reset
PB4/SI3
PB7/RMC
PBSL register
IP
Hi-Z
"0" after a reset
Internal data bus
SI3, RMC
RD
CMOS Schmitt input
– 8 –
CXP921064A
Pin
Circuit format
After a reset
SO3
0
MPX
PB register
1
"0" after a reset
PB5/SO3
Hi-Z
Internal data bus
RD
PBSL register
"0" after a reset
SO3 output enable
0
SCK3
MPX
1
PB register
"0" after a reset
Internal data bus
PB6/SCK3
Hi-Z
RD
PBSL register
IP
"0" after a reset
SCK3 output enable
SCK3
CMOS Schmitt input
PULC register
"0" after a reset
SDA0, SCL0, SDA1, SCL1
1
MPX
PC register
0
Underfined after a reset
PC0/SDA0
PC1/SCL0
PC2/SDA1
PC3/SCL1
PCSL register
"0" after a reset
PCD register
Hi-Z
IP
"0" after a reset
Internal data bus
RD
SDA0, SCL0
SDA1, SCL1
CMOS Schmitt input
Pull-up transistor
approximately 15kΩ (VDD = 2.7 to 3.3V)
– 9 –
CXP921064A
Pin
Circuit format
After a reset
PULC register
"0" after a reset
PC register
Underfined after a reset
PC4 to PC7
Hi-Z
PCD register
IP
"0" after a reset
Internal data bus
RD
Pull-up transistor
approximately 15kΩ (VDD = 2.7 to 3.3V)
PD register
Underfined after a reset
PDD register
IP
PD0/KS0
Hi-Z
"0" after a reset
to PD7/KS7
Internal data bus
RD
Standby release
Large current drive
5mA (VDD = 2.7 to 3.3V)
PE register
Underfined after a reset
PE0 to PE7
Hi-Z
PED register
IP
"0" after a reset
Internal data bus
RD
– 10 –
CXP921064A
Pin
Circuit format
After a reset
IP
IP
Internal data bus
Hi-Z
Hi-Z
PF0
RD
RD
Internal data bus
EC
PF1/EC
CMOS Schmitt input
IP
Internal data bus
PFSL register
RD
CMOS Schmitt input
PF2/CS0
PF3/SI0
Hi-Z
"0" after a reset
CS0, SI0
SO0
PF register
1
MPX
0
"0" after a reset
Internal
data bus
RD
PF4/SO0
Hi-Z
PFSL register
"0" after a reset
SO0 output enable
PF register write
Reset
S
Q
R
SCK0
1
MPX
0
PF register
"0" after a reset
Internal
data bus
RD
PF5/SCK0
Hi-Z
PFSL register
"0" after a reset
IP
SCK0 output enable
PF register write
Reset
S
Q
SCK0
R
CMOS Schmitt input
– 11 –
CXP921064A
Pin
Circuit format
After a reset
PF register write
Reset
S
R
Q
"H" level
("H" level at ON
resistance of pull-
up transistor during
a reset.)
1
TO, TMO
MPX
0
PF6/TO
PF7/TMO
PF register
"0" after a reset
Internal
data bus
RD
PFSL register
Pull-up transistor
"0" after a reset
approximately 150kΩ (VDD = 2.7 to 3.3V)
PG register
Underfined after a reset
PGD register
IP
PG0/CS1
PG1/SI1
PG4/CS2
PG5/SI2
"0" after a reset
Hi-Z
Internal
data bus
RD
CMOS Schmitt input
PGSL register
"0" after a reset
CS1, SI1
CS2, SI2
SO1, SCK1
SO2, SCK2
1
MPX
0
PG register
Underfined after a reset
PGSL register
PG2/SO1
PG3/SCK1
PG6/SO2
PG7/SCK2
"0" after a reset
Hi-Z
PGD register
IP
"0" after a reset
SO1, SCK1
SO2, SCK2
output enable
Internal
data bus
RD
SCK1
CMOS Schmitt input
(PG3 only)
– 12 –
CXP921064A
Pin
Circuit format
After a reset
RTO0 to RTO4
PH register
PH0/RTO0
Hi-Z
to PH4/RTO4
Underfined after a reset
Internal
data bus
RD
PH register write
S
R
Q
Reset
XOUT
PH register
1
MPX
0
Underfined after a reset
Internal
data bus
RD
Hi-Z
PH5/XOUT
PHSL register
"0" after a reset
PH register write
S
Q
Reset
R
Internal data bus
Interrupt circuit
IP
PH6/INT0
to PH7/INT1
Hi-Z
Hi-Z
RD
CMOS Schmitt input
Internal data bus
Interrupt circuit
IP
PI0/INT2
to PI5/INT7
RD
CMOS Schmitt input
– 13 –
CXP921064A
Pin
Circuit format
After a reset
PISL register
"0" after a reset
Interrupt circuit (NMI)
PI6/NMI
IP
Hi-Z
CMOS Schmitt input
Internal data bus
RD
PISL register
"0" after a reset
Internal data bus
PI7/AN0
Hi-Z
Hi-Z
IP
RD
A/D converter
Input multiplexer
Input multiplexer
A/D converter
IP
AN1 to AN3
PJ register
Underfined after a reset
PJD register
"0" after a reset
PJ0/AN4/
KS8
to PJ7/AN11/
KS15
Hi-Z
Internal data bus
RD
Standby release
IP
PJSL register
"0" after a reset
A/D converter
Input multiplexer
– 14 –
CXP921064A
Pin
Circuit format
After a reset
EXTAL
IP
Timing generator
• Diagram shows circuit
configuration during
oscillation.
EXTAL
XTAL
Oscillation
• Feedback registor is
removed during stop
mode, and XTAL is
driven at "H" level.
Oscillation stop control
XTAL
Oscillation stop control
TEX
Timing generator,
clock prescaler
IP
IP
TEX
TX
Oscillation
• TX is driver at Hi-Z
during stop.
TX
Mask option
OP
"L" level
(during a reset)
RST
IP
CMOS Schmitt input
Pull-up transistor
approximately 30kΩ (VDD = 2.7 to 3.3V)
– 15 –
CXP921064A
Absolute Maximum Ratings
(VSS = 0V reference)
Item
Symbol
VDD
Rating
–0.3 to +4.6
AVSS to +4.6
AVSS to +4.6
–0.3 to +0.3
–0.3 to +4.6
–0.3 to +4.6
–5
Unit
V
Remarks
1
1
AVDD
AVREF
AVSS
VIN
V
Supply voltage
V
V
2
Input voltage
V
2
Output voltage
VOUT
IOH
V
High level output current
mA
mA
Output (value per pin)
Total for all output pins
High level total output current ∑IOH
–50
All pins excluding large current output
pins (value per pin)
IOL
Low level output current
IOLC
15
20
mA
mA
3
Large current output pins
(value per pin)
Low level total output current
Operating temperature
Storage temperature
∑IOL
Topr
Tstg
130
–20 to +75
–55 to +150
600
mA
°C
Total for all output pins
°C
mW QFP-100P-L01
mW LQFP-100P-L01
mW LFLGA-104P-02
Allowable power dissipation
PD
380
500
1
AVDD and AVREF must be the same voltage with VDD.
VIN and VOUT must not exceed VDD + 0.3V.
2
3
The large current drive transistor is N-ch transistor of PD.
Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should
be conducted under the recommended operating conditions. Exceeding these conditions may adversely
affect the reliability of the LSI.
– 16 –
CXP921064A
(Vss = 0V reference)
Recommended Operating Conditions
Item
Symbol
Min.
2.7
Max.
3.3
Unit
V
Remarks
2.2
3.3
V
Guaranteed operation range with TEX clock
Guaranteed operation range for clock mode
VDD
2.2
3.3
V
Supply voltage
2.0
3.3
V
Guaranteed data hold range during stop mode
1
AVDD
AVREF
VIH
2.7
3.3
V
1
2
2.7
3.3
V
0.7VDD
0.8VDD
VDD
VDD
V
High level input
voltage
3
VIHS
VIHEX
VIL
V
CMOS Schmitt input
0.7VDD VDD+0.3
V
EXTAL, TEX
2
0
0
0.2VDD
0.2VDD
0.3VDD
+75
V
Low level input
voltage
3
VILS
V
CMOS Schmitt input
VILEX
Topr
–0.3
–20
V
EXTAL, TEX
°C
Operating temperature
1
AVDD and AVREF must be the same voltage with VDD.
2
3
PC4 to PC7, PD, PE, PF0, PG2, PG6, PI7, PJ for normal input port.
PB4, PB6, PB7, PC0 to PC3, PF1 to PF3, PF5, PG0, PG1, PG3 to PG5, PG7, PH6, PH7, PI0 to PI6, RST.
– 17 –
CXP921064A
Electrical Characteristics
DC Characteristics
(Topr = –20 to +75°C, Vss = 0V reference)
Item
Symbol
Pins
Conditions
Min.
2.4
2.0
1.3
Typ.
Max.
Unit
PA, PB, PD, PE,
PF4 to PF7, PG,
PH0 to PH5, PJ
VDD = 2.7V, IOH = –0.15mA
V
V
V
High level
output
voltage
VOH
VDD = 2.7V, IOH = –0.5mA
VDD = 2.7V, IOH = –0.05mA
PC
PA, PB,
VDD = 2.7V, IOL = 1.2mA
0.3
0.5
V
PC4 to PC7, PE,
PF4 to PF7, PG,
PH0 to PH5, PJ
VDD = 2.7V, IOL = 1.6mA
VDD = 2.7V, IOL = 2.0mA
V
V
Low level
output
VOL
PC0 to PC3
(SCL0, SCL1,
SDA0, SDA1)
0.3
0.5
voltage
VDD = 2.7V, IOL = 3.0mA
VDD = 2.7V, IOL = 5.0mA
VDD = 3.3V, VIH = 3.3V
VDD = 3.3V, VIL = 0.3V
V
PD
1.0
V
0.3
IIHE
IILE
IILR
20
µA
µA
µA
µA
µA
EXTAL
–0.3
–0.9
–20
–250
–250
Input
current
1
RST
VDD = 3.3V, VIL = 0.3V
VDD = 2.7V, VIH = 2.4V
2
PC
IIL
–1.0
PA, PB,
PD to PG,
PH6, PH7,
PI, PJ,
AN1 to AN3,
TEX, RST
I/O leakage
current
±10
10
µA
µA
IIZ
DD = 3.3V, VI = 0, 3.3V
V
1
Open drain
output
leakage
2
PC
VDD = 3.3V, VIH = 3.3V
ILOH
current (N-ch
Tr. off state)
VDD = 3.0 ± 0.3V, 20MHz crystal
oscillation, A/D off state
(C1 = C2 = 10pF)
4
20
50
10
mA
µA
12
25
5
IDD1
VDD = 3.0 ± 0.3V, 32kHz crystal
oscillation, 20MHz oscillation stop,
A/D off state (C1 = C2 = 47pF)
IDD2
VDD = 3.0 ± 0.3V, 20MHz crystal
oscillation, A/D off state
4
mA
IDDS1
Supply
current
(C1 = C2 = 10pF), sleep mode
VDD, VSS
3
VDD = 3.0 ± 0.3V, 32kHz crystal
oscillation, 20MHz oscillation stop,
A/D off state (C1 = C2 = 47pF),
sleep mode
IDDS2
25
µA
10
5
VDD = 3.0V, 32kHz crystal
IDDS3
IDDS4
oscillation, 20MHz oscillation stop
(C1 = C2 = 47pF), clock mode
15
10
µA
µA
VDD = 3.0V, stop mode
– 18 –
CXP921064A
Item
Symbol
Pins
Conditions
Min.
Typ.
10
Max.
Unit
pF
PA, PB0 to PB4,
PB6, PB7,
PC to PE,
PF0 to PF3,
PF5, PG, PH6,
PH7, PI, PJ,
AN1 to AN3,
EXTAL, TEX,
RST
Clock 1MHz
0V for all pins excluding measured
pins
Input
capacitance
20
CIN
1
RST specifies the input current when pull-up resistor has been selected; the leakage current when no
resistor has been selected.
2
PC specifies the input current when pull-up resistor has been selected; the leakage current when no
resistor has been selected.
3
4
When all output pins are open.
When the upper two bits (PCK1, PCK0) of the clock control register (CLC: 0002FEh) are set to "00" and
the LSI is operated in high-speed mode (2 frequency dividing clock).
– 19 –
CXP921064A
AC Characteristics
(1) Clock timing
(Topr = –20 to +75°C, VDD = 2.7 to 3.3V, Vss = 0V reference)
Item
Symbol
Pins
Conditions
Min.
15
Typ. Max. Unit
Main clock base oscillation
frequency
EXTAL,
XTAL
VDD = 3.0 ± 0.3V
VDD = 3.0 ± 0.3V
fEX
Fig.1
20
20.5 MHz
ns
Fig.1, Fig.2
External clock
drive
t
t
t
t
XH
XL
XR
XF
Main clock base oscillation
input pulse width
20
EXTAL
EXTAL
Fig.1, Fig.2
External clock
drive
Main clock base oscillation
input rise time, fall time
VDD = 3.0 ± 0.3V
VDD = 2.2 to 3.3V
14
ns
Sub clock base oscillation
frequency
TEX,
TX
Fig.1
fTEX
32.735 32.768 33.096 kHz
Fig.1, Fig.2
External clock
drive
VDD = 3.3V
VDD = 2.2V
VDD = 3.3V
VDD = 2.2V
t
t
t
t
TH
TL
TR
TF
15.3
15.3
µs
µs
ns
ns
Sub clock base oscillation
input pulse width
TEX
TEX
Fig.1, Fig.2
External clock
drive
200
200
Sub clock base oscillation
input rise time, fall time
Note) tsys indicates the four values below according to the upper two bits (PCK1,PCK0) of the clock control
register (CLC: 0002FEh) during main mode and tsys = 2/fTEX = 61.04µs during sub mode.
tsys [ns] = 2/fEX (PCK1, PCK0 = 00), 4/fEX (PCK1, PCK0 = 01), 8/fEX (PCK1, PCK0 = 10), 16/fEX (PCK1,
PCK0 = 11)
1/fc
0.7VDD
EXTAL
0.3VDD
tXH
tXF
tXL
tXR
1/fTEX
0.7VDD
0.3VDD
TEX
tTH
tTF
tTL
tTR
Fig.1. Clock timing
Oscillator connection
example of
main oscillation circuit
Oscillator connection
example of
sub oscillation circuit
Connection example of
external clock
(TEX)
(TX)
EXTAL
XTAL
TEX
TX
EXTAL
XTAL
74HC04
Fig.2. Oscillator connection and clock applied conditions
– 20 –
CXP921064A
(2) Event count input
(Topr = –20 to +75°C, VDD = 2.7 to 3.3V, Vss = 0V reference)
Item
Symbol
Pins
EC
Conditions
Min.
Max.
Unit
ns
Event count input clock
pulse width
tEH,
EL
Fig.3
tsys + 100
t
0.8VDD
0.2VDD
EC
tEH
tEL
Fig.3. Event count input timing
(3) Interruption and reset input
(Topr = –20 to +75°C, VDD = 2.7 to 3.3V, Vss = 0V reference)
Item
Symbol
Pins
Conditions
Main mode
Sub mode
Sleep mode
Min.
Max.
Unit
ns
tsys + 100
NMI
INT0 to INT7
KS0 to KS15
Clock mode
Stop mode
µs
ns
ns
t
t
IH,
IL
1
External interruption
high, low level width
2tsys + 100
32/fEX + 100
128/fEX + 100
φ
Noise filter
selected
INT4 to INT7
PS4
PS6
Reset input low level
width
t
RST
RST
Fig.5
3tsys + 200
tIH
tIL
0.8VDD
NMI
INT0 to INT7
KS0 to KS15
0.2VDD
Fig.4. Interruption input timing
tRST
RST
0.2VDD
Fig.5. Reset input timing
– 21 –
CXP921064A
(4) A/D converter characteristics
(Topr = –20 to +75°C, VDD = AVDD = AVREF = 2.7 to 3.3V, Vss = AVss = 0V reference)
Item
Symbol
Pins
Conditions
Min.
Typ.
Max.
8
Unit
Bits
LSB
LSB
µs
Resolution
±1
Linearity error
Absolute error
Conversion time
Sampling time
VDD = AVDD = AVREF = 3.0V
±3
t
t
CONV
SAMP
34tsys
9tsys
µs
Reference input
voltage
VREF
VIAN
IREF
AVREF
VDD = AVDD = AVREF
3.3
AVREF
1.5
V
V
2.7
0
Analog input
voltage
AN0 to AN23
Main mode
Sub mode
mA
1.1
AVREF0
AVREF1
AVREF current
Clock mode
Stop mode
IREFS
10
µA
during ADC off state
When Bit 14 (ADOFF) of A/D control status register (ADCS0: 00013Ch,ADCS1: 00014Ch) is specified to "1".
Note) AVDD and AVREF must be the same voltage with VDD.
(100h)
FFh
FEh
FFh
FEh
Linearity error
Analog input
Absolute error
Analog input
01h
00h
01h
00h
2
1
AVREF
VFT
VZT
Absolute error
1 VZT: Value at which the digital conversion value changes from 00h to 01h and vice versa.
2 VFT: Value at which the digital conversion value changes from FEh to FFh and vice versa.
Fig.6. Definition of A/D converter terms
– 22 –
CXP921064A
(5) Serial transfer (CH0, CH1, CH2)
(Topr = –20 to +75°C, VDD = 2.7 to 3.3V, Vss = 0V reference)
Item
Symbol Pins
Conditions
Min.
Max.
Unit
ns
SCK0
SCK1
SCK2
CS ↓ → SCK
delay time
External start transfer mode
(SCK = output mode)
tDCSK
tDCSKF
tDCSO
tDCSOF
tWHCS
t
KCY
1.5
1.5
1.5
1.5
t
t
t
t
sys + 200
SCK0
SCK1
SCK2
CS ↑ → SCK
float delay time
External start transfer mode
(SCK = output mode)
ns
ns
ns
ns
sys + 200
sys + 200
sys + 200
SO0
SO1
SO2
CS ↓ → SO
delay time
External start transfer mode
External start transfer mode
External start transfer mode
CS0
CS1
CS2
CS ↑ → SO
float delay time
CS0
CS1
CS2
CS high level width
SCK cycle time
tsys + 100
Input mode
SCK0
SCK1
SCK2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2tsys + 200
16/fEX
Output mode
Input mode
SCK0
SCK1
SCK2
tsys + 100
8/fEX – 100
100
t
t
KH
KL
SCK
high, low pulse width
Output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
SI0
SI1
SI2
SI input data setup time
(for SCK ↑)
tSIK
tKSI
tKSO
t
INT
200 – tsys
tsys + 100
tsys + 100
SI0
SI1
SI2
SI input data hold time
(for SCK ↑)
SO0
SO1
SO2
tsys + 150
100
SCK ↓ → SO
delay time
SCK0 SCK input mode
SCK1
SCK output mode
SCK2
3tsys + 100
8/fEX – 100
Minimum interval time
Note) The load condition for the SCK output mode and SO output delay time is 100pF.
– 23 –
CXP921064A
tWHCS
0.8VDD
CS0
CS1
CS2
0.2VDD
tKCY
tDCSK
tDCSKF
tKL
tKH
0.8VDD
0.2VDD
SCK0
SCK1
SCK2
tSIK tKSI
0.8VDD
0.2VDD
SI0
SI1
SI2
Input data
tDCSOF
tDCSO
tKSO
0.8VDD
SO0
SO1
SO2
Output data
0.2VDD
tINT
0.8VDD
SCK0
SCK1
SCK2
Fig.7. Serial transfer CH0, CH1, CH2 timing
– 24 –
CXP921064A
(6) Serial transfer (CH3) [SIO mode]
(Topr = –20 to +75°C, VDD = 2.7 to 3.3V, Vss = 0V reference)
Item
Symbol Pins
Conditions
Min.
2tsys + 200
16/fEX
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Input mode
t
KCY
SCK cycle time
Output mode
SCK3
Input mode
tsys + 100
8/fEX – 100
100
t
t
KH
KL
SCK high, low pulse
width
Output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
SI input data setup
time (for SCK ↑)
t
t
t
SIK
200
SI3
tsys + 100
200
SI input data hold
time (for SCK ↑)
KSI
tsys + 150
100
SCK ↓ → SO delay
SO3
KSO
time
Note) The load condition for the SCK output mode and SO output delay time is 100pF.
tKCY
tKL
tKH
SCK3
0.8VDD
0.2VDD
tSIK
tKSI
0.8VDD
0.2VDD
Input data
SI3
tKSO
0.8VDD
Output data
SO3
0.2VDD
Fig.8. Serial transfer CH3 timing (SIO mode)
– 25 –
CXP921064A
(7) Serial transfer (CH3) [Special mode]
(Topr = –20 to +75°C, VDD = 2.7 to 3.3V, Vss = 0V reference)
Item
SO cycle time
Symbol Pins
SO3
Conditions
Min. Typ. Max. Unit
104
tLCY
tLSU
tLHD
tLSBH
t
LIO
SI3
SI input setup time
SI input hold time
fEX = 20MHZ
SI3
2
µs
SI3
2
1
Input start bit high level
width
SI3
Communication slave mode
SI → SO
delay time
SO3
1
When lower 2 bits (SCK1, SCK0) of serial mode register (SIOM3: 0001A4h) is specified to "00".
Note) The load condition for the SO output delay time is 100pF.
tLCY
tLCY
0.5VDD
Start bit
Output data bit
SO3
tLCY/2
tLSU tLHD
0.8VDD
Input data
bit
SI3
0.2VDD
Fig.9. Serial transfer CH3 timing (Special mode)
tLSBH
0.8VDD
0.2VDD
Input data bit
SI3
tLSU
tLHD
tLHD
tLSU
tLCY/2
tLCY
tLIO
tLCY
tLCY
SO3
Output data bit
0.5VDD
Fig.10. Serial transfer CH3 timing (Special mode)
– 26 –
CXP921064A
(8) I2C bus (CH0, CH1)
(Topr = –20 to +75°C, VDD = 2.7 to 3.3V, Vss = 0V reference)
Standard mode
High-speed mode
Item
Symbol
Pins
SCL0
Unit
Min.
0
Max.
100
Min.
0
Max.
400
t
t
t
t
t
t
t
t
SCL
kHz
µs
µs
µs
µs
µs
µs
ns
ns
ns
µs
SCK clock frequency
SCL1
Bus free time between
stop and start conditions
SDA0
SDA1
BUF
4.7
4.0
4.7
4.0
4.7
0
1.3
0.6
Hold time under (resend)
start condition
SDA0, SDA1
SCL0, SCL1
HD;STA
Low
Hold time in SCL clock
low state
SCL0
SCL1
1.3
Hold time in SCL clock
high state
SCL0
SCL1
High
0.6
Setup time under (resend)
start condition
SDA0, SDA1
SCL0, SCL1
SU;STA
HD;DAT
SU;DAT
0.6
SDA0, SDA1
SCL0, SCL1
0.9
0
Data hold time
Data setup time
SDA0, SDA1
SCL0, SCL1
250
100
20 + α
20 + α
0.6
t
Rd
Rc
SCL, SDA signal output
rise time
SDA0, SDA1
SCL0, SCL1
1000
300
300
300
t
t
Fd
Fc
SCL, SDA signal output
fall time
SDA0, SDA1
SCL0, SCL1
t
Setup time under stop
condition
SDA0, SDA1
SCL0, SCL1
tSU;STO
4.0
Due to the total capacitance of the bus.
tSU;DAT
tBUF
SDA0
SDA1
tHD;STA
tRd
tFd
tSCL
tRc
tFc
tLow
SCL0
SCL1
tHD;STA
tHD;DAT
tHigh
tSU;STA
tSU;STO
Fig.11. I2C bus timing
– 27 –
CXP921064A
(9) Remote control reception
(Topr = –20 to +75°C, VDD = 2.7 to 3.3V, Vss = 0V reference)
Item
Symbol Pins
Conditions
PS5 selected
Min.
Max.
Unit
128/fEX + 100
512/fEX + 100
2048/fEX + 100
4/fTEX + 100
8/fTEX + 100
PS7 selected
PS9 selected
32k selected
Main mode
Remote control receive
high, low level width
ns
RMC
tRMC
Sub mode
0.8VDD
RMC
0.2VDD
tRMC
tRMC
Fig.12. Remote control signal input timing
– 28 –
CXP921064A
Appendix
(i) Main oscillation circuit
(ii) Main oscillation circuit
(iii) Sub oscillation circuit
EXTAL
XTAL
Rd
EXTAL
XTAL
Rd
TEX
TX
Rf
Rd
C1
C2
C1
C2
C2
C1
Fig.13. Recommended oscillation circuit
Manufacturer
Model
fc (MHz)
12.0
C1 (pF)
30
C2 (pF)
30
Rd (Ω) Circuit example
Remarks
CSA12.0MG
0
0
0
0
0
(i)
CSA16.00MXZ040
CSA20.00MXZ040
CST12.0MTW
CST16.00MXW0C3
16.0
15
15
MURATA MFG
CO., LTD.
20.00
12.0
10
10
30
30
(ii)
(i)
16.0
15
15
RIVER ELETEC
CO., LTD.
CL = 10pF
CL = 12pF
HC-49/U03
HC-49/U-S
12.00
10
10
220
12.0
16.0
20.0
12.0
16.0
20.0
12
12
12
12
12
12
1.0k
470
390
(i)
KINSEKI LTD.
CCR12.0MSC5
CCR16.0MSC6
CCR20.0MSC6
VTC-200
20 (±20%) 20 (±20%)
10 (±20%) 10 (±20%)
10 (±20%) 10 (±20%)
TDK
Corporation
(ii)
0
Seiko
Rf = 10MΩ
CL = 12.5pF
32.768kHZ
20
18
150k
(iii)
Instruments Inc. SP-T
Indicates types with on-chip grounding capacitor (C1, C2). CCR : Surface mounted type ceramic oscillator.
CL : Load capacitor
Mask option table
Item
Content
Reset pin pull-up resistor
Non-existent
Existent
– 29 –
CXP921064A
Notes on PF7 Usage
FLASH EEPROM incorporated PF7 is also used as flash mode setting function. Note the followings:
1. "H" is output to PF7 during a reset. That is driven at comparatively high impedance (approximately 150 kΩ),
and take care that VOH should not fall under 0.7 VDD by the partial pressure with external circuit load
impedance.
2. When using software reset functions, PF7 may not rise enough during a reset. Switching PF7 to "H" output
prior to software reset execution or connecting pull-up resistor is recommended.
RST
Normal operation
PF7
Flash mode
Keep PF7 above 0.7 VDD during
this period.
Mask ROM and piggy/evaluation chip do not have flash mode setting function. Considering that EEPROM
incorporated type is used, above countermeasure should be performed.
– 30 –
CXP921064A
Characteristics Curve
IDD vs. VDD
(fEX = 20MHz, Topr = 25°C, Typical)
IDD vs. VDD
(fEX = 20MHz, Topr = 25°C, Typical)
20
20
18
16
14
12
10
8
18
16
14
12
10
8
2 frequency dividing mode
4 frequency dividing mode
6
Sleep mode (2 frequency division)
Sleep mode (4 frequency division)
6
8 frequency dividing mode
16 frequency dividing mode
4
4
Sleep mode (8 frequency division)
Sleep mode (16 frequency division)
2
2
0
2.1
2.4
2.7
3
3.3
3.6
3.9
2.1
2.4
2.7
3
3.3
3.6
3.9
VDD – Supply voltage [V]
VDD – Supply voltage [V]
IDD vs. fEX
(VDD = 3V, Topr = 25°C, Typical)
IDD vs. VDD
(fTEX = 32kHz, Topr = 25°C, Typical)
30
20
18
16
14
12
10
8
32kHz mode
(instruction execution)
25
20
15
10
5
2 frequency dividing mode
4 frequency dividing mode
32kHz
sleep mode
6
32kHz
clock mode
4
8 frequency dividing mode
16 frequency dividing mode
2
0
0
2.1
2.4
2.7
3
3.3
3.6
3.9
0
5
10
15
20
25
VDD – Supply voltage [V]
fEX – Main clock base oscillation frequency [MHz]
IDD vs. fEX
(VDD = 3V, Topr = 25°C, Typical)
20
18
16
14
12
10
8
6
Sleep mode (2 frequency division)
4
Sleep mode (4 frequency division)
Sleep mode (8 frequency division)
Sleep mode (16 frequency division)
2
0
0
5
10
15
20
25
fEX– Main clock base oscillation frequency [MHz]
– 31 –
CXP921064A
Package Outline
Unit: mm
100PIN QFP (PLASTIC)
23.9 ± 0.4
+ 0.1
0.15 – 0.05
+ 0.4
20.0 – 0.1
80
51
50
81
A
31
100
1
30
+ 0.15
0.65
+ 0.35
2.75 – 0.15
0.3 – 0.1
0.13
0.15
M
+ 0.2
0.1 – 0.05
0° to 10°
DETAIL
A
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
EPOXY RESIN
SOLDER PLATING
QFP-100P-L01
QFP100-P-1420
SONY CODE
EIAJ CODE
LEAD MATERIAL
PACKAGE MASS
42/COPPER ALLOY
1.7g
JEDEC CODE
100PIN LQFP (PLASTIC)
16.0 ± 0.2
14.0 ± 0.1
75
51
76
50
A
26
M
100
(0.22)
1
25
0.13
+ 0.08
0.18 – 0.03
+ 0.05
0.127 – 0.02
0.5
+ 0.2
1.5 – 0.1
0.1
0.1 ± 0.1
NOTE: Dimension “ ” does not include mold protrusion.
0° to 10°
DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SOLDER PLATING
LQFP-100P-L01
LQFP100-P-1414
LEAD TREATMENT
LEAD MATERIAL
SONY CODE
EIAJ CODE
42 ALLOY
0.8g
JEDEC CODE
PACKAGE MASS
– 32 –
CXP921064A
Package Outline
Unit: mm
104PIN LFLGA
S
A
0.15
12.0
1.4MAX
0.01
X
PIN 1 INDEX
x4
0.20
S
DETAIL X
0.8
A
103 – φ0.40 ± 0.05
N
M
L
M
φ0.08
S A B
K
J
B
H
G
F
E
D
C
B
A
2
1
3 4 5 6 7 8 9 10111213
1.2
0.4
1.6
PACKAGE STRUCTURE
ORGANIC SUBSTRATE
PACKAGE MATERIAL
TERMINAL TREATMENT
TERMINAL MATERIAL
PACKAGE MASS
SONY CODE
EIAJ CODE
LFLGA-104P-02
GOLD PLATING
NICKEL PLATING
0.4g
LFLGA104-P-1212
JEDEC CODE
– 33 –
相关型号：
CXP921F064AGA
Microcontroller, 16-Bit, FLASH, SPC950 CPU, 20.5MHz, CMOS, PBGA104, 12 X 12 MM, 0.80 MM PITCH, PLASTIC, LFLGA-104
SONY
CXP921F064AR
Microcontroller, 16-Bit, FLASH, SPC950 CPU, 20.5MHz, CMOS, PQFP100, 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100
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CXP922032Q
Microcontroller, 16-Bit, MROM, SPC950 CPU, 20MHz, CMOS, PQFP100, 14 X 20 MM, PLASTIC, QFP-100
SONY
CXP922P032Q
Microcontroller, 16-Bit, OTPROM, SPC950 CPU, 20MHz, CMOS, PQFP100, 14 X 20 MM, PLASTIC, QFP-100
SONY
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