LCX033AK [SONY]
1.1cm (0.44 Type) NTSC/PAL Color LCD Panel; 1.1厘米（ 0.44型）的NTSC / PAL彩色液晶面板
| 型号： | LCX033AK |
| 厂家： | 
SONY CORPORATION |
| 描述： | 1.1cm (0.44 Type) NTSC/PAL Color LCD Panel |
| 文件： | 总23页 (文件大小：278K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LCX033AK
1.1cm (0.44 Type) NTSC/PAL Color LCD Panel
Description
The LCX033AK is a 1.1cm diagonal active matrix
TFT-LCD panel addressed by polycrystalline silicon
super thin film transistors with built-in peripheral
driving circuit. This panel provides full-color
representation in NTSC/PAL mode. RGB dots are
arranged in a delta pattern featuring high picture
quality of no fixed color patterns, which is inherent in
vertical stripes and mosaic pattern arrangements.
Features
• The number of active dots: 180,000 (0.44 Type; 1.115cm in diagonal)
• Horizontal resolution: 400 TV lines
• High optical transmittance: 4.0% (typ.)
• High contrast ratio with normally white mode: 200 (typ.)
• Built-in H and V drivers (built-in input level conversion circuit, TTL drive possible)
• High quality picture representation with RGB delta arranged color filters
• Full-color representation
• NTSC/PAL compatible
• Up/down and/or right/left inverse display function
• 4:3 and 16:9 aspect switching function
• Power save mode (Through current reduction by stop of level shifter and scanner during power supply cutoff)
Element Structure
• Dots
Total dots : 827 (H) × 228 (V) = 188,556
Active dots: 800 (H) × 225 (V) = 180,000
• Built-in peripheral driver using polycrystalline silicon super thin film transistors.
Applications
• Viewfinders
• Super compact liquid crystal monitors etc.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E99715A03
LCX033AK
Block Diagram
13
6
12 11 10
9
8
7
5
4
3
2
1
15 14
16
H Level
Conversion
Circuit
H Shift Register
Up/down
BLK Control
Circuit
V Level
Conversion
Circuit
CS
LC
COM
Pad
– 2 –
LCX033AK
Absolute Maximum Ratings (VSS = 0V)
• H and V driver supply voltages
• Common pad voltage
VDD
–1.0 to +17
–1.0 to +17
–1.0 to +17
V
V
V
COM
• H driver input pin voltage
HST, HCK1, HCK2
RGT
• V driver input pin voltage
VST, VCK
EN, BLK, DWN
STB
–1.0 to +17
V
• Power save mode input pin voltage
• Video signal input pin voltage
• Operating temperature
–1.0 to +17
–1.0 to +15
–10 to +70
–30 to +85
V
V
GREEN, RED, BLUE
Topr
°C
°C
• Storage temperature
Tstg
Operating Conditions (VSS = 0V)
Supply voltage
VDD
11.4 to 14.0
V
Input pulse voltage (Vp-p of all input pins except video signal input pins)
Vin
2.6V (more than)
Pin Description
Pin
No.
Pin
No.
Symbol
COM
Description
Symbol
RGT
Description
Drive direction pulse for H shift
register (H: normal, L: reverse)
1
Common voltage of panel
Video signal (G) to panel
Video signal (R) to panel
Video signal (B) to panel
Top/bottom block display pulse
9
Drive direction pulse for V shift
register (H: normal, L: reverse)
2
3
4
5
6
7
8
GREEN
RED
10
11
12
13
14
15
16
DWN
EN
Enable pulse for gate selection
For power save mode control
(L-power save mode)
BLUE
BLK
STB
VCK
VST
Vss
Clock pulse for V shift register
drive
Clock pulse for H shift register
drive
Start pulse for V shift register
drive
HCK1
HCK2
HST
Clock pulse for H shift register
drive
GND (H, V drivers)
Start pulse for H shift register
drive
VDD
Power supply for H and V drivers
– 3 –
LCX033AK
Input Equivalent Circuit
To prevent static charges, protective diodes are provided for each pin except the power supply. In addition,
protective resistors are added to all pins except video signal input. All pins are connected to Vss with a high
resistance of 1MΩ (typ.). The equivalent circuit of each input pin is shown below: (The resistor value: typ.)
(1) Video signal input
From H driver
VDD
Input
1MΩ
Signal line
(2) HCK1, HCK2
VDD
250Ω
Level conversion
circuit (2-phase
input)
250Ω
250Ω
HCK1
250Ω
1MΩ
1MΩ
HCK2
(3) HST
VDD
Level conversion
circuit (single-
phase input)
250Ω
250Ω
Input
1MΩ
(4) RGT, VST, EN, VCK, BLK, DWN, STB
VDD
2.5kΩ
Level conversion
circuit (single-
phase input)
2.5kΩ
Input
1MΩ
(5) COM
VDD
Input
1MΩ
LC
– 4 –
LCX033AK
Level Conversion Circuit
The LCX033AK has a built-in level conversion circuit in the clock input unit located inside the panel. The circuit
voltage is stepped up to VDD inside the panel. This level conversion circuit meets the specifications of a 3.0V
power supply of the externally-driven IC.
1. I/O characteristics of level conversion circuit
VDD
(For a single-phase input unit)
An example of the I/O voltage characteristics of a level
conversion circuit is shown in the figure to the right.
Example of single-phase
I/O characteristics
The input voltage value that becomes half the output
voltage (after voltage conversion) is defined as Vth.
VDD
2
The Vth value varies depending on the VDD voltage.
The Vth values under standard conditions are
indicated in the table below. (HST, VST, EN, RGT,
VCK, BLK, DWN and STB in the case of a single-
Vth
phase input)
Input voltage [V]
VDD = 12.0V
Item
Symbol
Vth
Min.
0.35
Typ.
1.50
Max. Unit
2.60
Vth voltage of circuit
V
VDD
(For a differential input unit)
An example of I/O voltage characteristics of a level
conversion circuit for a differential input is shown in
the figure to the right. Although the characteristics,
including those of the Vth voltage, are basically the
same as those for a single-phased input, the two-
phased input phase is defined. (Refer to clock
timing conditions.)
Example of differential I/O
characteristics
VDD
2
Vth
Input voltage [V]
2. Current characteristics at the input pin of level conversion circuit
VDD
A slight pull-in current is generated at the input pin
of the level conversion circuit. (The equivalent
circuit is shown to the right.) The current volume
increases as the voltage at the input pin decreases,
and is maximized when the pin is grounded. (Refer
to electrical characteristics.)
Input pin voltage [V]
10
0
output
0
HCK1
input
HCK2
input
Max. value
Level conversion equivalent circuit
Pull-in current characteristics at the input pin
– 5 –
LCX033AK
Input Signals
1. Input signal voltage conditions (VSS = 0V, VDD = 11.4 to 14V)
Item
H driver input voltage
Symbol
VHIL
Min.
–0.35
2.6
Typ.
0.0
3.0
0.0
3.0
Max.
0.35
3.5
Unit
(Low)
(High)
(Low)
(High)
V
V
V
V
V
(HST, HCK1, HCK2, RGT)
VHIH
VVIL
–0.35
2.6
0.35
3.5
V driver input voltage
(VST, VCK, EN, BLK, DWN)
VVIH
VCOM
Common voltage of panel
VVC – 0.45 VVC – 0.3 VVC – 0.15
Item
Video signal input range
Video signal input white level
Symbol
Vsig
Min.
VSS + 1.3
0.5
Typ.
Max.
Unit
V
VDD – 1.8
VsigL
V
Note) Video signal shall be symmetrical to video signal center voltage VVC.
Supplement1) Video signal input range is set within the range shown below for VDD and VSS.
Also, video signal white level is defined for VVC as shown below.
VDD
VDD – 1.8
Video signal input range
Max. VDD – 1.8 [V]
Min. VSS + 1.3 [V]
White level
VsigL
VsigL
VVC
VSS + 1.3
VSS
Supplement2) When power save mode is used, use video signal and COM pin within the condition ±0.15V to
prevent DC applying to LCD.
– 6 –
LCX033AK
2. Clock timing conditions (Ta = 25°C, Input voltage = 3.0V, VDD = 12.0V)
Item
Symbol
trHst
Min.
Typ.
Max.
30
Unit
Hst rise time
Hst fall time
tfHst
30
HST
HCK
VST
Hst data set-up time
Hst data hold time
Hckn 2 rise time
Hckn 2 fall time
Hck1 fall to Hck2 rise time
Hck1 rise to Hck2 fall time
Vst rise time
tdHst
thHst
trHckn
tfHckn
to1Hck
to2Hck
trVst
–100
–200
60
100
–50
30
–120
ns
30
–15
–15
0
0
15
15
100
100
50
Vst fall time
tfVst
Vst data set-up time
Vst data hold time
Vck rise time
tdVst
thVst
trVck
tfVck
trEn
–50
–50
32
µs
ns
–32
–20
100
100
100
100
100
100
100
VCK
EN
Vck fall time
En rise time
En fall time
tfEn
Vck rise/fall to En fall time
BLK rise time
tdVck
trBlk
–100
600
0
BLK fall time
tfBlk
3
BLK
BLK pulse width
BLK fall to CLR fall time
twBlk
toClr
1.0
ms
ns
700
800
2 Hckn means Hck1, Hck2. (fHckn = 1.84MHz, fVckn = 7.865kHz)
3 BLK pulse is used only for 16:9 mode. For 4:3 mode, connect to VSS.
– 7 –
LCX033AK
<Horizontal Shift Register Driving Waveform>
Item
Symbol
Waveform
Conditions
90%
90%
2
• HCKn
Hst rise time
trHst
duty cycle 50%
to1Hck = 0ns
to2Hck = 0ns
HST 10%
10%
tfHst
Hst fall time
tfHst
trHst
4
HST
50%
HST
50%
Hst data set-up time
tdHst
2
• HCKn
duty cycle 50%
to1Hck = 0ns
to2Hck = 0ns
HCK1
50%
50%
Hst data hold time
thHst
tdHst
90%
10%
thHst
90%
10%
2
• HCKn
Hckn 2 rise time
Hckn 2 fall time
trHckn
tfHckn
duty cycle 50%
to1Hck = 0ns
to2Hck = 0ns
tdHst = 135ns
thHst = –135ns
2
HCKn
trHckn
tfHckn
HCK
4
50%
50%
Hck1 fall to Hck2 rise
time
HCK1
to1Hck
to2Hck
• tdHst = 135ns
thHst = –135ns
50%
50%
HCK2
Hck1 rise to Hck2 fall
time
to2Hck
to1Hck
– 8 –
LCX033AK
<Vertical Shift Register Driving Waveform>
Item
Symbol
Waveform
Conditions
90%
90%
Vst rise time
trVst
• VCK
duty cycle 50%
VST
10%
50%
10%
50%
Vst fall time
tfVst
trVst
tfVst
4
VST
VCK
EN
Vst data set-up time
tdVst
VST
50%
50%
• VCK
duty cycle 50%
VCK
VCK
Vst data hold time
thVst
tdVst
thVst
90%
10%
90%
10%
Vck rise time
Vck fall time
En rise time
En fall time
trVck
tfVck
trEn
• VCK
duty cycle 50%
tdVst = 32µs
thVst = –32µs
trVck
tfVck
90%
90%
• VCK
10% 10%
duty cycle 50%
to1Vck = 0ns
to2Vck = 0ns
EN
tfEn
tfEn
trEn
4
50%
50%
VCK
Vck rise to En rise time tdVck
Vck rise to En fall time tdVck
• VCK
duty cycle 50%
to1Vck = 0ns
to2Vck = 0ns
50%
50%
EN
tdVck
90%
tdVck
90%
BLK rise time
BLK fall time
trBlk
tfBlk
10%
trBlk
10%
tfBlk
BLK
4
50%
50%
twBlk
BLK pulse width
twBlk
toClr
BLK
50%
BLK fall to CLR fall
time
CLR
4
Definitions:
The right-pointing arrow (
The left-pointing arrow (
The black dot at an arrow (
) means +.
) means –.
) indicates the start of measurement.
– 9 –
LCX033AK
Electrical Characteristics
(Ta = 25°C, VDD = 12.0V, Input voltage = 3.0V)
1. Horizontal drivers
Item
Symbol
CHckn
CHst
IHck1
IHck2
IHst
Min.
Typ.
5
Max.
10
Unit
pF
pF
µA
µA
µA
µA
µA
pF
Condition
Input pin capacitance
HCKn
HST
5
10
Input pin current
HCK1
HCK2
HST
–500
–500
–300
–100
–100
–130
–150
–20
–15
–15
50
HCK1 = GND
HCK2 = GND
HST = GND
RGT = GND
STB = GND
RGT
STB
IRgt
Istb
Video signal input pin capacitance
Csig
2. Vertical drivers
Item
Symbol
CVck
Min.
Typ.
5
Max.
10
Unit
pF
Condition
Input pin capacitance
VCK
VST
CVst
5
10
pF
VST
EN
DWN
VCK
BLK
IVst
IEn
IDwn
IVck
IBlk
VST, EN, DWN, VCK,
BLK = GND
–100
–15
µA
3. Total power consumption of the panel
Item
Symbol
PWR
Min.
Typ.
Max.
Unit
Total power consumption of
the panel (NTSC)
30
50
mW
mW
Power consumption during
power save
0.6
4. VCOM input resistance, Video signal input resistance
Item
Symbol
Min.
0.5
Typ.
1
Max.
1.2
Unit
MΩ
MΩ
VCOM – Vss input resistance Rcom
Video signal – Vss input resistance Rsig
0.5
1
1.2
– 10 –
LCX033AK
Electro-optical Characteristics
Item
(Ta = 25°C, NTSC mode)
Measurement
method
Symbol
Unit
Min
Typ.
Max.
60°C
25°C
60°C
X
CR4.060
CR4.025
T
70
70
200
200
4.0
—
—
Contrast VDD = 12.0V
—
%
1
2
ratio
Vsig = 6.0 ± 4.0V
Optical transmittance
3.2
—
Rx
0.580
0.300
0.250
0.550
0.105
0.070
1.1
0.620
0.340
0.290
0.590
0.140
0.110
1.6
0.660
0.380
0.330
0.630
0.175
0.150
2.2
R
G
Y
Ry
X
Gx
CIE
standards
Chromaticity
3
Y
Gy
X
Bx
B
Y
By
25°C
60°C
25°C
60°C
25°C
60°C
V90-25
V90-60
V50-25
V50-60
V10-25
V10-60
V90
V50
V10
1.0
1.5
2.1
1.5
2.0
2.5
V-T
characteristics
4
V
1.4
1.9
2.4
2.2
2.6
3.2
2.1
2.5
3.1
R vs. G V50RG
B vs. G V50BG
—
–0.10
0.07
30
–0.25
0.45
100
40
Half tone color reproduction
range
5
6
V
—
0°C
25°C
0°C
ton0
ton25
toff0
toff25
F
—
ON time
Response time
—
20
ms
—
65
150
60
OFF time
25°C
60°C
—
25
Flicker
7
8
—
—
–40
20
dB
s
Image retention time
60 min. YT60
—
—
– 11 –
LCX033AK
<Electro-optical Characteristics Measurement>
Basic measurement conditions
(1) Driving voltage
VDD = 12.0V
VVC = 6.0V, VCOM = 5.70V
(2) Measurement temperature
25°C unless otherwise specified.
(3) Measurement point
One point in the center of screen unless otherwise specified.
(4) Measurement systems
Two types of measurement system are used as shown below.
(5) RGB input signal voltage (Vsig)
Vsig = 6.0 ± VAC [V] (VAC: signal amplitude)
Measurement system I
3.5mm
Measurement
Equipment
Luminance
Meter
Back light: color temperature 8500K, +0.004uV (25°C)
Back light spectrum (reference) is listed on another page.
LCD panel
Measurement system II
Optical fiber
Measurement
Equipment
Light receptor lens
Light Detector
Drive Circuit
LCD panel
Light Source
1. Contrast Ratio
Contrast Ratio (CR4.0) is given by the following formula (1).
L4.0 (White)
L4.0 (Black)
CR4.0 =
...(1)
L4.0 (White): Surface luminance of the TFT-LCD panel at VDD = 12.0V, VVC = 6.0V, VCOM = 5.7V and the
RGB signal amplitude VAC = 0.5V.
L4.0 (Black): Surface luminance of the panel at VAC = 4.0V.
– 12 –
LCX033AK
2. Optical Transmittance
Optical Transmittance (T) is given by the following formula (2).
L (White)
Luminance of Back Light
T =
× 100 [%] ...(2)
L (White) is the same expression as defined in the "Contrast Ratio" section.
3. Chromaticity
Chromaticity of the panels are measured by System I. Raster modes of each color are defined by the
representations at the input signal amplitude conditions shown in the table below. System I uses
Chromaticity of x and y on the CIE standards here.
Signal amplitudes (VAC) supplied to each input
R input
0.5
G input
4.0
B input
4.0
R
G
B
0.5
4.0
4.0
4.0
4.0
0.5
(Unit: V)
4. V-T Characteristics
V-T characteristics, the relationship between signal
amplitude and the transmittance of the panels, are
measured by System II. V90, V50 and V10 correspond to
the each voltage which defines 90%, 50% and 10% of
transmittance respectively. (Transmittance at VAC =
0.5V is 100%.)
90
50
10
V90 V50 V10
VAC – Signal amplitude [V]
5. Half Tone Color Reproduction Range
Half tone color reproduction range of the LCD panels is
characterized by the differences between the V-T
characteristics of R, G and B. The differences of these
V-T characteristics are measured by System II. System
II defines signal voltages of each R, G, B raster modes
which correspond to 50% of transmittance, V50R, V50G
and V50B respectively. V50RG and V50BG, the voltage
differences between V50R and V50G, V50B and V50G, are
simply given by the following formulas (3) and (4)
respectively.
100
50
0
V50RG
V50BG
G raster
B raster
R raster
V50R V50B
V50G
V50RG = V50R – V50G ...(3)
V50BG = V50B – V50G ...(4)
VAC – Signal amplitude [V]
– 13 –
LCX033AK
6. Response Time
Input signal voltage (waveform applied to the measured pixels)
Response time ton and toff are defined by
the formulas (5) and (6) respectively.
4.0V
6.0V
0.5V
ton = t1 – tON ...(5)
toff = t2 – tOFF ...(6)
t1: time which gives 10% transmittance of
the panel.
0V
t2: time which gives 90% transmittance of
the panel.
Optical transmittance output waveform
100%
90%
The relationships between t1, t2, tON and
tOFF are shown in the right figure.
10%
0%
tON t1
ton
tOFF t2
toff
7. Flicker
Flicker (F) is given by the formula (7). DC and AC (NTSC: 30Hz, rms, PAL: 25Hz, rms) components of the
panel output signal for gray raster mode are measured by a DC voltmeter and a spectrum analyzer in
System II.
AC component
DC component
R, G, B input signal condition for gray raster mode
is given by Vsig = 6.0 ± V50 (V)
F (dB) = 20log
...(7)
{
}
where: V50 is the signal amplitude which gives 50%
of transmittance in V-T characteristics.
8. Image Retention Time
Apply the monoscope signal to the LCD panel for 60 minutes and then change this signal to the gray scale
of Vsig = 6.0 ± VAC (VAC: 3 to 4V), judging by sight at VAC that hold the maximum image retention, measure
the time till the residual image becomes indistinct.
Monoscope signal conditions:
Vsig = 6.0 ± 4.0 or 6 ± 2.0 (V)
(shown in the right figure)
VCOM = 5.7V
Black level
White level
4.0V
2.0V
6.0V
0V
2.0V
4.0V
Vsig waveform
– 14 –
LCX033AK
9. Method of Measuring the Optimum Vcom
There are two methods of measuring the optimum Vcom using the photoelectric element.
9-1. Method of Measuring Flicker
In the field invert drive mode, adjust the flicker level of the half tone (Vsig = 1.5 to 2.5V) using the
photoelectric element and oscilloscope so that its 30Hz component becomes minimum. The Vcom value
at this time is taken to be the optimum Vcom.
9-2. Method of Measuring Contrast
In the normal 1H invert drive mode, adjust the optical output voltage of the half tone (Vsig = 1.5 to 2.5V)
so that it becomes minimum. The Vcom value at this time is taken to be the optimum Vcom.
Example of Back Light Spectrum (Reference)
0.6
0.4
0.2
0
380
480
580
680
780
Wave length 380 – 780 [nm]
– 15 –
LCX033AK
Description of Operation
1. Color Coding
Color filters are coded in a delta arrangement.
The shaded area is used for the dark border around the display.
Gate SW
dummy1 to 4
Gate SW
dummy5 to 8
Gate SW
Gate SW
Gate SW
Gate SW
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
R
G
B
R
G
B
R
G
B
B
R
R
G
B
R
G
B
R
G
B
B
R
R
G
G
B
B
R
R
G
G
B
B
R
G
B
R
G
G
B
B
R
R
G
G
B
B
R
R
R
R
G
G
B
B
R
R
G
G
B
B
R
R
G
G
G
B
B
R
R
G
G
B
B
R
R
G
G
Active area
R
R
B
R
G
B
B
R
R
G
G
B
B
R
R
G
G
B
B
R
R
G
G
B
B
R
R
G
G
B
B
R
R
R
G
B
R
R
G
G
B
B
R
R
G
G
B
B
G
G
B
B
R
R
G
G
B
B
R
R
G
G
Photo-shielding
R
G
B
827
14
800
13
– 16 –
LCX033AK
2. LCD Panel Operations
• A vertical driver, which consists of vertical shift registers, enable-gates and buffers, applies a selected pulse
to every 225 gate lines sequentially in every horizontal scanning period. A vertical shift register scans the
gate lines from the top to bottom of the panel at DWN = High level.
• The selected pulse is delivered when the enable pin turns to High level. PAL mode images are displayed by
controlling the enable and VCK pin. The enable pin should be High when not in use.
• A horizontal driver, which consists of horizontal shift registers, gates and CMOS sample-and-hold circuits
applies selected pulses to every 800 signal electrodes sequentially in a single horizontal scanning period.
• Through current of the level shifter during power supply cutoff can be reduced by STB pin. (power save
mode)
Power save mode is set at STB = Low level.
• Vertical and horizontal drivers address one pixel and then turn on Thin Film Transistors (TFTs; two TFTs) to
apply a video signal to the dot. The same procedures lead to the entire 225 × 800 dots to display a picture in
a single vertical scanning period.
• Pixel dots are arranged in a delta pattern, where sets of RGB pixels are positioned with 1.5-dot shifted
against adjacent horizontal line. 1.5-dot shift of a horizontal driver output pulse against horizontal
synchronized signal is required to apply a video signal to each dot properly. 1H reversed displaying mode is
required to apply video signal to the panel.
• The video signal shall be input with polarity-inverted system in every horizontal cycle.
• The relationship between the vertical shift register start pulse VST and the vertical display period, and the
horizontal shift register start pulse HST during right scan (RGT = High level) and the horizontal display period
are shown below.
– 17 –
LCX033AK
• This LCD panel provides the following functions.
• Right/left inverse mode
• Up/down inverse mode
These modes are controlled by two signals, RGT and DWN.
RGT
H
Mode
Right scan
Left scan
DWN
Mode
Down scan
Up scan
H
L
L
When the horizontal direction is displayed with the left scan (RGT = low level), invert HCK1 and HCK2 and
input them. The center of image is not shifted away the correct position by inverting them. (When the system
configuration indicated on this data sheet is used, timing generator performs this operation automatically.)
(1) Vertical display cycle
VD
VST
VCK
1
2
224
225
Vertical display cycle 225H (14.3ms)
(2) Horizontal display cycle (right scan)
BLK
HST
270
271
HCK1
1
2
3
4
5
6
HCK2
Horizontal display cycle (48.4µs)
The horizontal display cycle consists of 800/3 = 267 clock pulses because of RGB simultaneous sampling.
Refer to Description of Operation "3. RGB Simultaneous Sampling."
– 18 –
LCX033AK
3. RGB Simultaneous Sampling
Horizontal driver samples R, G and B signal simultaneously, which requires the phase matching between R,
G and B signals to prevent horizontal resolution from deteriorating. Thus phase matching between each
signal is required using an external signal delaying circuit before applying video signal to the LCD panel.
Two methods are applied for the delaying procedure: Sample and hold and Delay circuit. These two block
diagrams are as follows.
The LCX033AK has the right/left inverse function. The following phase relationship diagram indicates the
phase setting for the right scan (RGT = High level). For the left scan (RGT = Low level), the phase setting
shall be inverted between B and G signals.
(1) Sample and hold (right scan)
B
4
3
2
BLUE
S/H
S/H
AC Amp
CKB
CKG
S/H
R
G
RED
S/H
AC Amp
AC Amp
CKR
CKG
S/H
GREEN
CKG
<Phase relationship of delaying sample-and-hold pulses> (right scan)
HCKn
CKB
CKR
CKG
(2) Delay circuit (right scan)
Delay
Delay
Delay
AC Amp
BLUE
B
4
3
2
RED
AC Amp
AC Amp
R
G
GREEN
– 19 –
LCX033AK
Example of Color Filter Spectrum (Reference)
100
Color Filter Spectrum
R
80
60
40
G
B
20
0
400
500
600
700
Wavelength [nm]
– 20 –
LCX033AK
Color Display System Block Diagram
An example of single-chip display system is shown below.
+12V
+3V
+12V
RED
GREEN
BLUE
Y/C
Y/color difference
VCOM
BLK
LCD panel
NTSC/PAL
LCX033AK
CXA3503R
HST
HCK1
HCK2
VST
VCK
EN
STB
DWN
RGT
Serial control
Control circuit
(microcomputer, etc.)
– 21 –
LCX033AK
Notes on Handling
(1) Static charge prevention
Be sure to take following protective measures. TFT-LCD panels are easily damaged by static charge.
a) Use non-chargeable gloves, or simply use bare hands.
b) Use an earth-band when handling.
c) Do not touch any electrodes of a panel.
d) Wear non-chargeable clothes and conductive shoes.
e) Install conductive mat on the working floor and working table.
f) Keep panels away from any charged materials.
g) Use ionized air to discharge the panels.
(2) Protection from dust and dirt
a) Operate in clean environment.
b) When delivered, a surface of a panel (Polarizer) is covered by a protective sheet. Peel off the
protective sheet carefully not to damage the panel.
c) Do not touch the surface of a panel. The surface is easily scratched. When cleaning, use a clean-room
wiper with isopropyl alcohol. Be careful not to leave stain on the surface.
d) Use ionized air to blow off dust at a panel.
(3) Other handling precautions
a) Do not twist or bend the flexible PC board especially at the connecting region because the board is
easily deformed.
b) Do not drop a panel.
c) Do not twist or bend a panel or a panel frame.
d) Keep a panel away from heat source.
e) Do not dampen a panel with water or other solvents.
f) Avoid to store or to use a panel in a high temperature or in a high humidity, which may result in panel
damages.
– 22 –
LCX033AK
Package Outline
Unit: mm
Thickness of the connector 0.3 ± 0.05
1.2 ± 0.3
12.5 ± 0.3
8.5 ± 0.05
4
1
5
2
3
6
Incident
light
Active area
6
2.7 ± 0.15
(8.96)
8.0 ± 0.25
16.0 ± 0.15
P 0.5 ± 0.02
No
1
Description
F P C
× 15 = 7.5 ± 0.03
Molding material
Outside frame
+ 0.04
0.35
2
– 0.03
3
0.5 ± 0.1
PIN 1
PIN 16
Reinforcing board
4
5
6
Reinforcing material
Polarizing film
Mass 1g
Electrode (enlarged)
– 23 –
Sony Corporation
相关型号：
LCX037BL
High Picture Quality 3.4 cm (1.35-Type) 1.05M-dot Wide XGA HDTV Projector LCD for the Coming Digital Age
SONY
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