AM27X512-150PI [SPANSION]
OTP ROM, 64KX8, 150ns, CMOS, PDIP28, PLASTIC, DIP-28;
| 型号： | AM27X512-150PI |
| 厂家： | 
SPANSION |
| 描述： | OTP ROM, 64KX8, 150ns, CMOS, PDIP28, PLASTIC, DIP-28 OTP只读存储器 有原始数据的样本ROM 光电二极管 内存集成电路 |
| 文件： | 总10页 (文件大小：135K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FINAL
Am27X512
512 Kilobit (64 K x 8-Bit) CMOS ExpressROM Device
DISTINCTIVE CHARACTERISTICS
■ As an OTP EPROM alternative:
— Factory optimized programming
— Fully tested and guaranteed
■ ±10% power supply tolerance
■ High noise immunity
■ Low power dissipation
— 100 µA maximum CMOS standby current
■ As a Mask ROM alternative:
— Shorter leadtime
■ Available in Plastic Dual-In-line Package (PDIP)
and Plastic Leaded Chip Carrier (PLCC)
— Lower volume per code
■ Latch-up protected to 100 mA from –1 V to
■ Fast access time
— 70 ns
VCC + 1 V
■ Versatile features for simple interfacing
— Both CMOS and TTL input/output compatibility
— Two line control functions
■ Single +5 V power supply
■ Compatible with JEDEC-approved EPROM
pinout
GENERAL DESCRIPTION
The Am27X512 is a factory programmed and tested
OTP EPROM. It is programmed after packaging prior to
final test. Every device is rigorously tested under AC
and DC operating conditions to your stable code. It is
organized as 64 Kwords by 8 bits per word and is avail-
able in plastic dual in-line packages (PDIP), as well as
plastic leaded chip carrier (PLCC) packages. Express-
ROM devices provide a board-ready memory solution
for medium to high volume codes with short leadtimes.
This offers manufacturers a cost-effective and flexible
alternative to OTP EPROMs and mask programmed
ROMs.
Data can be accessed as fast as 70 ns, allowing
high-performance microprocessors to operate with re-
duced WAIT states. The device offers separate Output
Enable (OE#) and Chip Enable (CE#) controls, thus
eliminating bus contention in a multiple bus micropro-
cessor system.
AMD’s CMOS process technology provides high
speed, low power, and high noise immunity. Typical
power consumption is only 80 mW in active mode, and
100 µW in standby mode.
BLOCK DIAGRAM
Data Outputs DQ0–DQ7
V
V
CC
SS
Output Enable
Chip Enable
and
OE#
CE#
Output
Buffers
Prog Logic
Y
Y
Gating
Decoder
A0–A15
Address
Inputs
524,288
Bit Cell
Matrix
X
Decoder
12081F-1
Publication# 12081 Rev: F Amendment/0
Issue Date: May 1998
PRODUCT SELECTOR GUIDE
Family Part Number
Am27X512
V
V
= 5.0 V ± 5%
= 5.0 V ± 10%
-255
CC
Speed Options
-70
70
70
70
-90
90
90
40
-120
-150
150
150
65
-200
200
200
75
CC
Max Access Time (ns)
CE# (E#) Access (ns)
OE# (G#) Access (ns)
120
120
50
250
250
100
CONNECTION DIAGRAMS
Top View
DIP
PLCC
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
A15
A12
A7
2
A14
A13
A8
4
3
2
1 32 31 30
3
A6
A5
5
6
A8
A9
29
28
A6
4
A5
A9
5
A4
A3
A2
A1
A0
NC
7
A11
NC
27
26
25
24
23
22
21
A4
A11
6
8
A3
OE# (G#)/VPP
A10
9
7
OE# (G#)/VPP
A10
10
11
12
13
A2
8
CE# (E#)
DQ7
A1
CE# (E#)
DQ7
9
A0
10
11
12
13
14
DQ0
DQ6
DQ0
DQ6
16 17
19 20
18
15
14
DQ1
DQ2
VSS
DQ5
DQ4
DQ3
12081F-3
12081F-2
Notes:
1. JEDEC nomenclature is in parenthesis.
2. Don’t use (DU) for PLCC.
PIN DESIGNATIONS
LOGIC SYMBOL
A0–A15
= Address Inputs
CE# (E#)
= Chip Enable Input
16
DQ0–DQ7 = Data Input/Outputs
OE# (G#) = Output Enable Input
PGM# (P#) = Program Enable Input
8
A0–A15
DQ0–DQ7
CE# (E#)
OE# (G#)
VCC
VPP
VSS
NC
= VCC Supply Voltage
= Program Voltage Input
= Ground
12081F-4
= No Internal Connection
2
Am27X512
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed
by a combination of the following:
AM27X512
XXXXX
-70
J
C
CODE DESIGNATION
Assigned by AMD
TEMPERATURE RANGE
C
I
= Commercial (0°C to +70°C)
= Industrial (–40°C to +85°C)
PACKAGE TYPE
P
J
= 28-Pin Plastic Dual In-Line Package (PD 028)
= 32-Pin Plastic Leaded Chip Carrier (PL 032)
SPEED OPTION
See Product Selector Guide and Valid Combinations
DEVICE NUMBER/DESCRIPTION
Am27X512
512 Kilobit (64 K x 8-Bit) CMOS ExpressROM Device
Valid Combinations
Valid Combinations
AM27X512-70
Valid Combinations list configurations planned to be sup-
ported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.
AM27X512-90
AM27X512-120
AM27X512-150
AM27X512-200
AM27X512-255
PC, JC, PI, JI
V
= 5.0 V ± 5%
CC
Am27X512
3
FUNCTIONAL DESCRIPTION
Read Mode
CE# should be decoded and used as the primary de-
vice-selecting function, while OE#/VPP be made a com-
mon connection to all devices in the array and
connected to the READ line from the system control
bus. This assures that all deselected memory devices
are in their low-power standby mode and that the out-
put pins are only active when data is desired from a
particular memory device.
To obtain data at the device outputs, Chip Enable (CE#)
and Output Enable (OE#) must be driven low. CE# con-
trols the power to the device and is typically used to se-
lect the device. OE# enables the device to output data,
independent of device selection. Addresses must be
stable for at least tACC–tOE. Refer to the Switching
Waveforms section for the timing diagram.
System Applications
Standby Mode
During the switch between active and standby condi-
tions, transient current peaks are produced on the ris-
ing and falling edges of Chip Enable. The magnitude of
these transient current peaks is dependent on the out-
put capacitance loading of the device. At a minimum, a
0.1 µF ceramic capacitor (high frequency, low inherent
inductance) should be used on each device between
VCC and VSS to minimize transient effects. In addition,
to overcome the voltage drop caused by the inductive
effects of the printed circuit board traces on Express-
ROM device arrays, a 4.7 µF bulk electrolytic capacitor
should be used between VCC and VSS for each eight
devices. The location of the capacitor should be close
to where the power supply is connected to the array.
The device enters the CMOS standby mode when CE#
is at VCC ± 0.3 V. Maximum VCC current is reduced to
100 µA. The device enters the TTL-standby mode
when CE# is at VIH. Maximum VCC current is reduced
to 1.0 mA. When in either standby mode, the device
places its outputs in a high-impedance state, indepen-
dent of the OE# input.
Output OR-Tieing
To accommodate multiple memory connections, a
two-line control function provides:
■ Low memory power dissipation, and
■ Assurance that output bus contention will not occur.
MODE SELECT TABLE
Mode
CE#
OE#/V
Outputs
PP
Read
V
V
D
OUT
IL
IL
Output Disable
Standby (TTL)
X
V
High Z
High Z
High Z
IH
V
X
IH
Standby (CMOS)
V
± 0.3 V
X
CC
Note:
X = Either V or V .
IH
IL
4
Am27X512
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature
Commercial (C) Devices
OTP Products. . . . . . . . . . . . . . . . . . –65°C to +125°C
Ambient Temperature
with Power Applied. . . . . . . . . . . . . . –55°C to +125°C
Ambient Temperature (TA) . . . . . . . . . . .0°C to +70°C
Industrial (I) Devices
Ambient Temperature (TA) . . . . . . . . .–40°C to +85°C
Supply Read Voltages
Voltage with Respect to VSS
All pins except VCC . . . . . . . . . –0.6 V to VCC + 0.6 V
VCC (Note 1). . . . . . . . . . . . . . . . . . . . .–0.6 V to 7.0 V
Note:
VCC for ± 5% devices . . . . . . . . . . +4.75 V to +5.25 V
VCC for ± 10% devices . . . . . . . . . +4.50 V to +5.50 V
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
1. Minimum DC voltage on input or I/O pins –0.5 V. During
voltage transitions, the input may overshoot V to –2.0 V
SS
for periods of up to 20 ns. Maximum DC voltage on input
and I/O pins is V + 5 V. During voltage transitions, input
CC
and I/O pins may overshoot to V + 2.0 V for periods up
CC
to 20 ns.
Stresses above those listed under “Absolute Maximum Rat-
ings” may cause permanent damage to the device. This is a
stress rating only; functional operation of the device at these
or any other conditions above those indicated in the opera-
tional sections of this specification is not implied. Exposure of
the device to absolute maximum ratings for extended periods
may affect device reliability.
Am27X512
5
DC CHARACTERISTICS over operating range (unless otherwise specified)
Parameter
Symbol
Parameter Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Test Conditions
Min
Max
Unit
V
V
I
= –400 µA
= 2.1 mA
2.4
OH
OH
OL
V
I
0.45
V
OL
V
2.0
V
+ 0.5
V
IH
CC
V
Input LOW Voltage
–0.5
+0.8
1.0
V
IL
I
Input Load Current
V
V
= 0 V to V
µA
µA
LI
IN
CC
I
Output Leakage Current
= 0 V to V
CC
1.0
LO
OUT
I
V
Active Current (Note 2)
CE# = V , f = 10 MHz,
IL
CC1
CC
30
mA
I
= 0 mA
OUT
I
I
V
V
TTL Standby Current
CE# = V
IH
1.0
mA
µA
CC2
CC3
CC
CC
CMOS Standby Current
CE# = V ± 0.3 V
100
CC
Caution: The device must not be removed from (or inserted into) a socket when V or V is applied.
CC
PP
Notes:
1. V must be applied simultaneously or before V , and removed simultaneously or after V ..
CC
PP
PP
2. I
is tested with OE# = V to simulate open outputs.
IH
CC1
3. Minimum DC Input Voltage is –0.5 V. During transitions, the inputs may overshoot to –2.0 V for periods less than 20 ns.
Maximum DC Voltage on output pins is V + 0.5 V, which may overshoot to V + 2.0 V for periods less than 20 ns.
CC
CC
30
25
20
15
10
30
25
20
15
10
–75 –50 –55
0
25 50 75 100 125 150
1
2
3
4
5
6
7
8
9
10
Temperature in °C
Frequency in MHz
12081F-5
12081F-6
Figure 1. Typical Supply Current vs. Frequency
Figure 2. Typical Supply Current vs. Temperature
VCC = 5.5 V, f = 10 MHz
VCC = 5.5 V, T = 25°C
6
Am27X512
TEST CONDITIONS
5.0 V
Table 1. Test Specifications
Test Condition All
Output Load 1 TTL gate
Unit
2.7 kΩ
Device
Under
Test
Output Load Capacitance, C
(including jig capacitance)
L
100
pF
C
L
6.2 kΩ
Input Rise and Fall Times
Input Pulse Levels
≤ 20
ns
0.45–2.4
V
Input timing measurement reference
levels
0.8, 2.0
0.8, 2.0
V
V
Note:
Output timing measurement
reference levels
Diodes are IN3064 or equivalents.
12081F-7
Figure 3. Test Setup
SWITCHING TEST WAVEFORM
2.4 V
2.0 V
0.8 V
2.0 V
0.8 V
Test Points
0.45 V
Input
Output
Note: For C = 100 pF.
L
12081F-8
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Does Not Apply
Changing, State Unknown
Center Line is High Impedance State (High Z)
KS000010-PAL
Am27X512
7
AC CHARACTERISTICS
Parameter Symbols
Am27X512
JEDEC Standard
Description
Address to Output Delay
Test Setup
CE#,
-70
70
70
40
-90
90
90
40
-120 -150 -200 -255
Unit
ns
t
t
t
Max
120
120
50
150
150
50
200
200
50
250
250
50
AVQV
ELQV
GLQV
ACC
OE# = V
IL
t
Chip Enable to Output Delay OE# = V Max
ns
CE
OE
IL
Output Enable to Output
Delay
t
t
CE# = V Max
ns
IL
Chip Enable High or Output
Enable High to Output High Z,
Whichever Occurs First
t
t
t
EHQZ
GHQZ
DF
Max
Min
25
0
30
0
30
0
30
0
30
0
30
0
ns
ns
(Note 2)
Output Hold Time from
Addresses, CE# or OE#,
Whichever Occurs First
t
t
OH
AXQX
Caution: Do not remove the device from (or insert it into) a socket or board that has V or V applied.
PP
CC
Notes:
1. V must be applied simultaneously or before V , and removed simultaneously or after V .
PP
CC
PP
2. This parameter is sampled and not 100% tested.
3. Switching characteristics are over operating range, unless otherwise specified.
4. See Figure 3 and Table 1 for test specifications.
SWITCHING WAVEFORMS
2.4
2.0
0.8
2.0
0.8
Addresses
0.45
Addresses Valid
CE#
t
CE
OE#
t
(Note 2)
DF
t
OE
t
ACC
t
OH
(Note 1)
High Z
High Z
Output
Valid Output
12081F-9
Notes:
1. OE# may be delayed up to t
– t after the falling edge of the addresses without impact on t .
ACC
ACC
OE
2. t is specified from OE# or CE#, whichever occurs first.
DF
PACKAGE CAPACITANCE
PD 028
PL 032
Parameter
Symbol
Parameter Description
Input Capacitance
Test Conditions
Typ
Max
10
Typ
9
Max
Unit
pF
C
V
V
= 0
6
8
12
12
IN
IN
C
Output Capacitance
= 0
10
9
pF
OUT
OUT
Notes:
1. This parameter is only sampled and not 100% tested.
2. T = +25°C, f = 1 MHz.
A
8
Am27X512
PHYSICAL DIMENSIONS
PD 028—28-Pin Plastic Dual In-Line Package (measured in inches)
1.440
1.480
.600
.625
15
14
28
.530
.580
.008
.015
Pin 1 I.D.
.630
.700
.045
.065
0°
10°
.005 MIN
.140
.225
16-038-SB-AG
PD 028
DG75
SEATING PLANE
.015
.060
.014
.022
7-13-95 ae
.120
.160
.090
.110
PL 032—32-Pin Plastic Leaded Chip Carrier (measured in inches)
.485
.495
.447
.453
.009
.015
.042
.056
.125
.140
.585
.595
Pin 1 I.D.
.080
.095
.547
.553
SEATING
PLANE
.400
REF.
.490
.530
.013
.021
.050 REF.
16-038FPO-5
PL 032
DA79
.026
.032
TOP VIEW
SIDE VIEW
6-28-94 ae
Am27X512
9
REVISION SUMMARY FOR AM27X512
Revision F
Global
Changed formatting to match current data sheets.
Trademarks
Copyright © 1998 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc.
Flashrite is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
10
Am27X512
相关型号：
©2020 ICPDF网 联系我们和版权申明