AM29F016D-70SC 概述
Flash, 2MX8, 70ns, PDSO44, MO-180AA, SOP-44 闪存
AM29F016D-70SC 规格参数
是否无铅: | 含铅 | 是否Rohs认证: | 不符合 |
生命周期: | Obsolete | 零件包装代码: | SOIC |
包装说明: | MO-180AA, SOP-44 | 针数: | 44 |
Reach Compliance Code: | unknown | ECCN代码: | EAR99 |
HTS代码: | 8542.32.00.51 | 风险等级: | 5.48 |
Is Samacsys: | N | 最长访问时间: | 70 ns |
命令用户界面: | YES | 通用闪存接口: | YES |
数据轮询: | YES | JESD-30 代码: | R-PDSO-G44 |
JESD-609代码: | e0 | 长度: | 28.2 mm |
内存密度: | 16777216 bit | 内存集成电路类型: | FLASH |
内存宽度: | 8 | 湿度敏感等级: | 3 |
功能数量: | 1 | 部门数/规模: | 32 |
端子数量: | 44 | 字数: | 2097152 words |
字数代码: | 2000000 | 工作模式: | ASYNCHRONOUS |
最高工作温度: | 70 °C | 最低工作温度: | |
组织: | 2MX8 | 封装主体材料: | PLASTIC/EPOXY |
封装代码: | SOP | 封装等效代码: | SOP44,.63 |
封装形状: | RECTANGULAR | 封装形式: | SMALL OUTLINE |
并行/串行: | PARALLEL | 峰值回流温度(摄氏度): | 240 |
电源: | 5 V | 编程电压: | 5 V |
认证状态: | Not Qualified | 就绪/忙碌: | YES |
座面最大高度: | 2.8 mm | 部门规模: | 64K |
最大待机电流: | 0.000005 A | 子类别: | Flash Memories |
最大压摆率: | 0.06 mA | 最大供电电压 (Vsup): | 5.5 V |
最小供电电压 (Vsup): | 4.5 V | 标称供电电压 (Vsup): | 5 V |
表面贴装: | YES | 技术: | CMOS |
温度等级: | COMMERCIAL | 端子面层: | Tin/Lead (Sn/Pb) |
端子形式: | GULL WING | 端子节距: | 1.27 mm |
端子位置: | DUAL | 处于峰值回流温度下的最长时间: | 30 |
切换位: | YES | 类型: | NOR TYPE |
宽度: | 13.3 mm | Base Number Matches: | 1 |
AM29F016D-70SC 数据手册
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Data Sheet (Retired Product)
Am29F016D Cover Sheet
This product has been retired and is not recommended for designs. Please contact your Spansion representative for
alternates. Availability of this document is retained for reference and historical purposes only.
The following document contains information on Spansion memory products.
Continuity of Specifications
There is no change to this data sheet as a result of offering the device as a Spansion product. Any changes that have been
made are the result of normal data sheet improvement and are noted in the document revision summary.
For More Information
Please contact your local sales office for additional information about Spansion memory solutions.
Publication Number 21444
Revision E
Amendment 7
Issue Date March 3, 2009
D a t a S h e e t ( R e t i r e d P r o d u c t )
This page left intentionally blank.
2
Am29F016D
21444_E7 March 3, 2009
DATA SHEET
Am29F016D
16 Megabit (2 M x 8-Bit)
CMOS 5.0 Volt-only, Uniform Sector Flash Memory
This product has been retired and is not recommended for designs. Please contact your Spansion representative
for alternates. Availability of this document is retained for reference and historical purposes only.
DISTINCTIVE CHARACTERISTICS
■ 5.0 V ± 10%, single power supply operation
■ Unlock Bypass Program Command
— Minimizes system level power requirements
— Reduces overall programming time when
issuing multiple program command sequences
■ Manufactured on 0.23 µm process technology
■ Minimum 1,000,000 program/erase cycles per
— Compatible with 0.5 µm Am29F016 and 0.32 µm
Am29F016B devices
sector guaranteed
■ 20-year data retention at 125°C
— Reliable operation for the life of the system
■ Package options
■ High performance
— Access times as fast as 70 ns
■ Low power consumption
— 48-pin and 40-pin TSOP
— 44-pin SO
— 25 mA typical active read current
— 30 mA typical program/erase current
— Known Good Die (KGD)
— 1 µA typical standby current (standard access
time to active mode)
(see publication number 21551)
■ Compatible with JEDEC standards
■ Flexible sector architecture
— 32 uniform sectors of 64 Kbytes each
— Any combination of sectors can be erased
— Supports full chip erase
— Pinout and software compatible with
single-power-supply Flash standard
— Superior inadvertent write protection
■ Data# Polling and toggle bits
— Group sector protection:
— Provides a software method of detecting
program or erase cycle completion
A hardware method of locking sector groups to
prevent any program or erase operations within
that sector group
■ Ready/Busy# output (RY/BY#)
— Provides a hardware method for detecting
program or erase cycle completion
Temporary Sector Group Unprotect allows code
changes in previously locked sectors
■ Embedded Algorithms
■ Erase Suspend/Erase Resume
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
— Suspends a sector erase operation to read data
from, or program data to, a non-erasing sector,
then resumes the erase operation
— Embedded Program algorithm automatically
writes and verifies bytes at specified addresses
■ Hardware reset pin (RESET#)
— Resets internal state machine to the read mode
Publication# 21444 Rev: E Amendment: 7
Issue Date: March 3, 2009
This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data
Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
D A T A S H E E T
GENERAL DESCRIPTION
The Am29F016D is a 16 Mbit, 5.0 volt-only Flash mem-
ory organized as 2,097,152 bytes. The 8 bits of data
appear on DQ0–DQ7. The Am29F016D is offered in
48-pin TSOP, 40-pin TSOP, and 44-pin SO packages.
The device is also available in Known Good Die (KGD)
form. For more information, refer to publication number
21551. This device is designed to be programmed
algorithm—an internal algorithm that automatically
preprograms the array (if it is not already programmed)
before executing the erase operation. During erase, the
device automatically times the erase pulse widths and
verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, or by reading the DQ7 (Data# Polling) and DQ6
(toggle) status bits. After a program or erase cycle has
been completed, the device is ready to read array data
or accept another command.
in-system with the standard system 5.0 volt V supply.
CC
A 12.0 volt V is not required for program or erase
PP
operations. The device can also be programmed in
standard EPROM programmers.
This device is manufactured using AMD’s 0.23 µm pro-
cess technology, and offers all the features and
benefits of the Am29F016, which was manufactured
using 0.5 µm process technology.
The sector erase architecture allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
The standard device offers access times of 70, 90, and
120 ns, allowing high-speed microprocessors to oper-
ate without wait states. To eliminate bus contention, the
device has separate chip enable (CE#), write enable
(WE#), and output enable (OE#) controls.
Hardware data protection measures include a low
V
detector that automatically inhibits write opera-
CC
tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of the sectors of mem-
ory. This can be achieved via programming equipment.
The device requires only a single 5.0 volt power sup-
ply for both read and write functions. Internally
generated and regulated voltages are provided for the
program and erase operations.
The Erase Suspend feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved.
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard. Com-
mands are written to the command register using
standard microprocessor write timings. Register con-
tents serve as input to an internal state-machine that
controls the erase and programming circuitry. Write cy-
cles also internally latch addresses and data needed
for the programming and erase operations. Reading
data out of the device is similar to reading from other
Flash or EPROM devices.
The hardware RESET# pin terminates any operation
in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.
The system can place the device into the standby
mode. Power consumption is greatly reduced in
this mode.
Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithm—an internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective-
ness. The device electrically erases all bits within a
sector simultaneously via Fowler-Nordheim tunneling.
The data is programmed using hot electron injection.
Device erasure occurs by executing the erase com-
mand sequence. This initiates the Embedded Erase
2
Am29F016D
21444E7 March 3, 2009
D A T A S H E E T
TABLE OF CONTENTS
Product Selector Guide. . . . . . . . . . . . . . . . . . . . . 4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 5
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . 6
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . 7
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 8
Table 1. Am29F016D Device Bus Operations .................................. 8
Requirements for Reading Array Data ..................................... 8
Writing Commands/Command Sequences .............................. 8
Program and Erase Operation Status ...................................... 9
Standby Mode .......................................................................... 9
RESET#: Hardware Reset Pin ................................................. 9
Output Disable Mode................................................................ 9
Table 2. Sector Address Table........................................................ 10
Autoselect Mode..................................................................... 11
Table 3. Am29F016D Autoselect Codes (High Voltage Method).... 11
Sector Group Protection/Unprotection.................................... 11
Table 4. Sector Group Addresses................................................... 11
Temporary Sector Group Unprotect ....................................... 11
Figure 1. Temporary Sector Group Unprotect Operation............... 12
Hardware Data Protection ...................................................... 12
Low VCC Write Inhibit...................................................................... 12
Write Pulse “Glitch” Protection........................................................ 12
Logical Inhibit .................................................................................. 12
Power-Up Write Inhibit .................................................................... 12
Common Flash Memory Interface (CFI). . . . . . . 13
Table 5. CFI Query Identification String.......................................... 13
Table 6. System Interface String..................................................... 13
Table 7. Device Geometry Definition .............................................. 14
Table 8. Primary Vendor-Specific Extended Query ........................ 14
Command Definitions . . . . . . . . . . . . . . . . . . . . . 15
Reading Array Data................................................................ 15
Reset Command..................................................................... 15
Autoselect Command Sequence............................................ 15
Byte Program Command Sequence....................................... 15
Unlock Bypass Command Sequence.............................................. 16
Figure 2. Program Operation ......................................................... 16
Chip Erase Command Sequence........................................... 16
Sector Erase Command Sequence........................................ 17
Erase Suspend/Erase Resume Commands........................... 17
Figure 3. Erase Operation.............................................................. 18
Command Definitions ............................................................. 19
Table 9. Am29F016D Command Definitions................................... 19
Write Operation Status . . . . . . . . . . . . . . . . . . . . 20
DQ7: Data# Polling................................................................. 20
Figure 4. Data# Polling Algorithm ................................................. 20
RY/BY#: Ready/Busy#............................................................ 21
DQ6: Toggle Bit I.................................................................... 21
DQ2: Toggle Bit II................................................................... 21
Reading Toggle Bits DQ6/DQ2............................................... 21
DQ5: Exceeded Timing Limits ................................................ 22
DQ3: Sector Erase Timer ....................................................... 22
Figure 5. Toggle Bit Algorithm....................................................... 22
Table 10. Write Operation Status................................................... 23
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 24
Figure 6. Maximum Negative Overshoot Waveform ..................... 24
Figure 7. Maximum Positive Overshoot Waveform....................... 24
Operating Ranges. . . . . . . . . . . . . . . . . . . . . . . . . 24
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 25
TTL/NMOS Compatible .......................................................... 25
CMOS Compatible.................................................................. 25
Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 8. Test Setup..................................................................... 26
Table 11. Test Specifications......................................................... 26
Key to Switching Waveforms. . . . . . . . . . . . . . . . 26
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 27
Read-only Operations............................................................. 27
Figure 9. Read Operation Timings................................................ 27
Figure 10. RESET# Timings ......................................................... 28
Erase/Program Operations..................................................... 29
Figure 11. Program Operation Timings......................................... 30
Figure 12. Chip/Sector Erase Operation Timings ......................... 31
Figure 13. Data# Polling Timings (During Embedded Algorithms) 32
Figure 14. Toggle Bit Timings (During Embedded Algorithms)..... 32
Figure 15. DQ2 vs. DQ6................................................................ 33
Figure 16. Temporary Sector Group Unprotect Timings............... 33
Erase and Program Operations.............................................. 34
Alternate CE# Controlled Writes .................................................... 34
Figure 17. Alternate CE# Controlled Write Operation Timings ..... 35
Erase and Programming Performance . . . . . . . 36
Latchup Characteristics. . . . . . . . . . . . . . . . . . . . 36
TSOP and SO Pin Capacitance . . . . . . . . . . . . . . 36
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 37
TS 040—40-Pin Standard Thin Small Outline Package ......... 37
TS 048—48-Pin Standard Thin Small Outline Package ......... 38
SO 044—44-Pin Small Outline Package ................................ 39
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 40
March 3, 2009 21444E7
Am29F016D
3
D A T A S H E E T
PRODUCT SELECTOR GUIDE
Family Part Number
Speed Options (VCC = 5.0 V ± 10%)
Max Access Time (ns)
CE# Access (ns)
Am29F016D
-70
70
70
40
-90
90
90
40
-120
120
120
50
OE# Access (ns)
Note: See the AC Characteristics section for more information.
BLOCK DIAGRAM
DQ0–DQ7
Sector Switches
VCC
VSS
Erase Voltage
Generator
Input/Output
Buffers
RY/BY#
RESET#
State
Control
WE#
Command
Register
PGM Voltage
Generator
Data
Latch
Chip Enable
Output Enable
Logic
STB
CE#
OE#
Y-Decoder
Y-Gating
STB
VCC Detector
Timer
Cell Matrix
X-Decoder
A0–A20
4
Am29F016D
21444E7 March 3, 2009
D A T A S H E E T
CONNECTION DIAGRAMS
This device is also available in Known Good Die (KGD) form. Refer to publication number 21551 for
more information.
A19
A18
A17
A16
A15
A14
A13
A12
CE#
VCC
NC
1
2
3
4
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A20
NC
WE#
OE#
RY/BY#
DQ7
DQ6
DQ5
DQ4
VCC
VSS
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40-Pin Standard TSOP
RESET#
A11
A10
A9
VSS
DQ3
DQ2
DQ1
DQ0
A0
A8
A7
A6
A1
A5
A2
A4
A3
NC
NC
1
48 NC
47 NC
46 A20
45 NC
2
3
4
5
6
7
8
9
A19
A18
A17
A16
A15
A14
A13
A12 10
CE# 11
VCC 12
NC 13
44 WE#
43 OE#
42 RY/BY#
41 DQ7
40 DQ6
39 DQ5
38 DQ4
37 VCC
36 VSS
35 VSS
34 DQ3
33 DQ2
32 DQ1
31 DQ0
30 A0
48-Pin Standard TSOP
RESET# 14
A11 15
A10 16
A9 17
A8 18
A7 19
A6 20
29 A1
A5 21
28 A2
A4 22
27 A3
NC 23
26 NC
24
25 NC
NC
March 3, 2009 21444E7
Am29F016D
5
D A T A S H E E T
CONNECTION DIAGRAMS
This device is also available in Known Good Die (KGD) form. Refer to publication number 21551 for
more information.
NC
RESET#
A11
A10
A9
1
2
3
4
5
6
7
8
9
44 VCC
43 CE#
42 A12
41 A13
40 A14
39 A15
38 A16
37 A17
36 A18
35 A19
34 NC
A8
A7
A6
A5
A4 10
NC 11
NC 12
A3 13
SO
33 NC
32 A20
31 NC
A2 14
A1 15
30 WE#
29 OE#
28 RY/BY#
27 DQ7
26 DQ6
25 DQ5
24 DQ4
23 VCC
A0 16
DQ0 17
DQ1 18
DQ2 19
DQ3 20
VSS 21
VSS 22
PIN CONFIGURATION
LOGIC SYMBOL
A0–A20
=
21 Addresses
21
DQ0–DQ7 = 8 Data Inputs/Outputs
A0–A20
8
CE#
=
=
=
=
=
Chip Enable
DQ0–DQ7
WE#
Write Enable
OE#
Output Enable
CE#
OE#
RESET#
RY/BY#
Hardware Reset Pin, Active Low
Ready/Busy Output
WE#
V
=+5.0 V single power supply
(see Product Selector Guide for
device speed ratings and voltage
supply tolerances)
CC
RESET#
RY/BY#
V
=
=
Device Ground
SS
NC
Pin Not Connected Internally
6
Am29F016D
21444E7 March 3, 2009
D A T A S H E E T
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is
formed by a combination of the following:
Am29F016D -70
E
I
TEMPERATURE RANGE
C
D
I
=
=
=
=
Commercial (0°C to +70°C)
Commercial (0°C to +70°C) with Pb-free package
Industrial (–40°C to +85°C)
F
Industrial (–40°C to +85°C)with Pb-free package
PACKAGE TYPE
E
=
48-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 048)
E4 = 40-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 040)
S
= 44-Pin Small Outline Package (SO 044)
This device is also available in Known Good Die (KGD) form. See publication number
21551 for more information.
SPEED OPTION
See Product Selector Guide and Valid Combinations
DEVICE NUMBER/DESCRIPTION
Am29F016D
16 Megabit (2 M x 8-Bit) CMOS 5.0 Volt-only Sector Erase Flash Memory
5.0 V Read, Program, and Erase
Valid Combinations
Valid Combinations
Valid Combinations list configurations planned to be sup-
ported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.
EC, EI, ED, EF, E4D, E4F,
SD, SF, E4C, E4I, SC, SI
AM29F016D-70
AM29F016D-90
AM29F016D-120
EC, EI, E4C, E4I, SC, SI, ED,
EF, E4D, E4F, SD, SF
March 3, 2009 21444E7
Am29F016D
7
D A T A S H E E T
DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register it-
self does not occupy any addressable memory
location. The register is composed of latches that store
the commands, along with the address and data infor-
mation needed to execute the command. The contents
of the register serve as inputs to the internal state ma-
chine. The state machine outputs dictate the function of
the device. The appropriate device bus operations
table lists the inputs and control levels required, and the
resulting output. The following subsections describe
each of these operations in further detail.
Table 1. Am29F016D Device Bus Operations
Operation
CE#
OE#
L
WE#
H
RESET#
A0–A20
DQ0–DQ7
DOUT
Read
Write
L
H
AIN
AIN
X
L
H
L
H
DIN
CMOS Standby
TTL Standby
VCC 0.5 V
X
X
VCC 0.5 V
High-Z
High-Z
High-Z
High-Z
H
L
X
X
H
H
L
X
Output Disable
Hardware Reset
H
H
X
X
X
X
X
Temporary Sector Unprotect
(See Note)
X
X
X
VID
AIN
DIN
Legend:
L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’t Care, DIN = Data In, DOUT = Data Out, AIN = Address In
Note: See the sections on Sector Group Protection and Temporary Sector Unprotect for more information
Requirements for Reading Array Data
Writing Commands/Command Sequences
To read array data from the outputs, the system must
To write a command or command sequence (which in-
cludes programming data to the device and erasing
sectors of memory), the system must drive WE# and
drive the CE# and OE# pins to V . CE# is the power
IL
control and selects the device. OE# is the output control
and gates array data to the output pins. WE# should re-
CE# to V , and OE# to V .
IL
IH
main at V .
IH
An erase operation can erase one sector, multiple sec-
tors, or the entire device. The Sector Address Tables
indicate the address space that each sector occupies.
A “sector address” consists of the address bits required
to uniquely select a sector. See the “Command Defini-
tions” section for details on erasing a sector or the
entire chip, or suspending/resuming the erase
operation.
The internal state machine is set for reading array
data upon device power-up, or after a hardware reset.
This ensures that no spurious alteration of the mem-
ory content occurs during the power transition. No
command is necessary in this mode to obtain array
data. Standard microprocessor read cycles that as-
sert valid addresses on the device address inputs
produce valid data on the device data outputs. The
device remains enabled for read access until the
command register contents are altered.
After the system writes the autoselect command se-
quence, the device enters the autoselect mode. The
system can then read autoselect codes from the inter-
nal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in this
mode. Refer to the “Autoselect Mode” and “Autoselect
Command Sequence” sections for more information.
See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifica-
tions and to the Read Operations Timings diagram for
the timing waveforms. I
in the DC Characteristics
CC1
table represents the active current specification for
reading array data.
I
in the DC Characteristics table represents the ac-
CC2
tive current specification for the write mode. The “AC
Characteristics” section contains timing specification
tables and timing diagrams for write operations.
8
Am29F016D
21444E7 March 3, 2009
D A T A S H E E T
the device immediately terminates any operation in
Program and Erase Operation Status
progress, tristates all data output pins, and ignores all
read/write attempts for the duration of the RESET#
pulse. The device also resets the internal state ma-
chine to reading array data. The operation that was
interrupted should be reinitiated once the device is
ready to accept another command sequence, to en-
sure data integrity.
During an erase or program operation, the system may
check the status of the operation by reading the status
bits on DQ7–DQ0. Standard read cycle timings and I
CC
read specifications apply. Refer to “Write Operation
Status” for more information, and to each AC Charac-
teristics section for timing diagrams.
Standby Mode
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V , the device enters
IL
When the system is not reading or writing to the device,
it can place the device in the standby mode. In this
mode, current consumption is greatly reduced, and the
outputs are placed in the high impedance state, inde-
pendent of the OE# input.
the TTL standby mode; if RESET# is held at V
SS
0.5 V, the device enters the CMOS standby mode.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
The device enters the CMOS standby mode when CE#
and RESET# pins are both held at V
0.5 V. (Note
CC
that this is a more restricted voltage range than V .)
The device enters the TTL standby mode when CE#
If RESET# is asserted during a program or erase oper-
ation, the RY/BY# pin remains a “0” (busy) until the
internal reset operation is complete, which requires a
IH
and RESET# pins are both held at V . The device re-
IH
quires standard access time (t ) for read access when
time of t
(during Embedded Algorithms). The
CE
READY
the device is in either of these standby modes, before it
is ready to read data.
system can thus monitor RY/BY# to determine whether
the reset operation is complete. If RESET# is asserted
when a program or erase operation is not executing
(RY/BY# pin is “1”), the reset operation is completed
The device also enters the standby mode when the RE-
SET# pin is driven low. Refer to the next section,
“RESET#: Hardware Reset Pin”.
within a time of t
(not during Embedded Algo-
READY
rithms). The system can read data t
after the
RH
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
RESET# pin returns to V .
IH
Refer to the AC Characteristics tables for RESET# pa-
rameters and timing diagram.
In the DC Characteristics tables, I
standby current specification.
represents the
CC3
Output Disable Mode
When the OE# input is at V , output from the device is
disabled. The output pins are placed in the high imped-
ance state.
IH
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of reset-
ting the device to reading array data. When the system
drives the RESET# pin low for at least a period of t ,
RP
March 3, 2009 21444E7
Am29F016D
9
D A T A S H E E T
Table 2. Sector Address Table
Sector
SA0
A20
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A19
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A18
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A17
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A16
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Address Range
000000h-00FFFFh
010000h-01FFFFh
020000h-02FFFFh
030000h-03FFFFh
040000h-04FFFFh
050000h-05FFFFh
060000h-06FFFFh
070000h-07FFFFh
080000h-08FFFFh
090000h-09FFFFh
0A0000h-0AFFFFh
0B0000h-0BFFFFh
0C0000h-0CFFFFh
0D0000h-0DFFFFh
0E0000h-0EFFFFh
0F0000h-0FFFFFh
100000h-10FFFFh
110000h-11FFFFh
120000h-12FFFFh
130000h-13FFFFh
140000h-14FFFFh
150000h-15FFFFh
160000h-16FFFFh
170000h-17FFFFh
180000h-18FFFFh
190000h-19FFFFh
1A0000h-1AFFFFh
1B0000h-1BFFFFh
1C0000h-1CFFFFh
1D0000h-1DFFFFh
1E0000h-1EFFFFh
1F0000h-1FFFFFh
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
Note: All sectors are 64 Kbytes in size.
10
Am29F016D
21444E7 March 3, 2009
D A T A S H E E T
address must appear on the appropriate highest order
Autoselect Mode
address bits. Refer to the corresponding Sector Ad-
dress Tables. The Command Definitions table shows
the remaining address bits that are don’t care. When all
necessary bits have been set as required, the program-
ming equipment may then read the corresponding
identifier code on DQ7–DQ0.
The autoselect mode provides manufacturer and de-
vice identification, and sector protection verification,
through identifier codes output on DQ7–DQ0. This
mode is primarily intended for programming equipment
to automatically match a device to be programmed with
its corresponding programming algorithm. However,
the autoselect codes can also be accessed in-system
through the command register.
To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in the Command Defini-
When using programming equipment, the autoselect
mode requires V (11.5 V to 12.5 V) on address pin
tions table. This method does not require V . See
ID
ID
“Command Definitions” for details on using the autose-
lect mode.
A9. Address pins A6, A1, and A0 must be as shown in
Autoselect Codes (High Voltage Method) table. In addi-
tion, when verifying sector protection, the sector
Table 3. Am29F016D Autoselect Codes (High Voltage Method)
CE# OE# WE# A20-A18 A17-A10 A9 A8-A7 A6 A5-A2 A1 A0
Description
DQ7-DQ0
Manufacturer ID:
AMD
L
L
L
L
H
H
X
X
X
X
VID
VID
X
X
VIL
VIL
X
X
VIL VIL
01h
Device ID:
Am29F016D
VIL VIH
ADh
Sector Group
Protection
Verification
Sector
Group
Address
01h (protected)
L
L
H
X
VID
X
VIL
X
VIH VIL
00h (unprotected)
L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.
It is possible to determine whether a sector group is
protected or unprotected. See “Autoselect Mode” for
details.
Sector Group Protection/Unprotection
The hardware sector group protection feature dis-
ables both program and erase operations in any
sector group. Each sector group consists of four adja-
cent sectors. Table 4 shows how the sectors are
grouped, and the address range that each sector
group contains. The hardware sector group unprotec-
tion feature re-enables both program and erase
operations in previously protected sector groups.
Table 4. Sector Group Addresses
Sector
Group
SGA0
SGA1
SGA2
SGA3
SGA4
SGA5
SGA6
SGA7
A20
A19
A18
Sectors
0
0
0
SA0–SA3
0
0
1
SA4–SA7
Sector group protection/unprotection must be imple-
mented using programming equipment. The procedure
0
1
0
SA8–SA11
SA12–SA15
SA16–SA19
SA20–SA23
SA24–SA27
SA28–SA31
0
1
1
requires a high voltage (V ) on address pin A9 and the
ID
1
0
0
control pins. Details on this method are provided in a
supplement, publication number 23922. Contact an
AMD representative to obtain a copy of the appropriate
document. Note that the sector group protection and
unprotection scheme differs from that used with the
previous versions of this device, namely the
Am29F016B and Am29F016.
1
0
1
1
1
0
1
1
1
Temporary Sector Group Unprotect
This feature allows temporary unprotection of previ-
ously protected sector groups to change data
in-system. The Sector Group Unprotect mode is acti-
The device is shipped with all sector groups unpro-
tected. AMD offers the option of programming and
protecting sector groups at its factory prior to shipping
the device through AMD’s ExpressFlash™ Service.
Contact an AMD representative for details.
vated by setting the RESET# pin to V . During this
ID
mode, formerly protected sector groups can be pro-
grammed or erased by selecting the sector group
March 3, 2009 21444E7
Am29F016D
11
D A T A S H E E T
addresses. Once V is removed from the RESET#
pin, all the previously protected sector groups are
Hardware Data Protection
ID
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to the Command Defi-
nitions table). In addition, the following hardware data
protection measures prevent accidental erasure or pro-
gramming, which might otherwise be caused by
protected again. Figure 1 shows the algorithm, and
the Temporary Sector Group Unprotect diagram (Fig-
ure 16) shows the timing waveforms, for this feature.
spurious system level signals during V power-up and
power-down transitions, or from system noise.
CC
START
Low V
Write Inhibit
CC
RESET# = VID
(Note 1)
When V
is less than V
, the device does not ac-
LKO
CC
cept any write cycles. This protects data during V
CC
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
Perform Erase or
Program Operations
device resets. Subsequent writes are ignored until V
CC
is greater than V
. The system must provide the
LKO
proper signals to the control pins to prevent uninten-
RESET# = VIH
tional writes when V is greater than V
.
CC
LKO
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
Temporary
Sector Group Unprotect
Completed (Note 2)
Logical Inhibit
Write cycles are inhibited by holding any one of OE#
Notes:
= V , CE# = V or WE# = V . To initiate a write cy-
IL
IH
IH
1. All protected sector groups unprotected.
cle, CE# and WE# must be a logical zero while OE#
is a logical one.
2. All previously protected sector groups are protected
once again.
Power-Up Write Inhibit
Figure 1. Temporary Sector Group Unprotect
Operation
If WE# = CE# = V and OE# = V during power up, the
IL
IH
device does not accept commands on the rising edge
of WE#. The internal state machine is automatically
reset to reading array data on power-up.
12
Am29F016D
21444E7 March 3, 2009
D A T A S H E E T
The system can read CFI information at the addresses
given in Tables 5–8. To terminate reading CFI data, the
system must write the reset command.
COMMON FLASH MEMORY INTERFACE
(CFI)
The Common Flash Interface (CFI) specification out-
lines device and host system software interrogation
handshake, which allows specific vendor-specified
software algorithms to be used for entire families of de-
vices. Software support can then be device-
independent, JEDEC ID-independent, and forward-
and backward-compatible for the specified flash device
families. Flash vendors can standardize their existing
interfaces for long-term compatibility.
The system can also write the CFI query command
when the device is in the autoselect mode. The device
enters the CFI query mode, and the system can read
CFI data at the addresses given in Tables 5–8. The sys-
tem must write the reset command to return the device
to the autoselect mode.
For further information, please refer to the CFI Specifi-
cation and CFI Publication 100, available via the World
Wide Web at http://www.amd.com/products/nvd/over-
view/cfi.html. Alternatively, contact an AMD
representative for copies of these documents.
This device enters the CFI Query mode when the sys-
tem writes the CFI Query command, 98h, to address
55h, any time the device is ready to read array data.
Table 5. CFI Query Identification String
Description
Addresses
Data
10h
11h
12h
51h
52h
59h
Query Unique ASCII string “QRY”
Primary OEM Command Set
13h
14h
02h
00h
15h
16h
40h
00h
Address for Primary Extended Table
17h
18h
00h
00h
Alternate OEM Command Set (00h = none exists)
Address for Alternate OEM Extended Table (00h = none exists)
19h
1Ah
00h
00h
Table 6. System Interface String
Description
Addresses
Data
VCC Min. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Bh
45h
VCC Max. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Ch
55h
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
00h
00h
03h
00h
0Ah
00h
05h
00h
04h
00h
VPP Min. voltage (00h = no VPP pin present)
VPP Max. voltage (00h = no VPP pin present)
Typical timeout per single byte/word write 2N µs
Typical timeout for Min. size buffer write 2N µs (00h = not supported)
Typical timeout per individual block erase 2N ms
Typical timeout for full chip erase 2N ms (00h = not supported)
Max. timeout for byte/word write 2N times typical
Max. timeout for buffer write 2N times typical
Max. timeout per individual block erase 2N times typical
Max. timeout for full chip erase 2N times typical (00h = not supported)
March 3, 2009 21444E7
Am29F016D
13
D A T A S H E E T
Table 7. Device Geometry Definition
Addresses
Data
Description
27h
15h
Device Size = 2N byte
28h
29h
00h
00h
Flash Device Interface description (refer to CFI publication 100)
2Ah
2Bh
00h
00h
Max. number of byte in multi-byte write = 2N
(00h = not supported)
2Ch
01h
Number of Erase Block Regions within device
2Dh
2Eh
2Fh
30h
1Fh
00h
00h
01h
Erase Block Region 1 Information
(refer to the CFI specification or CFI publication 100)
Table 8. Primary Vendor-Specific Extended Query
Data Description
Addresses
40h
41h
42h
50h
52h
49h
Query-unique ASCII string “PRI”
43h
44h
31h
31h
Major version number, ASCII
Minor version number, ASCII
Address Sensitive Unlock
0 = Required, 1 = Not Required
45h
46h
00h
02h
Erase Suspend
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
Sector Protect
0 = Not Supported, X = Number of sectors in per group
47h
48h
04h
01h
Sector Temporary Unprotect: 00 = Not Supported, 01 = Supported
Sector Protect/Unprotect scheme
49h
04h
01 = 29F040 mode, 02 = 29F016 mode,
03 = 29F400 mode, 04 = 29LV800A mode
4Ah
4Bh
00h
00h
Simultaneous Operation: 00 = Not Supported, 01 = Supported
Burst Mode Type: 00 = Not Supported, 01 = Supported
Page Mode Type: 00 = Not Supported, 01 = 4 Word Page,
02 = 8 Word Page
4Ch
00h
4Dh
4Eh
00h
00h
ACC supply minimum
ACC supply maximum
Top/bottom boot sector flag
2 = bottom, 3 = top. If address 2Ch = 01h, ignore this field
4Fh
00h
14
Am29F016D
21444E7 March 3, 2009
D A T A S H E E T
COMMAND DEFINITIONS
Writing specific address and data commands or se-
quences into the command register initiates device
operations. The Command Definitions table defines the
valid register command sequences. Writing incorrect
address and data values or writing them in the im-
proper sequence resets the device to reading array
data.
however, the device ignores reset commands until the
operation is complete.
The reset command may be written between the se-
quence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command must
be written to return to reading array data (also applies
to autoselect during Erase Suspend).
All addresses are latched on the falling edge of WE# or
CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in the
“AC Characteristics” section.
If DQ5 goes high during a program or erase operation,
writing the reset command returns the device to read-
ing array data (also applies during Erase Suspend).
Autoselect Command Sequence
The autoselect command sequence allows the host
system to access the manufacturer and devices codes,
and determine whether or not a sector is protected.
The Command Definitions table shows the address
and data requirements. This method is an alternative to
that shown in the Autoselect Codes (High Voltage
Method) table, which is intended for PROM program-
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array
data after completing an Embedded Program or Em-
bedded Erase algorithm.
After the device accepts an Erase Suspend command,
the device enters the Erase Suspend mode. The sys-
tem can read array data using the standard read
timings, except that if it reads at an address within
erase-suspended sectors, the device outputs status
data. After completing a programming operation in the
Erase Suspend mode, the system may once again
read array data with the same exception. See “Erase
Suspend/Erase Resume Commands” for more infor-
mation on this mode.
mers and requires V on address bit A9.
ID
The autoselect command sequence is initiated by
writing two unlock cycles, followed by the autoselect
command. The device then enters the autoselect
mode, and the system may read at any address any
number of times, without initiating another command
sequence.
A read cycle at address XX00h retrieves the manufac-
turer code. A read cycle at address XX01h returns the
device code. A read cycle containing a sector address
(SA) and the address 02h in returns 01h if that sector
is protected, or 00h if it is unprotected. Refer to the
Sector Address tables for valid sector addresses.
The system must issue the reset command to re-en-
able the device for reading array data if DQ5 goes high,
or while in the autoselect mode. See the “Reset Com-
mand” section, next.
The system must write the reset command to exit the
autoselect mode and return to reading array data.
See also “Requirements for Reading Array Data” in the
“Device Bus Operations” section for more information.
The Read Operations table provides the read parame-
ters, and Read Operation Timings diagram shows the
timing diagram.
Byte Program Command Sequence
Programming is a four-bus-cycle operation. The pro-
gram command sequence is initiated by writing two
unlock write cycles, followed by the program set-up
command. The program address and data are written
next, which in turn initiate the Embedded Program al-
gorithm. The system is not required to provide further
controls or timings. The device automatically provides
internally generated program pulses and verify the pro-
grammed cell margin. The Command Definitions take
shows the address and data requirements for the byte
program command sequence.
Reset Command
Writing the reset command to the device resets the de-
vice to reading array data. Address bits are don’t care
for this command.
The reset command may be written between the se-
quence cycles in an erase command sequence before
erasing begins. This resets the device to reading array
data. Once erasure begins, however, the device ig-
nores reset commands until the operation is complete.
When the Embedded Program algorithm is complete,
the device then returns to reading array data and ad-
dresses are no longer latched. The system can
determine the status of the program operation by using
DQ7, DQ6, or RY/BY#. See “Write Operation Status”
for information on these status bits.
The reset command may be written between the se-
quence cycles in a program command sequence
before programming begins. This resets the device to
reading array data (also applies to programming in
Erase Suspend mode). Once programming begins,
March 3, 2009 21444E7
Am29F016D
15
D A T A S H E E T
Any commands written to the device during the Em-
bedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the program-
ming operation. The program command sequence
should be reinitiated once the device has reset to read-
ing array data, to ensure data integrity.
START
Write Program
Command Sequence
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
from a “0” back to a “1”. Attempting to do so may halt
the operation and set DQ5 to “1”, or cause the Data#
Polling algorithm to indicate the operation was suc-
cessful. However, a succeeding read will show that the
data is still “0”. Only erase operations can convert a “0”
to a “1”.
Data Poll
from System
Embedded
Program
algorithm
in progress
Unlock Bypass Command Sequence
Verify Data?
Yes
No
The unlock bypass feature allows the system to pro-
gram bytes or words to the device faster than using the
standard program command sequence. The unlock by-
pass command sequence is initiated by first writing two
unlock cycles. This is followed by a third write cycle
containing the unlock bypass command, 20h. The de-
vice then enters the unlock bypass mode. A two-cycle
unlock bypass program command sequence is all that
is required to program in this mode. The first cycle in
this sequence contains the unlock bypass program
command, A0h; the second cycle contains the program
address and data. Additional data is programmed in
the same manner. This mode dispenses with the initial
two unlock cycles required in the standard program
command sequence, resulting in faster total program-
ming time. Table 9 shows the requirements for the
command sequence.
No
Increment Address
Last Address?
Yes
Programming
Completed
Note:
See the appropriate Command Definitions table for program
command sequence.
Figure 2. Program Operation
During the unlock bypass mode, only the Unlock By-
pass Program and Unlock Bypass Reset commands
are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset com-
mand sequence. The first cycle must contain the data
90h; the second cycle the data 00h. Addresses are
don’t care for both cycles. The device then returns to
reading array data.
Chip Erase Command Sequence
Chip erase is a six-bus-cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algo-
rithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
trols or timings during these operations. The Command
Definitions table shows the address and data require-
ments for the chip erase command sequence.
16
Am29F016D
21444E7 March 3, 2009
D A T A S H E E T
Any commands written to the chip during the Embed-
Timer” section.) The time-out begins from the rising
edge of the final WE# pulse in the command sequence.
ded Erase algorithm are ignored. Note that a hardware
reset during the chip erase operation immediately ter-
minates the operation. The Chip Erase command
sequence should be reinitiated once the device has re-
turned to reading array data, to ensure data integrity.
Once the sector erase operation has begun, only the
Erase Suspend command is valid. All other commands
are ignored. Note that a hardware reset during the
sector erase operation immediately terminates the op-
eration. The Sector Erase command sequence should
be reinitiated once the device has returned to reading
array data, to ensure data integrity.
The system can determine the status of the erase
operation by using DQ7, DQ6, DQ2, or RY/BY#. See
“Write Operation Status” for information on these
status bits. When the Embedded Erase algorithm is
complete, the device returns to reading array data
and addresses are no longer latched.
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses are
no longer latched. The system can determine the sta-
tus of the erase operation by using DQ7, DQ6, DQ2, or
RY/BY#. Refer to “Write Operation Status” for informa-
tion on these status bits.
Figure 3 illustrates the algorithm for the erase opera-
tion. See the Erase/Program Operations tables in “AC
Characteristics” for parameters, and to the Chip/Sector
Erase Operation Timings for timing waveforms.
Figure 3 illustrates the algorithm for the erase opera-
tion. Refer to the Erase/Program Operations tables in
the “AC Characteristics” section for parameters, and to
the Sector Erase Operations Timing diagram for timing
waveforms.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two un-
lock cycles, followed by a set-up command. Two
additional unlock write cycles are then followed by the
address of the sector to be erased, and the sector
erase command. The Command Definitions table
shows the address and data requirements for the sec-
tor erase command sequence.
Erase Suspend/Erase Resume Commands
The Erase Suspend command allows the system to in-
terrupt a sector erase operation and then read data
from, or program data to, any sector not selected for
erasure. This command is valid only during the sector
erase operation, including the 50 µs time-out period
during the sector erase command sequence. The
Erase Suspend command is ignored if written during
the chip erase operation or Embedded Program algo-
rithm. Writing the Erase Suspend command during the
Sector Erase time-out immediately terminates the
time-out period and suspends the erase operation. Ad-
dresses are “don’t-cares” when writing the Erase
Suspend command.
The device does not require the system to preprogram
the memory prior to erase. The Embedded Erase algo-
rithm automatically programs and verifies the sector for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or tim-
ings during these operations.
After the command sequence is written, a sector erase
time-out of 50 µs begins. During the time-out period,
additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of sec-
tors may be from one sector to all sectors. The time
between these additional cycles must be less than 50
µs, otherwise the last address and command might not
be accepted, and erasure may begin. It is recom-
mended that processor interrupts be disabled during
this time to ensure all commands are accepted. The in-
terrupts can be re-enabled after the last Sector Erase
command is written. If the time between additional sec-
tor erase commands can be assumed to be less than
50 µs, the system need not monitor DQ3. Any com-
mand other than Sector Erase or Erase Suspend
during the time-out period resets the device to
reading array data. The system must rewrite the com-
mand sequence and any additional sector addresses
and commands.
When the Erase Suspend command is written during a
sector erase operation, the device requires a maximum
of 20 µs to suspend the erase operation. However,
when the Erase Suspend command is written during
the sector erase time-out, the device immediately ter-
minates the time-out period and suspends the erase
operation.
After the erase operation has been suspended, the
system can read array data from or program data to
any sector not selected for erasure. (The device “erase
suspends” all sectors selected for erasure.) Normal
read and write timings and command definitions apply.
Reading at any address within erase-suspended sec-
tors produces status data on DQ7–DQ0. The system
can use DQ7, or DQ6 and DQ2 together, to determine
if a sector is actively erasing or is erase-suspended.
See “Write Operation Status” for information on these
status bits.
The system can monitor DQ3 to determine if the sector
erase timer has timed out. (See the “DQ3: Sector Erase
March 3, 2009 21444E7
Am29F016D
17
D A T A S H E E T
After an erase-suspended program operation is com-
plete, the system can once again read array data within
non-suspended sectors. The system can determine
the status of the program operation using the DQ7 or
DQ6 status bits, just as in the standard program oper-
ation. See “Write Operation Status” for more
information.
START
Write Erase
Command Sequence
The system may also write the autoselect command
sequence when the device is in the Erase Suspend
mode. The device allows reading autoselect codes
even at addresses within erasing sectors, since the
codes are not stored in the memory array. When the
device exits the autoselect mode, the device reverts to
the Erase Suspend mode, and is ready for another
valid operation. See “Autoselect Command Sequence”
for more information.
Data Poll
from System
Embedded
Erase
algorithm
in progress
No
Data = FFh?
The system must write the Erase Resume command
(address bits are “don’t care”) to exit the erase suspend
mode and continue the sector erase operation. Further
writes of the Resume command are ignored. Another
Erase Suspend command can be written after the de-
vice has resumed erasing.
Yes
Erasure Completed
Notes:
1. See the appropriate Command Definitions table for erase command sequence.
2. See “DQ3: Sector Erase Timer” for more information.
Figure 3. Erase Operation
18
Am29F016D
21444E7 March 3, 2009
D A T A S H E E T
Command Definitions
Table 9. Am29F016D Command Definitions
Bus Cycles (Notes 2–4)
Command
Sequence
(Note 1)
First
Second
Third
Addr
Fourth
Data Addr Data
Fifth
Sixth
Addr Data Addr Data
Addr Data Addr Data
Read (Note 5)
Reset (Note 6)
Manufacturer ID
1
1
4
4
RA
RD
F0
XXX
555
555
AA
AA
2AA
2AA
55
55
555
555
90
90
X00
X01
01
Autoselect
Device ID
AD
(Note 7)
XX00
XX01
Sector Group Protect
Verify (Note 8)
SGA
X02
4
555
AA
2AA
55
555
90
CFI Query (Note 9)
Program
1
4
3
2
2
6
6
1
1
55
98
AA
AA
A0
90
AA
AA
B0
30
555
555
XXX
XXX
555
555
XXX
XXX
2AA
2AA
PA
55
55
PD
00
55
55
555
555
A0
20
PA
PD
Unlock Bypass
Unlock Bypass Program (Note 10)
Unlock Bypass Reset (Note 11)
Chip Erase
XXX
2AA
2AA
555
555
80
80
555
555
AA
AA
2AA
2AA
55
55
555
SA
10
30
Sector Erase
Erase Suspend (Note 9)
Erase Resume (Note 10)
Legend:
X = Don’t care
PD = Data to be programmed at location PA. Data latches on
the rising edge of WE# or CE# pulse, whichever happens first.
RA = Address of the memory location to be read.
SA = Address of the sector to be verified (in autoselect mode)
or erased. Address bits A20–A16 select a unique sector.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed.
Addresses latch on the falling edge of the WE# or CE# pulse,
whichever happens later.
SGA = Address of the sector group to be verified. Address bits
A20–A18 select a unique sector group.
Notes:
1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
9. Command is valid when device is ready to read array data
or when device is in autoselect mode.
3. Except when reading array or autoselect data, all bus
cycles are write operations.
10. The Unlock Bypass command is required prior to the
Unlock Bypass Program command.
4. Address bits A20–A11 are don’t cares for unlock and
command cycles, unless SA or PA required.
11. The Unlock Bypass Reset command is required to return
to reading array data when the device is in the unlock
bypass mode.
5. No unlock or command cycles required when reading
array data.
12. The system may read and program in non-erasing
sectors, or enter the autoselect mode, when in the Erase
Suspend mode. The Erase Suspend command is valid
only during a sector erase operation.
6. The Reset command is required to return to reading array
data when device is in the autoselect mode, or if DQ5
goes high (while the device is providing status data).
7. The fourth cycle of the autoselect command sequence is
a read cycle.
13. The Erase Resume command is valid only during the
Erase Suspend mode.
8. The data is 00h for an unprotected sector group and 01h
for a protected sector group.See “Autoselect Command
Sequence” for more information.
March 3, 2009 21444E7
Am29F016D
19
D A T A S H E E T
WRITE OPERATION STATUS
The device provides several bits to determine the sta-
tus of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7,
and RY/BY#. Table 10 and the following subsections
describe the functions of these bits. DQ7, RY/BY#, and
DQ6 each offer a method for determining whether a
program or erase operation is complete or in progress.
These three bits are discussed first.
rithms) figure in the “AC Characteristics” section
illustrates this.
Table 10 shows the outputs for Data# Polling on DQ7.
Figure 4 shows the Data# Polling algorithm.
START
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host
system whether an Embedded Algorithm is in
progress or completed, or whether the device is in
Erase Suspend. Data# Polling is valid after the rising
edge of the final WE# pulse in the program or erase
command sequence.
Read DQ7–DQ0
Addr = VA
During the Embedded Program algorithm, the device
outputs on DQ7 the complement of the datum pro-
grammed to DQ7. This DQ7 status also applies to
programming during Erase Suspend. When the Em-
bedded Program algorithm is complete, the device
outputs the datum programmed to DQ7. The system
must provide the program address to read valid status
information on DQ7. If a program address falls within a
protected sector, Data# Polling on DQ7 is active for ap-
proximately 2 µs, then the device returns to reading
array data.
Yes
DQ7 = Data?
No
No
DQ5 = 1?
Yes
During the Embedded Erase algorithm, Data# Polling
produces a “0” on DQ7. When the Embedded Erase al-
gorithm is complete, or if the device enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7.
This is analogous to the complement/true datum output
described for the Embedded Program algorithm: the
erase function changes all the bits in a sector to “1”;
prior to this, the device outputs the “complement,” or
“0.” The system must provide an address within any of
the sectors selected for erasure to read valid status in-
formation on DQ7.
Read DQ7–DQ0
Addr = VA
Yes
DQ7 = Data?
No
After an erase command sequence is written, if all sec-
tors selected for erasing are protected, Data# Polling
on DQ7 is active for approximately 100 µs, then the de-
vice returns to reading array data. If not all selected
sectors are protected, the Embedded Erase algorithm
erases the unprotected sectors, and ignores the se-
lected sectors that are protected.
PASS
FAIL
Notes:
1. VA = Valid address for programming. During a sector
erase operation, a valid address is an address within any
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.
When the system detects DQ7 has changed from the
complement to true data, it can read valid data at
DQ7–DQ0 on the following read cycles. This is be-
cause DQ7 may change asynchronously with
DQ0–DQ6 while Output Enable (OE#) is asserted low.
The Data# Polling Timings (During Embedded Algo-
2. DQ7 should be rechecked even if DQ5 = “1” because
DQ7 may change simultaneously with DQ5.
Figure 4. Data# Polling Algorithm
20
Am29F016D
21444E7 March 3, 2009
D A T A S H E E T
The Write Operation Status table shows the outputs for
RY/BY#: Ready/Busy#
Toggle Bit I on DQ6. Refer to Figure 5 for the toggle bit
algorithm, and to the Toggle Bit Timings figure in the
“AC Characteristics” section for the timing diagram.
The DQ2 vs. DQ6 figure shows the differences be-
tween DQ2 and DQ6 in graphical form. See also the
subsection on “DQ2: Toggle Bit II”.
The RY/BY# is a dedicated, open-drain output pin that
indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY# status is valid after
the rising edge of the final WE# pulse in the command
sequence. Since RY/BY# is an open-drain output, sev-
eral RY/BY# pins can be tied together in parallel with a
pull-up resistor to V
.
CC
DQ2: Toggle Bit II
If the output is low (Busy), the device is actively erasing
or programming. (This includes programming in the
Erase Suspend mode.) If the output is high (Ready),
the device is ready to read array data (including during
the Erase Suspend mode), or is in the standby mode.
The “Toggle Bit II” on DQ2, when used with DQ6, indi-
cates whether a particular sector is actively erasing
(that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of the final WE# pulse in
the command sequence.
Table 10 shows the outputs for RY/BY#. The timing di-
agrams for read, reset, program, and erase shows the
relationship of RY/BY# to other signals.
DQ2 toggles when the system reads at addresses
within those sectors that have been selected for era-
sure. (The system may use either OE# or CE# to
control the read cycles.) But DQ2 cannot distinguish
whether the sector is actively erasing or is erase-sus-
pended. DQ6, by comparison, indicates whether the
device is actively erasing, or is in Erase Suspend, but
cannot distinguish which sectors are selected for era-
sure. Thus, both status bits are required for sector and
mode information. Refer to Table 10 to compare out-
puts for DQ2 and DQ6.
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or complete,
or whether the device has entered the Erase Suspend
mode. Toggle Bit I may be read at any address, and is
valid after the rising edge of the final WE# pulse in the
command sequence (prior to the program or erase op-
eration), and during the sector erase time-out.
During an Embedded Program or Erase algorithm op-
eration, successive read cycles to any address cause
DQ6 to toggle. (The system may use either OE# or
CE# to control the read cycles.) When the operation is
complete, DQ6 stops toggling.
Figure 5 shows the toggle bit algorithm in flowchart
form, and the section “DQ2: Toggle Bit II” explains the
algorithm. See also the “DQ6: Toggle Bit I” subsection.
Refer to the Toggle Bit Timings figure for the toggle bit
timing diagram. The DQ2 vs. DQ6 figure shows the dif-
ferences between DQ2 and DQ6 in graphical form.
After an erase command sequence is written, if all
sectors selected for erasing are protected, DQ6 tog-
gles for approximately 100 µs, then returns to reading
array data. If not all selected sectors are protected,
the Embedded Erase algorithm erases the unpro-
tected sectors, and ignores the selected sectors that
are protected.
Reading Toggle Bits DQ6/DQ2
Refer to Figure 5 for the following discussion. When-
ever the system initially begins reading toggle bit
status, it must read DQ7–DQ0 at least twice in a row
to determine whether a toggle bit is toggling. Typically,
a system would note and store the value of the toggle
bit after the first read. After the second read, the sys-
tem would compare the new value of the toggle bit
with the first. If the toggle bit is not toggling, the device
has completed the program or erase operation. The
system can read array data on DQ7–DQ0 on the fol-
lowing read cycle.
The system can use DQ6 and DQ2 together to deter-
mine whether a sector is actively erasing or is erase-
suspended. When the device is actively erasing (that is,
the Embedded Erase algorithm is in progress), DQ6
toggles. When the device enters the Erase Suspend
mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing
or erase-suspended. Alternatively, the system can use
DQ7 (see the subsection on “DQ7: Data# Polling”).
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the
system also should note whether the value of DQ5 is
high (see the section on DQ5). If it is, the system
should then determine again whether the toggle bit is
toggling, since the toggle bit may have stopped tog-
gling just as DQ5 went high. If the toggle bit is no longer
toggling, the device has successfully completed the
program or erase operation. If it is still toggling, the
device did not complete the operation successfully, and
If a program address falls within a protected sector,
DQ6 toggles for approximately 2 µs after the program
command sequence is written, then returns to reading
array data.
DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded Pro-
gram algorithm is complete.
March 3, 2009 21444E7
Am29F016D
21
D A T A S H E E T
the system must write the reset command to return to
reading array data.
erase command. If DQ3 is high on the second status
check, the last command might not have been ac-
cepted. Table 10 shows the outputs for DQ3.
The remaining scenario is that the system initially de-
termines that the toggle bit is toggling and DQ5 has not
gone high. The system may continue to monitor the
toggle bit and DQ5 through successive read cycles, de-
termining the status as described in the previous
paragraph. Alternatively, it may choose to perform
other system tasks. In this case, the system must start
at the beginning of the algorithm when it returns to de-
termine the status of the operation (top of Figure 5).
START
Read DQ7–DQ0
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under
these conditions DQ5 produces a “1.” This is a failure
condition that indicates the program or erase cycle was
not successfully completed.
Read DQ7–DQ0
(Note
The DQ5 failure condition may appear if the system
tries to program a “1” to a location that is previously pro-
grammed to “0.” Only an erase operation can change
a “0” back to a “1.” Under this condition, the device
halts the operation, and when the operation has ex-
ceeded the timing limits, DQ5 produces a “1.”
No
Toggle Bit
= Toggle?
Yes
Under both these conditions, the system must issue the
reset command to return the device to reading array
data.
No
DQ5 = 1?
Yes
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not an
erase operation has begun. (The sector erase timer
does not apply to the chip erase command.) If addi-
tional sectors are selected for erasure, the entire time-
out also applies after each additional sector erase
command. When the time-out is complete, DQ3
switches from “0” to “1.” The system may ignore DQ3
if the system can guarantee that the time between ad-
ditional sector erase commands will always be less
than 50 µs. See also the “Sector Erase Command Se-
quence” section.
(Notes
1, 2)
Read DQ7–DQ0
Twice
Toggle Bit
= Toggle?
No
Yes
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
After the sector erase command sequence is written,
the system should read the status on DQ7 (Data# Poll-
ing) or DQ6 (Toggle Bit I) to ensure the device has
accepted the command sequence, and then read DQ3.
If DQ3 is “1”, the internally controlled erase cycle has
begun; all further commands (other than Erase Sus-
pend) are ignored until the erase operation is complete.
If DQ3 is “0”, the device will accept additional sector
erase commands. To ensure the command has been
accepted, the system software should check the status
of DQ3 prior to and following each subsequent sector
Notes:
1. Read toggle bit twice to determine whether or not it is
toggling. See text.
2. Recheck toggle bit because it may stop toggling as DQ5
changes to “1”. See text.
Figure 5. Toggle Bit Algorithm
22
Am29F016D
21444E7 March 3, 2009
D A T A S H E E T
Table 10. Write Operation Status
DQ7
DQ5
DQ2
Operation
(Note 1)
DQ6
(Note 2)
DQ3
N/A
1
(Note 1)
RY/BY#
Embedded Program Algorithm
Embedded Erase Algorithm
DQ7#
0
Toggle
Toggle
0
0
No toggle
Toggle
0
0
Standard
Mode
Reading within Erase
Suspended Sector
1
No toggle
0
N/A
Toggle
1
Erase
Suspend Reading within Non-Erase
Data
Data
Data
0
Data
N/A
Data
N/A
1
0
Mode
Suspended Sector
Erase-Suspend-Program
DQ7#
Toggle
Notes:
1. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
2. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
See “DQ5: Exceeded Timing Limits” for more information.
March 3, 2009 21444E7
Am29F016D
23
D A T A S H E E T
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
Plastic Packages . . . . . . . . . . . . . . . –65°C to +125°C
Voltage with Respect to Ground
(Note 1). . . . . . . . . . . . . . . . . –2.0 V to 7.0 V
V
CC
Ambient Temperature
with Power Applied. . . . . . . . . . . . . . –55°C to +125°C
A9, OE#, RESET# (Note 2) . . . . –2.0 V to 12.5 V
All other pins (Note 1). . . . . . . . . . –2.0 V to 7.0 V
Output Short Circuit Current (Note 3) . . . . . . 200 mA
Notes:
1. Minimum DC voltage on input or I/O pins is –0.5 V.
During voltage transitions, inputs may overshoot VSS to
–2.0 V for periods of up to 20 ns. See . Maximum DC
voltage on output and I/O pins is VCC + 0.5 V. During
voltage transitions, outputs may overshoot to VCC + 2.0
V for periods up to 20 ns. See .
20 ns
20 ns
+0.8 V
2. Minimum DC input voltage on A9, OE#, RESET# pins is
–0.5V. During voltage transitions, A9, OE#, RESET# pins
may overshoot VSS to –2.0 V for periods of up to 20 ns.
See . Maximum DC input voltage on A9, OE#, and
RESET# is 12.5 V which may overshoot to 13.5 V for
periods up to 20 ns.
–0.5 V
–2.0 V
20 ns
3. No more than one output shorted at a time. Duration of
the short circuit should not be greater than one second.
Figure 6. Maximum Negative
Overshoot Waveform
Stresses greater than those listed in this section may cause
permanent damage to the device. This is a stress rating
only; functional operation of the device at these or any other
conditions above those indicated in the operational sections
of this specification is not implied. Exposure of the device to
absolute maximum rating conditions for extended periods
may affect device reliability.
20 ns
VCC
+2.0 V
VCC
+0.5 V
2.0 V
20 ns
20 ns
Figure 7. Maximum Positive
Overshoot Waveform
OPERATING RANGES
Commercial (C) Devices
Ambient Temperature (T ). . . . . . . . . . . 0°C to +70°C
C
Industrial (I) Devices
Ambient Temperature (T ). . . . . . . . . –40°C to +85°C
C
V
Supply Voltages
CC
V
for 10% devices. . . . . . . . . . . .+4.5 V to +5.5 V
CC
Operating ranges define those limits between which the
functionality of the device is guaranteed.
24
Am29F016D
21444E7 March 3, 2009
D A T A S H E E T
DC CHARACTERISTICS
TTL/NMOS Compatible
Parameter
Symbol
Parameter Description
Test Description
VIN = VSS to VCC, VCC = VCC Max
VCC = VCC Max, A9 = 12.5 V
VOUT = VSS to VCC, VCC = VCC Max
CE# = VIL, OE# = VIH
Min
Typ
Max
±1.0
50
Unit
µA
ILI
Input Load Current
ILIT
A9 Input Load Current
µA
ILO
Output Leakage Current
VCC Read Current (Note 1)
VCC Write Current (Notes 2, 3)
±1.0
40
µA
ICC1
ICC2
25
40
mA
mA
CE# = VIL, OE# = VIH
60
VCC Standby Current
(CE# Controlled)
VCC = VCC Max, CE# = VIH,
RESET# = VIH
ICC3
ICC4
0.4
0.4
1.0
1.0
mA
mA
VCC Standby Current
(RESET# Controlled)
VCC = VCC Max, RESET# = VIL
VIL
Input Low Level
Input High Level
–0.5
2.0
0.8
V
V
VIH
VCC + 0.5
Voltage for Autoselect and Sector
Protect
VID
VCC = 5.0 V
11.5
12.5
0.45
V
VOL
VOH
VLKO
Output Low Voltage
Output High Level
IOL = 12 mA, VCC = VCC Min
IOH = –2.5 mA VCC = VCC Min
V
V
V
2.4
3.2
Low VCC Lock-out Voltage
4.2
CMOS Compatible
Parameter
Symbol
Parameter Description
Test Description
VIN = VSS to VCC, VCC = VCC Max
VCC = VCC Max, A9 = 12.5 V
VOUT = VSS to VCC, VCC = VCC Max
CE# = VIL, OE# = VIH
Min
Typ
Max
±1.0
50
Unit
µA
ILI
Input Load Current
ILIT
A9 Input Load Current
µA
ILO
Output Leakage Current
VCC Read Current (Note 1)
VCC Write Current (Notes 2, 3)
±1.0
40
µA
ICC1
ICC2
25
30
mA
mA
CE# = VIL, OE# = VIH
40
VCC Standby Current
(CE# Controlled) (Note 4)
VCC = VCC Max, CE# = VCC ± 0.5 V,
RESET# = VCC ± 0.5 V
ICC3
ICC4
1
1
5
5
µA
µA
VCC Standby Current
(RESET# Controlled) (Note 4)
VCC = VCC Max,
RESET# = VSS ± 0.5 V
VIL
VIH
Input Low Level
Input High Level
–0.5
0.8
V
V
0.7x VCC
VCC + 0.3
Voltage for Autoselect
and Sector Protect
VID
VCC = 5.0 V
11.5
12.5
0.45
V
VOL
Output Low Voltage
IOL = 12 mA, VCC = VCC Min
IOH = –2.5 mA, VCC = VCC Min
IOH = –100 μA, VCC = VCC Min
V
V
V
V
VOH1
VOH2
VLKO
0.85 VCC
VCC – 0.4
3.2
Output High Voltage
Low VCC Lock-out Voltage
4.2
Notes for DC Characteristics (both tables):
1. The ICC current is typically less than 1 mA/MHz, with OE# at VIH.
2. ICC active while Embedded Program or Embedded Erase algorithm is in progress.
3. Not 100% tested.
4. For CMOS mode only ICC3, ICC4 = 20 µA at extended temperature (>+85°C).
March 3, 2009 21444E7
Am29F016D
25
D A T A S H E E T
TEST CONDITIONS
Table 11. Test Specifications
All speed
5.0 V
Test Condition
options
Unit
2.7 kΩ
Device
Under
Test
Output Load
1 TTL gate
Output Load Capacitance, CL
(including jig capacitance)
100
pF
C
L
6.2 kΩ
Input Rise and Fall Times
Input Pulse Levels
20
ns
V
0.45–2.4
Input timing measurement
reference levels
0.8
2.0
V
V
Note: Diodes are IN3064 or equivalent
Output timing measurement
reference levels
Figure 8. Test Setup
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Does Not Apply
Changing, State Unknown
Center Line is High Impedance State (High Z)
KS000010-PAL
26
Am29F016D
21444E7 March 3, 2009
D A T A S H E E T
AC CHARACTERISTICS
Read-only Operations
Parameter Symbol
Speed Options
JEDEC
Std
Parameter Description
Read Cycle Time (Note 1)
Test Setup
-70
-90
-120
Unit
tAVAV
tRC
Min
70
90
120
120
ns
CE# = VIL
OE# = VIL
tAVQV
tACC
Address to Output Delay
Max
70
90
ns
tELQV
tGLQV
tCE
tOE
Chip Enable to Output Delay
Output Enable to Output Delay
OE# = VIL
Max
Max
Min
70
40
0
90
40
0
120
50
0
ns
ns
ns
Read
Output Enable Hold Time
(Note 1)
tOEH
Toggle and
Min
10
10
10
ns
Data# Polling
tEHQZ
tGHQZ
tDF
tDF
Chip Enable to Output High Z (Note 1)
Output Enable to Output High Z (Note 1)
Max
Max
20
20
20
20
30
30
ns
ns
Output Hold Time From Addresses CE# or
OE# Whichever Occurs First
tAXQX
tOH
Min
0
0
0
ns
µs
RESET# Pin Low to Read Mode
(Note 1)
tReady
Max
20
20
20
Notes:
1. Not 100% tested.
2. Refer to and for test specifications.
tRC
Addresses Stable
tACC
Addresses
CE#
tDF
tOE
OE#
WE#
tOEH
tCE
tOH
HIGH Z
HIGH Z
Output Valid
Outputs
RESET#
RY/BY#
0 V
Figure 9. Read Operation Timings
March 3, 2009 21444E7
Am29F016D
27
D A T A S H E E T
AC CHARACTERISTICS
Hardware Reset (RESET#)
Parameter
JEDEC
Std Description
Test Setup
All Speed Options
Unit
RESET# Pin Low (During Embedded
Algorithms) to Read or Write (See Note)
tREADY
Max
Max
20
µs
RESET# Pin Low (NOT During Embedded
Algorithms) to Read or Write (See Note)
tREADY
500
ns
tRP
tRH
tRB
RESET# Pulse Width
Min
Min
Min
500
50
0
ns
ns
ns
RESET# High Time Before Read (See Note)
RY/BY# Recovery Time
Note:
Not 100% tested.
RY/BY#
CE#, OE#
RESET#
tRH
tRP
tReady
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
tReady
RY/BY#
tRB
CE#, OE#
RESET#
tRP
Figure 10. RESET# Timings
28
Am29F016D
21444E7 March 3, 2009
D A T A S H E E T
AC CHARACTERISTICS
Erase/Program Operations
Parameter
Speed Options
JEDEC
tAVAV
Std
tWC
tAS
Parameter Description
Write Cycle Time (Note 1)
-70
-90
90
0
-120
Unit
ns
Min
Min
Min
Min
Min
Min
70
120
tAVWL
tWLAX
tDVWH
tWHDX
Address Setup Time
Address Hold Time
Data Setup Time
ns
tAH
40
40
45
45
0
50
50
ns
tDS
ns
tDH
tOES
Data Hold Time
ns
Output Enable Setup Time
0
ns
Read Recover Time Before Write
(OE# high to WE# low)
tGHWL
tGHWL
Min
0
ns
tELWL
tWHEH
tWLWH
tWHWL
tWHWH1
tCS
tCH
CE# Setup Time
Min
Min
Min
Min
Typ
Typ
Max
Min
Max
0
0
ns
ns
CE# Hold Time
tWP
Write Pulse Width
Write Pulse Width High
40
45
20
7
50
ns
tWPH
ns
tWHWH1 Byte Programming Operation (Note 2)
µs
1
sec
sec
µs
tWHWH2
tWHWH2 Sector Erase Operation (Note 2)
8
tVCS
VCC Set Up Time (Note 1)
WE# to RY/BY# Valid
50
40
tBUSY
40
50
ns
Notes:
1. Not 100% tested.
2. See the “Erase And Programming Performance” section for more information.
March 3, 2009 21444E7
Am29F016D
29
D A T A S H E E T
AC CHARACTERISTICS
Program Command Sequence (last two cycles)
Read Status Data (last two cycles)
tAS
tWC
Addresses
555h
PA
PA
PA
tAH
CE#
OE#
tCH
tWHWH1
tWP
WE#
Data
tWPH
tCS
tDS
tDH
PD
DOUT
A0h
Status
tBUSY
tRB
RY/BY#
VCC
tVCS
Note: PA = program address, PD = program data, DOUT is the true data at the program address.
Figure 11. Program Operation Timings
30
Am29F016D
21444E7 March 3, 2009
D A T A S H E E T
AC CHARACTERISTICS
tAS
SA
tWC
2AAh
VA
VA
Addresses
CE#
555h for chip erase
tAH
tCH
OE#
tWP
WE#
tWPH
tWHWH2
tCS
tDS
tDH
In
Data
Complete
55h
30h
Progress
10 for Chip Erase
tBUSY
tRB
RY/BY#
VCC
tVCS
Note:
SA = Sector Address. VA = Valid Address for reading status data.
Figure 12. Chip/Sector Erase Operation Timings
March 3, 2009 21444E7
Am29F016D
31
D A T A S H E E T
AC CHARACTERISTICS
tRC
VA
Addresses
VA
VA
tACC
tCE
CE#
tCH
tOE
OE#
WE#
tOEH
tDF
tOH
Complement
High Z
High Z
DQ7
Valid Data
Complement
Status Data
True
DQ0–DQ6
Valid Data
Status Data
True
tBUSY
RY/BY#
Note:
VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.
Figure 13. Data# Polling Timings (During Embedded Algorithms)
tRC
Addresses
CE#
VA
tACC
tCE
VA
VA
VA
tCH
tOE
OE#
WE#
tOEH
tDF
tOH
High Z
DQ6/DQ2
RY/BY#
Valid Status
(first read)
Valid Status
Valid Status
Valid Data
(second read)
(stops toggling)
tBUSY
Note:
VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle,
and array data read cycle.
Figure 14. Toggle Bit Timings (During Embedded Algorithms)
32
Am29F016D
21444E7 March 3, 2009
D A T A S H E E T
AC CHARACTERISTICS
Enter
Embedded
Erasing
Erase
Suspend
Enter Erase
Suspend Program
Erase
Resume
Erase
Erase Suspend
Read
Erase
Suspend
Program
Erase
Complete
WE#
Erase
Erase Suspend
Read
DQ6
DQ2
Note:
The system may use OE# or CE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within the erase-suspended
sector.
Figure 15. DQ2 vs. DQ6
Temporary Sector Unprotect
Parameter
JEDEC
Std
Description
All Speed Options
Unit
tVIDR
VID Rise and Fall Time (See Note)
Min
Min
500
ns
RESET# Setup Time for Temporary Sector
Unprotect
tRSP
4
µs
Note:
Not 100% tested.
12 V
RESET#
0 or 5 V
0 or 5 V
tVIDR
tVIDR
Program or Erase Command Sequence
CE#
WE#
tRSP
RY/BY#
Figure 16. Temporary Sector Group Unprotect Timings
March 3, 2009 21444E7
Am29F016D
33
D A T A S H E E T
AC CHARACTERISTICS
Erase and Program Operations
Alternate CE# Controlled Writes
Parameter Symbol
Speed Options
JEDEC
tAVAV
Std
tWC
Parameter Description
Write Cycle Time (Note 1)
-70
-90
90
0
-120
Unit
ns
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Typ
Typ
Max
70
120
tAVEL
tAS
Address Setup Time
Address Hold Time
ns
tELAX
tAH
40
40
45
45
0
50
50
ns
tDVEH
tEHDX
tGHEL
tWLEL
tEHWH
tELEH
tEHEL
tWHWH1
tDS
Data Setup Time
ns
tDH
Address Hold Time
ns
tGHEL
tWS
Read Recover Time Before Write
CE# Setup Time
0
ns
0
ns
tWH
CE# Hold Time
0
ns
tCP
Write Pulse Width
40
45
20
7
50
ns
tCPH
tWHWH1
Write Pulse Width High
Byte Programming Operation (Note 2)
ns
µs
1
sec
sec
tWHWH2
tWHWH2
Sector Erase Operation (Note 2)
8
Notes:
1. Not 100% tested.
2. See the “Erase And Programming Performance” section for more information.
34
Am29F016D
21444E7 March 3, 2009
D A T A S H E E T
AC CHARACTERISTICS
555 for program
PA for program
2AA for erase
SA for sector erase
555 for chip erase
Data# Polling
Addresses
PA
tWC
tWH
tAS
tAH
WE#
OE#
tGHEL
tWHWH1 or 2
tCP
CE#
Data
tWS
tCPH
tDS
tBUSY
tDH
DQ7#
DOUT
tRH
A0 for program
55 for erase
PD for program
30 for sector erase
10 for chip erase
RESET#
RY/BY#
Notes:
1. PA = Program Address, PD = Program Data, SA = Sector Address, DQ7# = Complement of Data Input, DOUT = Array Data.
2. Figure indicates the last two bus cycles of the command sequence.
Figure 17. Alternate CE# Controlled Write Operation Timings
March 3, 2009 21444E7
Am29F016D
35
D A T A S H E E T
ERASE AND PROGRAMMING PERFORMANCE
Parameter
Sector Erase Time
Typ (Note 1)
Max (Note 2)
Unit
sec
sec
µs
Comments
1
32
7
8
Excludes 00h programming prior to
erasure (Note 4)
Chip Erase Time
256
300
43.2
Byte Programming Time
Chip Programming Time (Note 3)
Excludes system-level overhead
(Note 5)
14.4
sec
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 5.0 V VCC, 1,000,000 cycles. Additionally,
programming typicals assume checkerboard pattern.
2. Under worst case conditions of 90°C, VCC = 4.5 V, 1,000,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum byte program time listed. If the maximum byte program time given is exceeded, only then
does the device set DQ5 = 1. See the section on DQ5 for further information.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the four-bus-cycle sequence for programming. See Table 6 for further
information on command definitions.
6. The device has a guaranteed minimum erase and program cycle endurance of 1,000,000 cycles.
LATCHUP CHARACTERISTICS
Min
Max
Input Voltage with respect to VSS on I/O pins
VCC Current
–1.0 V
VCC + 1.0 V
+100 mA
–100 mA
Note: Includes all pins except VCC. Test conditions: VCC = 5.0 Volt, one pin at a time.
TSOP AND SO PIN CAPACITANCE
Parameter
Symbol
Parameter Description
Input Capacitance
Test Conditions
Min
6
Max
7.5
12
Unit
CIN
VIN = 0
VOUT = 0
VIN = 0
pF
pF
pF
COUT
CIN2
Output Capacitance
8.5
7.5
Control Pin Capacitance
9
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.
DATA RETENTION
Parameter
Test Conditions
150°C
Min
10
Unit
Years
Years
Minimum Pattern Data Retention Time
125°C
20
36
Am29F016D
21444E7 March 3, 2009
D A T A S H E E T
PHYSICAL DIMENSIONS
TS 040—40-Pin Standard Thin Small Outline Package
Dwg rev AA; 10/99
March 3, 2009 21444E7
Am29F016D
37
D A T A S H E E T
PHYSICAL DIMENSIONS (continued)
TS 048—48-Pin Standard Thin Small Outline Package
Dwg rev AA; 10/99
38
Am29F016D
21444E7 March 3, 2009
D A T A S H E E T
PHYSICAL DIMENSIONS (continued)
SO 044—44-Pin Small Outline Package
Dwg rev AC; 10/99
March 3, 2009 21444E7
Am29F016D
39
D A T A S H E E T
REVISION SUMMARY
Distinctive Characteristics
Revision A (May 1997)
Added:
Initial release of Am29F016B (0.35 µm) device.
■ 20-year data retention at 125°C
— Reliable operation for the life of the system
DC Characteristics—CMOS Compatible
Revision B (January 1998)
Global
Made formatting and layout consistent with other data
sheets. Used updated common tables and diagrams.
I
, I
: Added Note 4, “For CMOS mode only I
,
CC3 CC4
CC3
I
= 20 µA at extended temperature (>+85°C)”.
CC4
Revision B+1 (January 1998)
AC Characteristics—Read-only Operations
DC Characteristics—TTL/NMOS Compatible and
CMOS Compatible
Deleted note referring to output driver disable time.
I
, I
, I
, I
: Added Note 2 “Maximum I
CC1 CC2 CC3 CC4 CC
specifications are tested with V = V
”.
CCmax
Figure 16—Temporary Sector Group Unprotect
Timings
CC
I
, I
: Deleted V = V Max.
CC3 CC4 CC CC
Corrected title to indicate “sector group.”
Revision C+1 (March 23, 1999)
Operating Ranges
Revision B+2 (April 1998)
Global
The temperature ranges are now specified as ambient.
Added -70 speed option, deleted -75 speed option.
Revision C+2 (May 17, 1999)
Product Selector Guide
Distinctive Characteristics
Changed minimum 100K write/erase cycles guaran-
teed to 1,000,000.
Corrected the t specification for the -150 speed op-
tion to 55 ns.
OE
Ordering Information
Operating Ranges
Added extended temperature availability to -90, -120,
and -150 speed options.
V
Supply Voltages: Added “V for 5% devices .
CC
CC
+4.75 V to +5.25 V”.
Operating Ranges
Revision C+3 (July 2, 1999)
Global
Added extended temperature range.
DC Characteristics, CMOS Compatible
Added references to availability of device in Known
Good Die (KGD) form.
Corrected the CE# and RESET# test conditions for
I
and I
to V
0.5 V.
CC3
CC4
CC
Revision D (November 16, 1999)
AC Characteristics
AC Characteristics—Figure 11. Program
Operations Timing and Figure 12. Chip/Sector
Erase Operations
Erase/Program Operations; Erase and Program Oper-
ations Alternate CE# Controlled Writes: Corrected the
notes reference for t
and t
. These param-
WHWH1
WHWH2
Deleted t
high.
and changed OE# waveform to start at
GHWL
eters are 100% tested. Corrected the note reference for
. This parameter is not 100% tested.
t
VCS
Physical Dimensions
Temporary Sector Unprotect Table
Replaced figures with more detailed illustrations.
Added note reference for t
100% tested.
. This parameter is not
VIDR
Revision E (May 19, 2000)
Global
Erase and Programming Performance
Changed part number to Am29F016D. This reflects the
new 0.23 µm process technology upon which this de-
vice will now be built.
Changed minimum 100K program and erase cycles
guaranteed to 1,000,000.
Revision C (January 1999)
Global
The Am29F016D is compatible with the previous 0.32
µm Am29F016B device, with the exception of the sec-
tor group protect and unprotect algorithms. These
algorithms are provided in a seperate document. Con-
tact AMD for more information or to request a copy of
that document.
Updated for CS39S process technology.
40
Am29F016D
21444E7 March 3, 2009
D A T A S H E E T
This data sheet will be marked preliminary until the de-
vice has been in full production for a number of months.
Revision E+4 (January 4, 2006)
Global
The -75 speed option (70 ns, 5% V ) has been re-
CC
Deleted 150 speed option
placed by a -70 speed option (70 ns, 10 V ).
CC
Deleted TSR048 48-pin Reverse Thin Small Outline
Package Option
The burn-in option is no longer available.
The device now has the Unlock Bypass Program
feature.
Deleted TSR040 40-pin Reverse Thin Small Outline
Package Option
The publication number of the document describing
sector protection/unprotection implementation is now
23922.
Revision E5 (July 27, 2006)
Global
Added product availability notice to cover page and first
page of data sheet.
Revision E+1 (December 4, 2000)
Global
AC Characteristics
Added table of contents. Removed Preliminary status
from document.
Erase/Program Operations table: Changed t
to a
BUSY
maximum specification.
Revision E+2 (March 23, 2001)
Common Flash Memory Interface (CFI)
Added section.
Revision E6 (November 2, 2006)
Global
Deleted product availability notice to cover page and
first page of data sheet.
Table 9, Am29F016D Command Definitions
Corrected the addresses for the three-cycle unlock by-
pass command sequence. Added Note 9 and CFI
Query command to table.
Revision E7 (March 3, 2009)
Global
Added obsolescence information.
Revision E+3 (June 4, 2004)
Ordering Information
Added Lead-free (Pb-free) options to the Temperature
Range breakout of the OPN table and the Valid Combi-
nations table..
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as
contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the
public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,
aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for
any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to
you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor
devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design
measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal
operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under
the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country,
the prior authorization by the respective government entity will be required for export of those products.
Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a Spansion product under
development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this
document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose,
merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any
damages of any kind arising out of the use of the information in this document.
Copyright © 1997–2005 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered
trademarks of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks
of their respective companies.
Copyright © 2006-2009 Spansion Inc. All rights reserved. Spansion®, the Spansion Logo, MirrorBit®, MirrorBit® Eclipse™, ORNAND™
,
ORNAND2™, HD-SIM™, EcoRAM™ and combinations thereof, are trademarks of Spansion LLC in the US and other countries. Other names
used are for informational purposes only and may be trademarks of their respective owners.
March 3, 2009 21444E7
Am29F016D
41
AM29F016D-70SC 替代型号
型号 | 制造商 | 描述 | 替代类型 | 文档 |
M29F016B70M1T | STMICROELECTRONICS | 16 Mbit 2Mb x8, Uniform Block Single Supply Flash Memory | 功能相似 | |
M29F016B70M6T | STMICROELECTRONICS | 16 Mbit 2Mb x8, Uniform Block Single Supply Flash Memory | 功能相似 | |
AM29F016B-70SC | AMD | 16 Megabit (2 M x 8-Bit) CMOS 5.0 Volt-only, Uniform Sector Flash Memory | 功能相似 |
AM29F016D-70SC 相关器件
型号 | 制造商 | 描述 | 价格 | 文档 |
AM29F016D-70SCB | AMD | 16 Megabit (2 M x 8-Bit) CMOS 5.0 Volt-only, Uniform Sector Flash Memory | 获取价格 | |
AM29F016D-70SD | AMD | 16 Megabit (2 M x 8-Bit) CMOS 5.0 Volt-only, Uniform Sector Flash Memory | 获取价格 | |
AM29F016D-70SD | SPANSION | Flash, 2MX8, 70ns, PDSO44, LEAD FREE, MO-180AA, SOP-44 | 获取价格 | |
AM29F016D-70SE | AMD | 16 Megabit (2 M x 8-Bit) CMOS 5.0 Volt-only, Uniform Sector Flash Memory | 获取价格 | |
AM29F016D-70SEB | AMD | 16 Megabit (2 M x 8-Bit) CMOS 5.0 Volt-only, Uniform Sector Flash Memory | 获取价格 | |
AM29F016D-70SF | AMD | 16 Megabit (2 M x 8-Bit) CMOS 5.0 Volt-only, Uniform Sector Flash Memory | 获取价格 | |
AM29F016D-70SF | SPANSION | Flash, 2MX8, 70ns, PDSO44, LEAD FREE, MO-180AA, SOP-44 | 获取价格 | |
AM29F016D-70SI | AMD | 16 Megabit (2 M x 8-Bit) CMOS 5.0 Volt-only, Uniform Sector Flash Memory | 获取价格 | |
AM29F016D-70SI | SPANSION | Flash, 2MX8, 70ns, PDSO44, MO-180AA, SOP-44 | 获取价格 | |
AM29F016D-70SIB | AMD | 16 Megabit (2 M x 8-Bit) CMOS 5.0 Volt-only, Uniform Sector Flash Memory | 获取价格 |
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