AM29LV001BB-90FD [SPANSION]
Flash, 128KX8, 90ns, PDSO32, REVERSE, MO-142BD, TSOP-32;型号: | AM29LV001BB-90FD |
厂家: | SPANSION |
描述: | Flash, 128KX8, 90ns, PDSO32, REVERSE, MO-142BD, TSOP-32 光电二极管 |
文件: | 总45页 (文件大小:18491K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Am29LV001B
Data Sheet
July 2003
The following document specifies Spansion memory products that are now offered by both Advanced
Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig-
inally developed the specification, these products will be offered to customers of both AMD and
Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal datasheet improvement and are noted in the
document revision summary, where supported. Future routine revisions will occur when appropriate,
and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order
these products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about Spansion
memory solutions.
Publication Number 21557 Revision F Amendment 2 Issue Date August 19, 2005
THIS PAGE LEFT INTENTIONALLY BLANK.
Am29LV001B
1 Megabit (128 K x 8-Bit)
CMOS 3.0 Volt-only Boot Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
■ Single power supply operation
■ Unlock Bypass Mode Program Command
— Full voltage range: 2.7 to 3.6 volt read and write
operations for battery-powered applications
— Reduces overall programming time when issuing
multiple program command sequences
— Regulated voltage range: 3.0 to 3.6 volt read and
write operations and for compatibility with high
performance 3.3 volt microprocessors
■ Top or bottom boot block configurations available
■ Embedded Algorithms
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
■ Manufactured on 0.32 µm process technology
■ High performance
— Full voltage range: access times as fast as 55 ns
— Embedded Program algorithm automatically
writes and verifies data at specified addresses
— Regulated voltage range: access times as fast as
45 ns
■ Minimum 1 million erase cycle guarantee per sector
■ 20 Year data retention at 125°C
— Reliable operation for the life of the system
■ Package option
■ Ultra low power consumption (typical values at 5
MHz)
— 200 nA Automatic Sleep mode current
— 200 nA standby mode current
— 7 mA read current
— 32-pin TSOP
— 32-pin PLCC
— 15 mA program/erase current
■ Compatibility with JEDEC standards
■ Flexible sector architecture
— Pinout and software compatible with single-
power supply Flash
— One 8 Kbyte, two 4 Kbyte, and seven 16 Kbyte
— Supports full chip erase
— Superior inadvertent write protection
— Sector Protection features:
■ Data# Polling and toggle bits
Hardware method of locking a sector to prevent any
program or erase operations within that sector
— Provides a software method of detecting program
or erase operation completion
Sectors can be locked in-system or via
programming equipment
■ Erase Suspend/Erase Resume
— Supports reading data from or programming data
to a sector that is not being erased
Temporary Sector Unprotect feature allows code
changes in previously locked sectors
■ Hardware reset pin (RESET#)
— Hardware method for resetting the device to
reading array data
This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data
Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
Publication# 21557 Rev: F Amendment/2
Issue Date: August 19, 2005
GENERAL DESCRIPTION
The Am29LV001B is a 1 Mbit, 3.0 Volt-only Flash
memory device organized as 131,072 bytes. The
Am29LV001B has a boot sector architecture.
erase operation. During erase, the device automatically
times the erase pulse widths and verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by reading the DQ7 (Data#
Polling) and DQ6 (toggle) status bits. After a program
or erase cycle has been completed, the device is ready
to read array data or accept another command.
The device is offered in 32-pin PLCC and 32-pin TSOP
packages. The byte-wide (x8) data appears on DQ7-DQ0.
All read, erase, and program operations are accomplished
using only a single power supply. The device can also be
programmed in standard EPROM programmers.
The sector erase architecture allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
The standard Am29LV001B offers access times of 45,
55, 70, and 90 ns, allowing high speed microprocessors
to operate without wait states. To eliminate bus contention,
the device has separate chip enable (CE#), write enable
(WE#) and output enable (OE#) controls.
Hardware data protection measures include a low VCC
detector that automatically inhibits write operations during
power transitions. The hardware sector protection feature
disables both program and erase operations in any com-
bination of the sectors of memory. This can be achieved
in-system or via programming equipment.
The device requires only a single power supply (2.7 V–3.6V)
for both read and write functions. Internally generated and
regulated voltages are provided for the program and
erase operations.
The Am29LV001B is entirely command set compatible
with the JEDEC single-power-supply Flash standard.
Commands are written to the command register using
standard microprocessor write timings. Register con-
tents serve as input to an internal state-machine that
controls the erase and programming circuitry. Write
cycles also internally latch addresses and data needed
for the programming and erase operations. Reading
data out of the device is similar to reading from other
Flash or EPROM devices.
The Erase Suspend feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved.
The hardware RESET# pin terminates any operation in
progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.
Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithm—an internal algorithm that automatically
times the program pulse widths and verifies proper cell
margin. The Unlock Bypass mode facilitates faster pro-
gramming times by requiring only two write cycles to
program data instead of four.
The device offers two power-saving features. When
addresses are stable for a specified amount of time, the
device enters the automatic sleep mode. The system can
also place the device into the standby mode. Power con-
sumption is greatly reduced in both these modes.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the highest
levels of quality, reliability and cost effectiveness. The
device electrically erases all bits within a sector simulta-
neously via Fowler-Nordheim tunneling. The data is
programmed using hot electron injection.
Device erasure occurs by executing the erase command
sequence. This initiates the Embedded Erase algorithm—
an internal algorithm that automatically preprograms the
array (if it is not already programmed) before executing the
4
Am29LV001B
August 19, 2005
Table of Contents
Product Selector Guide . . . . . . . . . . . . . . . . . . . . .6
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . .7
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . .8
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Ordering Information . . . . . . . . . . . . . . . . . . . . . . .9
Device Bus Operations . . . . . . . . . . . . . . . . . . . . .10
Am29LV001B Device Bus Operations ............................................10
Requirements for Reading Array Data ................................... 10
Writing Commands/Command Sequences ............................ 10
Program and Erase Operation Status .................................... 11
Standby Mode ........................................................................ 11
Automatic Sleep Mode ........................................................... 11
RESET#: Hardware Reset Pin ............................................... 11
Output Disable Mode .............................................................. 11
Am29LV001B Top Boot Sector Architecture ..................................12
Am29LV001B Bottom Boot Sector Architecture ..............................12
Autoselect Mode ..................................................................... 13
Am29LV001B Autoselect Codes .....................................................13
Sector Protection/Unprotection ............................................... 13
Temporary Sector Unprotect .................................................. 13
In-System Sector Protect/Unprotect Algorithms ..............................14
Temporary Sector Unprotect Operation ..........................................15
Hardware Data Protection ...................................................... 15
DQ6: Toggle Bit I .................................................................... 21
DQ2: Toggle Bit II ................................................................... 21
Reading Toggle Bits DQ6/DQ2 ............................................... 21
Toggle Bit Algorithm ....................................................................... 22
DQ5: Exceeded Timing Limits ................................................ 22
DQ3: Sector Erase Timer ....................................................... 22
Write Operation Status ................................................................... 23
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 24
Maximum Negative Overshoot Waveform ..................................... 24
Maximum Positive Overshoot Waveform ....................................... 24
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . 24
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 25
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Test Setup ...................................................................................... 27
Test Specifications ......................................................................... 27
Key to Switching Waveforms . . . . . . . . . . . . . . . 27
Input Waveforms and Measurement Levels ................................... 27
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 28
Read Operations .................................................................... 28
Read Operations Timings .............................................................. 28
Hardware Reset (RESET#) .................................................... 29
RESET# Timings ............................................................................ 29
Erase/Program Operations ..................................................... 30
Program Operation Timings ........................................................... 31
Chip/Sector Erase Operation Timings ............................................ 32
Data# Polling Timings (During Embedded Algorithms) .................. 33
Toggle Bit Timings (During Embedded Algorithms) ....................... 33
DQ2 vs. DQ6 .................................................................................. 34
Temporary Sector Unprotect .................................................. 34
Temporary Sector Unprotect Timing Diagram ............................... 34
In-System Sector Protect/Unprotect Timing Diagram .................... 35
Alternate CE# Controlled Erase/Program Operations ............ 36
Alternate CE# Controlled Write Operation Timings ........................ 37
Erase and Programming Performance . . . . . . . 37
Latchup Characteristics . . . . . . . . . . . . . . . . . . . 38
TSOP Pin Capacitance . . . . . . . . . . . . . . . . . . . . 38
PLCC Pin Capacitance . . . . . . . . . . . . . . . . . . . . 38
Data Retention . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 39
PL 032—32-Pin Plastic Leaded Chip Carrier ......................... 39
TS 032—32-Pin Standard Thin Small Outline Package ......... 40
TSR032—32-Pin Reverse Thin Small Outline Package......... 41
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 42
Low V Write Inhibit.............................................................. 15
CC
Write Pulse “Glitch” Protection ............................................... 15
Logical Inhibit .......................................................................... 15
Power-Up Write Inhibit ............................................................ 15
Command Definitions . . . . . . . . . . . . . . . . . . . . . .15
Reading Array Data ................................................................ 15
Reset Command ..................................................................... 15
Autoselect Command Sequence ............................................ 16
Byte Program Command Sequence ....................................... 16
Unlock Bypass Command Sequence ..................................... 16
Program Operation ..........................................................................17
Chip Erase Command Sequence ........................................... 17
Sector Erase Command Sequence ........................................ 17
Erase Suspend/Erase Resume Commands ........................... 18
Erase Operation ..............................................................................18
Command Definitions ............................................................. 19
Am29LV001B Command Definitions ..............................................19
Write Operation Status . . . . . . . . . . . . . . . . . . . . 20
DQ7: Data# Polling ................................................................. 20
Data# Polling Algorithm ...................................................................20
August 19, 2005
Am29LV001B
5
PRODUCT SELECTOR GUIDE
Family Part Number
Am29LV001B
Regulated Voltage Range: V =3.0–3.6 V
-45R
CC
Speed Options
Full Voltage Range: V = 2.7–3.6 V
-55
-70
70
70
30
-90
90
90
35
CC
Max access time, ns (t
)
45
45
25
55
55
30
ACC
Max CE# access time, ns (t
)
CE
Max OE# access time, ns (t
)
OE
Note:See “AC Characteristics” for full specifications.
BLOCK DIAGRAM
DQ0–DQ7
VCC
VSS
Sector Switches
Erase Voltage
Generator
Input/Output
Buffers
RESET#
State
Control
WE#
Command
Register
PGM Voltage
Generator
Data
Chip Enable
Output Enable
STB
CE#
OE#
Y-Decoder
Y-Gating
STB
V
Detec-
Timer
CC
Cell Matrix
X-Decoder
A0–
6
Am29LV001B
August 19, 2005
CONNECTION DIAGRAMS
A11
A9
A8
OE#
A10
CE#
1
2
3
32
31
30
A13
A14
NC
4
5
6
7
8
9
10
11
12
13
14
15
16
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
29
28
27
26
25
24
23
22
21
20
19
18
17
WE#
VCC
RESET#
A16
A15
A12
A7
32-Pin Standard TSOP
A6
A5
A4
A1
A2
A3
1
2
3
A11
A9
A8
OE#
A10
CE#
32
31
30
4
5
6
7
8
9
10
11
12
13
14
15
16
A13
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
29
28
27
26
25
24
23
22
21
20
19
18
17
A14
NC
WE#
VCC
32-Pin Reverse TSOP
RESET#
A16
A15
A12
A7
A6
A5
A4
A1
A2
A3
4
3 2 1 32 31 30
A7
A6
5
6
A14
A13
29
28
A5
A4
7
A8
27
26
25
24
23
22
21
8
A9
PLCC
A3
9
A11
OE#
A10
CE#
DQ7
A2
10
11
12
13
A1
A0
DQ0
16 17
19 20
18
15
14
August 19, 2005
Am29LV001B
7
Logic Symbol
17
PIN CONFIGURATION
A0–A16=17 addresses
DQ0–DQ7=8 data inputs/outputs
CE# = Chip enable
A0–
8
DQ0–DQ7
OE# = Output enable
CE#
WE# = Write enable
OE#
RESET#=Hardware reset pin, active low
WE#
V
= 3.0 volt-only single power supply
(see Product Selector Guide for speed
options and voltage supply tolerances)
CC
RESET#
V
= Device ground
SS
NC = Pin not connected internally
8
Am29LV001B
August 19, 2005
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combi-
nation) is formed by a combination of the elements below.
Am29LV001B
T
-45R
E
C
TEMPERATURE RANGE
C= Commercial (0°C to +70°C)
I = Industrial (–40×C to +85×C)
E =Extended (–55×C to +125×C)
D= Commercial (0°C to +70°C) for Pb-free Package
F= Industrial (–40×C to +85×C) for Pb-free Package
K= Extended (–55×C to +125×C) for Pb-free Package
PACKAGE TYPE
E= 32-Pin Thin Small Outline Package (TSOP)
Standard Pinout (TS 032)
F= 32-Pin Thin Small Outline Package (TSOP)
Reverse Pinout (TSR032)
J = 32-Pin Rectangular Plastic Leaded Chip
Carrier (PL 032)
SPEED OPTION
See Product Selector Guide and Valid Combinations
BOOT CODE SECTOR ARCHITECTURE
T= Top Sector
B= Bottom Sector
DEVICE NUMBER/DESCRIPTION
Am29LV001B
1 Megabit (128 K x 8-Bit) CMOS Flash Memory
3.0 Volt-only Read, Program and Erase
Valid Combinations
EC, EI, EF,
FC, FI,
JC, JI, JD, JF
AM29LV001BT-45R,
AM29LV001BB-45R,
AM29LV001BT-55,
AM29LV001BB-55,
EC, EI, EE, ED, EF, EK,
FC, FI, FE,
JC, JI, JE, JD, JF, JK
AM29LV001BT-70,
AM29LV001BB-70,
AM29LV001BT-90,
AM29LV001BB-90,
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and to check on newly released combinations.
August 19, 2005
Am29LV001B
9
DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register
itself does not occupy any addressable memory loca-
tion. The register is composed of latches that store the
commands, along with the address and data informa-
tion needed to execute the command. The contents of
the register serve as inputs to the internal state
machine. The state machine outputs dictate the func-
tion of the device. Table 1 lists the device bus
operations, the inputs and control levels they require,
and the resulting output. The following subsections
describe each of these operations in further detail.
Table 1. Am29LV001B Device Bus Operations
Operation
CE#
L
OE# WE#
RESET#
Addresses (Note 1)
DQ0–DQ7
Read
L
H
X
H
X
H
L
H
H
A
A
D
OUT
IN
IN
Write
L
D
IN
Standby
V
± 0.3 V
X
H
X
V
± 0.3 V
CC
X
High-Z
High-Z
High-Z
CC
Output Disable
Reset
L
H
L
X
X
X
Sector Address, A6 =
L, A1 = H, A0 = L
Sector Protect (Note 2)
L
L
H
H
X
L
L
V
D , D
IN
ID
ID
ID
OUT
OUT
Sector Address, A6 =
H, A1 = H, A0 = L
Sector Unprotect (Note 2)
V
V
D , D
IN
Temporary Sector
Unprotect
X
X
A
D
IN
IN
Legend:
L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 0.5 V, X = Don’t Care, A = Address In, DIN = Data In,
IN
DOUT = Data Out
Notes:
1. Addresses are A16–A0.
2. The in-system method of sector protection/unprotection is available. Sector protection/unprotection can be im-
plemented by using programming equipment. See ““Sector Protection/Unprotection” on page 13” .
table for timing specifications and to Figure 13, on page
Requirements for Reading Array Data
To read array data from the outputs, the system must
30 for the timing diagram. I
in the DC Characteris-
CC1
tics table represents the active current specification for
reading array data.
drive the CE# and OE# pins to V . CE# is the power
IL
control and selects the device. OE# is the output
control and gates array data to the output pins. WE#
Writing Commands/Command Sequences
should remain at V .
IH
To write a command or command sequence (which
includes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to VIL, and OE# to VIH.
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
content occurs during the power transition. No
command is necessary in this mode to obtain array
data. Standard microprocessor read cycles that assert
valid addresses on the device address inputs produce
valid data on the device data outputs. The device
remains enabled for read access until the command
register contents are altered.
The device features an Unlock Bypass mode to facili-
tate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are
required to program a byte, instead of four. The “Byte
Program Command Sequence” on page 16 section
contains details on programming data to the device
using both standard and Unlock Bypass command
sequences.
See “Reading Array Data” on page 16 for more infor-
mation. Refer to the AC “Read Operations” on page 30
10
Am29LV001B
August 19, 2005
An erase operation can erase one sector, multiple sec-
tors, or the entire device. Table 2 on page 12 indicate
the address space that each sector occupies. A “sector
address” consists of the address bits required to
uniquely select a sector. The “Command Definitions”
on page 16 section contains details on erasing a sector
or the entire chip, or suspending/resuming the erase
operation.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
ICC3 in the DC Characteristics table represents the
standby current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device
energy consumption. The device automatically enables
After the system writes the autoselect command
sequence, the device enters the autoselect mode. The
system can then read autoselect codes from the
internal register (which is separate from the memory
array) on DQ7–DQ0. Standard read cycle timings apply
in this mode. Refer to “Autoselect Mode” on page 12
and “Autoselect Command Sequence” on page 16 for
more information.
this mode when addresses remain stable for t
+ 30
ACC
ns. The automatic sleep mode is independent of the
CE#, WE#, and OE# control signals. Standard address
access timings provide new data when addresses are
changed. While in sleep mode, output data is latched
and always available to the system. I
in the DC
CC5
Characteristics table represents the automatic sleep
mode current specification.
I
in the DC Characteristics table represents the
CC2
active current specification for the write mode. The “AC
Characteristics” on page 30 section contains timing
specification tables and timing diagrams for write
operations.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of reset-
ting the device to reading array data. When the
RESET# pin is driven low for at least a period of t , the
RP
Program and Erase Operation Status
device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the internal state
machine to reading array data. The operation that was
interrupted should be reinitiated once the device is
ready to accept another command sequence, to
ensure data integrity.
During an erase or program operation, the system may
check the status of the operation by reading the status
bits on DQ7–DQ0. Standard read cycle timings and I
CC
read specifications apply. Refer to “Write Operation
Status” on page 22 for more information, and to “AC
Characteristics” on page 30 for timing diagrams.
Standby Mode
Current is reduced for the duration of the RESET#
When the system is not reading or writing to the device,
it can place the device in the standby mode. In this
mode, current consumption is greatly reduced, and the
outputs are placed in the high impedance state, inde-
pendent of the OE# input.
pulse. When RESET# is held at V
0.3 V, the device
). If RESET# is held
SS
draws CMOS standby current (I
CC4
at V but not within V
0.3 V, the standby current is
IL
SS
greater.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.The system may use the
RESET# pin to force the device into the standby mode.
Refer to “Standby Mode” on page 11 for more
information.
The device enters the CMOS standby mode when the
CE# and RESET# pins are both held at VCC 0.3 V.
(Note that this is a more restricted voltage range than
V .) If CE# and RESET# are held at V , but not within
IH
IH
VCC 0.3 V, the device will be in the standby mode, but
the standby current is greater. The device requires
standard access time (tCE) for read access when the
device is in either of these standby modes, before it is
ready to read data.
Refer to the AC Characteristics tables for RESET#
parameters and to Figure 14, on page 31 for the timing
diagram.
The device also enters the standby mode when the
RESET# pin is driven low. Refer to the next section,
RESET#: Hardware Reset Pin.
Output Disable Mode
When the OE# input is at VIH, output from the device is
disabled. The output pins are placed in the high imped-
ance state.
August 19, 2005
Am29LV001B
11
Table 2. Am29LV001B Top Boot Sector Architecture
Sector Size
Address Range
(in hexadecimal)
Sector
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
A16
A15
A14
A13
A12
(Kbytes)
16 Kbytes
16 Kbytes
16 Kbytes
16 Kbytes
16 Kbytes
16 Kbytes
16 Kbytes
4 Kbytes
4 Kbytes
8 Kbytes
0
0
0
X
X
00000h–03FFFh
04000h–07FFFh
08000h–0BFFFh
0C000h–0FFFFh
10000h–13FFFh
14000h–17FFFh
18000h–1BFFFh
1C000h–1CFFFh
1D000h–1DFFFh
1E000h–1FFFFh
0
0
1
X
X
0
1
0
X
X
0
1
1
X
X
1
0
0
X
X
1
0
1
X
X
1
1
0
X
X
1
1
1
0
0
1
1
1
0
1
1
1
1
1
X
Table 3. Am29LV001B Bottom Boot Sector Architecture
Sector Size
Address Range (in
hexadecimal)
Sector
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
A16
A15
A14
A13
A12
(Kbytes)
8 Kbytes
4 Kbytes
4 Kbytes
16 Kbytes
16 Kbytes
16 Kbytes
16 Kbytes
16 Kbytes
16 Kbytes
16 Kbytes
0
0
0
0
X
00000h–01FFFh
02000h–02FFFh
03000h–03FFFh
04000h–07FFFh
08000h–0BFFFh
0C000h–0FFFFh
10000h–13FFFh
14000h–17FFFh
18000h–1BFFFh
1C000h–1FFFFh
0
0
0
1
0
0
0
0
1
1
0
0
1
X
X
0
1
0
X
X
0
1
1
X
X
1
0
0
X
X
1
0
1
X
X
1
1
0
X
X
1
1
1
X
X
the sector address must appear on the appropriate
highest order address bits (see Table 2 on page 12).
Table 4 shows the remaining address bits that are don’t
care. When all necessary bits are set as required, the
programming equipment may then read the corre-
sponding identifier code on DQ7-DQ0.
Autoselect Mode
The autoselect mode provides manufacturer and
device identification, and sector protection verification,
through identifier codes output on DQ7–DQ0. This
mode is primarily intended for programming equipment
to automatically match a device to be programmed with
its corresponding programming algorithm. However,
the autoselect codes can also be accessed in-system
through the command register.
To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in Table 5 on page 20.
This method does not require V . See “Command Def-
initions” on page 16 for details on using the autoselect
mode.
ID
When using programming equipment, the autoselect
mode requires V (11.5 V to 12.5 V) on address pin
ID
A9. Address pins A6, A1, and A0 must be as shown in
Table 4. In addition, when verifying sector protection,
12
Am29LV001B
August 19, 2005
Table 4. Am29LV001B Autoselect Codes
A16 A11
to to
CE# OE# WE# A12 A10 A9
A8
to
A7
A5
to
A2
DQ7
to
DQ0
Description
A6
L
A1
L
A0
L
Manufacturer ID: AMD
L
L
L
L
H
H
X
X
X
X
V
V
X
X
X
X
01h
ID
ID
Device ID: Am29LV001BT
(Top Boot Block)
L
L
L
L
H
H
EDh
Device ID: Am29LV001BB
(Bottom Boot Block)
L
L
L
L
H
H
X
X
X
V
V
X
X
X
X
6Dh
ID
ID
01h
(protected)
Sector Protection
Verification
SA
L
H
L
00h
(unprotected)
L = Logic Low = V , H = Logic High = V , SA = Sector Address, X = Don’t care.
IL
IH
details; contact an AMD representative to request a
copy.
Sector Protection/Unprotection
The device is shipped with all sectors unprotected.
AMD offers the option of programming and protecting
sectors at its factory prior to shipping the device
through AMD’s ExpressFlash™ Service. Contact an
AMD representative for details.
The hardware sector protection feature disables both
program and erase operations in any sector. The hard-
ware sector unprotection feature re-enables both
program and erase operations in previously protected
sectors. Sector protection/unprotection can be imple-
mented via two methods.
It is possible to determine whether a sector is protected
or unprotected. See “Autoselect Mode” on page 12” for
details.
The primary method requires V on the RESET# pin
ID
only, and can be implemented either in-system or via
programming equipment. Figure 1, on page 14 shows
the algorithms and Figure 21, on page 37 shows the
timing diagram. This method uses standard micropro-
cessor bus cycle timing. For sector unprotect, all
unprotected sectors must first be protected prior to the
first sector unprotect write cycle.
Temporary Sector Unprotect
This feature allows temporary unprotection of previ-
ously protected sectors to change data in-system. The
Sector Unprotect mode is activated by setting the
RESET# pin to V . During this mode, formerly pro-
ID
tected sectors can be programmed or erased by
selecting the sector addresses. Once V is removed
ID
The alternate method intended only for programming
from the RESET# pin, all the previously protected
sectors are protected again. Figure 2, on page 15
shows the algorithm, and Figure 20, on page 36 shows
the timing diagrams, for this feature.
equipment requires V on address pin A9, OE#, and
ID
RESET#. This method is compatible with programmer
routines written for earlier 3.0 volt-only AMD flash
devices. Publication number 22134 contains further
August 19, 2005
Am29LV001B
13
START
START
Protect all sectors:
The indicated portion
of the sector protect
algorithm must be
performed for all
PLSCNT = 1
PLSCNT = 1
RESET# = VID
RESET# = VID
unprotected sectors
prior to issuing the
first sector
Wait 1 μs
Wait 1 μs
unprotect address
No
First Write
Cycle = 60h?
No
First Write
Cycle = 60h?
Temporary Sector
Unprotect Mode
Temporary Sector
Unprotect Mode
Yes
Yes
Set up sector
address
No
All sectors
protected?
Sector Protect:
Write 60h to sector
address with
A6 = 0, A1 = 1,
A0 = 0
Yes
Set up first sector
address
Sector Unprotect:
Wait 150 µs
Write 60h to sector
address with
A6 = 1, A1 = 1,
A0 = 0
Verify Sector
Protect: Write 40h
to sector address
with A6 = 0,
Reset
PLSCNT = 1
Increment
PLSCNT
Wait 15 ms
A1 = 1, A0 = 0
Verify Sector
Unprotect: Write
40h to sector
address with
A6 = 1, A1 = 1,
A0 = 0
Read from
sector address
with A6 = 0,
A1 = 1, A0 = 0
Increment
PLSCNT
No
No
PLSCNT
= 25?
Read from
sector address
with A6 = 1,
Data = 01h?
Yes
A1 = 1, A0 = 0
No
Yes
Set up
next sector
address
Yes
No
PLSCNT
= 1000?
Protect another
sector?
Data = 00h?
Yes
Device failed
No
Yes
Remove VID
from RESET#
No
Last sector
verified?
Device failed
Write reset
command
Yes
Remove VID
Sector Unprotect
Algorithm
from RESET#
Sector Protect
Algorithm
Sector Protect
complete
Write reset
command
Sector Unprotect
complete
Figure 1. In-System Sector Protect/Unprotect Algorithms
14
Am29LV001B
August 19, 2005
against inadvertent writes (refer to Table 5 on page 20
for command definitions). In addition, the following
hardware data protection measures prevent accidental
erasure or programming, which might otherwise be
caused by spurious system level signals during VCC
power-up and power-down transitions, or from system
noise.
START
RESET# = VID
(Note 1)
Low V Write Inhibit
CC
Perform Erase or
When VCC is less than VLKO, the device does not
accept any write cycles. This protects data during VCC
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until
VCC is greater than VLKO. The system must provide
the proper signals to the control pins to prevent unin-
tentional writes when VCC is greater than VLKO.
Program Operations
RESET# = V
IH
Temporary Sector
Unprotect Completed
(Note 2)
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
Notes:
Logical Inhibit
1. All protected sectors unprotected.
Write cycles are inhibited by holding any one of OE# =
VIL, CE# = VIH or WE# = VIH. To initiate a write cycle,
CE# and WE# must be a logical zero while OE# is a
logical one.
2. All previously protected sectors are protected once
again.
Figure 2. Temporary Sector Unprotect Operation
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power up,
the device does not accept commands on the rising
edge of WE#. The internal state machine is automati-
cally reset to reading array data on power-up.
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
August 19, 2005
Am29LV001B
15
COMMAND DEFINITIONS
Writing specific address and data commands or
sequences into the command register initiates device
operations. Table 5 on page 20 defines the valid reg-
ister command sequences. Note that writing incorrect
address and data values or writing them in the
improper sequence may place the device in an
unknown state. A reset command is required to return
the device to reading array data.
The reset command may be written between the
sequence cycles in a program command sequence
before programming begins. This resets the device to
reading array data (also applies to programming in
Erase Suspend mode). Once programming begins,
however, the device ignores reset commands until the
operation is complete.
The reset command may be written between the
sequence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command must
be written to return to reading array data (also applies
to autoselect during Erase Suspend).
All addresses are latched on the falling edge of WE# or
CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in “AC
Characteristics” on page 30.
If DQ5 goes high during a program or erase operation,
writing the reset command returns the device to
reading array data (also applies during Erase
Suspend).
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array
data after completing an Embedded Program or
Embedded Erase algorithm.
See “AC Characteristics” on page 30 for parameters,
and Figure 14, on page 31 for the timing diagram.
Autoselect Command Sequence
After the device accepts an Erase Suspend command,
the device enters the Erase Suspend mode. The
system can read array data using the standard read
timings, except that if it reads at an address within
erase-suspended sectors, the device outputs status
data. After completing a programming operation in the
Erase Suspend mode, the system may once again
read array data with the same exception. See “Erase
Suspend/Erase Resume Commands” on page 18 for
more information on this mode.
The autoselect command sequence allows the host
system to access the manufacturer and devices codes,
and determine whether or not a sector is protected.
Table 5 on page 20 shows the address and data
requirements. This method is an alternative to that
shown in Table 4 on page 13, which is intended for
PROM programmers and requires VID on address bit
A9.
The autoselect command sequence is initiated by
writing two unlock cycles, followed by the autoselect
command. The device then enters the autoselect
mode, and the system may read at any address any
number of times, without initiating another command
sequence. A read cycle at address XX00h retrieves the
manufacturer code. A read cycle at address XX01h
returns the device code. A read cycle containing a
sector address (SA) and the address 02h returns 01h if
that sector is protected, or 00h if it is unprotected. Refer
to Table 2 on page 12 for valid sector addresses.
The system must issue the reset command to re-
enable the device for reading array data if DQ5 goes
high, or while in the autoselect mode. See the “Reset
Command” on page 16 section.
See also “Requirements for Reading Array Data” on
page 10 for more information. The Read Operations
table provides the read parameters, and Figure 13, on
page 30 shows the timing diagram.
The system must write the reset command to exit the
autoselect mode and return to reading array data.
Reset Command
Writing the reset command to the device resets the
device to reading array data. Address bits are don’t
care for this command.
Byte Program Command Sequence
The device programs one byte of data for each program
operation. The command sequence requires four bus
cycles, and is initiated by writing two unlock write
cycles, followed by the program set-up command. The
program address and data are written next, which in
turn initiate the Embedded Program algorithm. The
system is not required to provide further controls or tim-
ings. The device automatically provides internally
generated program pulses and verify the programmed
cell margin. Table 5 on page 20 shows the address and
The reset command may be written between the
sequence cycles in an erase command sequence
before erasing begins. This resets the device to reading
array data. Once erasure begins, however, the device
ignores reset commands until the operation is
complete.
16
Am29LV001B
August 19, 2005
data requirements for the byte program command
sequence.
When the Embedded Program algorithm is complete,
the device then returns to reading array data and
addresses are no longer latched. The system can
determine the status of the program operation by using
DQ7 or DQ6. See “Write Operation Status” on page 22
for information on these status bits.
START
Write Program
Command Sequence
Any commands written to the device during the
Embedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the program-
ming operation. The Byte Program command
sequence should be reinitiated once the device has
reset to reading array data, to ensure data integrity.
Data Poll
from System
Embedded
Program
algorithm
in progress
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed from a
“0” back to a “1”. Attempting to do so may halt the oper-
ation and set DQ5 to “1,” or cause the Data# Polling
algorithm to indicate the operation was successful.
However, a succeeding read shows that the data is still
“0”. Only erase operations can convert a “0” to a “1”.
Verify Data?
Yes
No
No
Unlock Bypass Command Sequence
Increment Address
Last Address?
Yes
The unlock bypass feature allows the system to
program bytes to the device faster than using the stan-
dard program command sequence. The unlock bypass
command sequence is initiated by first writing two
unlock cycles. This is followed by a third write cycle
containing the unlock bypass command, 20h. The
device then enters the unlock bypass mode. A two-
cycle unlock bypass program command sequence is all
that is required to program in this mode. The first cycle
in this sequence contains the unlock bypass program
command, A0h; the second cycle contains the program
address and data. Additional data is programmed in
the same manner. This mode dispenses with the initial
two unlock cycles required in the standard program
command sequence, resulting in faster total program-
ming time. Table 5 on page 20 shows the requirements
for the command sequence.
Programming
Completed
Note:
See Table 5 on page 20 for program command
sequence.
Figure 3. Program Operation
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algo-
rithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
trols or timings during these operations. Table 5 on
page 20 shows the address and data requirements for
the chip erase command sequence.
During the unlock bypass mode, only the Unlock
Bypass Program and Unlock Bypass Reset commands
are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset
command sequence. The first cycle must contain the
data 90h; the second cycle the data 00h. Addresses
are don’t cares for both cycles. The device then returns
to reading array data.
Figure 3 illustrates the algorithm for the program oper-
ation. See the table “Erase/Program Operations” on
page 32 for parameters, and Figure 15, on page 33 for
timing diagrams.
Any commands written to the chip during the
Embedded Erase algorithm are ignored. Note that a
hardware reset during the chip erase operation imme-
August 19, 2005
Am29LV001B
17
diately terminates the operation. The Chip Erase
command sequence should be reinitiated once the
device has returned to reading array data, to ensure
data integrity.
Once the sector erase operation has begun, only the
Erase Suspend command is valid. All other commands
are ignored. Note that a hardware reset during the
sector erase operation immediately terminates the
operation. The Sector Erase command sequence
should be reinitiated once the device has returned to
reading array data, to ensure data integrity.
The system can determine the status of the erase oper-
ation by using DQ7, DQ6, or DQ2. See “Write
Operation Status” on page 22 for information on these
status bits. When the Embedded Erase algorithm is
complete, the device returns to reading array data and
addresses are no longer latched.
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses are
no longer latched. The system can determine the
status of the erase operation by using DQ7, DQ6, or
DQ2. (Refer to “Write Operation Status” on page 22 for
information on these status bits.)
Figure 4, on page 19 illustrates the algorithm for the
erase operation. See the tables “Erase/Program Oper-
ations” on page 32 for parameters, and Figure 16, on
page 34 for timing diagrams.
Figure 4 illustrates the algorithm for the erase opera-
tion. Refer to the tables “Erase/Program Operations”
on page 32 for parameters, and Figure 16, on page 34
for timing diagrams.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two
additional unlock write cycles are then followed by the
address of the sector to be erased, and the sector
erase command. Table 5 on page 20 shows the
address and data requirements for the sector erase
command sequence.
Erase Suspend/Erase Resume Commands
The Erase Suspend command allows the system to
interrupt a sector erase operation and then read data
from, or program data to, any sector not selected for
erasure. This command is valid only during the sector
erase operation, including the 50 µs time-out period
during the sector erase command sequence. The
Erase Suspend command is ignored if written during
the chip erase operation or Embedded Program algo-
rithm. Writing the Erase Suspend command during the
Sector Erase time-out immediately terminates the
time-out period and suspends the erase operation.
Addresses are “don’t-cares” when writing the Erase
Suspend command.
The device does not require the system to preprogram
the memory prior to erase. The Embedded Erase algo-
rithm automatically programs and verifies the sector for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or
timings during these operations.
After the command sequence is written, a sector erase
time-out of 50 µs begins. During the time-out period,
additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of
sectors may be from one sector to all sectors. The time
between these additional cycles must be less than 50
µs, otherwise the last address and command might not
be accepted, and erasure may begin. It is recom-
mended that processor interrupts be disabled during
this time to ensure all commands are accepted. The
interrupts can be re-enabled after the last Sector Erase
command is written. If the time between additional
sector erase commands can be assumed to be less
than 50 µs, the system need not monitor DQ3. Any
command other than Sector Erase or Erase Suspend
during the time-out period resets the device to reading
array data. The system must rewrite the command
sequence and any additional sector addresses and
commands.
When the Erase Suspend command is written during a
sector erase operation, the device requires a maximum
of 20 µs to suspend the erase operation. However,
when the Erase Suspend command is written during
the sector erase time-out, the device immediately ter-
minates the time-out period and suspends the erase
operation.
After the erase operation has been suspended, the
system can read array data from or program data to
any sector not selected for erasure. (The device “erase
suspends” all sectors selected for erasure.) Normal
read and write timings and command definitions apply.
Reading at any address within erase-suspended
sectors produces status data on DQ7–DQ0. The
system can use DQ7, or DQ6 and DQ2 together, to
determine if a sector is actively erasing or is erase-sus-
pended. See “Write Operation Status” on page 22 for
information on these status bits.
The system can monitor DQ3 to determine if the sector
erase timer has timed out. (See “DQ3: Sector Erase
Timer” on page 24.) The time-out begins from the rising
edge of the final WE# pulse in the command sequence.
After an erase-suspended program operation is com-
plete, the system can once again read array data within
non-suspended sectors. The system can determine
the status of the program operation using the DQ7 or
DQ6 status bits, just as in the standard program oper-
18
Am29LV001B
August 19, 2005
ation. See “Write Operation Status” on page 22 for
more information.
The system may also write the autoselect command
sequence when the device is in the Erase Suspend
mode. The device allows reading autoselect codes
even at addresses within erasing sectors, since the
codes are not stored in the memory array. When the
device exits the autoselect mode, the device reverts to
the Erase Suspend mode, and is ready for another
valid operation. See “Autoselect Command Sequence”
on page 16 for more information.
START
Write Erase
Command Sequence
The system must write the Erase Resume command
(address bits are “don’t care”) to exit the erase suspend
mode and continue the sector erase operation. Further
writes of the Resume command are ignored. Another
Erase Suspend command can be written after the
device has resumed erasing.
Data Poll
from System
Embedded
Erase
algorithm
in progress
No
Data = FFh?
Yes
Erasure Completed
Notes:
1. See Table 5 on page 20 for erase command
sequence.
2. See “DQ3: Sector Erase Timer” on page 24 for
more information.
Figure 4. Erase Operation
August 19, 2005
Am29LV001B 1
19
Command Definitions
Table 5. Am29LV001B Command Definitions
Bus Cycles (Notes 2–4)
Command Sequence
(Note 1)
First
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
RA RD
XXX F0
Second
Third
Fourth
Fifth
Sixth
Read (Note 5)
Reset (Note 6)
1
1
4
Manufacturer ID
555
AA
2AA
55
555
90
X00
01
Device ID, Top
Boot Block
ED
4
555
AA
2AA
55
555
90
X01
Device ID, Bottom
Boot Block
6D
00
01
Sector Protect
Verify (Note 8)
SA
X02
4
555
AA
2AA
55
555
90
Byte Program
4
3
555
555
AA
AA
2AA
2AA
55
55
555
555
A0
20
PA
PD
Unlock Bypass
Unlock Bypass
Program
2
XXX A0
PA
PD
(Note 9)
Unlock Bypass Reset
(Note 10)
2
XXX
90
XXX
00
Chip Erase
6
6
555
555
AA
AA
2AA
2AA
55
55
555
555
80
80
555
555
AA 2AA
AA 2AA
55
55
555
SA
10
30
Sector Erase
Erase Suspend (Note
11)
1
1
XXX B0
XXX 30
Erase Resume (Note
12)
Legend:
X = Don’t care
PD = Data to be programmed at location PA. Data is
latched on the rising edge of WE# or CE# pulse.
RA = Address of the memory location to be read.
SA = Address of the sector to be erased or verified.
Address bits A16–A12 uniquely select any sector.
RD = Data read from location RA during read
operation.
PA = Address of the memory location to be
programmed. Addresses are latched on the falling
edge of the WE# or CE# pulse.
Notes:
1. See Table 1 on page 10 for descriptions of bus
operations.
6. The Reset command is required to return to the
read mode when the device is in the autoselect
mode or if DQ5 goes high.
2. All values are in hexadecimal.
7. The fourth cycle of the autoselect command
sequence is a read cycle.
3. Except when reading array or autoselect data, all
bus cycles are write operations.
8. The data is 00h for an unprotected sector and 01h
for a protected sector. The complete bus address in
the fourth cycle is composed of the sector address
(A16–A12),
4. Address bits A16–A11 are don’t care for unlock and
command cycles, unless SA or PA required.
5. No unlock or command cycles required when
device is in read mode.
A1 = 1, and A0 = 0.
20
Am29LV001B
August 19, 2005
9. The Unlock Bypass command is required prior to
the Unlock Bypass Program command.
12.The Erase Resume command is valid only during
the Erase Suspend mode.
10.The Unlock Bypass Reset command is required to
return to reading array data when the device is in
the Unlock Bypass mode.
13.See “Erase and Programming Performance” on
page 40 for more information.
11.The system may read and program functions in
non-erasing sectors, or enter the autoselect mode,
when in the Erase Suspend mode. The Erase
Suspend command is valid only during a sector
erase operation.
August 19, 2005
Am29LV001B
21
WRITE OPERATION STATUS
The device provides several bits to determine the
status of a write operation: DQ2, DQ3, DQ5, DQ6, and
DQ7. Table 6 on page 25 and the following subsections
describe the functions of these bits. DQ7, and DQ6
each offer a method for determining whether a program
or erase operation is complete or in progress. These
three bits are discussed first.
START
DQ7: Data# Polling
Read DQ7–DQ0
Addr = VA
The Data# Polling bit, DQ7, indicates to the host
system whether an Embedded Algorithm is in progress
or completed, or whether the device is in Erase Sus-
pend. Data# Polling is valid after the rising edge of the
final WE# pulse in the program or erase command
sequence.
Yes
DQ7 = Data?
During the Embedded Program algorithm, the device
outputs on DQ7 the complement of the datum pro-
grammed to DQ7. This DQ7 status also applies to
programming during Erase Suspend. When the
Embedded Program algorithm is complete, the device
outputs the datum programmed to DQ7. The system
must provide the program address to read valid status
information on DQ7. If a program address falls within a
protected sector, Data# Polling on DQ7 is active for
approximately 1 µs, then the device returns to reading
array data.
No
No
DQ5 = 1?
Yes
Read DQ7–DQ0
Addr = VA
During the Embedded Erase algorithm, Data# Polling
produces a “0” on DQ7. When the Embedded Erase
algorithm is complete, or if the device enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7.
This is analogous to the complement/true datum output
described for the Embedded Program algorithm: the
erase function changes all the bits in a sector to “1”;
prior to this, the device outputs the “complement,” or
“0.” The system must provide an address within any of
the sectors selected for erasure to read valid status
information on DQ7.
Yes
DQ7 = Data?
No
PASS
FAIL
After an erase command sequence is written, if all
sectors selected for erasing are protected, Data#
Polling on DQ7 is active for approximately 100 µs, then
the device returns to reading array data. If not all
selected sectors are protected, the Embedded Erase
algorithm erases the unprotected sectors, and ignores
the selected sectors that are protected.
Notes:
1. VA = Valid address for programming. During a
sector erase operation, a valid address is an
address within any sector selected for erasure.
During chip erase, a valid address is any
non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = “1” be-
cause DQ7 may change simultaneously with DQ5.
When the system detects DQ7 has changed from the
complement to true data, it can read valid data at DQ7–
DQ0 on the following read cycles. This is because DQ7
may change asynchronously with DQ0–DQ6 while
Output Enable (OE#) is asserted low. Figure 17, on
page 35, Data# Polling Timings (During Embedded
Algorithms), illustrates this.
Figure 5. Data# Polling Algorithm
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or complete,
or whether the device has entered the Erase Suspend
mode. Toggle Bit I may be read at any address, and is
Table 6 on page 25 shows the outputs for Data# Polling
on DQ7. Figure 5 shows the Data# Polling algorithm.
22
Am29LV001B
August 19, 2005
valid after the rising edge of the final WE# pulse in the
command sequence (prior to the program or erase
operation), and during the sector erase time-out.
erasing, or is in Erase Suspend, but cannot distinguish
which sectors are selected for erasure. Thus, both
status bits are required for sector and mode informa-
tion. Refer to Table 6 on page 25 to compare outputs
for DQ2 and DQ6.
During an Embedded Program or Erase algorithm
operation, successive read cycles to any address
cause DQ6 to toggle (The system may use either OE#
or CE# to control the read cycles). When the operation
is complete, DQ6 stops toggling.
Figure 6, on page 24 shows the toggle bit algorithm in
flowchart form, and the section “Reading Toggle Bits
DQ6/DQ2” explains the algorithm. See also the DQ6:
Toggle Bit I subsection. Figure 18, on page 35 shows
the toggle bit timing diagram. Figure 19, on page 36
shows the differences between DQ2 and DQ6 in graph-
ical form.
After an erase command sequence is written, if all
sectors selected for erasing are protected, DQ6 toggles
for approximately 100 µs, then returns to reading array
data. If not all selected sectors are protected, the
Embedded Erase algorithm erases the unprotected
sectors, and ignores the selected sectors that are
protected.
Reading Toggle Bits DQ6/DQ2
Refer to Figure 6, on page 24 for the following discus-
sion. Whenever the system initially begins reading
toggle bit status, it must read DQ7–DQ0 at least twice
in a row to determine whether a toggle bit is toggling.
Typically, the system would note and store the value of
the toggle bit after the first read. After the second read,
the system would compare the new value of the toggle
bit with the first. If the toggle bit is not toggling, the
device has completed the program or erase operation.
The system can read array data on DQ7–DQ0 on the
following read cycle.
The system can use DQ6 and DQ2 together to deter-
mine whether a sector is actively erasing or is erase-
suspended. When the device is actively erasing (that is,
the Embedded Erase algorithm is in progress), DQ6
toggles. When the device enters the Erase Suspend
mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing
or erase-suspended. Alternatively, the system can use
DQ7 (see the subsection on DQ7: Data# Polling).
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the
system also should note whether the value of DQ5 is
high (see the section on “DQ5: Exceeded Timing
Limits” on page 24). If it is, the system should then
determine again whether the toggle bit is toggling,
since the toggle bit may have stopped toggling just as
DQ5 went high. If the toggle bit is no longer toggling,
the device has successfully completed the program or
erase operation. If it is still toggling, the device did not
completed the operation successfully, and the system
must write the reset command to return to reading
array data.
If a program address falls within a protected sector,
DQ6 toggles for approximately 1 µs after the program
command sequence is written, then returns to reading
array data.
DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded
Program algorithm is complete.
Table 6 on page 25 shows the outputs for Toggle Bit I
on DQ6. Figure 6, on page 24 shows the toggle bit
algorithm in flowchart form, and the section “Reading
Toggle Bits DQ6/DQ2” on page 23 explains the algo-
rithm. Figure 18, on page 35 shows the toggle bit timing
diagrams. Figure 19, on page 36 shows the differences
between DQ2 and DQ6 in graphical form. See also the
subsection on “DQ2: Toggle Bit II”, next.
The remaining scenario is that the system initially
determines that the toggle bit is toggling and DQ5 has
not gone high. The system may continue to monitor the
toggle bit and DQ5 through successive read cycles,
determining the status as described in the previous
paragraph. Alternatively, it may choose to perform
other system tasks. In this case, the system must start
at the beginning of the algorithm when it returns to
determine the status of the operation (top of Figure 6,
on page 24).
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indi-
cates whether a particular sector is actively erasing
(that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of the final WE# pulse in
the command sequence.
Table 6 on page 25 shows the outputs for Toggle Bit I
on DQ6. Figure 6, on page 24 shows the toggle bit
algorithm. Figure 18, on page 35 shows the toggle bit
timing diagrams. Figure 19, on page 36 shows the dif-
ferences between DQ2 and DQ6 in graphical form. See
also the subsection on “DQ2: Toggle Bit II” on page 23.
DQ2 toggles when the system reads at addresses
within those sectors that were selected for erasure.
(The system may use either OE# or CE# to control the
read cycles.) But DQ2 cannot distinguish whether the
sector is actively erasing or is erase-suspended. DQ6,
by comparison, indicates whether the device is actively
August 19, 2005
Am29LV001B
23
DQ5: Exceeded Timing Limits
START
DQ5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under
these conditions DQ5 produces a “1.” This is a failure
condition that indicates the program or erase cycle was
not successfully completed.
Read DQ7–DQ0
The DQ5 failure condition may appear if the system
tries to program a “1” to a location that is previously pro-
grammed to “0.” Only an erase operation can change a
“0” back to a “1.” Under this condition, the device halts
the operation, and when the operation has exceeded
the timing limits, DQ5 produces a “1.”
Read DQ7–DQ0
(Note 1)
No
Toggle Bit
= Toggle?
Under both these conditions, the system must issue the
reset command to return the device to reading array
data.
Yes
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not an
erase operation has begun. (The sector erase timer
does not apply to the chip erase command.) If addi-
tional sectors are selected for erasure, the entire time-
out also applies after each additional sector erase com-
mand. When the time-out is complete, DQ3 switches
from “0” to “1.” If the time between additional sector
erase commands from the system can be assumed to
be less than 50 µs, the system need not monitor DQ3.
See also “Sector Erase Command Sequence” on
page 18.
No
DQ5 = 1?
Yes
Read DQ7–DQ0
Twice
(Notes
1, 2)
Toggle Bit
= Toggle?
No
After the sector erase command sequence is written,
the system should read the status on DQ7 (Data#
Polling) or DQ6 (Toggle Bit I) to ensure the device has
accepted the command sequence, and then read DQ3.
If DQ3 is “1”, the internally controlled erase cycle has
begun; all further commands (other than Erase Sus-
pend) are ignored until the erase operation is complete.
If DQ3 is “0”, the device accepts additional sector erase
commands. To ensure the command has been
accepted, the system software should check the status
of DQ3 prior to and following each subsequent sector
erase command. If DQ3 is high on the second status
check, the last command might not have been
accepted. Table 6 on page 25 shows the outputs for
DQ3.
Yes
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Notes:
1. Read toggle bit twice to determine whether or not it
is toggling. See text.
2. Recheck toggle bit because it may stop toggling as
DQ5 changes to “1”. See text.
Figure 6. Toggle Bit Algorithm
24
Am29LV001B
August 19, 2005
Table 6. Write Operation Status
DQ7
DQ5
DQ2
Operation
(Note 2)
DQ7#
0
DQ6
(Note 1)
DQ3
N/A
1
(Note 2)
Embedded Program Algorithm
Embedded Erase Algorithm
Toggle
Toggle
0
0
No toggle
Toggle
Standard
Mode
Reading within Erase
Suspended Sector
1
No toggle
0
N/A
Toggle
Erase
Suspend Reading within Non-Erase
Data
Data
Data
0
Data
N/A
Data
N/A
Mode
Suspended Sector
Erase-Suspend-Program
DQ7#
Toggle
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum
timing limits. See “DQ5: Exceeded Timing Limits” for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for
further details.
August 19, 2005
Am29LV001B
25
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C
DC input voltage on pin A9 is +12.5 V which may
overshoot to 14.0 V for periods up to 20 ns.
Ambient Temperature
with Power Applied. . . . . . . . . . . . . . –65°C to +125°C
3. No more than one output may be shorted to ground
at a time. Duration of the short circuit should not be
greater than one second.
Voltage with Respect to Ground
All pins except A9, OE# and RESET#
(Note 1) . . . . . . . . . . . . . . . . . . . –0.5 V to V +0.5 V
4. Stresses above those listed under “Absolute Maxi-
mum Ratings” may cause permanent damage to
the device. This is a stress rating only; functional op-
eration of the device at these or any other conditions
above those indicated in the operational sections of
this data sheet is not implied. Exposure of the device
to absolute maximum rating conditions for extended pe-
riods may affect device reliability.
CC
V
(Note 1). . . . . . . . . . . . . . . . . . . .–0.5 V to +3.6 V
CC
A9, OE#, and RESET# (Note 2) . . .–0.5 V to +12.5 V
Output Short Circuit Current (Note 3) . . . . . . 200 mA
Notes:
1. Minimum DC voltage on input or I/O pins is –0.5 V.
During voltage transitions, input or I/O pins may
undershoot V to –2.0 V for periods of up to 20 ns.
SS
See Figure 7. Maximum DC voltage on input or I/O
20 ns
20 ns
pins is V +0.5 V. During voltage transitions, input
CC
+0.8 V
or I/O pins may overshoot to V +2.0 V for periods
CC
up to 20 ns. See Figure 8.
–0.5 V
–2.0
2. Minimum DC input voltage on pins A9, OE#, and
RESET# is –0.5 V. During voltage transitions, A9,
OE#, and RESET# may undershoot V to –2.0 V
for periods of up to 20 ns. See Figure 7. Maximum
SS
20 ns
Figure 7. Maximum Negative Overshoot Waveform
Operating Ranges
Commercial (C) Devices
Ambient Temperature (T ) . . . . . . . . . . . 0°C to +70°C
A
Industrial (I) Devices
Ambient Temperature (T ) . . . . . . . . . –40°C to +85°C
A
Extended (E) Devices
Ambient Temperature (T ) . . . . . . . . –55°C to +125°C
A
V
V
V
Supply Voltages
CC
CC
CC
for regulated voltage range. . . . . .+3.0 V to 3.6 V
for full voltage range . . . . . . . . . . .+2.7 V to 3.6 V
Operating ranges define those limits between which
the functionality of the device is guaranteed.
26
Am29LV001B
August 19, 2005
DC CHARACTERISTICS
CMOS Compatible
Parameter
Description
Test Conditions
= V to V
Min
Typ
Max
±1.0
35
Unit
µA
V
V
,
CC
IN
SS
I
Input Load Current
LI
= V
= V
= V
CC
CC max
CC max
CC max
I
A9 Input Load Current
RESET# Input Load Current
V
V
; A9 = 12.5 V
; RESET# =
µA
LIT
CC
CC
I
35
µA
LR
12.5 V
= V to V ,
CC
V
V
OUT
SS
I
Output Leakage Current
±1.0
µA
mA
mA
LO
= V
CC
CC max
5 MHz
1 MHz
7
2
12
4
V
Active Read Current
(Notes 1, 2)
CC
I
CE# = V , OE# = V
IL IH
CC1
CC2
V
Active Write Current
(Notes 2, 3, 5)
CC
I
CE# = V , OE# = V
15
30
IL
IH
V
2)
Standby Current (Note
CC
I
I
I
CE#, RESET# = V ± 0.3 V
0.2
0.2
0.2
5
5
µA
µA
µA
CC3
CC4
CC5
CC
V
Reset Current (Note 2) RESET# = V ± 0.3 V
SS
CC
Automatic Sleep Mode
(Notes 2, 4)
V
= V
0.3 V;
IH
CC
5
V = V ± 0.3 V
IL
SS
V
Input Low Voltage
Input High Voltage
–0.5
0.8
V
V
IL
V
V
0.7 x V
V
+ 0.3
IH
CC
CC
Voltage for Autoselect and
Temporary Sector Unprotect
V
= 3.3 V
11.5
12.5
0.45
V
ID
CC
V
Output Low Voltage
I
I
I
= 4.0 mA, V = V
CC min
V
V
OL
OL
OH
OH
CC
V
= –2.0 mA, V = V
0.85 V
OH1
OH2
CC
CC min
CC min
CC
Output High Voltage
V
= –100 µA, V = V
V
–0.4
CC
CC
Low V Lock-Out Voltage
(Note 5)
CC
V
2.3
2.5
V
LKO
Notes:
1. The I current listed is typically less than 2 mA/MHz, with OE# at V .
CC
IH
2. Maximum I specifications are tested with V = V .
CCmax
CC
CC
3. I active while Embedded Erase or Embedded Program is in progress.
CC
4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical
sleep mode current is 200 nA.
5. Not 100% tested.
August 19, 2005
Am29LV001B
27
DC CHARACTERISTICS (Continued)
Zero Power Flash
20
15
10
5
0
0
500
1000
1500
2000
2500
3000
3500
4000
Time in ns
Note: Addresses are switching at 1 MHz
Figure 9.
I
Current vs. Time (Showing Active and Automatic Sleep Currents)
CC1
10
8
3.6 V
2.7 V
6
4
2
0
1
2
3
4
5
Frequency in MHz
Note: T = 25 °C
Figure 10. Typical I
vs. Frequency
CC1
28
Am29LV001B
August 19, 2005
TEST CONDITIONS
Table 7. Test Specifications
-45R,
3.3
-70,
-90
Test Condition
-55
Unit
pF
2.7 kW
Output Load
1 TTL gate
Device
Under
Test
Output Load Capacitance,
C
30
100
L
CL
6.2 kW
(including jig capacitance)
Input Rise and Fall Times
Input Pulse Levels
5
ns
V
0.0–3.0
1.5
Input timing measurement
reference levels
V
V
Note: Diodes are IN3064 or equivalent
Figure 11. Test Setup
Output timing
measurement reference
levels
1.5
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Does Not Apply
Changing, State Unknown
Center Line is High Impedance State (High Z)
3.0 V
1.5 V
1.5 V
Input
Measurement Level
Output
0.0 V
Figure 12. Input Waveforms and Measurement Levels
August 19, 2005
Am29LV001B
29
AC CHARACTERISTICS
Read Operations
Parameter
Speed Option
JEDEC
Std Description
Test Setup
Min
-45R -55
-70
70
-90 Unit
t
t
Read Cycle Time (Note 1)
Address to Output Delay
45
45
55
55
90
90
ns
ns
AVAV
RC
CE# = V
IL
IL
t
t
Max
70
AVQV
ACC
OE# = V
t
t
Chip Enable to Output Delay
OE# = V
Max
Max
Max
Max
Min
45
25
10
10
55
30
15
15
70
30
16
16
90
35
16
16
ns
ns
ns
ns
ns
ELQV
GLQV
EHQZ
GHQZ
CE
IL
t
t
t
Output Enable to Output Delay
OE
t
t
Chip Enable to Output High Z (Note 1)
Output Enable to Output High Z (Note 1)
DF
DF
t
Read
0
Output Enable
Hold Time (Note 1)
t
OEH
Toggle and
Data# Polling
Min
Min
10
ns
ns
Output Hold Time From Addresses, CE#
or OE#, Whichever Occurs First (Note 1)
t
t
0
AXQX
OH
Notes:
1. Not 100% tested.
2. See Figure 11 and Table 7 for test specifications.
tRC
Addresses Stable
tACC
Addresses
CE#
tDF
tOE
OE#
tOEH
WE#
tCE
tOH
HIGH Z
HIGH Z
Output Valid
Outputs
RESET#
Figure 13. Read Operations Timings
30
Am29LV001B
August 19, 2005
AC CHARACTERISTICS
Hardware Reset (RESET#)
Parameter
JEDEC
Std Description
Test Setup
Max
All Speed Options
20
Unit
µs
t
t
RESET# Pin Low (During Embedded
Algorithms) to Read or Write (See Note)
READ
Y
RESET# Pin Low (NOT During
Embedded Algorithms) to Read or Write
(See Note)
READ
Y
Max
500
ns
t
RESET# Pulse Width
Min
Min
Min
500
50
ns
ns
µs
RP
RESET# High Time Before Read (See
Note)
t
RH
t
RESET# Low to Standby Mode
20
RPD
Note:
Not 100% tested.
CE#, OE#
tRH
RESET#
n/a Am29F002NB
tRP
tReady
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
RESET#
n/a Am29F002NB
tRP
Figure 14. RESET# Timings
August 19, 2005
Am29LV001B
31
AC CHARACTERISTICS
Erase/Program Operations
Parameter
Speed Options
JEDEC
Std
Description
-45R
45
-55
55
-70
70
-90
90
Unit
ns
t
t
Write Cycle Time (Note 1)
Address Setup Time
Address Hold Time
Data Setup Time
Min
Min
Min
Min
Min
Min
AVAV
WC
t
t
0
ns
AVWL
WLAX
DVWH
WHDX
AS
AH
DS
DH
t
t
35
20
45
20
45
35
45
45
ns
t
t
ns
t
t
Data Hold Time
0
0
ns
ns
t
Output Enable Setup Time (Note 1)
OES
Read Recovery Time Before Write
(OE# High to WE# Low)
t
t
Min
0
ns
GHWL
GHWL
t
t
CE# Setup Time
Min
Min
Min
Min
0
0
ns
ns
ns
ns
ELWL
WHEH
WLWH
WHWL
CS
CH
WP
t
t
CE# Hold Time
t
t
Write Pulse Width
Write Pulse Width High
25
30
35
35
t
t
30
9
WPH
t
t
WHWH
1
t
t
Programming Operation (Note 2)
Sector Erase Operation (Note 2)
Typ
µs
WHWH1
WHWH2
WHWH
2
Typ
Min
0.7
50
sec
µs
t
V
Setup Time (Note 1)
CC
VCS
Notes:
1. Not 100% tested.
2. See “Erase and Programming Performance” for more information.
32
Am29LV001B
August 19, 2005
AC CHARACTERISTICS
Program Command Sequence (last two cycles)
Read Status Data (last two cycles)
tAS
tWC
Addresses
555h
PA
PA
PA
tAH
CE#
OE#
tCH
tWHWH1
tWP
WE#
tWPH
tCS
tDS
tDH
PD
DOUT
A0h
Status
Data
VCC
tVCS
Notes:
1. PA = program address, PD = program data, D
is the true data at the program address.
OUT
Figure 15. Program Operation Timings
August 19, 2005
Am29LV001B
33
AC CHARACTERISTICS
Erase Command Sequence (last two cycles)
Read Status Data
VA
tAS
SA
tWC
VA
Addresses
CE#
2AAh
555h for chip erase
tAH
tCH
OE#
tWP
WE#
tWPH
tWHWH2
tCS
tDS
tDH
In
Data
VCC
Complete
55h
30h
Progress
10 for Chip Erase
tVCS
Note:
SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”).
Figure 16. Chip/Sector Erase Operation Timings
34
Am29LV001B
August 19, 2005
AC CHARACTERISTICS
tRC
VA
Addresses
VA
VA
tACC
tCE
CE#
tCH
tOE
OE#
tOEH
WE#
tDF
tOH
High Z
High Z
DQ7
Valid Data
Complement
Complement
True
DQ0–DQ6
Valid Data
Status Data
True
Status Data
Note:
VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array
data read cycle.
Figure 17. Data# Polling Timings (During Embedded Algorithms)
tRC
Addresses
CE#
VA
tACC
tCE
VA
VA
VA
tCH
tOE
OE#
WE#
tOEH
tDF
tOH
High Z
DQ6/DQ2
Valid Status
(first read)
Valid Status
Valid Status
Valid Data
(second read)
(stops toggling)
Note:
VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last
status read cycle, and array data read cycle.
Figure 18. Toggle Bit Timings (During Embedded Algorithms)
August 19, 2005
Am29LV001B
35
AC CHARACTERISTICS
Enter
Erase
Suspend
Enter Erase
Suspend Program
Embedded
Erasing
Erase
Resume
Erase
Erase Suspend
Read
Erase
Erase
WE#
Erase
Erase Suspend
Suspend
Program
Complete
Read
DQ6
DQ2
Note:
The system can use OE# or CE# to toggle DQ2/DQ6. DQ2 toggles only when read at an address within an
erase-suspended sector.
Figure 19. DQ2 vs. DQ6
TEMPORARY SECTOR UNPROTECT
Parameter
JEDEC
Std
Description
Rise and Fall Time
All Speed Options
500
Unit
ns
t
V
Min
Min
VIDR
ID
RESET# Setup Time for Temporary
Sector Unprotect
t
4
µs
RSP
Note: Not 100% tested.
12 V
RESET#
0 or 3 V
0 or 3 V
tVIDR
tVIDR
Program or Erase Command Sequence
CE#
WE#
t
Figure 20. Temporary Sector Unprotect Timing Diagram
36
Am29LV001B
August 19, 2005
AC Characteristics
V
V
ID
IH
RESET#
SA, A6,
A1, A0
Valid*
Valid*
Valid*
Status
Sector Protect/Unprotect
Verify
40h
Data
60h
60h
Sector Protect: 100 µs
Sector Unprotect: 10 ms
1 µs
CE#
WE#
OE#
Note:
For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.
Figure 21. In-System Sector Protect/Unprotect Timing Diagram
August 19, 2005
Am29LV001B
37
AC CHARACTERISTICS
Alternate CE# Controlled Erase/Program Operations
Parameter
Speed Options
JEDEC
Std
Description
-45
45
-55
55
-70
70
-90
90
Unit
ns
ns
ns
ns
ns
ns
t
t
t
Write Cycle Time (Note 1)
Address Setup Time
Address Hold Time
Data Setup Time
Min
Min
Min
Min
Min
Min
AVAV
AVEL
ELAX
DVEH
EHDX
WC
t
0
AS
AH
DS
DH
t
t
35
20
45
20
45
35
45
45
t
t
t
t
Data Hold Time
0
0
t
Output Enable Setup Time (Note 1)
OES
Read Recovery Time Before Write
(OE# High to WE# Low)
t
t
t
Min
0
ns
GHEL
GHEL
t
WE# Setup Time
Min
Min
Min
Min
Typ
Typ
0
0
ns
ns
WLEL
WS
t
t
WE# Hold Time
EHWH
WH
t
t
CE# Pulse Width
25
30
35
35
ns
ELEH
EHEL
CP
t
t
CE# Pulse Width High
Programming Operation (Notes 1, 2)
Sector Erase Operation (Notes 1, 2)
30
9
ns
CPH
t
t
t
t
µs
WHWH1
WHWH2
WHWH1
WHWH2
0.7
sec
Notes:
1. Not 100% tested.
2. See “Erase and Programming Performance” on page 40 for more information.
38
Am29LV001B
August 19, 2005
AC CHARACTERISTICS
555 for program
PA for program
2AA for erase
SA for sector erase
555 for chip erase
Data# Polling
Addresses
PA
tWC
tWH
tAS
tAH
WE#
OE#
tGHEL
tWHWH1 or 2
tCP
CE#
tWS
tCPH
tDS
tDH
DQ7#
DOUT
Data
tRH
A0 for program
55 for erase
PD for program
30 for sector erase
10 for chip erase
RESET#
Notes:
1. Figure indicates the last two bus cycles of the program or erase command sequence.
2. PA program address, SA = Sector Address, PD = program data, DQ7# = complement of the data written to the
device,
D
= data written to the device.
OUT
Figure 22. Alternate CE# Controlled Write Operation Timings
August 19, 2005
Am29LV001B
39
ERASE AND PROGRAMMING PERFORMANCE
Typ (Note
Parameter
1)
0.7
7
Max (Note 2)
15
Unit
s
Comments
Sector Erase Time
Excludes 00h programming
prior to erasure (Note 4)
Chip Erase Time
s
Byte Programming Time
Chip Programming Time (Note 3)
9
300
3.3
µs
s
Excludes system level
overhead (Note 5)
1.1
Notes:
1. Typical program and erase times assume the following conditions: 25×C, 3.0 V VCC, 1,000,000 cycles.
Additionally, programming typicals assume checkerboard pattern.
2. Under worst case conditions of 90°C, VCC = 2.7 V (3.0 V for -45R), 1,000,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since
most bytes program faster than the maximum program times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program
command. See Table 5 on page 20 for further information on command definitions.
6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles.
LATCHUP CHARACTERISTICS
Description
Min
Max
Input voltage with respect to V on all pins except I/O pins
(including A9, OE#, and RESET#)
SS
–1.0 V
13.0 V
Input voltage with respect to V on all I/O pins
–1.0 V
VCC + 1.0 V
+100 mA
SS
V
Current
–100 mA
CC
Includes all pins except V . Test conditions: V = 3.0 V, one pin at a time.
CC
CC
TSOP PIN CAPACITANCE
Parameter
Symbol
Parameter Description
Test Setup
= 0
Typ
6
Max
7.5
12
Unit
C
Input Capacitance
Output Capacitance
V
pF
pF
pF
IN
IN
C
V
= 0
8.5
7.5
OUT
OUT
C
Control Pin Capacitance
V
= 0
IN
9
IN2
Notes:
1. Sampled, not 100% tested.
2. Test conditions T = 25°C, f = 1.0 MHz.
A
40
Am29LV001B
August 19, 2005
PLCC PIN CAPACITANCE
Parameter Symbol
Parameter Description
Test Setup
= 0
Typ
4
Max
6
Unit
pF
C
Input Capacitance
V
V
V
IN
IN
C
Output Capacitance
Control Pin Capacitance
= 0
8
12
12
pF
OUT
OUT
C
= 0
PP
8
pF
IN2
Notes:
1. Sampled, not 100% tested.
2. Test conditions T = 25°C, f = 1.0 MHz.
A
DATA RETENTION
Parameter
Test Conditions
150×C
Min
Unit
10
20
Years
Years
Minimum Pattern Data Retention Time
125×C
August 19, 2005
Am29LV001B
41
Physical Dimensions
PL 032—32-Pin Plastic Leaded Chip Carrier
Dwg rev AH; 10/99
42
Am29LV001B
August 19, 2005
Physical Dimensions*
TS 032—32-Pin Standard Thin Small Outline Package
Dwg rev AA; 10/99
* For reference only. BSC is an ANSI standard for Basic Space Centering
August 19, 2005
Am29LV001B
43
REVISION SUMMARY
Revision A (January 1998)
Revision E+1 (November 13, 2000)
Initial release. (This revision also represented the
Am29LV010B device.)
Added table of contents. Deleted the burn-in option
from the Ordering Information section.
Revision A+1 (February 1998)
Revision F (September 26, 2002)
Logic Symbol
Global
Deleted the BYTE# input from the drawing. (This revi-
sion also represented the Am29LV010B device.)
The 45 ns speed option is now available in the indus-
trial temperature range.
Command Definitions
Revision B (April 1998)
In the introductory paragraph, modified text to indicate
that incorrectly written command sequences may place
the device in an unknown state.
Split the Am29LV001B/Am29LV010B data sheet, with
the elimination of all references to Am29LV010B.
Revision C (April 1998)
DC Characteristics
Global
Added RESET# input load current specification to
table.
Deleted 120 ns speed option; added 90 ns speed
option.
AC Characteristics, Read Operations
Distinctive Characteristics
Changed t to 16 ns for 70 and 90 ns speed options.
DF
Changed process technology to 0.35 µm.
Temporary Sector Unprotect
Revision F +1 (October 21, 2004)
Entered timing specifications for t
and t
.
VIDR
RSP
Global
Erase and Programming Performance
Added Colophon
Changed endurance in Note 2 to 1 million cycles;
added worst case voltage for -45R speed option.
Ordering Information
Added temperature ranges for Pb-free package types
Revision D (January 1999)
Valid Combinations
Distinctive Characteristics
Added valid combination types
Changed process technology to 0.32 µm.
DC Characteristics—CMOS Compatible
Revision F +2 (August 19, 2005)
I
, I
, I
, I
, I
: Added Note 2 “Maximum
CC1 CC2 CC3 CC4 CC5
I
specifications are tested with V = V
”.
CCmax
CC
CC
Ordering Information
I
, I
: Deleted V = V
.
CCmax
Changed to include Pb-free for PDIP or PLCC
package.
CC3 CC4
CC
Figure 20. Temporary Sector Unprotect Timing
Diagram
Modified second t
parameter.
VIDR
Data Retention
Added new table.
Revision E (November 17, 1999)
AC Characteristics—Figure 15. Program
Operations Timing and Figure 16. Chip/Sector
Erase Operations
Deleted t
high.
and changed OE# waveform to start at
GHWL
Physical Dimensions
Replaced figures with more detailed illustrations.
44
Am29LV001B
August 19, 2005
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without limita-
tion, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as con-
templated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the
public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,
aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for
any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion LLC will not be liable
to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor
devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design
measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating
conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign
Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior au-
thorization by the respective government entity will be required for export of those products.
Trademarks
Copyright © 2000-2005 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.
ExpressFlash is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
August 19, 2005
Am29LV001B
45
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