AM29LV004BB-90EE

更新时间:2024-10-29 18:26:32
品牌:SPANSION
描述:Flash, 512KX8, 90ns, PDSO40, MO-142CD, TSOP-40

AM29LV004BB-90EE 概述

Flash, 512KX8, 90ns, PDSO40, MO-142CD, TSOP-40 闪存

AM29LV004BB-90EE 规格参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:TSOP1包装说明:TSSOP, TSSOP40,.8,20
针数:40Reach Compliance Code:not_compliant
ECCN代码:3A001.A.2.CHTS代码:8542.32.00.51
风险等级:5.59Is Samacsys:N
最长访问时间:90 ns其他特性:MIN 1000K WRITE CYCLES; 20 YEAR DATA RETENTION; BOTTOM BOOT BLOCK
启动块:BOTTOM命令用户界面:YES
数据轮询:YES数据保留时间-最小值:20
耐久性:1000000 Write/Erase CyclesJESD-30 代码:R-PDSO-G40
JESD-609代码:e0长度:18.4 mm
内存密度:4194304 bit内存集成电路类型:FLASH
内存宽度:8湿度敏感等级:3
功能数量:1部门数/规模:1,2,1,7
端子数量:40字数:524288 words
字数代码:512000工作模式:ASYNCHRONOUS
最高工作温度:125 °C最低工作温度:-55 °C
组织:512KX8封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP40,.8,20
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
并行/串行:PARALLEL峰值回流温度(摄氏度):240
电源:3/3.3 V编程电压:3 V
认证状态:Not Qualified就绪/忙碌:YES
座面最大高度:1.2 mm部门规模:16K,8K,32K,64K
最大待机电流:0.000005 A子类别:Flash Memories
最大压摆率:0.03 mA最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2.7 V标称供电电压 (Vsup):3 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.5 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
切换位:YES类型:NOR TYPE
宽度:10 mmBase Number Matches:1

AM29LV004BB-90EE 数据手册

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Am29LV004B  
Data Sheet  
The Am29LV004B is not offered for new designs. Please contact a Spansion representative for alter-  
nates.  
The following document contains information on Spansion memory products. Although the document  
is marked with the name of the company that originally developed the specification, Spansion will  
continue to offer these products to existing customers.  
Continuity of Specifications  
There is no change to this data sheet as a result of offering the device as a Spansion product. Any  
changes that have been made are the result of normal data sheet improvement and are noted in the  
document revision summary, where supported. Future routine revisions will occur when appro and  
changes will be noted in a revision summary.  
Continuity of Ordering Part Numbers  
Spansion continues to support existing part numbers beginning with “Am” and “MBM. To order these  
products, please use only the Ordering Part Numbers listed in this document.  
For More Information  
Please contact your local sales office for additional information about Spansion memory solutions.  
Publication Number 21522 Revision D Amendment 5 Issue Date October 11, 2006  
THIS PAGE LEFT INTENTIONALLY BLANK  
DATA SHEET  
Am29LV004B  
4 Megabit (512 K x 8-Bit)  
CMOS 3.0 Volt-only Boot Sector Flash Memory  
The Am29LV004B is not offered for new designs. Please contact a Spansion representative for alternates.  
DISTINCTIVE CHARACTERISTICS  
Single power supply operation  
Top or bottom boot block configurations  
available  
— 2.7 to 3.6 volt read and write operations for  
battery-powered applications  
Embedded Algorithms  
Manufactured on 0.32 µm process technology  
— Embedded Erase algorithm automatically  
preprograms and erases the entire chip or any  
combination of designated sectors  
— Compatible with 0.5 µm Am29LV004 device  
High performance  
— Embedded Program algorithm automatically  
writes and verifies data at specified addresses  
— Access times as fast as 70 ns  
Ultra low power consumption (typical values at  
Minimum 1,000,000 write cycle guarantee per sector  
20-year data retention at 125°C  
— Reliable operation for the life of the system  
Package option  
5 MHz)  
— 200 nA Automatic Sleep mode current  
— 200 nA standby mode current  
— 7 mA read current  
— 40-pin TSOP  
— 15 mA program/erase current  
Compatibility with JEDEC standards  
Flexible sector architecture  
— Pinout and software compatible with single-  
power supply Flash  
— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and  
seven 64 Kbyte sectors  
— Superior inadvertent write protection  
— Supports full chip erase  
— Sector Protection features:  
Data# Polling and toggle bits  
A hardware method of locking a sector to  
prevent any program or erase operations within  
that sector  
— Provides a software method of detecting  
program or erase operation completion  
Ready/Busy# pin (RY/BY#)  
Sectors can be locked in-system or via  
programming equipment  
— Provides a hardware method of detecting  
program or erase cycle completion  
Temporary Sector Unprotect feature allows code  
changes in previously locked sectors  
Erase Suspend/Erase Resume  
— Suspends an erase operation to read data from,  
or program data to, a sector that is not being  
erased, then resumes the erase operation  
Unlock Bypass Program Command  
— Reduces overall programming time when  
issuing multiple program command sequences  
Hardware reset pin (RESET#)  
— Hardware method to reset the device to reading  
array data  
This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data  
Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.  
Publication# 21522 Rev: D Amendment: 5  
Issue Date: October 11, 2006  
D A T A S H E E T  
GENERAL DESCRIPTION  
The Am29LV004B is an 4 Mbit, 3.0 volt-only Flash  
memory organized as 524,288 bytes. The device is  
offered in a 40-pin TSOP package. The byte-wide (x8)  
data appears on DQ7–DQ0. This device requires only  
a single, 3.0 volt VCC supply to perform read, program,  
and erase operations. A standard EPROM programmer  
can also be used to program and erase the device.  
before executing the erase operation. During erase, the  
device automatically times the erase pulse widths and  
verifies proper cell margin.  
The host system can detect whether a program or  
erase operation is complete by observing the RY/BY#  
pin, or by reading the DQ7 (Data# Polling) and DQ6  
(toggle) status bits. After a program or erase cycle has  
been completed, the device is ready to read array data  
or accept another command.  
This device is manufactured using AMD’s 0.32 µm  
process technology, and offers all the features and ben-  
efits of the Am29LV004, which was manufactured using  
0.5 µm process technology. In addition, the  
Am29LV004B features unlock bypass programming  
and in-system sector protection/unprotection.  
The sector erase architecture allows memory sectors  
to be erased and reprogrammed without affecting the  
data contents of other sectors. The device is fully  
erased when shipped from the factory.  
The standard device offers access times of 70, 90, and  
120 ns, allowing high speed microprocessors to  
operate without wait states. To eliminate bus contention  
the device has separate chip enable (CE#), write  
enable (WE#) and output enable (OE#) controls.  
Hardware data protection measures include a low  
V
detector that automatically inhibits write opera-  
CC  
tions during power transitions. The hardware sector  
protection feature disables both program and erase  
operations in any combination of the sectors of  
memory. This can be achieved in-system or via pro-  
gramming equipment.  
The device requires only a single 3.0 volt power  
supply for both read and write functions. Internally  
generated and regulated voltages are provided for the  
program and erase operations.  
The Erase Suspend feature enables the user to put  
erase on hold for any period of time to read data from,  
or program data to, any sector that is not selected for  
erasure. True background erase can thus be achieved.  
The device is entirely command set compatible with the  
JEDEC single-power-supply Flash standard. Com-  
mands are written to the command register using  
standard microprocessor write timings. Register con-  
tents serve as input to an internal state-machine that  
controls the erase and programming circuitry. Write  
cycles also internally latch addresses and data needed  
for the programming and erase operations. Reading  
data out of the device is similar to reading from other  
Flash or EPROM devices.  
The hardware RESET# pin terminates any operation  
in progress and resets the internal state machine to  
reading array data. The RESET# pin may be tied to the  
system reset circuitry. A system reset would thus also  
reset the device, enabling the system microprocessor  
to read the boot-up firmware from the Flash memory.  
The device offers two power-saving features. When  
addresses have been stable for a specified amount of  
time, the device enters the automatic sleep mode.  
The system can also place the device into the standby  
mode. Power consumption is greatly reduced in both  
these modes.  
Device programming occurs by executing the program  
command sequence. This initiates the Embedded  
Program algorithm—an internal algorithm that auto-  
matically times the program pulse widths and verifies  
proper cell margin. The Unlock Bypass mode facili-  
tates faster programming times by requiring only two  
write cycles to program data instead of four.  
AMD’s Flash technology combines years of Flash  
memory manufacturing experience to produce the  
highest levels of quality, reliability and cost effectiveness.  
The device electrically erases all bits within a sector  
simultaneously via Fowler-Nordheim tunneling. The  
data is programmed using hot electron injection.  
Device erasure occurs by executing the erase  
command sequence. This initiates the Embedded Erase  
algorithm—an internal algorithm that automatically  
pre-programs the array (if it is not already programmed)  
4
Am29LV004B  
21522D5 October 11, 2006  
D A T A S H E E T  
TABLE OF CONTENTS  
Product Selector Guide . . . . . . . . . . . . . . . . . . . . .6  
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6  
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . .7  
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . .7  
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
Ordering Information . . . . . . . . . . . . . . . . . . . . . . .8  
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . .9  
Table 1. Am29LV004B Device Bus Operations ................................ 9  
Requirements for Reading Array Data ..................................... 9  
Writing Commands/Command Sequences .............................. 9  
Program and Erase Operation Status .................................... 10  
Standby Mode ........................................................................ 10  
Automatic Sleep Mode ........................................................... 10  
RESET#: Hardware Reset Pin ............................................... 10  
Output Disable Mode .............................................................. 10  
Table 2. Am29LV004BT Top Boot Block Sector Address Table..... 11  
Table 3. Am29LV004BB Bottom Boot Block Sector Address Table 11  
Autoselect Mode ..................................................................... 12  
Table 4. Am29LV004B Autoselect Codes (High Voltage Method).. 12  
Sector Protection/Unprotection ............................................... 12  
Temporary Sector Unprotect .................................................. 12  
Figure 1. In-System Sector Protect/Unprotect Algorithms ...............13  
Figure 2. Temporary Sector Unprotect Operation ...........................14  
Hardware Data Protection ...................................................... 14  
RY/BY#: Ready/Busy# ............................................................ 20  
DQ6: Toggle Bit I .................................................................... 20  
DQ2: Toggle Bit II ................................................................... 20  
Reading Toggle Bits DQ6/DQ2 ............................................... 20  
DQ5: Exceeded Timing Limits ................................................ 21  
DQ3: Sector Erase Timer ....................................................... 21  
Figure 6. Toggle Bit Algorithm ........................................................ 21  
Table 6. Write Operation Status..................................................... 22  
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 23  
Figure 7. Maximum Negative Overshoot Waveform ...................... 23  
Figure 8. Maximum Positive Overshoot Waveform ........................ 23  
Operating Ranges. . . . . . . . . . . . . . . . . . . . . . . . . 23  
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 24  
Figure 9. ICC1 Current vs. Time (Showing Active and Automatic  
Sleep Currents) .............................................................................. 25  
Figure 10. Typical ICC1 vs. Frequency ........................................... 25  
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 26  
Figure 11. Test Setup ..................................................................... 26  
Table 7. Test Specifications........................................................... 26  
Key to Switching Waveforms. . . . . . . . . . . . . . . . 26  
Figure 12. Input Waveforms and Measurement Levels ................. 26  
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 27  
Read Operations .................................................................... 27  
Figure 13. Read Operations Timings ............................................. 27  
Hardware Reset (RESET#) .................................................... 28  
Figure 14. RESET# Timings .......................................................... 28  
Erase/Program Operations ..................................................... 29  
Figure 15. Program Operation Timings .......................................... 30  
Figure 16. Chip/Sector Erase Operation Timings .......................... 31  
Figure 17. Data# Polling Timings (During Embedded Algorithms) . 32  
Figure 18. Toggle Bit Timings (During Embedded Algorithms) ...... 32  
Figure 19. DQ2 vs. DQ6 ................................................................. 33  
Temporary Sector Unprotect .................................................. 33  
Figure 20. Temporary Sector Unprotect Timing Diagram .............. 33  
Figure 21. Sector Protect/Unprotect Timing Diagram .................... 34  
Alternate CE# Controlled Erase/Program Operations ............ 35  
Figure 22. Alternate CE# Controlled Write Operation Timings ...... 36  
Erase and Programming Performance . . . . . . . 37  
Latchup Characteristics. . . . . . . . . . . . . . . . . . . . 37  
TSOP and SO Pin Capacitance . . . . . . . . . . . . . . 37  
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 37  
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 38  
TS 040—40-Pin Standard TSOP ............................................ 38  
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 39  
Low V Write Inhibit .............................................................. 14  
CC  
Write Pulse “Glitch” Protection ............................................... 14  
Logical Inhibit .......................................................................... 14  
Power-Up Write Inhibit ............................................................ 14  
Command Definitions . . . . . . . . . . . . . . . . . . . . . 14  
Reading Array Data ................................................................ 14  
Reset Command ..................................................................... 15  
Autoselect Command Sequence ............................................ 15  
Byte Program Command Sequence ....................................... 15  
Unlock Bypass Command Sequence ..................................... 15  
Figure 3. Program Operation ..........................................................16  
Chip Erase Command Sequence ........................................... 16  
Sector Erase Command Sequence ........................................ 16  
Erase Suspend/Erase Resume Commands ........................... 17  
Figure 4. Erase Operation ...............................................................17  
Command Definitions ............................................................. 18  
Table 5. Am29LV004B Command Definitions................................. 18  
Write Operation Status . . . . . . . . . . . . . . . . . . . . .19  
DQ7: Data# Polling ................................................................. 19  
Figure 5. Data# Polling Algorithm ...................................................19  
21522D5 October 11, 2006  
Am29LV004B  
5
D A T A S H E E T  
PRODUCT SELECTOR GUIDE  
Family Part Number  
Am29LV004B  
Speed Options  
-70  
70  
70  
30  
-90  
90  
90  
35  
-120  
120  
120  
50  
Max access time, ns (tACC  
Max CE# access time, ns (tCE  
Max OE# access time, ns (tOE  
)
)
)
Note: See “AC Characteristics” for full specifications.  
BLOCK DIAGRAM  
DQ0DQ7  
RY/BY#  
VCC  
Sector Switches  
VSS  
Erase Voltage  
Generator  
Input/Output  
Buffers  
RESET#  
State  
Control  
WE#  
Command  
Register  
PGM Voltage  
Generator  
Data  
Latch  
Chip Enable  
Output Enable  
Logic  
STB  
CE#  
OE#  
Y-Decoder  
Y-Gating  
STB  
VCC Detector  
Timer  
Cell Matrix  
X-Decoder  
A0–A18  
6
Am29LV004B  
21522D5 October 11, 2006  
D A T A S H E E T  
CONNECTION DIAGRAMS  
A17  
VSS  
NC  
NC  
A10  
DQ7  
DQ6  
DQ5  
DQ4  
VCC  
VCC  
A16  
A15  
A14  
A13  
A12  
A11  
A9  
1
2
3
4
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
5
6
7
A8  
8
WE#  
RESET#  
NC  
RY/BY#  
A18  
A7  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
Standard TSOP  
NC  
DQ3  
DQ2  
DQ1  
DQ0  
OE#  
VSS  
A6  
A5  
A4  
A3  
A2  
A1  
CE#  
A0  
PIN CONFIGURATION  
LOGIC SYMBOL  
A0–A18  
= 19 addresses  
19  
DQ0–DQ7 = 8 data inputs/outputs  
A0–A18  
8
CE#  
=
=
=
=
=
=
Chip enable  
DQ0–DQ7  
OE#  
Output enable  
WE#  
Write enable  
CE#  
OE#  
RESET#  
RY/BY#  
Hardware reset pin, active low  
Ready/Busy# output  
WE#  
RESET#  
V
3.0 volt-only single power supply  
CC  
(see Product Selector Guide for speed  
options and voltage supply tolerances)  
RY/BY#  
V
=
=
Device ground  
SS  
NC  
Pin not connected internally  
21522D5 October 11, 2006  
Am29LV004B  
7
D A T A S H E E T  
ORDERING INFORMATION  
Standard Products  
AMD standard products are available in several packages and operating ranges. The order number (Valid Combi-  
nation) is formed by a combination of the elements below.  
Am29LV004B  
T
-70  
E
C
TEMPERATURE RANGE  
C
I
=
=
=
=
=
=
Commercial (0°C to +70°C)  
Industrial (–40°C to +85°C)  
Extended (–55°C to +125°C)  
Commercial (0°C to +70°C) for Pb-free Package  
Industrial (-40°C to +85°C) for Pb-free Package  
Extended (-55°C to +125°C) for Pb-free Package  
E
D
F
K
PACKAGE TYPE  
E
=
40-Pin Thin Small Outline Package (TSOP)  
Standard Pinout (TS 040)  
SPEED OPTION  
See Product Selector Guide and Valid Combinations  
BOOT CODE SECTOR ARCHITECTURE  
T
B
=
=
Top Sector  
Bottom Sector  
DEVICE NUMBER/DESCRIPTION  
Am29LV004B  
4 Megabit (512 K x 8-Bit) CMOS Flash Memory  
3.0 Volt-only Read, Program and Erase  
Valid Combinations  
Valid Combinations list configurations planned to be sup-  
ported in volume for this device. Consult the local AMD sales  
office to confirm availability of specific valid combinations and  
to check on newly released combinations.  
Valid Combinations  
AM29LV004BT-70,  
AM29LV004BB-70  
EC, EI, ED, EF  
AM29LV004BT-90,  
AM29LV004BB-90  
EC, EI, EE, ED, EF, EK  
AM29LV004BT-120,  
AM29LV004BB-120  
8
Am29LV004B  
21522D5 October 11, 2006  
D A T A S H E E T  
DEVICE BUS OPERATIONS  
This section describes the requirements and use of the  
device bus operations, which are initiated through the  
internal command register. The command register  
itself does not occupy any addressable memory loca-  
tion. The register is composed of latches that store the  
commands, along with the address and data informa-  
tion needed to execute the command. The contents of  
the register serve as inputs to the internal state  
machine. The state machine outputs dictate the func-  
tion of the device. Table 1 lists the device bus  
operations, the inputs and control levels they require,  
and the resulting output. The following subsections  
describe each of these operations in further detail.  
Table 1. Am29LV004B Device Bus Operations  
Operation  
CE#  
OE#  
L
WE#  
H
RESET#  
Addresses (Note 1)  
DQ0–DQ7  
DOUT  
Read  
L
H
AIN  
AIN  
X
Write  
L
H
L
H
DIN  
Standby  
VCC ± 0.3 V  
X
X
VCC ± 0.3 V  
High-Z  
High-Z  
High-Z  
Output Disable  
Reset  
L
H
H
H
L
X
X
X
X
X
Sector Address, A6 = L,  
A1 = H, A0 = L  
Sector Protect (Note 2)  
L
H
L
VID  
DIN, DOUT  
Sector Address, A6 = H,  
A1 = H, A0 = L  
Sector Unprotect (Note 2)  
Temporary Sector Unprotect  
Legend:  
L
H
X
L
VID  
VID  
DIN, DOUT  
DIN  
X
X
AIN  
L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’t Care, AIN = Address In, DIN = Data In, DOUT = Data Out  
Notes:  
1. Addresses are A18–A0.  
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector  
Protection/Unprotection” section.  
Requirements for Reading Array Data  
Writing Commands/Command Sequences  
To read array data from the outputs, the system must  
To write a command or command sequence (which  
includes programming data to the device and erasing  
sectors of memory), the system must drive WE# and  
drive the CE# and OE# pins to V . CE# is the power  
IL  
control and selects the device. OE# is the output  
control and gates array data to the output pins. WE#  
CE# to V , and OE# to V .  
IL  
IH  
should remain at V .  
IH  
The device features an Unlock Bypass mode to facili-  
tate faster programming. Once the device enters the  
Unlock Bypass mode, only two write cycles are  
required to program a byte, instead of four. The “Byte  
Program Command Sequence” section has details on  
programming data to the device using both standard  
and Unlock Bypass command sequences.  
The internal state machine is set for reading array data  
upon device power-up, or after a hardware reset. This  
ensures that no spurious alteration of the memory  
content occurs during the power transition. No  
command is necessary in this mode to obtain array  
data. Standard microprocessor read cycles that assert  
valid addresses on the device address inputs produce  
valid data on the device data outputs. The device  
remains enabled for read access until the command  
register contents are altered.  
An erase operation can erase one sector, multiple sec-  
tors, or the entire device. Tables 2 and 3 indicate the  
address space that each sector occupies. A “sector  
address” consists of the address bits required to  
uniquely select a sector. The “Command Definitions”  
section has details on erasing a sector or the entire  
chip, or suspending/resuming the erase operation.  
See “Reading Array Data” for more information. Refer  
to the AC Read Operations table for timing specifica-  
tions and to Figure 13 for the timing diagram. I  
in the  
CC1  
DC Characteristics table represents the active current  
specification for reading array data.  
After the system writes the autoselect command  
sequence, the device enters the autoselect mode. The  
system can then read autoselect codes from the  
21522D5 October 11, 2006  
Am29LV004B  
9
D A T A S H E E T  
internal register (which is separate from the memory  
access timings provide new data when addresses are  
changed. While in sleep mode, output data is latched  
array) on DQ7–DQ0. Standard read cycle timings apply  
in this mode. Refer to the Autoselect Mode and Autose-  
lect Command Sequence sections for more  
information.  
and always available to the system. I  
in the DC  
CC4  
Characteristics table represents the automatic sleep  
mode current specification.  
I
in the DC Characteristics table represents the  
CC2  
RESET#: Hardware Reset Pin  
The RESET# pin provides a hardware method of reset-  
ting the device to reading array data. When the  
active current specification for the write mode. The “AC  
Characteristics” section contains timing specification  
tables and timing diagrams for write operations.  
RESET# pin is driven low for at least a period of t , the  
RP  
device immediately terminates any operation in  
progress, tristates all output pins, and ignores all  
read/write commands for the duration of the RESET#  
pulse. The device also resets the internal state  
machine to reading array data. The operation that was  
interrupted should be reinitiated once the device is  
ready to accept another command sequence, to  
ensure data integrity.  
Program and Erase Operation Status  
During an erase or program operation, the system may  
check the status of the operation by reading the status  
bits on DQ7–DQ0. Standard read cycle timings and I  
CC  
read specifications apply. Refer to “Write Operation  
Status” for more information, and to “AC Characteris-  
tics” for timing diagrams.  
Standby Mode  
Current is reduced for the duration of the RESET#  
pulse. When RESET# is held at V  
0.3 V, the device  
SS  
When the system is not reading or writing to the device,  
it can place the device in the standby mode. In this  
mode, current consumption is greatly reduced, and the  
outputs are placed in the high impedance state, inde-  
pendent of the OE# input.  
draws CMOS standby current (I  
). If RESET# is held  
CC4  
at V but not within V  
0.3 V, the standby current will  
IL  
SS  
be greater.  
The RESET# pin may be tied to the system reset cir-  
cuitry. A system reset would thus also reset the Flash  
memory, enabling the system to read the boot-up firm-  
ware from the Flash memory.  
The device enters the CMOS standby mode when the  
CE# and RESET# pins are both held at V ± 0.3 V.  
(Note that this is a more restricted voltage range than  
CC  
V .) If CE# and RESET# are held at V , but not within  
If RESET# is asserted during a program or erase oper-  
ation, the RY/BY# pin remains a “0” (busy) until the  
internal reset operation is complete, which requires a  
IH  
IH  
V
± 0.3 V, the device will be in the standby mode, but  
CC  
the standby current will be greater. The device requires  
standard access time (t ) for read access when the  
time of t  
(during Embedded Algorithms). The  
CE  
READY  
device is in either of these standby modes, before it is  
ready to read data.  
system can thus monitor RY/BY# to determine whether  
the reset operation is complete. If RESET# is asserted  
when a program or erase operation is not executing  
(RY/BY# pin is “1”), the reset operation is completed  
If the device is deselected during erasure or program-  
ming, the device draws active current until the  
operation is completed.  
within a time of t  
(not during Embedded Algo-  
READY  
rithms). The system can read data t  
after the  
RH  
I
in the DC Characteristics table represents the  
RESET# pin returns to V .  
CC3  
IH  
standby current specification.  
Refer to the AC Characteristics tables for RESET#  
parameters and to Figure 14 for the timing diagram.  
Automatic Sleep Mode  
The automatic sleep mode minimizes Flash device  
energy consumption. The device automatically enables  
Output Disable Mode  
When the OE# input is at V , output from the device is  
IH  
this mode when addresses remain stable for t  
+ 30  
ACC  
disabled. The output pins are placed in the high imped-  
ance state.  
ns. The automatic sleep mode is independent of the  
CE#, WE#, and OE# control signals. Standard address  
10  
Am29LV004B  
21522D5 October 11, 2006  
D A T A S H E E T  
Table 2. Am29LV004BT Top Boot Block Sector Address Table  
Sector Size  
Address Range  
(in hexadecimal)  
Sector  
SA0  
SA1  
SA2  
SA3  
SA4  
SA5  
SA6  
SA7  
SA8  
SA9  
SA10  
A18  
0
A17  
A16  
A15  
X
X
X
X
X
X
X
0
A14  
A13  
(Kbytes)  
0
0
X
X
64  
64  
64  
64  
64  
64  
64  
32  
8
00000h-0FFFFh  
10000h-1FFFFh  
20000h-2FFFFh  
30000h-3FFFFh  
40000h-4FFFFh  
50000h-5FFFFh  
60000h-6FFFFh  
70000h-77FFFh  
78000h-79FFFh  
7A000h-7BFFFh  
7C000h-7FFFFh  
0
0
1
X
X
0
1
0
X
X
0
1
1
X
X
1
0
0
X
X
1
0
1
X
X
1
1
0
X
X
1
1
1
X
X
1
1
1
1
0
0
1
1
1
1
0
1
8
1
1
1
1
1
X
16  
Table 3. Am29LV004BB Bottom Boot Block Sector Address Table  
Sector Size  
Address Range  
(in hexadecimal)  
Sector  
SA0  
SA1  
SA2  
SA3  
SA4  
SA5  
SA6  
SA7  
SA8  
SA9  
SA10  
A18  
0
A17  
A16  
A15  
A14  
A13  
(Kbytes)  
0
0
0
0
X
16  
8
00000h-03FFFh  
04000h-05FFFh  
06000h-07FFFh  
08000h-0FFFFh  
10000h-1FFFFh  
20000h-2FFFFh  
30000h-3FFFFh  
40000h-4FFFFh  
50000h-5FFFFh  
60000h-6FFFFh  
70000h-7FFFFh  
0
0
0
0
1
0
0
0
0
0
1
1
8
0
0
0
1
X
X
32  
64  
64  
64  
64  
64  
64  
64  
0
0
1
X
X
X
X
X
X
X
X
X
0
1
0
X
X
0
1
1
X
X
1
0
0
X
X
1
0
1
X
X
1
1
0
X
X
1
1
1
X
X
21522D5 October 11, 2006  
Am29LV004B  
11  
D A T A S H E E T  
Table 4. In addition, when verifying sector protection,  
Autoselect Mode  
the sector address must appear on the appropriate  
highest order address bits (see Tables 2 and 3). Table  
4 shows the remaining address bits that are don’t care.  
When all necessary bits have been set as required, the  
programming equipment may then read the corre-  
sponding identifier code on DQ7–DQ0.  
The autoselect mode provides manufacturer and  
device identification, and sector protection verification,  
through identifier codes output on DQ7–DQ0. This  
mode is primarily intended for programming equipment  
to automatically match a device to be programmed with  
its corresponding programming algorithm. However,  
the autoselect codes can also be accessed in-system  
through the command register.  
To access the autoselect codes in-system, the host  
system can issue the autoselect command via the  
command register, as shown in Table 5. This method  
When using programming equipment, the autoselect  
mode requires V (11.5 V to 12.5 V) on address pin  
does not require V . See “Command Definitions” for  
ID  
ID  
details on using the autoselect mode.  
A9. Address pins A6, A1, and A0 must be as shown in  
Table 4. Am29LV004B Autoselect Codes (High Voltage Method)  
A18 A12  
to to  
CE# OE# WE# A13 A10 A9  
A8  
to  
A7  
A5  
to  
A2  
DQ7  
to  
DQ0  
Description  
A6  
A1  
A0  
Manufacturer ID: AMD  
L
L
L
L
H
H
X
X
X
X
VID  
VID  
X
X
L
X
X
L
L
01h  
B5h  
Device ID: Am29LV004BT  
(Top Boot Block)  
L
L
L
L
H
H
Device ID: Am29LV004BB  
(Bottom Boot Block)  
L
L
L
L
H
H
X
X
X
VID  
X
X
X
X
B6h  
01h  
(protected)  
Sector Protection Verification  
SA  
VID  
L
H
L
00h  
(unprotected)  
L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.  
details; contact an AMD representative to request a  
copy.  
Sector Protection/Unprotection  
The hardware sector protection feature disables both  
program and erase operations in any sector. The hard-  
ware sector unprotection feature re-enables both  
program and erase operations in previously protected  
sectors. Sector protection/unprotection can be imple-  
mented via two methods.  
The device is shipped with all sectors unprotected.  
AMD offers the option of programming and protecting  
sectors at its factory prior to shipping the device  
through AMD’s ExpressFlash™ Service. Contact an  
AMD representative for details.  
The primary method requires V on the RESET# pin  
It is possible to determine whether a sector is protected  
or unprotected. See “Autoselect Mode” for details.  
ID  
only, and can be implemented either in-system or via  
programming equipment. Figure 1 shows the algo-  
rithms and Figure 21 shows the timing diagram. This  
method uses standard microprocessor bus cycle  
timing. For sector unprotect, all unprotected sectors  
must first be protected prior to the first sector unprotect  
write cycle.  
Temporary Sector Unprotect  
This feature allows temporary unprotection of previ-  
ously protected sectors to change data in-system. The  
Sector Unprotect mode is activated by setting the  
RESET# pin to V . During this mode, formerly pro-  
ID  
tected sectors can be programmed or erased by  
The alternate method intended only for programming  
selecting the sector addresses. Once V is removed  
equipment requires V on address pin A9, OE#, and  
ID  
ID  
from the RESET# pin, all the previously protected  
sectors are protected again. Figure 2 shows the algo-  
rithm, and Figure 20 shows the timing diagrams, for this  
feature.  
RESET#. This method is compatible with programmer  
routines written for earlier 3.0 volt-only AMD flash  
devices. Publication number 20874 contains further  
12  
Am29LV004B  
21522D5 October 11, 2006  
D A T A S H E E T  
START  
START  
Protect all sectors:  
PLSCNT = 1  
PLSCNT = 1  
RESET# = VID  
The indicated portion  
of the sector protect  
algorithm must be  
performed for all  
unprotected sectors  
prior to issuing the  
first sector  
RESET# = VID  
Wait 1 μs  
Wait 1 μs  
unprotect address  
No  
First Write  
Cycle = 60h?  
No  
First Write  
Cycle = 60h?  
Temporary Sector  
Unprotect Mode  
Temporary Sector  
Unprotect Mode  
Yes  
Yes  
Set up sector  
address  
No  
All sectors  
protected?  
Sector Protect:  
Write 60h to sector  
address with  
A6 = 0, A1 = 1,  
A0 = 0  
Yes  
Set up first sector  
address  
Sector Unprotect:  
Wait 150 µs  
Write 60h to sector  
address with  
A6 = 1, A1 = 1,  
A0 = 0  
Verify Sector  
Protect: Write 40h  
to sector address  
with A6 = 0,  
Reset  
PLSCNT = 1  
Increment  
PLSCNT  
Wait 15 ms  
A1 = 1, A0 = 0  
Verify Sector  
Unprotect: Write  
40h to sector  
address with  
A6 = 1, A1 = 1,  
A0 = 0  
Read from  
sector address  
with A6 = 0,  
A1 = 1, A0 = 0  
Increment  
PLSCNT  
No  
No  
PLSCNT  
= 25?  
Read from  
sector address  
with A6 = 1,  
Data = 01h?  
Yes  
A1 = 1, A0 = 0  
No  
Yes  
Set up  
next sector  
address  
Yes  
No  
PLSCNT  
= 1000?  
Protect another  
sector?  
Data = 00h?  
Yes  
Device failed  
No  
Yes  
Remove VID  
from RESET#  
No  
Last sector  
verified?  
Device failed  
Write reset  
command  
Yes  
Remove VID  
Sector Unprotect  
Algorithm  
from RESET#  
Sector Protect  
Algorithm  
Sector Protect  
complete  
Write reset  
command  
Sector Unprotect  
complete  
Figure 1. In-System Sector Protect/Unprotect Algorithms  
21522D5 October 11, 2006  
Am29LV004B  
13  
D A T A S H E E T  
command definitions). In addition, the following hard-  
ware data protection measures prevent accidental  
erasure or programming, which might otherwise be  
START  
caused by spurious system level signals during V  
CC  
power-up and power-down transitions, or from system  
noise.  
RESET# = VID  
(Note 1)  
Low V  
Write Inhibit  
CC  
When V  
is less than V  
, the device does not  
LKO  
CC  
Perform Erase or  
Program Operations  
accept any write cycles. This protects data during V  
CC  
power-up and power-down. The command register and  
all internal program/erase circuits are disabled, and the  
device resets. Subsequent writes are ignored until V  
RESET# = VIH  
CC  
is greater than V  
. The system must provide the  
LKO  
proper signals to the control pins to prevent uninten-  
tional writes when V is greater than V  
.
CC  
LKO  
Temporary Sector  
Unprotect Completed  
(Note 2)  
Write Pulse “Glitch” Protection  
Noise pulses of less than 5 ns (typical) on OE#, CE# or  
WE# do not initiate a write cycle.  
Logical Inhibit  
Notes:  
Write cycles are inhibited by holding any one of OE# =  
1. All protected sectors unprotected.  
V , CE# = V or WE# = V . To initiate a write cycle,  
IL  
IH  
IH  
2. All previously protected sectors are protected once  
again.  
CE# and WE# must be a logical zero while OE# is a  
logical one.  
Power-Up Write Inhibit  
Figure 2. Temporary Sector Unprotect Operation  
If WE# = CE# = V and OE# = V during power up, the  
IL  
IH  
device does not accept commands on the rising edge  
of WE#. The internal state machine is automatically  
reset to reading array data on power-up.  
Hardware Data Protection  
The command sequence requirement of unlock cycles  
for programming or erasing provides data protection  
against inadvertent writes (refer to Table 5 for  
COMMAND DEFINITIONS  
Writing specific address and data commands or  
sequences into the command register initiates device  
operations. Table 5 defines the valid register command  
sequences. Writing incorrect address and data  
values or writing them in the improper sequence  
resets the device to reading array data.  
After the device accepts an Erase Suspend command,  
the device enters the Erase Suspend mode. The  
system can read array data using the standard read  
timings, except that if it reads at an address within  
erase-suspended sectors, the device outputs status  
data. After completing a programming operation in the  
Erase Suspend mode, the system may once again  
read array data with the same exception. See “Erase  
Suspend/Erase Resume Commands” for more infor-  
mation on this mode.  
All addresses are latched on the falling edge of WE# or  
CE#, whichever happens later. All data is latched on  
the rising edge of WE# or CE#, whichever happens  
first. Refer to the appropriate timing diagrams in the  
“AC Characteristics” section.  
The system must issue the reset command to re-  
enable the device for reading array data if DQ5 goes  
high, or while in the autoselect mode. See the “Reset  
Command” section, next.  
Reading Array Data  
The device is automatically set to reading array data  
after device power-up. No commands are required to  
retrieve data. The device is also ready to read array  
data after completing an Embedded Program or  
Embedded Erase algorithm.  
See also “Requirements for Reading Array Data” in the  
“Device Bus Operations” section for more information.  
The Read Operations table provides the read parame-  
ters, and Figure 13 shows the timing diagram.  
14  
Am29LV004B  
21522D5 October 11, 2006  
D A T A S H E E T  
program set-up command. The program address and  
Reset Command  
data are written next, which in turn initiate the  
Embedded Program algorithm. The system is not  
required to provide further controls or timings. The  
device automatically provides internally generated  
program pulses and verify the programmed cell margin.  
Table 5 shows the address and data requirements for  
the byte program command sequence.  
Writing the reset command to the device resets the  
device to reading array data. Address bits are don’t  
care for this command.  
The reset command may be written between the  
sequence cycles in an erase command sequence  
before erasing begins. This resets the device to reading  
array data. Once erasure begins, however, the device  
ignores reset commands until the operation is  
complete.  
When the Embedded Program algorithm is complete,  
the device then returns to reading array data and  
addresses are no longer latched. The system can  
determine the status of the program operation by using  
DQ7, DQ6, or RY/BY#. See “Write Operation Status”  
for information on these status bits.  
The reset command may be written between the  
sequence cycles in a program command sequence  
before programming begins. This resets the device to  
reading array data (also applies to programming in  
Erase Suspend mode). Once programming begins,  
however, the device ignores reset commands until the  
operation is complete.  
Any commands written to the device during the  
Embedded Program Algorithm are ignored. Note that a  
hardware reset immediately terminates the program-  
ming operation. The Byte Program command  
sequence should be reinitiated once the device has  
reset to reading array data, to ensure data integrity.  
The reset command may be written between the  
sequence cycles in an autoselect command sequence.  
Once in the autoselect mode, the reset command must  
be written to return to reading array data (also applies  
to autoselect during Erase Suspend).  
Programming is allowed in any sequence and across  
sector boundaries. A bit cannot be programmed  
from a “0” back to a “1”. Attempting to do so may halt  
the operation and set DQ5 to “1”, or cause the Data#  
Polling algorithm to indicate the operation was suc-  
cessful. However, a succeeding read will show that the  
data is still “0”. Only erase operations can convert a “0”  
to a “1”.  
If DQ5 goes high during a program or erase operation,  
writing the reset command returns the device to  
reading array data (also applies during Erase  
Suspend).  
Autoselect Command Sequence  
Unlock Bypass Command Sequence  
The autoselect command sequence allows the host  
system to access the manufacturer and devices codes,  
and determine whether or not a sector is protected.  
Table 5 shows the address and data requirements. This  
method is an alternative to that shown in Table 4, which  
The unlock bypass feature allows the system to  
program bytes to the device faster than using the stan-  
dard program command sequence. The unlock bypass  
command sequence is initiated by first writing two  
unlock cycles. This is followed by a third write cycle  
containing the unlock bypass command, 20h. The  
device then enters the unlock bypass mode. A two-  
cycle unlock bypass program command sequence is all  
that is required to program in this mode. The first cycle  
in this sequence contains the unlock bypass program  
command, A0h; the second cycle contains the program  
address and data. Additional data is programmed in  
the same manner. This mode dispenses with the initial  
two unlock cycles required in the standard program  
command sequence, resulting in faster total program-  
ming time. Table 5 shows the requirements for the  
command sequence.  
is intended for PROM programmers and requires V  
on address bit A9.  
ID  
The autoselect command sequence is initiated by  
writing two unlock cycles, followed by the autoselect  
command. The device then enters the autoselect  
mode, and the system may read at any address any  
number of times, without initiating another command  
sequence. A read cycle at address 00h retrieves the  
manufacturer code. A read cycle at address 01h  
returns the device code. A read cycle containing a  
sector address (SA) and the address 02h returns 01h if  
that sector is protected, or 00h if it is unprotected. Refer  
to Tables 2 and 3 for valid sector addresses.  
During the unlock bypass mode, only the Unlock  
Bypass Program and Unlock Bypass Reset commands  
are valid. To exit the unlock bypass mode, the system  
must issue the two-cycle unlock bypass reset  
command sequence. The first cycle must contain the  
data 90h; the second cycle the data 00h. The device  
then returns to reading array data.  
The system must write the reset command to exit the  
autoselect mode and return to reading array data.  
Byte Program Command Sequence  
The byte program command sequence programs one  
byte into the device. Programming is a four-bus-cycle  
operation. The program command sequence is initi-  
ated by writing two unlock write cycles, followed by the  
Figure 3 illustrates the algorithm for the program oper-  
ation. See the Erase/Program Operations table in “AC  
21522D5 October 11, 2006  
Am29LV004B  
15  
D A T A S H E E T  
Characteristics” for parameters, and to Figure 15 for  
command sequence should be reinitiated once the  
device has returned to reading array data, to ensure  
data integrity.  
timing diagrams.  
The system can determine the status of the erase oper-  
ation by using DQ7, DQ6, DQ2, or RY/BY#. See “Write  
Operation Status” for information on these status bits.  
When the Embedded Erase algorithm is complete, the  
device returns to reading array data and addresses are  
no longer latched.  
START  
Write Program  
Command Sequence  
Figure 4 illustrates the algorithm for the erase opera-  
tion. See the Erase/Program Operations tables in “AC  
Characteristics” for parameters, and to Figure 16 for  
timing diagrams.  
Data Poll  
from System  
Embedded  
Program  
algorithm  
Sector Erase Command Sequence  
Sector erase is a six bus cycle operation. The sector  
erase command sequence is initiated by writing two  
unlock cycles, followed by a set-up command. Two  
additional unlock write cycles are then followed by the  
address of the sector to be erased, and the sector  
erase command. Table 5 shows the address and data  
requirements for the sector erase command sequence.  
in progress  
Verify Data?  
Yes  
No  
No  
The device does not require the system to preprogram  
the memory prior to erase. The Embedded Erase algo-  
rithm automatically programs and verifies the sector for  
an all zero data pattern prior to electrical erase. The  
system is not required to provide any controls or  
timings during these operations.  
Increment Address  
Last Address?  
Yes  
Programming  
Completed  
After the command sequence is written, a sector erase  
time-out of 50 µs begins. During the time-out period,  
additional sector addresses and sector erase com-  
mands may be written. Loading the sector erase buffer  
may be done in any sequence, and the number of  
sectors may be from one sector to all sectors. The time  
between these additional cycles must be less than 50  
μs, otherwise the last address and command might not  
be accepted, and erasure may begin. It is recom-  
mended that processor interrupts be disabled during  
this time to ensure all commands are accepted. The  
interrupts can be re-enabled after the last Sector Erase  
command is written. If the time between additional  
sector erase commands can be assumed to be less  
than 50 µs, the system need not monitor DQ3. Any  
command other than Sector Erase or Erase  
Suspend during the time-out period resets the  
device to reading array data. The system must  
rewrite the command sequence and any additional  
sector addresses and commands.  
Note: See Table 5 for program command sequence.  
Figure 3. Program Operation  
Chip Erase Command Sequence  
Chip erase is a six bus cycle operation. The chip erase  
command sequence is initiated by writing two unlock  
cycles, followed by a set-up command. Two additional  
unlock write cycles are then followed by the chip erase  
command, which in turn invokes the Embedded Erase  
algorithm. The device does not require the system to  
preprogram prior to erase. The Embedded Erase algo-  
rithm automatically preprograms and verifies the entire  
memory for an all zero data pattern prior to electrical  
erase. The system is not required to provide any con-  
trols or timings during these operations. Table 5 shows  
the address and data requirements for the chip erase  
command sequence.  
The system can monitor DQ3 to determine if the sector  
erase timer has timed out. (See the “DQ3: Sector Erase  
Timer” section.) The time-out begins from the rising  
edge of the final WE# pulse in the command sequence.  
Any commands written to the chip during the  
Embedded Erase algorithm are ignored. Note that a  
hardware reset during the chip erase operation imme-  
diately terminates the operation. The Chip Erase  
Once the sector erase operation has begun, only the  
Erase Suspend command is valid. All other commands  
are ignored. Note that a hardware reset during the  
16  
Am29LV004B  
21522D5 October 11, 2006  
D A T A S H E E T  
sector erase operation immediately terminates the  
the status of the program operation using the DQ7 or  
DQ6 status bits, just as in the standard program oper-  
ation. See “Write Operation Status” for more  
information.  
operation. The Sector Erase command sequence  
should be reinitiated once the device has returned to  
reading array data, to ensure data integrity.  
When the Embedded Erase algorithm is complete, the  
device returns to reading array data and addresses are  
no longer latched. The system can determine the  
status of the erase operation by using DQ7, DQ6, DQ2,  
or RY/BY#. (Refer to “Write Operation Status” for infor-  
mation on these status bits.)  
The system may also write the autoselect command  
sequence when the device is in the Erase Suspend  
mode. The device allows reading autoselect codes  
even at addresses within erasing sectors, since the  
codes are not stored in the memory array. When the  
device exits the autoselect mode, the device reverts to  
the Erase Suspend mode, and is ready for another  
valid operation. See “Autoselect Command Sequence”  
for more information.  
Figure 4 illustrates the algorithm for the erase opera-  
tion. Refer to the Erase/Program Operations tables in  
the “AC Characteristics” section for parameters, and to  
Figure 16 for timing diagrams.  
The system must write the Erase Resume command  
(address bits are “don’t care”) to exit the erase suspend  
mode and continue the sector erase operation. Further  
writes of the Resume command are ignored. Another  
Erase Suspend command can be written after the  
device has resumed erasing.  
Erase Suspend/Erase Resume Commands  
The Erase Suspend command allows the system to  
interrupt a sector erase operation and then read data  
from, or program data to, any sector not selected for  
erasure. This command is valid only during the sector  
erase operation, including the 50 µs time-out period  
during the sector erase command sequence. The  
Erase Suspend command is ignored if written during  
the chip erase operation or Embedded Program algo-  
rithm. Writing the Erase Suspend command during the  
Sector Erase time-out immediately terminates the  
time-out period and suspends the erase operation.  
Addresses are “don’t-cares” when writing the Erase  
Suspend command.  
START  
Write Erase  
Command Sequence  
When the Erase Suspend command is written during a  
sector erase operation, the device requires a maximum  
of 20 µs to suspend the erase operation. However,  
when the Erase Suspend command is written during  
the sector erase time-out, the device immediately ter-  
minates the time-out period and suspends the erase  
operation.  
Data Poll  
from System  
Embedded  
Erase  
algorithm  
in progress  
No  
Data = FFh?  
After the erase operation has been suspended, the  
system can read array data from or program data to  
any sector not selected for erasure. (The device “erase  
suspends” all sectors selected for erasure.) Normal  
read and write timings and command definitions apply.  
Reading at any address within erase-suspended  
sectors produces status data on DQ7–DQ0. The  
system can use DQ7, or DQ6 and DQ2 together, to  
determine if a sector is actively erasing or is erase-sus-  
pended. See “Write Operation Status” for information  
on these status bits.  
Yes  
Erasure Completed  
Notes:  
1. See Table 5 for erase command sequence.  
2. See “DQ3: Sector Erase Timer” for more information.  
After an erase-suspended program operation is com-  
plete, the system can once again read array data within  
non-suspended sectors. The system can determine  
Figure 4. Erase Operation  
21522D5 October 11, 2006  
Am29LV004B  
17  
D A T A S H E E T  
Command Definitions  
Table 5. Am29LV004B Command Definitions  
Bus Cycles (Notes 2-4)  
Command  
Sequence  
(Note 1)  
First  
Second  
Third  
Fourth  
Fifth  
Sixth  
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data  
Read (Note 5)  
Reset (Note 6)  
Manufacturer ID  
1
1
4
4
4
RA  
XXX  
555  
555  
555  
RD  
F0  
AA  
AA  
AA  
2AA  
2AA  
2AA  
55  
55  
55  
555  
555  
555  
90  
90  
90  
X00  
X01  
X01  
01  
B5  
B6  
00  
01  
PD  
Device ID, Top Boot Block  
Auto-  
select  
Device ID, Bottom Boot Block  
(Note 7)  
Sector Protect Verify  
(Note 8)  
(SA)  
X02  
4
555  
AA  
2AA  
55  
555  
90  
Program  
4
3
2
2
6
6
1
1
555  
555  
AA  
AA  
A0  
90  
2AA  
2AA  
PA  
55  
55  
PD  
00  
55  
55  
555  
555  
A0  
20  
PA  
Unlock Bypass  
Unlock Bypass Program (Note 9)  
Unlock Bypass Reset (Note 10)  
Chip Erase  
XXX  
XXX  
555  
XXX  
2AA  
2AA  
AA  
AA  
B0  
30  
555  
555  
80  
80  
555  
555  
AA  
AA  
2AA  
2AA  
55  
55  
555  
SA  
10  
30  
Sector Erase  
555  
Erase Suspend (Note 11)  
Erase Resume (Note 12)  
XXX  
XXX  
Legend:  
X = Don’t care  
PD = Data to be programmed at location PA. Data latches on the  
rising edge of WE# or CE# pulse, whichever happens first.  
RA = Address of the memory location to be read.  
SA = Address of the sector to be verified (in autoselect mode) or  
erased. Address bits A18–A13 uniquely select any sector.  
RD = Data read from location RA during read operation.  
PA = Address of the memory location to be programmed.  
Addresses latch on the falling edge of the WE# or CE# pulse,  
whichever happens later.  
Notes:  
1. See Table 1 for description of bus operations.  
8. The data is 00h for an unprotected sector and 01h for a  
protected sector. See “Autoselect Command Sequence” for  
more information.  
2. All values are in hexadecimal.  
3. Except when reading array or autoselect data, all command  
bus cycles are write operations.  
9. The Unlock Bypass command is required prior to the Unlock  
Bypass Program command.  
4. Address bits A18–A11 are don’t cares for unlock and  
command cycles.  
10. The Unlock Bypass Reset command is required to return to  
reading array data when the device is in the unlock bypass  
mode.  
5. No unlock or command cycles required when reading array  
data.  
11. The system may read and program in non-erasing sectors, or  
enter the autoselect mode, when in the Erase Suspend  
mode. The Erase Suspend command is valid only during a  
sector erase operation.  
6. The Reset command is required to return to reading array  
data when device is in the autoselect mode, or if DQ5 goes  
high (while the device is providing status data).  
7. The fourth cycle of the autoselect command sequence is a  
read cycle.  
12. The Erase Resume command is valid only during the Erase  
Suspend mode.  
18  
Am29LV004B  
21522D5 October 11, 2006  
D A T A S H E E T  
WRITE OPERATION STATUS  
The device provides several bits to determine the  
status of a write operation: DQ2, DQ3, DQ5, DQ6,  
DQ7, and RY/BY#. Table 6 and the following subsec-  
tions describe the functions of these bits. DQ7,  
RY/BY#, and DQ6 each offer a method for determining  
whether a program or erase operation is complete or in  
progress. These three bits are discussed first.  
Table 6 shows the outputs for Data# Polling on DQ7.  
Figure 5 shows the Data# Polling algorithm.  
START  
DQ7: Data# Polling  
The Data# Polling bit, DQ7, indicates to the host  
system whether an Embedded Algorithm is in progress  
or completed, or whether the device is in Erase Sus-  
pend. Data# Polling is valid after the rising edge of the  
final WE# pulse in the program or erase command  
sequence.  
Read DQ7–DQ0  
Addr = VA  
Yes  
DQ7 = Data?  
During the Embedded Program algorithm, the device  
outputs on DQ7 the complement of the datum pro-  
grammed to DQ7. This DQ7 status also applies to  
programming during Erase Suspend. When the  
Embedded Program algorithm is complete, the device  
outputs the datum programmed to DQ7. The system  
must provide the program address to read valid status  
information on DQ7. If a program address falls within a  
protected sector, Data# Polling on DQ7 is active for  
approximately 1 µs, then the device returns to reading  
array data.  
No  
No  
DQ5 = 1?  
Yes  
During the Embedded Erase algorithm, Data# Polling  
produces a “0” on DQ7. When the Embedded Erase  
algorithm is complete, or if the device enters the Erase  
Suspend mode, Data# Polling produces a “1” on DQ7.  
This is analogous to the complement/true datum output  
described for the Embedded Program algorithm: the  
erase function changes all the bits in a sector to “1”;  
prior to this, the device outputs the “complement,or  
“0.The system must provide an address within any of  
the sectors selected for erasure to read valid status  
information on DQ7.  
Read DQ7–DQ0  
Addr = VA  
Yes  
DQ7 = Data?  
No  
PASS  
FAIL  
After an erase command sequence is written, if all  
sectors selected for erasing are protected, Data#  
Polling on DQ7 is active for approximately 100 µs, then  
the device returns to reading array data. If not all  
selected sectors are protected, the Embedded Erase  
algorithm erases the unprotected sectors, and ignores  
the selected sectors that are protected.  
Notes:  
1. VA = Valid address for programming. During a sector  
erase operation, a valid address is an address within any  
sector selected for erasure. During chip erase, a valid  
address is any non-protected sector address.  
When the system detects DQ7 has changed from the  
complement to true data, it can read valid data at DQ7–  
DQ0 on the following read cycles. This is because DQ7  
may change asynchronously with DQ0–DQ6 while  
Output Enable (OE#) is asserted low. Figure 17, Data#  
Polling Timings (During Embedded Algorithms), in the  
“AC Characteristics” section illustrates this.  
2. DQ7 should be rechecked even if DQ5 = “1” because  
DQ7 may change simultaneously with DQ5.  
Figure 5. Data# Polling Algorithm  
21522D5 October 11, 2006  
Am29LV004B  
19  
D A T A S H E E T  
Table 6 shows the outputs for Toggle Bit I on DQ6.  
RY/BY#: Ready/Busy#  
Figure 6 shows the toggle bit algorithm. Figure 18 in the  
“AC Characteristics” section shows the toggle bit timing  
diagrams. Figure 19 shows the differences between  
DQ2 and DQ6 in graphical form. See also the subsec-  
tion on DQ2: Toggle Bit II.  
The RY/BY# is a dedicated, open-drain output pin that  
indicates whether an Embedded Algorithm is in  
progress or complete. The RY/BY# status is valid after  
the rising edge of the final WE# pulse in the command  
sequence. Since RY/BY# is an open-drain output,  
several RY/BY# pins can be tied together in parallel  
DQ2: Toggle Bit II  
with a pull-up resistor to V  
.
CC  
The “Toggle Bit II” on DQ2, when used with DQ6, indi-  
cates whether a particular sector is actively erasing  
(that is, the Embedded Erase algorithm is in progress),  
or whether that sector is erase-suspended. Toggle Bit  
II is valid after the rising edge of the final WE# pulse in  
the command sequence.  
If the output is low (Busy), the device is actively erasing  
or programming. (This includes programming in the  
Erase Suspend mode.) If the output is high (Ready),  
the device is ready to read array data (including during  
the Erase Suspend mode), or is in the standby mode.  
Table 6 shows the outputs for RY/BY#. Figures 14, 15  
and 16 shows RY/BY# for reset, program, and erase  
operations, respectively.  
DQ2 toggles when the system reads at addresses  
within those sectors that have been selected for era-  
sure. (The system may use either OE# or CE# to  
control the read cycles.) But DQ2 cannot distinguish  
whether the sector is actively erasing or is erase-sus-  
pended. DQ6, by comparison, indicates whether the  
device is actively erasing, or is in Erase Suspend, but  
cannot distinguish which sectors are selected for era-  
sure. Thus, both status bits are required for sector and  
mode information. Refer to Table 6 to compare outputs  
for DQ2 and DQ6.  
DQ6: Toggle Bit I  
Toggle Bit I on DQ6 indicates whether an Embedded  
Program or Erase algorithm is in progress or complete,  
or whether the device has entered the Erase Suspend  
mode. Toggle Bit I may be read at any address, and is  
valid after the rising edge of the final WE# pulse in the  
command sequence (prior to the program or erase  
operation), and during the sector erase time-out.  
Figure 6 shows the toggle bit algorithm in flowchart  
form, and the section “DQ2: Toggle Bit II” explains the  
algorithm. See also the DQ6: Toggle Bit I subsection.  
Figure 18 shows the toggle bit timing diagram. Figure  
19 shows the differences between DQ2 and DQ6 in  
graphical form.  
During an Embedded Program or Erase algorithm  
operation, successive read cycles to any address  
cause DQ6 to toggle. The system may use either OE#  
or CE# to control the read cycles. When the operation  
is complete, DQ6 stops toggling.  
After an erase command sequence is written, if all  
sectors selected for erasing are protected, DQ6 toggles  
for approximately 100 µs, then returns to reading array  
data. If not all selected sectors are protected, the  
Embedded Erase algorithm erases the unprotected  
sectors, and ignores the selected sectors that are  
protected.  
Reading Toggle Bits DQ6/DQ2  
Refer to Figure 6 for the following discussion. When-  
ever the system initially begins reading toggle bit  
status, it must read DQ7–DQ0 at least twice in a row to  
determine whether a toggle bit is toggling. Typically, the  
system would note and store the value of the toggle bit  
after the first read. After the second read, the system  
would compare the new value of the toggle bit with the  
first. If the toggle bit is not toggling, the device has com-  
pleted the program or erase operation. The system can  
read array data on DQ7–DQ0 on the following read  
cycle.  
The system can use DQ6 and DQ2 together to deter-  
mine whether a sector is actively erasing or is erase-  
suspended. When the device is actively erasing (that is,  
the Embedded Erase algorithm is in progress), DQ6  
toggles. When the device enters the Erase Suspend  
mode, DQ6 stops toggling. However, the system must  
also use DQ2 to determine which sectors are erasing  
or erase-suspended. Alternatively, the system can use  
DQ7 (see the subsection on DQ7: Data# Polling).  
However, if after the initial two read cycles, the system  
determines that the toggle bit is still toggling, the  
system also should note whether the value of DQ5 is  
high (see the section on DQ5). If it is, the system  
should then determine again whether the toggle bit is  
toggling, since the toggle bit may have stopped tog-  
gling just as DQ5 went high. If the toggle bit is no longer  
toggling, the device has successfully completed the  
program or erase operation. If it is still toggling, the  
device did not completed the operation successfully,  
and the system must write the reset command to return  
to reading array data.  
If a program address falls within a protected sector,  
DQ6 toggles for approximately 2 µs after the program  
command sequence is written, then returns to reading  
array data.  
DQ6 also toggles during the erase-suspend-program  
mode, and stops toggling once the Embedded  
Program algorithm is complete.  
20  
Am29LV004B  
21522D5 October 11, 2006  
D A T A S H E E T  
The remaining scenario is that the system initially  
determines that the toggle bit is toggling and DQ5 has  
not gone high. The system may continue to monitor the  
toggle bit and DQ5 through successive read cycles,  
determining the status as described in the previous  
paragraph. Alternatively, it may choose to perform  
other system tasks. In this case, the system must start  
at the beginning of the algorithm when it returns to  
determine the status of the operation (top of Figure 6).  
START  
Read DQ7–DQ0  
(Note 1)  
Read DQ7–DQ0  
DQ5: Exceeded Timing Limits  
DQ5 indicates whether the program or erase time has  
exceeded a specified internal pulse count limit. Under  
these conditions DQ5 produces a “1.This is a failure  
condition that indicates the program or erase cycle was  
not successfully completed.  
No  
Toggle Bit  
= Toggle?  
The DQ5 failure condition may appear if the system  
tries to program a “1” to a location that is previously pro-  
grammed to “0.Only an erase operation can change  
a “0” back to a “1.Under this condition, the device  
halts the operation, and when the operation has  
exceeded the timing limits, DQ5 produces a “1.”  
Yes  
No  
DQ5 = 1?  
Yes  
Under both these conditions, the system must issue the  
reset command to return the device to reading array  
data.  
(Notes  
1, 2)  
Read DQ7–DQ0  
Twice  
DQ3: Sector Erase Timer  
After writing a sector erase command sequence, the  
system may read DQ3 to determine whether or not an  
erase operation has begun. (The sector erase timer  
does not apply to the chip erase command.) If addi-  
tional sectors are selected for erasure, the entire time-  
out also applies after each additional sector erase com-  
mand. When the time-out is complete, DQ3 switches  
from “0” to “1.If the time between additional sector  
erase commands from the system can be assumed to  
be less than 50 µs, the system need not monitor DQ3.  
See also the “Sector Erase Command Sequence”  
section.  
Toggle Bit  
= Toggle?  
No  
Yes  
Program/Erase  
Operation Not  
Complete, Write  
Reset Command  
Program/Erase  
Operation Complete  
Notes:  
After the sector erase command sequence is written,  
the system should read the status on DQ7 (Data#  
Polling) or DQ6 (Toggle Bit I) to ensure the device has  
accepted the command sequence, and then read DQ3.  
If DQ3 is “1”, the internally controlled erase cycle has  
begun; all further commands (other than Erase Sus-  
pend) are ignored until the erase operation is complete.  
If DQ3 is “0”, the device will accept additional sector  
erase commands. To ensure the command has been  
accepted, the system software should check the status  
of DQ3 prior to and following each subsequent sector  
erase command. If DQ3 is high on the second status  
check, the last command might not have been  
accepted. Table 6 shows the outputs for DQ3.  
1. Read toggle bit twice to determine whether or not it is  
toggling. See text.  
2. Recheck toggle bit because it may stop toggling as DQ5  
changes to “1” . See text.  
Figure 6. Toggle Bit Algorithm  
21522D5 October 11, 2006  
Am29LV004B  
21  
D A T A S H E E T  
Table 6. Write Operation Status  
DQ7  
DQ5  
DQ2  
Operation  
(Note 2)  
DQ6  
(Note 1)  
DQ3  
N/A  
1
(Note 2)  
RY/BY#  
Embedded Program Algorithm  
Embedded Erase Algorithm  
DQ7#  
0
Toggle  
Toggle  
0
0
No toggle  
Toggle  
0
0
Standard  
Mode  
Reading within Erase  
Suspended Sector  
1
No toggle  
0
N/A  
Toggle  
1
Erase  
Suspend Reading within Non-Erase  
Data  
Data  
Data  
0
Data  
N/A  
Data  
N/A  
1
0
Mode  
Suspended Sector  
Erase-Suspend-Program  
DQ7#  
Toggle  
Notes:  
1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.  
See “DQ5: Exceeded Timing Limits” for more information.  
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.  
22  
Am29LV004B  
21522D5 October 11, 2006  
D A T A S H E E T  
ABSOLUTE MAXIMUM RATINGS  
Storage Temperature  
Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C  
20 ns  
20 ns  
Ambient Temperature  
with Power Applied. . . . . . . . . . . . . . –65°C to +125°C  
+0.8 V  
Voltage with Respect to Ground  
–0.5 V  
–2.0 V  
V
(Note 1) . . . . . . . . . . . . . . . . .0.5 V to +4.0 V  
CC  
A9, OE#,  
and RESET# (Note 2). . . . . . . . .0.5 V to +12.5 V  
20 ns  
All other pins  
(Note 1). . . . . . . . . . . . . . . . . 0.5 V to V +0.5 V  
CC  
Figure 7. Maximum Negative  
Overshoot Waveform  
Output Short Circuit Current (Note 3) . . . . . . 200 mA  
Notes:  
1. Minimum DC voltage on input or I/O pins is –0.5 V. During  
voltage transitions, input or I/O pins may overshoot VSS to  
–2.0 V for periods of up to 20 ns. See Figure 7. Maximum  
DC voltage on input or I/O pins is VCC +0.5 V. During  
voltage transitions, input or I/O pins may overshoot to VCC  
+2.0 V for periods up to 20 ns. See Figure 8.  
20 ns  
VCC  
2. Minimum DC input voltage on pins A9, OE#, and RESET#  
is –0.5 V. During voltage transitions, A9, OE#, and  
RESET# may overshoot VSS to –2.0 V for periods of up to  
20 ns. See Figure 7. Maximum DC input voltage on pin A9  
is +12.5 V which may overshoot to 14.0 V for periods up  
to 20 ns.  
+2.0 V  
VCC  
+0.5 V  
2.0 V  
20 ns  
20 ns  
3. No more than one output may be shorted to ground at a  
time. Duration of the short circuit should not be greater  
than one second.  
Figure 8. Maximum Positive  
Overshoot Waveform  
Stresses above those listed under “Absolute Maximum  
Ratings” may cause permanent damage to the device. This is  
a stress rating only; functional operation of the device at  
these or any other conditions above those indicated in the  
operational sections of this data sheet is not implied.  
Exposure of the device to absolute maximum rating  
conditions for extended periods may affect device reliability.  
OPERATING RANGES  
Commercial (C) Devices  
Ambient Temperature (T ) . . . . . . . . . . . 0°C to +70°C  
A
Industrial (I) Devices  
Ambient Temperature (T ) . . . . . . . . . –40°C to +85°C  
A
Extended (E) Devices  
Ambient Temperature (T ) . . . . . . . . –55°C to +125°C  
A
V
Supply Voltages  
CC  
V
for all devices . . . . . . . . . . . . . . . . .2.7 V to 3.6 V  
CC  
Operating ranges define those limits between which the func-  
tionality of the device is guaranteed.  
21522D5 October 11, 2006  
Am29LV004B  
23  
D A T A S H E E T  
Test Conditions  
DC CHARACTERISTICS  
CMOS Compatible  
Parameter  
Description  
Min  
Typ  
Max  
±1.0  
35  
Unit  
µA  
VIN = VSS to VCC  
,
ILI  
Input Load Current  
VCC = VCC max  
ILIT  
ILO  
A9 Input Load Current  
Output Leakage Current  
VCC = VCC max; A9 = 12.5 V  
µA  
VOUT = VSS to VCC  
,
±1.0  
µA  
VCC = VCC max  
5 MHz  
1 MHz  
7
2
12  
4
VCC Active Read Current  
(Notes 1, 2)  
ICC1  
CE# = VIL, OE# = VIH  
mA  
mA  
VCC Active Write Current  
(Notes 2, 3, 5)  
ICC2  
CE# = VIL, OE# = VIH  
15  
30  
ICC3  
ICC4  
VCC Standby Current (Note 2)  
VCC Reset Current (Note 2)  
CE#, RESET# = VCC±0.3 V  
RESET# = VSS ± 0.3 V  
0.2  
0.2  
5
5
µA  
µA  
Automatic Sleep Mode  
(Notes 2, 4)  
VIH = VCC ± 0.3 V;  
VIL = VSS ± 0.3 V  
ICC5  
0.2  
5
µA  
VIL  
VIH  
Input Low Voltage  
Input High Voltage  
–0.5  
0.8  
V
V
0.7 x VCC  
VCC + 0.3  
Voltage for Autoselect and  
Temporary Sector Unprotect  
VID  
V
CC = 3.3 V  
11.5  
12.5  
0.45  
V
VOL  
VOH1  
VOH2  
Output Low Voltage  
IOL = 4.0 mA, VCC = VCC min  
IOH = –2.0 mA, VCC = VCC min  
IOH = –100 µA, VCC = VCC min  
V
V
0.85 VCC  
VCC–0.4  
Output High Voltage  
Low VCC Lock-Out Voltage  
(Note 5)  
VLKO  
2.3  
2.5  
V
Notes:  
1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH. Typical VCC is 3.0 V.  
2. Maximum ICC specifications are tested with VCC = VCCmax  
.
3. ICC active while Embedded Erase or Embedded Program is in progress.  
4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns.  
5. Not 100% tested.  
24  
Am29LV004B  
21522D5 October 11, 2006  
D A T A S H E E T  
DC CHARACTERISTICS (continued)  
Zero Power Flash  
20  
15  
10  
5
0
0
500  
1000  
1500  
2000  
2500  
3000  
3500  
4000  
Time in ns  
Note: Addresses are switching at 1 MHz  
Figure 9.  
I
Current vs. Time (Showing Active and Automatic Sleep Currents)  
CC1  
10  
8
3.6 V  
2.7 V  
6
4
2
0
1
2
3
4
5
Frequency in MHz  
Note: T = 25 °C  
Figure 10. Typical I  
vs. Frequency  
CC1  
21522D5 October 11, 2006  
Am29LV004B  
25  
D A T A S H E E T  
TEST CONDITIONS  
Table 7. Test Specifications  
-90,  
3.3 V  
Test Condition  
-70  
-120  
Unit  
2.7 kΩ  
Output Load  
1 TTL gate  
Device  
Under  
Test  
Output Load Capacitance, CL  
(including jig capacitance)  
30  
100  
pF  
C
L
6.2 kΩ  
Input Rise and Fall Times  
Input Pulse Levels  
5
0.0–3.0  
ns  
V
Input timing measurement  
reference levels  
1.5  
1.5  
V
V
Note: Diodes are IN3064 or equivalent  
Output timing measurement  
reference levels  
Figure 11. Test Setup  
KEY TO SWITCHING WAVEFORMS  
WAVEFORM  
INPUTS  
OUTPUTS  
Steady  
Changing from H to L  
Changing from L to H  
Don’t Care, Any Change Permitted  
Does Not Apply  
Changing, State Unknown  
Center Line is High Impedance State (High Z)  
3.0 V  
0.0 V  
1.5 V  
1.5 V  
Input  
Measurement Level  
Output  
Figure 12. Input Waveforms and Measurement Levels  
26  
Am29LV004B  
21522D5 October 11, 2006  
D A T A S H E E T  
AC CHARACTERISTICS  
Read Operations  
Parameter  
Speed Option  
JEDEC  
Std  
Description  
Test Setup  
Min  
-70  
-90  
-120  
Unit  
tAVAV  
tRC  
Read Cycle Time (Note 1)  
70  
90  
120  
ns  
CE# = VIL  
OE# = VIL  
tAVQV  
tACC Address to Output Delay  
Max  
70  
90  
120  
ns  
tELQV  
tGLQV  
tEHQZ  
tGHQZ  
tCE  
tOE  
tDF  
tDF  
Chip Enable to Output Delay  
OE# = VIL  
Max  
Max  
Max  
Max  
Min  
70  
30  
25  
25  
90  
35  
30  
30  
0
120  
50  
ns  
ns  
ns  
ns  
ns  
Output Enable to Output Delay  
Chip Enable to Output High Z (Note 1)  
Output Enable to Output High Z (Note 1)  
30  
30  
Read  
Output Enable  
Hold Time (Note 1)  
tOEH  
Toggle and  
Data# Polling  
Min  
Min  
10  
0
ns  
ns  
Output Hold Time From Addresses, CE# or  
OE#, Whichever Occurs First (Note 1)  
tAXQX  
tOH  
Notes:  
1. Not 100% tested.  
2. See Figure 11andTable 7 for test specifications.  
tRC  
Addresses Stable  
Addresses  
CE#  
tACC  
tDF  
tOE  
OE#  
tOEH  
WE#  
tCE  
tOH  
HIGH Z  
HIGH Z  
Output Valid  
Outputs  
RESET#  
RY/BY#  
0 V  
Figure 13. Read Operations Timings  
21522D5 October 11, 2006  
Am29LV004B  
27  
D A T A S H E E T  
AC CHARACTERISTICS  
Hardware Reset (RESET#)  
Parameter  
JEDEC  
Std  
Description  
Test Setup  
Max  
All Speed Options  
Unit  
RESET# Pin Low (During Embedded  
Algorithms) to Read or Write (See Note)  
tREADY  
20  
µs  
RESET# Pin Low (NOT During Embedded  
Algorithms) to Read or Write (See Note)  
tREADY  
Max  
500  
ns  
tRP  
tRH  
RESET# Pulse Width  
Min  
Min  
Min  
Min  
500  
50  
20  
0
ns  
ns  
µs  
ns  
RESET# High Time Before Read (See Note)  
tRPD RESET# Low to Standby Mode  
tRB RY/BY# Recovery Time  
Note: Not 100% tested.  
RY/BY#  
CE#, OE#  
RESET#  
tRH  
tRP  
tReady  
Reset Timings NOT during Embedded Algorithms  
Reset Timings during Embedded Algorithms  
tReady  
RY/BY#  
tRB  
CE#, OE#  
RESET#  
tRP  
Figure 14. RESET# Timings  
28  
Am29LV004B  
21522D5 October 11, 2006  
D A T A S H E E T  
AC CHARACTERISTICS  
Erase/Program Operations  
Parameter  
Speed Options  
JEDEC  
tAVAV  
Std  
tWC  
tAH  
Description  
Write Cycle Time (Note 1)  
-70  
70  
45  
35  
35  
-90  
90  
45  
45  
35  
0
-120  
120  
50  
Unit  
ns  
Min  
Min  
Min  
Min  
Min  
Min  
Min  
tWLAX  
tDVWH  
tWLWH  
tAVWL  
tWHDX  
Address Hold Time  
Data Setup Time  
ns  
tDS  
50  
ns  
tWP  
tAS  
tDH  
tOES  
Write Pulse Width  
Address Setup Time  
Data Hold Time  
50  
ns  
ns  
0
ns  
Output Enable Setup Time  
0
ns  
Read Recovery Time Before Write  
(OE# High to WE# Low)  
tGHWL  
tGHWL  
Min  
0
ns  
tELWL  
tWHEH  
tCS  
tCH  
CE# Setup Time  
Min  
Min  
Min  
Typ  
Typ  
Min  
Min  
Max  
0
0
ns  
ns  
ns  
µs  
sec  
µs  
ns  
ns  
CE# Hold Time  
tWHWL  
tWHWH1  
tWHWH2  
tWPH  
Write Pulse Width High  
30  
9
tWHWH1 Programming Operation (Note 2)  
tWHWH2 Sector Erase Operation (Note 2)  
0.7  
50  
0
tVCS  
tRB  
VCC Setup Time (Note 1)  
Recovery Time from RY/BY#  
Program/Erase Valid to RY/BY# Delay  
tBUSY  
90  
Notes:  
1. Not 100% tested.  
2. See the “Erase and Programming Performance” section for more information.  
21522D5 October 11, 2006  
Am29LV004B  
29  
D A T A S H E E T  
AC CHARACTERISTICS  
Program Command Sequence (last two cycles)  
Read Status Data (last two cycles)  
tAS  
PA  
tWC  
Addresses  
555h  
PA  
PA  
tAH  
CE#  
OE#  
tCH  
tWHWH1  
tWP  
WE#  
Data  
tWPH  
tCS  
tDS  
tDH  
PD  
DOUT  
A0h  
Status  
tBUSY  
tRB  
RY/BY#  
VCC  
tVCS  
Note: PA = program address, PD = program data, DOUT is the true data at the program address.  
Figure 15. Program Operation Timings  
30  
Am29LV004B  
21522D5 October 11, 2006  
D A T A S H E E T  
AC CHARACTERISTICS  
Erase Command Sequence (last two cycles)  
Read Status Data  
VA  
tAS  
SA  
tWC  
VA  
Addresses  
CE#  
2AAh  
555h for chip erase  
tAH  
tCH  
OE#  
tWP  
WE#  
tWPH  
tWHWH2  
tCS  
tDS  
tDH  
In  
Data  
Complete  
55h  
30h  
Progress  
10 for Chip Erase  
tBUSY  
tRB  
RY/BY#  
VCC  
tVCS  
Note: SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”).  
Figure 16. Chip/Sector Erase Operation Timings  
21522D5 October 11, 2006  
Am29LV004B  
31  
D A T A S H E E T  
AC CHARACTERISTICS  
tRC  
VA  
Addresses  
VA  
VA  
tACC  
tCE  
CE#  
tCH  
tOE  
OE#  
WE#  
tOEH  
tDF  
tOH  
High Z  
High Z  
DQ7  
Valid Data  
Complement  
Complement  
Status Data  
True  
DQ0–DQ6  
Valid Data  
Status Data  
True  
tBUSY  
RY/BY#  
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data  
read cycle.  
Figure 17. Data# Polling Timings (During Embedded Algorithms)  
tRC  
Addresses  
CE#  
VA  
tACC  
tCE  
VA  
VA  
VA  
tCH  
tOE  
OE#  
WE#  
tOEH  
tDF  
tOH  
High Z  
DQ6/DQ2  
RY/BY#  
Valid Status  
(first read)  
Valid Status  
Valid Status  
Valid Data  
(second read)  
(stops toggling)  
tBUSY  
Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read  
cycle, and array data read cycle.  
Figure 18. Toggle Bit Timings (During Embedded Algorithms)  
32  
Am29LV004B  
21522D5 October 11, 2006  
D A T A S H E E T  
AC CHARACTERISTICS  
Enter  
Embedded  
Erasing  
Erase  
Suspend  
Enter Erase  
Suspend Program  
Erase  
Resume  
Erase  
Erase Suspend  
Read  
Erase  
Suspend  
Program  
Erase  
Complete  
WE#  
Erase  
Erase Suspend  
Read  
DQ6  
DQ2  
Note: The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an  
erase-suspended sector.  
Figure 19. DQ2 vs. DQ6  
Temporary Sector Unprotect  
Parameter  
JEDEC  
Std  
Description  
All Speed Options  
Unit  
tVIDR  
VID Rise and Fall Time (See Note)  
Min  
Min  
500  
ns  
RESET# Setup Time for Temporary Sector  
Unprotect  
tRSP  
4
µs  
Note: Not 100% tested.  
12 V  
RESET#  
0 or 3 V  
0 or 3 V  
tVIDR  
tVIDR  
Program or Erase Command Sequence  
CE#  
WE#  
tRSP  
RY/BY#  
Figure 20. Temporary Sector Unprotect Timing Diagram  
21522D5 October 11, 2006  
Am29LV004B  
33  
D A T A S H E E T  
AC CHARACTERISTICS  
VID  
VIH  
RESET#  
SA, A6,  
A1, A0  
Valid*  
Sector Protect/Unprotect  
60h 60h  
Valid*  
Valid*  
Status  
Verify  
40h  
Data  
Sector Protect: 150 µs  
Sector Unprotect: 15 ms  
1 µs  
CE#  
WE#  
OE#  
* For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.  
Figure 21. Sector Protect/Unprotect Timing Diagram  
34  
Am29LV004B  
21522D5 October 11, 2006  
D A T A S H E E T  
AC CHARACTERISTICS  
Alternate CE# Controlled Erase/Program Operations  
Parameter  
Speed Options  
JEDEC  
tAVAV  
Std  
tWC  
tAH  
Description  
Write Cycle Time (Note 1)  
Address Hold Time  
Data Setup Time  
-70  
70  
45  
35  
35  
-90  
90  
45  
45  
35  
0
-120  
120  
50  
Unit  
ns  
Min  
Min  
Min  
Min  
Min  
Min  
Min  
tELAX  
tDVEH  
tELEH  
tAVEL  
ns  
tDS  
50  
ns  
tCP  
CE# Pulse Width  
50  
ns  
tAS  
Address Setup Time  
Data Hold Time  
ns  
tEHDX  
tDH  
tOES  
0
ns  
Output Enable Setup Time  
0
ns  
Read Recovery Time Before Write  
(OE# High to WE# Low)  
tGHEL  
tGHEL  
Min  
0
ns  
tWLEL  
tEHWH  
tEHEL  
tWS  
tWH  
WE# Setup Time  
Min  
Min  
Min  
Typ  
Typ  
0
0
ns  
ns  
WE# Hold Time  
tCPH  
CE# Pulse Width High  
Programming Operation (Note 2)  
Sector Erase Operation (Note 2)  
30  
9
ns  
tWHWH1  
tWHWH2  
Notes:  
tWHWH1  
tWHWH2  
µs  
0.7  
sec  
1. Not 100% tested.  
2. See the “Erase and Programming Performance” section for more information.  
21522D5 October 11, 2006  
Am29LV004B  
35  
D A T A S H E E T  
AC CHARACTERISTICS  
555 for program  
PA for program  
2AA for erase  
SA for sector erase  
555 for chip erase  
Data# Polling  
Addresses  
PA  
tWC  
tWH  
tAS  
tAH  
WE#  
OE#  
tGHEL  
tWHWH1 or 2  
tCP  
CE#  
Data  
tWS  
tCPH  
tDS  
tBUSY  
tDH  
DQ7#  
DOUT  
tRH  
A0 for program  
55 for erase  
PD for program  
30 for sector erase  
10 for chip erase  
RESET#  
RY/BY#  
Notes:  
1. PA = Program Address, PD = Program Data, DQ7# = complement of the data written to the device, DOUT is the data written  
to the device.  
2. Figure indicates the last two bus cycles of the command sequence.  
Figure 22. Alternate CE# Controlled Write Operation Timings  
36  
Am29LV004B  
21522D5 October 11, 2006  
D A T A S H E E T  
ERASE AND PROGRAMMING PERFORMANCE  
Parameter  
Typ (Note 1)  
Max (Note 2)  
Unit  
s
Comments  
Sector Erase Time  
Chip Erase Time  
Byte Programming Time  
0.7  
7
15  
Excludes 00h programming  
prior to erasure (Note 4)  
s
9
300  
µs  
Excludes system level  
overhead (Note 5)  
Chip Programming Time  
(Note 3)  
4.5  
13.5  
s
Notes:  
1. Typical program and erase times assume the following conditions: 25°C, 3.0 V VCC, 1,000,000 cycles. Additionally,  
programming typicals assume checkerboard pattern.  
2. Under worst case conditions of 90°C, VCC = 2.7 V, 1,000,000 cycles.  
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes  
program faster than the maximum program times listed.  
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.  
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See  
Table 5 for further information on command definitions.  
6. The device has a minimum guaranteed erase and program cycle endurance of 1,000,000 cycles.  
LATCHUP CHARACTERISTICS  
Description  
Min  
Max  
Input voltage with respect to VSS on all pins except I/O pins  
(including A9, OE#, and RESET#)  
–1.0 V  
12.5 V  
Input voltage with respect to VSS on all I/O pins  
VCC Current  
–1.0 V  
VCC + 1.0 V  
+100 mA  
–100 mA  
Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time.  
TSOP AND SO PIN CAPACITANCE  
Parameter  
Symbol  
Parameter Description  
Input Capacitance  
Test Setup  
VIN = 0  
Typ  
6
Max  
7.5  
12  
Unit  
pF  
CIN  
COUT  
CIN2  
Output Capacitance  
Control Pin Capacitance  
VOUT = 0  
VIN = 0  
8.5  
7.5  
pF  
9
pF  
Notes:  
1. Sampled, not 100% tested.  
2. Test conditions TA = 25°C, f = 1.0 MHz.  
DATA RETENTION  
Parameter  
Test Conditions  
Min  
10  
Unit  
Years  
Years  
150°C  
125°C  
Minimum Pattern Data Retention Time  
20  
21522D5 October 11, 2006  
Am29LV004B  
37  
D A T A S H E E T  
PHYSICAL DIMENSIONS*  
TS 040—40-Pin Standard TSOP  
Dwg rev AA; 10/99  
* For reference only. BSC is an ANSI standard for Basic Space Centering.  
38  
Am29LV004B  
21522D5 October 11, 2006  
D A T A S H E E T  
REVISION SUMMARY  
Revision A (January 1998)  
Revision D (November 18, 1999)  
Initial release.  
AC Characteristics—Figure 15. Program  
Operations Timing and Figure 16. Chip/Sector  
Erase Operations  
Revision B (June 1998)  
Expanded data sheet from Advanced Information to  
Preliminary version.  
Deleted t  
high.  
and changed OE# waveform to start at  
GHWL  
Distinctive Characteristics  
Physical Dimensions  
Changed “Manufactured on 0.35 µm process technology”  
to “Manufactured on 0.32 µm process technology”.  
Replaced figures with more detailed illustrations.  
Revision D+1 (November 13, 2000)  
Global  
General Description  
Second paragraph: Changed “This device is manufac-  
tured using AMD’s 0.35 µm process technology” to  
“This device is manufactured using AMD’s 0.32 µm  
process technology”.  
Added table of contents. Deleted burn-in option from  
Ordering Information section.  
Revision D+2 (March 9, 2005)  
Revision C (January 1999)  
Global  
Ordering Information  
Added temperature ranges for D, F, and K. Added valid  
combinations ED, EF, and EK.  
Removed the -80 speed option.  
Distinctive Characteristics  
Revision D+3 (January 10, 2006)  
Global  
Added bullet for 20-year data retention at 125°C.  
DC Characteristics—CMOS Compatible  
Removed Reverse TSOP  
I
, I  
, I  
, I  
, I  
: Added Note 2 “Maximum  
CC1 CC2 CC3 CC4 CC5  
Revision D+4 (September 12, 2006)  
I
specifications are tested with V = V  
”.  
CCmax  
CC  
CC  
Erase and Program Operations table  
Changed t  
to a maximum specification.  
BUSY  
Revision D5 (October 11, 2006)  
Global  
Added notice on product availability.  
Colophon  
The products described in this document are designed, developed and manufactured as contemplated for general use, including without limita-  
tion, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as con-  
templated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the  
public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,  
aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for  
any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion Inc. will not be liable  
to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor  
devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design  
measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating  
conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign  
Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior au-  
thorization by the respective government entity will be required for export of those products.  
Trademarks  
Copyright © 1998–2005 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trade-  
marks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are  
for identification purposes only and may be trademarks of their respective companies.  
Copyright © 2006 Spansion Inc. All Rights Reserved. Spansion, the Spansion logo, MirrorBit, ORNAND, HD-SIM, and combinations thereof are  
trademarks of Spansion Inc. Other names are for informational purposes only and may be trademarks of their respective owners.  
21522D5 October 11, 2006  
Am29LV004B  
39  

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