AM29LV040B-70FDB [SPANSION]
Flash, 512KX8, 70ns, PDSO32, REVERSE, MO-142BD, TSOP-32;
| 型号： | AM29LV040B-70FDB |
| 厂家： | 
SPANSION |
| 描述： | Flash, 512KX8, 70ns, PDSO32, REVERSE, MO-142BD, TSOP-32 光电二极管 |
| 文件： | 总34页 (文件大小：720K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Am29LV040B
4 Megabit (512 K x 8-Bit)
CMOS 3.0 Volt-only, Uniform Sector 32-Pin Flash Memory
DISTINCTIVE CHARACTERISTICS
■ Single power supply operation
■ Unlock Bypass Program Command
— Full voltage range: 2.7 to 3.6 volt read and write
operations for battery-powered applications
— Reduces overall programming time when issuing
multiple program command sequences
— Regulated voltage range: 3.0 to 3.6 volt read and
write operations and for compatibility with high
performance 3.3 volt microprocessors
■ Embedded Algorithms
— Embedded Erase algorithms automatically
preprogram and erase the entire chip or any
combination of designated sectors
■ Manufactured on 0.32 µm process technology
■ High performance
— Embedded Program algorithms automatically
writes and verifies data at specified addresses
— Full voltage range: access times as fast as 70 ns
— Regulated voltage range: access times as fast as
60 ns
■ Minimum 1,000,000 write/erase cycles
guaranteed
■ 20-year data retention at 125°C
— Reliable operation for the life of the system
■ Package option
■ Ultra low power consumption (typical values at
5 MHz)
— Automatic sleep mode: 1 µA
— Standby mode: 1 µA
— 32-pin PLCC
— Read mode: 7 mA
— 32-pin TSOP
— Program/erase mode: 15 mA
■ Compatibility with JEDEC standards
— Pinout and software compatible with single-
power supply Flash
■ Flexible sector architecture
— Eight 64 Kbyte sectors
— Superior inadvertent write protection
— Any combination of sectors can be erased;
supports full chip erase
■ Data# Polling and toggle bits
— Sector Protection features:
— Provides a software method of detecting program
or erase cycle completion
Hardware method of locking a sector to prevent
any program or erase operations within that sector
■ Erase Suspend/Resume
Sectors can be locked via programming
equipment
— Supports reading data from or programming data
to a sector not being erased
Publication# 21354 Rev: D Amendment/0
Issue Date: November 11, 1999
GENERAL DESCRIPTION
The Am29LV040B is a single power supply, 4 Mbit, 3.0
Volt-only Flash memory device organized as 524,288
bytes. The data appears on DQ0-DQ7. The device is
available in 32-pin PLCC and 32-pin TSOP packages. All
read, erase, and program operations are accomplished
using only a single power supply. The device can also be
programmed in standard EPROM programmers.
preprograms the array (if it is not already programmed)
before executing the erase operation. During erase, the
device automatically times the erase pulse widths and
verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by reading the DQ7 (Data#
Polling) and DQ6 (toggle) status bits. After a program
or erase cycle has been completed, the device is ready
to read array data or accept another command.
The device offers access times of 60, 70, 90, and 120 ns
allowing high speed microprocessors to operate without
wait states. To eliminate bus contention, the device has
separate control pins—chip enable (CE#), write enable
(WE#), and output enable (OE#)—to control normal
read and write operations.
The sector erase architecture allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
The device requires only a single power supply
(2.7 V–3.6V) for both read and write functions. Inter-
nally generated and regulated voltages are provided for
the program and erase operations.
Hardware data protection measures include a low
VCC detector that automatically inhibits write opera-
tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of the sectors of
memory. This is achieved via programming equipment.
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard. Com-
mands are written to the command register using
standard microprocessor write timings. Register con-
tents serve as input to an internal state-machine that
controls the erase and programming circuitry. Write
cycles also internally latch addresses and data needed
for the programming and erase operations. Reading
data out of the device is similar to reading from other
Flash or EPROM devices.
The Erase Suspend feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved.
The device offers two power-saving features. When
addresses have been stable for a specified amount of
time, the device enters the automatic sleep mode.
The system can also place the device into the standby
mode. Power consumption is greatly reduced in both
these modes.
Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithm—an internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin. The Unlock Bypass mode facili-
tates faster programming times by requiring only two
write cycles to program data instead of four.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effectiveness.
The device electrically erases all bits within a sector
simultaneously via Fowler-Nordheim tunneling. The
data is programmed using hot electron injection.
Device erasure occurs by executing the erase
command sequence. This initiates the Embedded
Erase algorithm—an internal algorithm that automatically
2
Am29LV040B
PRODUCT SELECTOR GUIDE
Family Part Number
Am29LV040B
Regulated Voltage Range: V =3.0–3.6 V
-60R
CC
Speed Options
Full Voltage Range: V = 2.7–3.6 V
-70
-90
90
90
30
-120
120
120
35
CC
Max access time, ns (t
)
60
60
30
70
70
30
ACC
Max CE# access time, ns (t
)
CE
Max OE# access time, ns (t
)
OE
Note: See “AC Characteristics” for full specifications.
BLOCK DIAGRAM
DQ0–DQ7
V
CC
Sector Switches
V
SS
Erase Voltage
Generator
Input/Output
Buffers
State
Control
WE#
Command
Register
PGM Voltage
Generator
Data
Latch
Chip Enable
Output Enable
Logic
STB
CE#
OE#
Y-Decoder
Y-Gating
STB
V
Detector
Timer
CC
Cell Matrix
X-Decoder
A0–A18
21354D-1
Am29LV040B
3
CONNECTION DIAGRAMS
4
3 2 1 32 31 30
A7
A6
5
6
A14
A13
29
28
A5
A4
A3
A2
A1
A0
7
A8
27
26
25
24
23
22
21
8
A9
32-Pin PLCC
9
A11
OE#
A10
CE#
DQ7
10
11
12
13
DQ0
16 17
19 20
18
15
14
A11
A9
A8
OE#
A10
CE#
1
2
3
32
31
30
A13
A14
A17
WE#
VCC
A18
A16
A15
A12
A7
4
5
6
7
8
9
10
11
12
13
14
15
16
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
29
28
27
26
25
24
23
22
21
20
19
18
17
32-pin Standard TSOP
A6
A5
A4
A1
A2
A3
1
2
3
A11
A9
A8
OE#
A10
CE#
32
31
30
4
5
6
7
8
9
10
11
12
13
14
15
16
A13
A14
A17
WE#
VCC
A18
A16
A15
A12
A7
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
29
28
27
26
25
24
23
22
21
20
19
18
17
32-Pin Reverse TSOP
A6
A5
A4
A1
A2
A3
21354D-2
4
Am29LV040B
PIN CONFIGURATION
LOGIC SYMBOL
A0–A18
= 19 address inputs
19
DQ0–DQ7 = 8 data inputs/outputs
A0–A18
8
CE#
OE#
WE#
VCC
=
=
=
=
Chip enable
Output enable
Write enable
DQ0–DQ7
CE#
OE#
3.0 volt-only single power supply
(see Product Selector Guide for speed
options and voltage supply tolerances)
WE#
VSS
=
Device ground
Am29LV040B
5
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combi-
nation) is formed by a combination of the elements below.
Am29LV040B
-60R
E
C
OPTIONAL PROCESSING
Blank = Standard Processing
B
=
Burn-in
(Contact an AMD representative for more information)
TEMPERATURE RANGE
C
I
=
=
=
Commercial (0°C to +70°C)
Industrial (–40°C to +85°C)
Extended (–55°C to +125°C)
E
PACKAGE TYPE
J
=
=
32-Pin Plastic Leaded Chip Carrier (PL 032)
E
32-Pin Thin Small Outline Package (TSOP)
Standard Pinout (TS 032)
F
=
32-Pin Thin Small Outline Package (TSOP)
Reverse Pinout (TSR032)
SPEED OPTION
See Product Selector Guide and Valid Combinations
DEVICE NUMBER/DESCRIPTION
Am29LV040B
4 Megabit (512 K x 8-Bit) CMOS Flash Memory
3.0 Volt-only Read, Program and Erase
Valid Combinations
Valid Combinations
Valid Combinations list configurations planned to be sup-
ported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.
AM29LV040B-60R
AM29LV040B-70
AM29LV040B-90
AM29LV040B-120
JC, JI, EC, EI, FC, FI
JC, JI, JE,
EC, EI, EE,
FC, FI, FE
6
Am29LV040B
DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register
itself does not occupy any addressable memory loca-
tion. The register is composed of latches that store the
commands, along with the address and data informa-
tion needed to execute the command. The contents of
the register serve as inputs to the internal state
machine. The state machine outputs dictate the func-
tion of the device. Table 1 lists the device bus
operations, the inputs and control levels they require,
and the resulting output. The following subsections
describe each of these operations in further detail.
Table 1. Am29LV040B Device Bus Operations
Operation
CE#
L
OE#
L
WE#
H
Addresses (Note 1)
DQ0–DQ7
Read
A
A
D
OUT
IN
IN
Write
L
H
L
D
IN
Standby
V
± 0.3 V
X
X
X
High-Z
High-Z
High-Z
CC
Output Disable
L
X
L
H
H
X
Reset
X
X
X
Sector Protect (Note 2)
Sector Unprotect (Note 2)
Temporary Sector Unprotect
H
L
Sector Address, A6 = L, A1 = H, A0 = L
Sector Address, A6 = H, A1 = H, A0 = L
D
D
, D
, D
IN
IN
OUT
OUT
L
H
L
X
X
X
A
D
IN
IN
Legend:
L = Logic Low = V , H = Logic High = V , V = 12.0 ± 0.5 V, X = Don’t Care, A = Address In, D = Data In, D = Data Out
IL
IH
ID
IN
IN
OUT
Notes:
1. Addresses are A18–A0.
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector
Protection/Unprotection” section.
Requirements for Reading Array Data
Writing Commands/Command Sequences
To read array data from the outputs, the system must
drive the CE# and OE# pins to VIL. CE# is the power
control and selects the device. OE# is the output
control and gates array data to the output pins. WE#
should remain at VIH.
To write a command or command sequence (which
includes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to VIL, and OE# to VIH.
The device features an Unlock Bypass mode to facili-
tate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are
required to program a byte, instead of four. The “Byte
Program Command Sequence” section has details on
programming data to the device using both standard
and Unlock Bypass command sequences.
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
content occurs during the power transition. No
command is necessary in this mode to obtain array
data. Standard microprocessor read cycles that assert
valid addresses on the device address inputs produce
valid data on the device data outputs. The device
remains enabled for read access until the command
register contents are altered.
An erase operation can erase one sector, multiple sec-
tors, or the entire device. Table 2 indicates the address
space that each sector occupies. A “sector address”
consists of the address bits required to uniquely select
a sector. The “Command Definitions” section has
details on erasing a sector or the entire chip, or sus-
pending/resuming the erase operation.
See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifica-
tions and to Figure 11 for the timing diagram. ICC1 in the
DC Characteristics table represents the active current
specification for reading array data.
After the system writes the autoselect command
sequence, the device enters the autoselect mode. The
system can then read autoselect codes from the
internal register (which is separate from the memory
array) on DQ7–DQ0. Standard read cycle timings apply
Am29LV040B
7
in this mode. Refer to the Autoselect Mode and Autose-
lect Command Sequence sections for more
information.
the standby mode, but the standby current will be
greater. The device requires standard access time (tCE
for read access when the device is in either of these
standby modes, before it is ready to read data.
)
ICC2 in the DC Characteristics table represents the
active current specification for the write mode. The “AC
Characteristics” section contains timing specification
tables and timing diagrams for write operations.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
ICC3 in the DC Characteristics table represents the
standby current specification.
Program and Erase Operation Status
During an erase or program operation, the system may
check the status of the operation by reading the status
bits on DQ7–DQ0. Standard read cycle timings and ICC
read specifications apply. Refer to “Write Operation
Status” for more information, and to “AC Characteris-
tics” for timing diagrams.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device
energy consumption. The device automatically enables
this mode when addresses remain stable for tACC + 30
ns. The automatic sleep mode is independent of the
CE#, WE#, and OE# control signals. Standard address
access timings provide new data when addresses are
changed. While in sleep mode, output data is latched
and always available to the system. ICC4 in the DC
Characteristics table represents the automatic sleep
mode current specification.
Standby Mode
When the system is not reading or writing to the device,
it can place the device in the standby mode. In this
mode, current consumption is greatly reduced, and the
outputs are placed in the high impedance state, inde-
pendent of the OE# input.
Output Disable Mode
The device enters the CMOS standby mode when the
CE# pin is both held at VCC ± 0.3 V. (Note that this is a
more restricted voltage range than VIH.) If CE# is held
at VIH, but not within VCC ± 0.3 V, the device will be in
When the OE# input is at VIH, output from the device is
disabled. The output pins are placed in the high imped-
ance state.
Table 2. Am29LV040BT Sector Address Table
Address Range
(in hexadecimal)
Sector
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
A18
0
A17
0
A16
0
00000h-0FFFFh
10000h-1FFFFh
20000h-2FFFFh
30000h-3FFFFh
40000h-4FFFFh
50000h-5FFFFh
60000h-6FFFFh
70000h-7FFFFh
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Table 3. In addition, when verifying sector protection,
the sector address must appear on the appropriate
highest order address bits (see Table 2). Table 3 shows
the remaining address bits that are don’t care. When all
necessary bits have been set as required, the program-
ming equipment may then read the corresponding
identifier code on DQ7–DQ0.
Autoselect Mode
The autoselect mode provides manufacturer and
device identification, and sector protection verification,
through identifier codes output on DQ7–DQ0. This
mode is primarily intended for programming equipment
to automatically match a device to be programmed with
its corresponding programming algorithm. However,
the autoselect codes can also be accessed in-system
through the command register.
To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in Table 4. This method
does not require VID. See “Command Definitions” for
details on using the autoselect mode.
When using programming equipment, the autoselect
mode requires VID (11.5 V to 12.5 V) on address pin
A9. Address pins A6, A1, and A0 must be as shown in
8
Am29LV040B
Table 3. Am29LV040B Autoselect Codes (High Voltage Method)
A18 A15
to to
CE# OE# WE# A16 A10 A9
A8
to
A7
A5
to
A2
DQ7
to
DQ0
Description
Manufacturer ID: AMD
Device ID: Am29LV040B
A6
L
A1
L
A0
L
L
L
L
L
H
H
X
X
X
X
V
V
X
X
X
X
01h
4Fh
ID
ID
L
L
H
01h
(protected)
Sector Protection Verification
L
L
H
SA
X
V
X
L
X
H
L
ID
00h
(unprotected)
L = Logic Low = V , H = Logic High = V , SA = Sector Address, X = Don’t care.
IL
IH
erasure or programming, which might otherwise be
caused by spurious system level signals during VCC
power-up and power-down transitions, or from system
noise.
Sector Protection/Unprotection
The hardware sector protection feature disables both
program and erase operations in any sector. The hard-
ware sector unprotection feature re-enables both
program and erase operations in previously protected
sectors.
Low V
Write Inhibit
CC
When VCC is less than VLKO, the device does not
accept any write cycles. This protects data during VCC
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until VCC
is greater than VLKO. The system must provide the
proper signals to the control pins to prevent uninten-
Sector protection/unprotection method intended only
for programming equipment requires VID on address
pin A9 and OE#. This method is compatible with pro-
grammer routines written for earlier 3.0 volt-only AMD
flash devices. Publication number 22168 contains
further details; contact an AMD representative to
request a copy.
tional writes when VCC is greater than VLKO
.
Write Pulse “Glitch” Protection
The device is shipped with all sectors unprotected.
AMD offers the option of programming and protecting
sectors at its factory prior to shipping the device
through AMD’s ExpressFlash™ Service. Contact an
AMD representative for details.
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
VIL, CE# = VIH or WE# = VIH. To initiate a write cycle,
CE# and WE# must be a logical zero while OE# is a
logical one.
It is possible to determine whether a sector is protected
or unprotected. See “Autoselect Mode” for details.
Hardware Data Protection
Power-Up Write Inhibit
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to Table 4 for
command definitions). In addition, the following hard-
ware data protection measures prevent accidental
If WE# = CE# = VIL and OE# = VIH during power up, the
device does not accept commands on the rising edge
of WE#. The internal state machine is automatically
reset to reading array data on power-up.
Am29LV040B
9
COMMAND DEFINITIONS
Writing specific address and data commands or
sequences into the command register initiates device
operations. Table 4 defines the valid register command
sequences. Writing incorrect address and data
values or writing them in the improper sequence
resets the device to reading array data.
however, the device ignores reset commands until the
operation is complete.
The reset command may be written between the
sequence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command must
be written to return to reading array data (also applies
to autoselect during Erase Suspend).
All addresses are latched on the falling edge of WE# or
CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in the
“AC Characteristics” section.
If DQ5 goes high during a program or erase operation,
writing the reset command returns the device to
reading array data (also applies during Erase
Suspend).
Reading Array Data
Autoselect Command Sequence
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array
data after completing an Embedded Program or
Embedded Erase algorithm.
The autoselect command sequence allows the host
system to access the manufacturer and devices codes,
and determine whether or not a sector is protected.
Table 4 shows the address and data requirements. This
method is an alternative to that shown in Table 3, which
is intended for PROM programmers and requires VID
on address bit A9.
After the device accepts an Erase Suspend command,
the device enters the Erase Suspend mode. The
system can read array data using the standard read
timings, except that if it reads at an address within
erase-suspended sectors, the device outputs status
data. After completing a programming operation in the
Erase Suspend mode, the system may once again
read array data with the same exception. See “Erase
Suspend/Erase Resume Commands” for more infor-
mation on this mode.
The autoselect command sequence is initiated by
writing two unlock cycles, followed by the autoselect
command. The device then enters the autoselect
mode, and the system may read at any address any
number of times, without initiating another command
sequence. A read cycle at address 00h retrieves the
manufacturer code. A read cycle at address 01h
returns the device code. A read cycle containing a
sector address (SA) and the address 02h returns 01h if
that sector is protected, or 00h if it is unprotected. Refer
to Table 2 for valid sector addresses.
The system must issue the reset command to re-
enable the device for reading array data if DQ5 goes
high, or while in the autoselect mode. See the “Reset
Command” section, next.
The system must write the reset command to exit the
autoselect mode and return to reading array data.
See also “Requirements for Reading Array Data” in the
“Device Bus Operations” section for more information.
The Read Operations table provides the read parame-
ters, and Figure 11 shows the timing diagram.
Byte Program Command Sequence
The byte program command sequence programs one
byte into the device. Programming is a four-bus-cycle
operation. The program command sequence is initi-
ated by writing two unlock write cycles, followed by the
program set-up command. The program address and
data are written next, which in turn initiate the
Embedded Program algorithm. The system is not
required to provide further controls or timings. The
device automatically provides internally generated
program pulses and verify the programmed cell margin.
Table 4 shows the address and data requirements for
the byte program command sequence.
Reset Command
Writing the reset command to the device resets the
device to reading array data. Address bits are don’t
care for this command.
The reset command may be written between the
sequence cycles in an erase command sequence
before erasing begins. This resets the device to reading
array data. Once erasure begins, however, the device
ignores reset commands until the operation is
complete.
When the Embedded Program algorithm is complete,
the device then returns to reading array data and
addresses are no longer latched. The system can
determine the status of the program operation by using
DQ7 or DQ6. See “Write Operation Status” for informa-
tion on these status bits.
The reset command may be written between the
sequence cycles in a program command sequence
before programming begins. This resets the device to
reading array data (also applies to programming in
Erase Suspend mode). Once programming begins,
10
Am29LV040B
Any commands written to the device during the
Embedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the program-
ming operation. The Byte Program command
sequence should be reinitiated once the device has
reset to reading array data, to ensure data integrity.
START
Write Program
Command Sequence
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
from a “0” back to a “1”. Attempting to do so may halt
the operation and set DQ5 to “1”, or cause the Data#
Polling algorithm to indicate the operation was suc-
cessful. However, a succeeding read will show that the
data is still “0”. Only erase operations can convert a “0”
to a “1”.
Data Poll
from System
Embedded
Program
algorithm
in progress
Unlock Bypass Command Sequence
Verify Data?
Yes
No
The unlock bypass feature allows the system to
program bytes to the device faster than using the stan-
dard program command sequence. The unlock bypass
command sequence is initiated by first writing two
unlock cycles. This is followed by a third write cycle
containing the unlock bypass command, 20h. The
device then enters the unlock bypass mode. A two-
cycle unlock bypass program command sequence is all
that is required to program in this mode. The first cycle
in this sequence contains the unlock bypass program
command, A0h; the second cycle contains the program
address and data. Additional data is programmed in
the same manner. This mode dispenses with the initial
two unlock cycles required in the standard program
command sequence, resulting in faster total program-
ming time. Table 4 shows the requirements for the
command sequence.
No
Increment Address
Last Address?
Yes
Programming
Completed
Note: See Table 4 for program command sequence.
21354D-3
Figure 1. Program Operation
During the unlock bypass mode, only the Unlock
Bypass Program and Unlock Bypass Reset commands
are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset
command sequence. The first cycle must contain the
data 90h; the second cycle the data 00h. The device
then returns to reading array data.
trols or timings during these operations. Table 4 shows
the address and data requirements for the chip erase
command sequence.
Any commands written to the chip during the
Embedded Erase algorithm are ignored. Note that a
hardware reset during the chip erase operation imme-
diately terminates the operation. The Chip Erase
command sequence should be reinitiated once the
device has returned to reading array data, to ensure
data integrity.
Figure 1 illustrates the algorithm for the program oper-
ation. See the Erase/Program Operations table in “AC
Characteristics” for parameters, and to Figure 12 for
timing diagrams.
Chip Erase Command Sequence
The system can determine the status of the erase oper-
ation by using DQ7, DQ6, or DQ2. See “Write
Operation Status” for information on these status bits.
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses are
no longer latched.
Chip erase is a six bus cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algo-
rithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
Figure 2 illustrates the algorithm for the erase opera-
tion. See the Erase/Program Operations tables in “AC
Characteristics” for parameters, and to Figure 13 for
timing diagrams.
Am29LV040B
11
Sector Erase Command Sequence
Erase Suspend/Erase Resume Commands
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two
additional unlock write cycles are then followed by the
address of the sector to be erased, and the sector
erase command. Table 4 shows the address and data
requirements for the sector erase command sequence.
The Erase Suspend command allows the system to
interrupt a sector erase operation and then read data
from, or program data to, any sector not selected for
erasure. This command is valid only during the sector
erase operation, including the 50 µs time-out period
during the sector erase command sequence. The
Erase Suspend command is ignored if written during
the chip erase operation or Embedded Program algo-
rithm. Writing the Erase Suspend command during the
Sector Erase time-out immediately terminates the
time-out period and suspends the erase operation.
Addresses are “don’t-cares” when writing the Erase
Suspend command.
The device does not require the system to preprogram
the memory prior to erase. The Embedded Erase algo-
rithm automatically programs and verifies the sector for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or
timings during these operations.
When the Erase Suspend command is written during a
sector erase operation, the device requires a maximum
of 20 µs to suspend the erase operation. However,
when the Erase Suspend command is written during
the sector erase time-out, the device immediately ter-
minates the time-out period and suspends the erase
operation.
After the command sequence is written, a sector erase
time-out of 50 µs begins. During the time-out period,
additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of
sectors may be from one sector to all sectors. The time
between these additional cycles must be less than 50
µs, otherwise the last address and command might not
be accepted, and erasure may begin. It is recom-
mended that processor interrupts be disabled during
this time to ensure all commands are accepted. The
interrupts can be re-enabled after the last Sector Erase
command is written. If the time between additional
sector erase commands can be assumed to be less
than 50 µs, the system need not monitor DQ3. Any
command other than Sector Erase or Erase
Suspend during the time-out period resets the
device to reading array data. The system must
rewrite the command sequence and any additional
sector addresses and commands.
After the erase operation has been suspended, the
system can read array data from or program data to
any sector not selected for erasure. (The device “erase
suspends” all sectors selected for erasure.) Normal
read and write timings and command definitions apply.
Reading at any address within erase-suspended
sectors produces status data on DQ7–DQ0. The
system can use DQ7, or DQ6 and DQ2 together, to
determine if a sector is actively erasing or is erase-sus-
pended. See “Write Operation Status” for information
on these status bits.
After an erase-suspended program operation is com-
plete, the system can once again read array data within
non-suspended sectors. The system can determine
the status of the program operation using the DQ7 or
DQ6 status bits, just as in the standard program oper-
ation. See “Write Operation Status” for more
information.
The system can monitor DQ3 to determine if the sector
erase timer has timed out. (See the “DQ3: Sector Erase
Timer” section.) The time-out begins from the rising
edge of the final WE# pulse in the command sequence.
Once the sector erase operation has begun, only the
Erase Suspend command is valid. All other commands
are ignored. Note that a hardware reset during the
sector erase operation immediately terminates the
operation. The Sector Erase command sequence
should be reinitiated once the device has returned to
reading array data, to ensure data integrity.
The system may also write the autoselect command
sequence when the device is in the Erase Suspend
mode. The device allows reading autoselect codes
even at addresses within erasing sectors, since the
codes are not stored in the memory array. When the
device exits the autoselect mode, the device reverts to
the Erase Suspend mode, and is ready for another
valid operation. See “Autoselect Command Sequence”
for more information.
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses are
no longer latched. The system can determine the
status of the erase operation by using DQ7, DQ6, or
DQ2. (Refer to “Write Operation Status” for information
on these status bits.)
The system must write the Erase Resume command
(address bits are “don’t care”) to exit the erase suspend
mode and continue the sector erase operation. Further
writes of the Resume command are ignored. Another
Erase Suspend command can be written after the
device has resumed erasing.
Figure 2 illustrates the algorithm for the erase opera-
tion. Refer to the Erase/Program Operations tables in
the “AC Characteristics” section for parameters, and to
Figure 13 for timing diagrams.
12
Am29LV040B
START
Write Erase
Command Sequence
Data Poll
from System
Embedded
Erase
algorithm
in progress
No
Data = FFh?
Yes
Erasure Completed
21354D-4
Notes:
1. See Table 4 for erase command sequence.
2. See “DQ3: Sector Erase Timer” for more information.
Figure 2. Erase Operation
Am29LV040B
13
Table 4. Am29LV040B Command Definitions
Bus Cycles (Notes 2-4)
Command
Sequence
(Note 1)
First
Second
Third
Fourth
Fifth
Sixth
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read (Note 5)
Reset (Note 6)
Manufacturer ID
1
1
4
4
RA
XXX
555
555
RD
F0
AA
AA
2AA
2AA
55
55
555
555
90
90
X00
X01
01
4F
00
01
PD
Auto-
select
(Note 7)
Device ID
Sector Protect Verify
(Note 8)
(SA)
X02
4
555
AA
2AA
55
555
90
Program
4
3
2
2
6
6
1
1
555
555
AA
AA
A0
90
2AA
2AA
PA
55
55
PD
00
55
55
555
555
A0
20
PA
Unlock Bypass
Unlock Bypass Program (Note 9)
Unlock Bypass Reset (Note 10)
Chip Erase
XXX
XXX
555
XXX
2AA
2AA
AA
AA
B0
30
555
555
80
80
555
555
AA
AA
2AA
2AA
55
55
555
SA
10
30
Sector Erase
555
Erase Suspend (Note 11)
Erase Resume (Note 12)
XXX
XXX
Legend:
X = Don’t care
PD = Data to be programmed at location PA. Data latches on the
rising edge of WE# or CE# pulse, whichever happens first.
RA = Address of the memory location to be read.
SA = Address of the sector to be verified (in autoselect mode) or
erased. Address bits A18–A13 uniquely select any sector.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed.
Addresses latch on the falling edge of the WE# or CE# pulse,
whichever happens later.
Notes:
1. See Table 1 for description of bus operations.
9. The Unlock Bypass command is required prior to the Unlock
Bypass Program command.
2. All values are in hexadecimal.
10. The Unlock Bypass Reset command is required to return to
reading array data when the device is in the unlock bypass
mode.
3. Except when reading array or autoselect data, all command
bus cycles are write operations.
4. Address bits A18–A11 are don’t cares for unlock and
command cycles.
11. The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Erase Suspend
mode. The Erase Suspend command is valid only during a
sector erase operation.
5. No unlock or command cycles required when reading array
data.
6. The Reset command is required to return to reading array
data when device is in the autoselect mode, or if DQ5 goes
high (while the device is providing status data).
12. The Erase Resume command is valid only during the Erase
Suspend mode.
7. The fourth cycle of the autoselect command sequence is a
read cycle.
8. The data is 00h for an unprotected sector and 01h for a
protected sector. See “Autoselect Command Sequence” for
more information.
14
Am29LV040B
WRITE OPERATION STATUS
The device provides several bits to determine the
status of a write operation: DQ2, DQ3, DQ5, DQ6, and
DQ7. Table 5 and the following subsections describe
the functions of these bits. DQ7 and DQ6 each offer a
method for determining whether a program or erase
operation is complete or in progress. These three bits
are discussed first.
Table 5 shows the outputs for Data# Polling on DQ7.
Figure 3 shows the Data# Polling algorithm.
START
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host
system whether an Embedded Algorithm is in progress
or completed, or whether the device is in Erase Sus-
pend. Data# Polling is valid after the rising edge of the
final WE# pulse in the program or erase command
sequence.
Read DQ7–DQ0
Addr = VA
Yes
DQ7 = Data?
During the Embedded Program algorithm, the device
outputs on DQ7 the complement of the datum pro-
grammed to DQ7. This DQ7 status also applies to
programming during Erase Suspend. When the
Embedded Program algorithm is complete, the device
outputs the datum programmed to DQ7. The system
must provide the program address to read valid status
information on DQ7. If a program address falls within a
protected sector, Data# Polling on DQ7 is active for
approximately 1 µs, then the device returns to reading
array data.
No
No
DQ5 = 1?
Yes
During the Embedded Erase algorithm, Data# Polling
produces a “0” on DQ7. When the Embedded Erase
algorithm is complete, or if the device enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7.
This is analogous to the complement/true datum output
described for the Embedded Program algorithm: the
erase function changes all the bits in a sector to “1”;
prior to this, the device outputs the “complement,” or
“0.” The system must provide an address within any of
the sectors selected for erasure to read valid status
information on DQ7.
Read DQ7–DQ0
Addr = VA
Yes
DQ7 = Data?
No
PASS
FAIL
After an erase command sequence is written, if all
sectors selected for erasing are protected, Data#
Polling on DQ7 is active for approximately 100 µs, then
the device returns to reading array data. If not all
selected sectors are protected, the Embedded Erase
algorithm erases the unprotected sectors, and ignores
the selected sectors that are protected.
Notes:
1. VA = Valid address for programming. During a sector
erase operation, a valid address is an address within any
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.
When the system detects DQ7 has changed from the
complement to true data, it can read valid data at DQ7–
DQ0 on the following read cycles. This is because DQ7
may change asynchronously with DQ0–DQ6 while
Output Enable (OE#) is asserted low. Figure 14, Data#
Polling Timings (During Embedded Algorithms), in the
“AC Characteristics” section illustrates this.
2. DQ7 should be rechecked even if DQ5 = “1” because
DQ7 may change simultaneously with DQ5.
21354D-5
Figure 3. Data# Polling Algorithm
Am29LV040B
15
DQ2 toggles when the system reads at addresses
within those sectors that have been selected for era-
sure. (The system may use either OE# or CE# to
control the read cycles.) But DQ2 cannot distinguish
whether the sector is actively erasing or is erase-sus-
pended. DQ6, by comparison, indicates whether the
device is actively erasing, or is in Erase Suspend, but
cannot distinguish which sectors are selected for era-
sure. Thus, both status bits are required for sector and
mode information. Refer to Table 5 to compare outputs
for DQ2 and DQ6.
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or complete,
or whether the device has entered the Erase Suspend
mode. Toggle Bit I may be read at any address, and is
valid after the rising edge of the final WE# pulse in the
command sequence (prior to the program or erase
operation), and during the sector erase time-out.
During an Embedded Program or Erase algorithm
operation, successive read cycles to any address
cause DQ6 to toggle. The system may use either OE#
or CE# to control the read cycles. When the operation
is complete, DQ6 stops toggling.
Figure 4 shows the toggle bit algorithm in flowchart
form, and the section “DQ2: Toggle Bit II” explains the
algorithm. See also the DQ6: Toggle Bit I subsection.
Figure 15 shows the toggle bit timing diagram. Figure
16 shows the differences between DQ2 and DQ6 in
graphical form.
After an erase command sequence is written, if all
sectors selected for erasing are protected, DQ6 toggles
for approximately 100 µs, then returns to reading array
data. If not all selected sectors are protected, the
Embedded Erase algorithm erases the unprotected
sectors, and ignores the selected sectors that are
protected.
Reading Toggle Bits DQ6/DQ2
Refer to Figure 4 for the following discussion. When-
ever the system initially begins reading toggle bit
status, it must read DQ7–DQ0 at least twice in a row to
determine whether a toggle bit is toggling. Typically, the
system would note and store the value of the toggle bit
after the first read. After the second read, the system
would compare the new value of the toggle bit with the
first. If the toggle bit is not toggling, the device has com-
pleted the program or erase operation. The system can
read array data on DQ7–DQ0 on the following read
cycle.
The system can use DQ6 and DQ2 together to deter-
mine whether a sector is actively erasing or is erase-
suspended. When the device is actively erasing (that is,
the Embedded Erase algorithm is in progress), DQ6
toggles. When the device enters the Erase Suspend
mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing
or erase-suspended. Alternatively, the system can use
DQ7 (see the subsection on DQ7: Data# Polling).
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the
system also should note whether the value of DQ5 is
high (see the section on DQ5). If it is, the system
should then determine again whether the toggle bit is
toggling, since the toggle bit may have stopped tog-
gling just as DQ5 went high. If the toggle bit is no longer
toggling, the device has successfully completed the
program or erase operation. If it is still toggling, the
device did not completed the operation successfully,
and the system must write the reset command to return
to reading array data.
If a program address falls within a protected sector,
DQ6 toggles for approximately 2 µs after the program
command sequence is written, then returns to reading
array data.
DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded
Program algorithm is complete.
Table 5 shows the outputs for Toggle Bit I on DQ6.
Figure 4 shows the toggle bit algorithm. Figure 15 in the
“AC Characteristics” section shows the toggle bit timing
diagrams. Figure 16 shows the differences between
DQ2 and DQ6 in graphical form. See also the subsec-
tion on DQ2: Toggle Bit II.
The remaining scenario is that the system initially
determines that the toggle bit is toggling and DQ5 has
not gone high. The system may continue to monitor the
toggle bit and DQ5 through successive read cycles,
determining the status as described in the previous
paragraph. Alternatively, it may choose to perform
other system tasks. In this case, the system must start
at the beginning of the algorithm when it returns to
determine the status of the operation (top of Figure 4).
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indi-
cates whether a particular sector is actively erasing
(that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of the final WE# pulse in
the command sequence.
16
Am29LV040B
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under
these conditions DQ5 produces a “1.” This is a failure
condition that indicates the program or erase cycle was
not successfully completed.
START
The DQ5 failure condition may appear if the system
tries to program a “1” to a location that is previously pro-
grammed to “0.” Only an erase operation can change
a “0” back to a “1.” Under this condition, the device
halts the operation, and when the operation has
exceeded the timing limits, DQ5 produces a “1.”
Read DQ7–DQ0
(Note 1)
Read DQ7–DQ0
Under both these conditions, the system must issue the
reset command to return the device to reading array
data.
No
Toggle Bit
= Toggle?
DQ3: Sector Erase Timer
Yes
After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not an
erase operation has begun. (The sector erase timer
does not apply to the chip erase command.) If addi-
tional sectors are selected for erasure, the entire time-
out also applies after each additional sector erase com-
mand. When the time-out is complete, DQ3 switches
from “0” to “1.” If the time between additional sector
erase commands from the system can be assumed to
be less than 50 µs, the system need not monitor DQ3.
See also the “Sector Erase Command Sequence”
section.
No
DQ5 = 1?
Yes
(Notes
1, 2)
Read DQ7–DQ0
Twice
After the sector erase command sequence is written,
the system should read the status on DQ7 (Data#
Polling) or DQ6 (Toggle Bit I) to ensure the device has
accepted the command sequence, and then read DQ3.
If DQ3 is “1”, the internally controlled erase cycle has
begun; all further commands (other than Erase Sus-
pend) are ignored until the erase operation is complete.
If DQ3 is “0”, the device will accept additional sector
erase commands. To ensure the command has been
accepted, the system software should check the status
of DQ3 prior to and following each subsequent sector
erase command. If DQ3 is high on the second status
check, the last command might not have been
accepted. Table 5 shows the outputs for DQ3.
Toggle Bit
= Toggle?
No
Yes
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Notes:
1. Read toggle bit twice to determine whether or not it is
toggling. See text.
2. Recheck toggle bit because it may stop toggling as DQ5
changes to “1” . See text.
21354D-6
Figure 4. Toggle Bit Algorithm
Am29LV040B
17
Table 5. Write Operation Status
DQ7
DQ5
DQ2
Operation
(Note 2)
DQ7#
0
DQ6
(Note 1)
DQ3
N/A
1
(Note 2)
Embedded Program Algorithm
Embedded Erase Algorithm
Toggle
Toggle
0
0
No toggle
Toggle
Standard
Mode
Reading within Erase
Suspended Sector
1
No toggle
0
N/A
Toggle
Erase
Suspend
Mode
Reading within Non-Erase
Suspended Sector
Data
Data
Data
0
Data
N/A
Data
N/A
Erase-Suspend-Program
DQ7#
Toggle
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
See “” for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
18
Am29LV040B
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature
Commercial (C) Devices
Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C
Ambient Temperature (TA) . . . . . . . . . . .0°C to +70°C
Industrial (I) Devices
Ambient Temperature
with Power Applied. . . . . . . . . . . . . . –65°C to +125°C
Ambient Temperature (TA) . . . . . . . . .–40°C to +85°C
Extended (E) Devices
Voltage with Respect to Ground
VCC (Note 1) . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V
A9, OE# (Note 2) . . . . . . . . . . . .–0.5 V to +12.5 V
Ambient Temperature (TA) . . . . . . . .–55°C to +125°C
VCC Supply Voltages
All other pins
(Note 1). . . . . . . . . . . . . . . . . –0.5 V to VCC+0.5 V
VCC for regulated voltage range . . . . . . 3.0 V to 3.6 V
VCC for full voltage range . . . . . . . . . . . 2.7 V to 3.6 V
Output Short Circuit Current (Note 3) . . . . . . 200 mA
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
Notes:
1. Minimum DC voltage on input or I/O pins is –0.5 V. During
voltage transitions, input or I/O pins may overshoot V to
SS
–2.0 V for periods of up to 20 ns. See Figure 5. Maximum
DC voltage on input or I/O pins is V +0.5 V. During
CC
voltage transitions, input or I/O pins may overshoot to V
+2.0 V for periods up to 20 ns. See Figure 6.
CC
2. Minimum DC input voltage on pins A9 and OE# is –0.5 V.
During voltage transitions, A9 and OE# may overshoot
V
to –2.0 V for periods of up to 20 ns. See Figure 5.
SS
Maximum DC input voltage on pin A9 is +12.5 V which
may overshoot to 14.0 V for periods up to 20 ns.
3. No more than one output may be shorted to ground at a
time. Duration of the short circuit should not be greater
than one second.
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This is
a stress rating only; functional operation of the device at
these or any other conditions above those indicated in the
operational sections of this data sheet is not implied.
Exposure of the device to absolute maximum rating
conditions for extended periods may affect device reliability.
20 ns
20 ns
20 ns
+0.8 V
V
CC
+2.0 V
–0.5 V
–2.0 V
V
CC
+0.5 V
2.0 V
20 ns
20 ns
20 ns
21354D-8
21354D-7
Figure 5. Maximum Negative Overshoot
Waveform
Figure 6. Maximum Positive Overshoot
Waveform
Am29LV040B
19
DC CHARACTERISTICS
CMOS Compatible
Parameter
Description
Test Conditions
= V to V
Min
Typ
Max
±1.0
35
Unit
µA
V
V
,
CC
IN
SS
I
Input Load Current
LI
= V
CC
CC max
I
A9 Input Load Current
Output Leakage Current
V
= V
; A9 = 12.5 V
µA
LIT
CC
CC max
V
V
= V to V
,
CC
OUT
SS
I
±1.0
µA
LO
= V
CC
CC max
5 MHz
1 MHz
7
2
12
4
V
Active Read Current
CC
I
CE# = V OE# = V
mA
mA
CC1
CC2
IL,
IH
(Notes 1, 2)
V
Active Write Current
CC
I
CE# = V OE# = V
15
30
IL,
IH
(Notes 2, 3, 4)
I
I
V
V
Standby Current (Note 2)
Reset Current (Note 2)
CE# = V ± 0.3 V
0.2
0.2
5
5
µA
µA
CC3
CC
CC
CC
CC4
Automatic Sleep Mode
(Notes 2, 5)
V
V
= V ± 0.3 V;
CC
IH
IL
I
0.2
5
µA
CC5
= V ± 0.3 V
SS
V
Input Low Voltage
Input High Voltage
–0.5
0.8
V
V
IL
V
0.7 x V
V
+ 0.3
IH
CC
CC
Voltage for Autoselect and
Temporary Sector Unprotect
V
V
= 3.3 V
11.5
12.5
0.45
V
ID
CC
V
Output Low Voltage
I
I
I
= 4.0 mA, V = V
CC min
V
V
OL
OL
OH
OH
CC
V
= –2.0 mA, V = V
CC min
0.85 V
OH1
OH2
CC
CC
Output High Voltage
V
= –100 µA, V = V
V
–0.4
CC
CC min
CC
Low V Lock-Out Voltage
(Note 4)
CC
V
2.3
2.5
V
LKO
Notes:
1. The I current listed is typically less than 2 mA/MHz, with OE# at V . Typical V is 3.0 V.
CC
IH
CC
2. Maximum I current specifications are tested with V =V max.
CC
CC
CC
3. I active while Embedded Erase or Embedded Program is in progress.
CC
4. Not 100% tested.
5. Automatic sleep mode enables the low power mode when addresses remain stable for t
+ 30 ns.
ACC
20
Am29LV040B
DC CHARACTERISTICS (continued)
Zero Power Flash
20
15
10
5
0
0
500
1000
1500
2000
2500
3000
3500
4000
Time in ns
Note: Addresses are switching at 1 MHz
21354D-9
Figure 7. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents)
10
8
3.6 V
2.7 V
6
4
2
0
1
2
3
4
5
Frequency in MHz
Note: T = 25 °C
21354D-10
Figure 8. Typical ICC1 vs. Frequency
Am29LV040B
21
TEST CONDITIONS
Table 6. Test Specifications
3.3 V
-60R,
-70
-90,
-120
Test Condition
Output Load
Unit
2.7 kΩ
Device
Under
Test
1 TTL gate
Output Load Capacitance, C
(including jig capacitance)
L
30
100
pF
C
L
6.2 kΩ
Input Rise and Fall Times
Input Pulse Levels
5
0.0–3.0
ns
V
Input timing measurement
reference levels
1.5
1.5
V
V
Note: Diodes are IN3064 or equivalent
Output timing measurement
reference levels
21354D-11
Figure 9. Test Setup
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Does Not Apply
Changing, State Unknown
Center Line is High Impedance State (High Z)
KS000010-PAL
3.0 V
0.0 V
1.5 V
1.5 V
Input
Measurement Level
Output
21354D-12
Figure 10. Input Waveforms and Measurement Levels
22
Am29LV040B
AC CHARACTERISTICS
Read Operations
Parameter
Speed Option
JEDEC
Std
Description
Test Setup
Min
-60R
-70
-90
-120 Unit
t
t
Read Cycle Time (Note 1)
60
70
90
120
120
ns
ns
AVAV
RC
CE# = V
IL
IL
t
t
Address to Output Delay
Max
60
70
90
AVQV
ACC
OE# = V
t
t
t
Chip Enable to Output Delay
OE# = V
Max
Max
Max
Max
Min
60
30
25
25
70
30
25
25
90
35
30
30
120
50
ns
ns
ns
ns
ns
ELQV
GLQV
EHQZ
GHQZ
CE
IL
t
t
Output Enable to Output Delay
OE
t
Chip Enable to Output High Z (Note 1)
Output Enable to Output High Z (Note 1)
30
DF
DF
t
t
30
Read
0
Output Enable
t
OEH
Toggle and
Data# Polling
Hold Time (Note 1)
Min
Min
10
ns
ns
Output Hold Time From Addresses, CE# or
OE#, Whichever Occurs First (Note 1)
t
t
0
AXQX
OH
Notes:
1. Not 100% tested.
2. See Figure 9 and Table 6 for test specifications.
tRC
Addresses Stable
tACC
Addresses
CE#
tDF
tOE
OE#
tOEH
WE#
tCE
tOH
HIGH Z
HIGH Z
Output Valid
Outputs
0 V
21354D-13
Figure 11. Read Operations Timings
Am29LV040B
23
AC CHARACTERISTICS
Erase/Program Operations
Parameter
Speed Options
JEDEC
Std
Description
Write Cycle Time (Note 1)
-60R
60
-70
70
45
35
35
-90
90
45
45
35
-120
120
50
Unit
ns
t
t
Min
Min
Min
Min
Min
Min
Min
AVAV
WC
t
t
Address Hold Time
Data Setup Time
45
ns
WLAX
DVWH
WLWH
AH
DS
WP
t
t
35
50
ns
t
t
t
t
Write Pulse Width
Address Setup Time
Data Hold Time
35
50
ns
t
t
0
0
0
ns
AVWL
AS
ns
WHDX
DH
t
Output Enable Setup Time
ns
OES
Read Recovery Time Before Write
(OE# High to WE# Low)
t
t
Min
0
ns
GHWL
GHWL
t
t
t
CE# Setup Time
Min
Min
Min
Typ
Typ
Min
0
0
ns
ns
ELWL
WHEH
WHWL
CS
t
CE# Hold Time
CH
t
t
Write Pulse Width High
Programming Operation (Note 2)
Sector Erase Operation (Note 2)
30
9
ns
WPH
t
t
µs
WHWH1
WHWH2
WHWH1
WHWH2
t
t
0.7
50
sec
µs
t
V
Setup Time (Note 1)
VCS
CC
Notes:
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more information.
24
Am29LV040B
AC CHARACTERISTICS
Program Command Sequence (last two cycles)
Read Status Data (last two cycles)
tAS
tWC
Addresses
555h
PA
PA
PA
tAH
CE#
OE#
tCH
tWHWH1
tWP
WE#
tWPH
tCS
tDS
tDH
PD
DOUT
A0h
Status
Data
VCC
tVCS
Note: PA = program address, PD = program data, D
is the true data at the program address.
OUT
21354D-14
Figure 12. Program Operation Timings
Erase Command Sequence (last two cycles)
Read Status Data
tAS
SA
tWC
VA
VA
Addresses
CE#
2AAh
555h for chip erase
tAH
tCH
OE#
tWP
WE#
tWPH
tWHWH2
tCS
tDS
tDH
In
Data
VCC
Complete
55h
30h
Progress
10 for Chip Erase
tVCS
Note: SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”).
21354D-15
Figure 13. Chip/Sector Erase Operation Timings
Am29LV040B
25
AC CHARACTERISTICS
tRC
VA
Addresses
VA
VA
tACC
tCE
CE#
tCH
tOE
OE#
WE#
tOEH
tDF
tOH
High Z
High Z
DQ7
Valid Data
Complement
Complement
True
DQ0–DQ6
Status Data
True
Valid Data
Status Data
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data
read cycle.
21354D-16
Figure 14. Data# Polling Timings (During Embedded Algorithms)
tRC
Addresses
CE#
VA
tACC
tCE
VA
VA
VA
tCH
tOE
OE#
WE#
tOEH
tDF
tOH
High Z
DQ6/DQ2
Valid Status
(first read)
Valid Status
Valid Status
Valid Data
(second read)
(stops toggling)
Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read
cycle, and array data read cycle.
21354D-17
Figure 15. Toggle Bit Timings (During Embedded Algorithms)
26
Am29LV040B
AC CHARACTERISTICS
Enter
Embedded
Erasing
Erase
Suspend
Enter Erase
Suspend Program
Erase
Resume
Erase
Erase Suspend
Read
Erase
Suspend
Program
Erase
Complete
WE#
Erase
Erase Suspend
Read
DQ6
DQ2
Note: The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an
erase-suspended sector.
21354D-18
Figure 16. DQ2 vs. DQ6
Am29LV040B
27
AC CHARACTERISTICS
Alternate CE# Controlled Erase/Program Operations
Parameter
Speed Options
JEDEC
Std
Description
Write Cycle Time (Note 1)
Address Hold Time
Data Setup Time
-60R
60
-70
70
45
35
35
-90
90
45
45
35
-120
120
50
Unit
ns
t
t
Min
Min
Min
Min
Min
Min
Min
AVAV
ELAX
DVEH
WC
t
t
45
ns
AH
DS
CP
t
t
35
50
ns
t
t
CE# Pulse Width
35
50
ns
ELEH
t
t
Address Setup Time
Data Hold Time
0
0
0
ns
AVEL
AS
DH
t
t
ns
EHDX
t
Output Enable Setup Time
ns
OES
Read Recovery Time Before Write
(OE# High to WE# Low)
t
t
t
Min
0
ns
GHEL
WLEL
GHEL
t
WE# Setup Time
Min
Min
Min
Typ
Typ
0
0
ns
ns
WS
t
t
WE# Hold Time
EHWH
WH
t
t
CE# Pulse Width High
Programming Operation (Note 2)
Sector Erase Operation (Note 2)
30
9
ns
EHEL
CPH
t
t
µs
WHWH1
WHWH2
WHWH1
WHWH2
t
t
0.7
sec
Notes:
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more information.
28
Am29LV040B
AC CHARACTERISTICS
555 for program
PA for program
2AA for erase
SA for sector erase
555 for chip erase
Data# Polling
Addresses
PA
tWC
tWH
tAS
tAH
WE#
OE#
tGHEL
tWHWH1 or 2
tCP
CE#
Data
tWS
tCPH
tDS
tDH
DQ7#
DOUT
A0 for program
55 for erase
PD for program
30 for sector erase
10 for chip erase
Notes:
1. PA = Program Address, PD = Program Data, DQ7# = complement of the data written to the device, D
to the device.
is the data written
21354D-19
OUT
2. Figure indicates the last two bus cycles of the command sequence.
Figure 17. Alternate CE# Controlled Write Operation Timings
Am29LV040B
29
ERASE AND PROGRAMMING PERFORMANCE
Parameter
Typ (Note 1)
Max (Note 2)
Unit
s
Comments
Sector Erase Time
Chip Erase Time
Byte Programming Time
0.7
11
9
15
Excludes 00h programming
prior to erasure (Note 4)
s
300
µs
Excludes system level
overhead (Note 5)
Chip Programming Time
(Note 3)
4.5
13.5
s
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 3.0 V V , 1,000,000 cycles. Additionally,
CC
programming typicals assume checkerboard pattern.
2. Under worst case conditions of 90°C, V = 2.7 V (3.0 V for -60R), 1,000,000 cycles.
CC
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum program times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See
Table 4 for further information on command definitions.
6. The device has a minimum guaranteed erase and program cycle endurance of 1,000,000 cycles.
LATCHUP CHARACTERISTICS
Description
Min
Max
Input voltage with respect to V on all pins except I/O pins
(including A9 and OE#)
SS
–1.0 V
12.5 V
Input voltage with respect to V on all I/O pins
–1.0 V
V
+ 1.0 V
CC
SS
V
Current
–100 mA
+100 mA
CC
Includes all pins except V . Test conditions: V = 3.0 V, one pin at a time.
CC
CC
TSOP AND SO PIN CAPACITANCE
Parameter
Symbol
Parameter Description
Input Capacitance
Test Setup
Typ
6
Max
7.5
12
Unit
pF
C
V
= 0
IN
IN
C
Output Capacitance
Control Pin Capacitance
V
= 0
8.5
7.5
pF
OUT
OUT
C
V
= 0
IN
9
pF
IN2
Notes:
1. Sampled, not 100% tested.
2. Test conditions T = 25°C, f = 1.0 MHz.
A
DATA RETENTION
Parameter
Test Conditions
150°C
Min
10
Unit
Years
Years
Minimum Pattern Data Retention Time
125°C
20
30
Am29LV040B
PHYSICAL DIMENSIONS*
TS 032—32-Pin Standard TSOP (measured in millimeters)
Dwg rev AA; 10/99
* For reference only. BSC is an ANSI standard for Basic Space Centering.
Am29LV040B
31
PHYSICAL DIMENSIONS
TSR032—32-Pin Reverse TSOP (measured in millimeters)
Dwg rev AA; 10/99
* For reference only. BSC is an ANSI standard for Basic Space Centering.
32
Am29LV040B
PHYSICAL DIMENSIONS
PL 032—32-Pin Plastic Leaded Chip Carrier (measured in inches)
PL 032
Dwg rev AH; 10/99
Am29LV040B
33
REVISION SUMMARY
Revision B (April 1998)
Revision C+2 (July 20, 1999)
Expanded data sheet from Advanced Information to
Preliminary version.
Physical Dimensions
Corrected the unit of measurement for the 32-pin PLCC
to inches.
Revision B+1 (November 1998)
Connection Diagrams
Revision D (November 11, 1999)
Corrected the standard TSOP pinout.
Global
Changed all references to 55R speed option (55 ns,
regulated voltage range) to 60R (60 ns, regulated
voltage range).
Revision C (January 1999)
Distinctive Characteristics
Added 20-year data retention subbullet.
Physical Dimensions
Replaced all drawings with new versions.
Revision C+1 (May 18, 1999)
AC Characteristics—Figure 12. Program
Operations Timing and Figure 13. Chip/Sector
Erase Operations
Removed preliminary designation from data sheet.
Deleted tGHWL and changed OE# waveform to start at
high.
Trademarks
Copyright © 1999 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.
ExpressFlash is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
34
Am29LV040B
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