AM29LV065MU90FF [SPANSION]

Flash, 8MX8, 90ns, PDSO48, REVERSE, TSOP-48;


型号：	AM29LV065MU90FF
厂家：	SPANSION
描述：	Flash, 8MX8, 90ns, PDSO48, REVERSE, TSOP-48 光电二极管内存集成电路
文件：	总8页 (文件大小：104K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADVANCE INFORMATION

Am29LV065M

64 Megabit (8 M x 8-Bit) MirrorBit 3.0 Volt-only

Uniform Sector Flash Memory with VersatileI/O Control

DISTINCTIVE CHARACTERISTICS

ARCHITECTURAL ADVANTAGES

— 8-byte read page buffer

— 32-byte write buffer

■ Single power supply operation

■ Low power consumption (typical values at 3.0 V,

— 2.7–3.6 volt read, erase, and program operations

5 MHz)

■ Enhanced VersatileI/O control

— 30 mA typical active read current

— 50 mA typical erase/program current

— 1 µA typical standby mode current

— Device generates data output voltages and tolerates

data input voltages as determined by the voltage on

the V_IOpin; operates from 1.65 to 3.6 V

■ Package options

— 48-pin TSOP

■ Manufactured on 0.23 µm MirrorBit process

technology

— 63-ball FBGA

■ SecSi (Secured Silicon) Sector region

— 256-byte sector for permanent, secure identification

through an 16-byte random Electronic Serial Number,

accessible through a command sequence

SOFTWARE & HARDWARE FEATURES

■ Software features

— Program Suspend & Resume: read other sectors

before programming operation is completed

— May be programmed and locked at the factory or by

the customer

— Erase Suspend & Resume: read/program other

sectors before an erase operation is completed

■ Flexible sector architecture

— One hundred twenty-eight 64 Kbyte sectors

— Data# polling & toggle bits provide status

■ Compatibility with JEDEC standards

— Unlock Bypass Program command reduces overall

multiple-byte programming time

— Provides pinout and software compatibility for

single-power supply flash, and superior inadvertent

write protection

— CFI (Common Flash Interface) compliant: allows host

system to identify and accommodate multiple flash

devices

■ Minimum 100,000 erase cycle guarantee per sector

■ 20-year data retention at 125°C

■ Hardware features

— Sector Group Protection: hardware method of

preventing write operations within a sector group

PERFORMANCE CHARACTERISTICS

■ High performance

— Temporary Sector Unprotect: V_ID-level method of

changing code in locked sectors

— 90 ns access time

— ACC (high voltage) pin accelerates programming

time for higher throughput during system production

— 25 ns page read times

— 1 s typical sector erase time

— Hardware reset pin (RESET#) resets device

— 3.0 µs typical write buffer byte programming time:

32-byte write buffer reduces overall programming

time for multiple-byte updates

— Ready/Busy# pin (RY/BY#) detects program or erase

cycle completion

Publication# 25262

Issue Date: August 3, 2001

Rev: A Amendment/0

This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data

Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.

Refer to AMD’s Website (www.amd.com) for the latest information.

A D V A N C E I N F O R M A T I O N

GENERAL DESCRIPTION

The Am29LV065M is a 64 Mbit, 3.0 volt (3.0 V to 3.6

V) single power supply flash memory devices orga-

nized as 8,388,608 bytes. The device has an 8-bit

wide data bus, and can be programmed either in the

host system or in standard EPROM programmers.

at its data outputs and the voltages tolerated at its data

inputs to the same voltage level that is asserted on the

_IOpin. This allows the device to operate in a 1.8 V or

3 V system environment as required.

Hardware data protection measures include a low

V_CCdetector that automatically inhibits write opera-

tions during power transitions. The hardware sector

protection feature disables both program and erase

operations in any combination of sectors of memory.

This can be achieved in-system or via programming

equipment.

An access time of 90 ns is available for applications

where V_IO≥ 3.0 V. An access time of 100 ns is avail-

able for applications where V_IO< 3.0 V. The device is

offered in a 48-pin TSOP or 63-ball FBGA package.

Each device has separate chip enable (CE#), write en-

able (WE#) and output enable (OE#) controls.

Each device requires only a single 3.0 volt power

supply (2.7 V to 3.6 V) for both read and write func-

tions. In addition to a V_CCinput, a high-voltage accel-

erated program (ACC) input provides shorter

programming times through increased current. This

feature is intended to facilitate factory throughput dur-

ing system production, but may also be used in the

field if desired.

The Erase Suspend/Erase Resume feature allows

the host system to pause an erase operation in a given

sector to read or program any other sector and then

complete the erase operation. The Program Sus-

pend/Program Resume feature enables the host sys-

tem to pause a program operation in a given sector to

read any other sector and then complete the program

operation.

The device is entirely command set compatible with

the JEDEC single-power-supply Flash standard.

Commands are written to the device using standard

microprocessor write timing. Write cycles also inter-

nally latch addresses and data needed for the pro-

gramming and erase operations.

The hardware RESET# pin terminates any operation

in progress and resets the device, after which it is then

ready for a new operation. The RESET# pin may be

tied to the system reset circuitry. A system reset would

thus also reset the device, enabling the host system to

read boot-up firmware from the Flash memory device.

The sector erase architecture allows memory sec-

tors to be erased and reprogrammed without affecting

the data contents of other sectors. The device is fully

erased when shipped from the factory.

The device reduces power consumption in the

standby mode when it detects specific voltage levels

on CE# and RESET#, or when addresses have been

stable for a specified period of time.

Device programming and erasure are initiated through

command sequences. Once a program or erase oper-

ation has begun, the host system need only poll the

DQ7 (Data# Polling) or DQ6 (toggle) status bits or

monitor the Ready/Busy# (RY/BY#) output to deter-

mine whether the operation is complete. To facilitate

programming, an Unlock Bypass mode reduces com-

mand sequence overhead by requiring only two write

cycles to program data instead of four.

The SecSi (Secured Silicon) Sector provides a 256

byte area for code or data that can be permanently

protected. Once this sector is protected, no further

changes within the sector can occur.

AMD MirrorBit flash technology combines years of

Flash memory manufacturing experience to produce

the highest levels of quality, reliability and cost effec-

tiveness. The device electrically erases all bits within a

sector simultaneously via hot-hole assisted erase. The

data is programmed using hot electron injection.

The VersatileI/O™ (V_IO) control allows the host sys-

tem to set the voltage levels that the device generates

Am29LV065M

A D V A N C E I N F O R M A T I O N

PRODUCT SELECTOR GUIDE

Part Number

Am29LV065M

101

102

Speed Option

V_CC= 2.7–3.6 V all devices

(V_IO= 3.0–3.6 V)

(V_IO= 2.7–3.0 V) (V_IO= 1.65–2.7 V)

Max. Access Time (ns)

100

Max. CE# Access Time (ns)

Max. Page access time (t_PACC

Max. OE# Access Time (ns)

)

BLOCK DIAGRAM

DQ0–DQ7

RY/BY#

V_CC

Sector Switches

V_SS

V_IO

Erase Voltage

Generator

Input/Output

Buffers

RESET#

WE#

State

ACC

Control

Command

PGM Voltage

Generator

Data

Latch

Chip Enable

Output Enable

Logic

STB

CE#

OE#

Y-Decoder

X-Decoder

Y-Gating

STB

V_CCDetector

Timer

Cell Matrix

A22–A0

Am29LV065M

A D V A N C E I N F O R M A T I O N

CONNECTION DIAGRAMS

A17

V_SS

A20

A19

A10

DQ7

DQ6

DQ5

DQ4

V_CC

V_IO

A22

A16

A15

A14

A13

A12

A11

48-Pin Standard TSOP

WE#

RESET#

ACC

RY/BY#

A18

A21

DQ3

DQ2

DQ1

DQ0

OE#

V_SS

CE#

A17

V_SS

A22

A16

A15

A14

A13

A12

A11

A20

A19

A10

DQ7

DQ6

DQ5

DQ4

V_CC

V_IO

A21

DQ3

DQ2

DQ1

DQ0

OE#

V_SS

CE#

48-Pin Reverse TSOP

WE#

RESET#

ACC

RY/BY#

A18

Am29LV065M

A D V A N C E I N F O R M A T I O N

CONNECTION DIAGRAMS

63-Ball FBGA

Top View, Balls Facing Down

NC*

A14

A13

A15

A16

A17

A20

NC*

A11

A12

A19

A10

DQ6

DQ7

WE# RESET# A22

DQ5

DQ4

RY/BY# ACC

DQ2

DQ3

A21

A18

DQ0

DQ1

NC*

CE#

OE#

NC*

* Balls are shorted together via the substrate but not connected to the die.

NC*

Flash memory devices in FBGA packages may be

damaged if exposed to ultrasonic cleaning methods.

The package and/or data integrity may be compromised

if the package body is exposed to temperatures above

150°C for prolonged periods of time.

Special Handling Instructions for FBGA

Package

Special handling is required for Flash Memory products

in FBGA packages.

Am29LV065M

A D V A N C E I N F O R M A T I O N

PIN DESCRIPTION

LOGIC SYMBOL

A22–A0

= 23 Addresses inputs

DQ7–DQ0 = 8 Data inputs/outputs

A22–A0

CE#

= Chip Enable input

DQ7–DQ0

CE#

OE#

= Output Enable input

= Write Enable input

= Acceleration Input

= Hardware Reset Pin input

= Ready/Busy output

OE#

WE#

ACC

RESET#

RY/BY#

V_CC

RESET#

RY/BY#

= 3.0 volt-only single power supply

(see Product Selector Guide for

speed options and voltage

supply tolerances)

V_IO

V_SS

= Output Buffer power

= Device Ground

= Pin Not Connected Internally

Am29LV065M

A D V A N C E I N F O R M A T I O N

ORDERING INFORMATION

Standard Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is

formed by a combination of the following:

Am29LV065M

TEMPERATURE RANGE

Industrial (–40°C to +85°C)

PACKAGE TYPE

48-Pin Standard Pinout Thin Small Outline Package (TS 048)

48-Pin Reverse Pinout Thin Small Outline Package (TSR048)

63-Ball Fine-Pitch Ball Grid Array (FBGA)

0.80 mm pitch, 11 x 12 mm package (FBE063)

SPEED OPTION

See Product Selector Guide and Valid Combinations

SECTOR ARCHITECTURE

Uniform sector device

DEVICE NUMBER/DESCRIPTION

Am29LV065M

64 Megabit (8 M x 8-Bit) MirrorBit Uniform Sector Flash Memory with VersatileIO Control

3.0 Volt-only Read, Program, and Erase

Valid Combinations for TSOP

Packages

Valid Combinations for FBGA Packages

Package

Speed/V_IORange

Speed/

Am29LV065MU90,

Am29LV065MU90

90ns,

_IO= 3.0 V – 3.6 V

Order Number

Marking

_IORange

90 ns, V_IO

3.0 V – 3.6 V

100 ns, V_IO

2.7 V – 3.0 V

100 ns, V_IO

1.65 V – 2.7 V

Am29LV065MU90

L065MU90V

Am29LV065MU101,

EI, FI

100 ns,

_IO= 2.7 V – 3.0 V

Am29LV065MU101

Am29LV065MU102

WHI L065MU01V

L065MU02V

Am29LV065MU102,

Am29LV065MU102

100 ns,

_IO= 1.65 V – 2.7 V

Valid Combinations

Valid Combinations list configurations planned to be supported in

volume for this device. Consult the local AMD sales office to con-

firm availability of specific valid combinations and to check on

newly released combinations.

Am29LV065M

A D V A N C E I N F O R M A T I O N

REVISION SUMMARY

Revision A (August 3, 2001)

Initial release as abbreviated Advance Information

data sheet.

Trademarks

AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.

ExpressFlash is a trademark of Advanced Micro Devices, Inc.

Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

Am29LV065M

AM29LV065MU90FF [SPANSION]

相关型号：

AM29LV065MU90FI

AM29LV065MU90FI

AM29LV065MU90RE

AM29LV065MU90REF

AM29LV065MU90REI

AM29LV065MU90RF

AM29LV065MU90RFF

AM29LV065MU90RFI

AM29LV065MU90RWH

AM29LV065MU90RWHF

AM29LV065MU90RWHI

AM29LV065MU90WHF