AM29LV116MB120RED [SPANSION]
Flash, 2MX8, 120ns, PDSO40, PLASTIC, MO-142CD, TSOP-40;型号: | AM29LV116MB120RED |
厂家: | SPANSION |
描述: | Flash, 2MX8, 120ns, PDSO40, PLASTIC, MO-142CD, TSOP-40 CD 光电二极管 内存集成电路 |
文件: | 总47页 (文件大小:925K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Am29LV116M
Data Sheet
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For More Information
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PRODUCTION PENDING
Production is subject to customer demand. Contact your
local AMD sales representative for more information
Am29LV116M
16 Megabit (2 M x 8-Bit) MirrorBitTM
3.0 Volt-only Boot Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
■ Single power supply operation
■ Embedded Algorithms
— 2.7 to 3.6 volt read and write operations for
battery-powered applications
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
■ Manufactured on 0.23 µm MirrorBit process
technology
— Embedded Program algorithm automatically
writes and verifies data at specified addresses
— Compatible with and replaces Am29LV116D and
Am29LV116B
■ Minimum 100,000 write cycle guarantee
■ SecSiTM (Secured Silicon) Sector region
per sector
■ 20-year data retention at 125°C
— Reliable operation for the life of the system
■ Package option
— 128-word/256-byte sector for permanent, secure
identification through an 8-word/16-byte random
Electronic Serial Number, accessible through a
command sequence
— 40-pin TSOP
— May be programmed and locked at the factory or by
the customer
■ CFI (Common Flash Interface) compliant
— Provides device-specific information to the
system, allowing host software to easily
reconfigure for different Flash devices
■ High performance
— Access times as fast as 70 ns
■ Ultra low power consumption (typical values at
■ Compatibility with JEDEC standards
5 MHz)
— Pinout and software compatible with single-
power supply Flash
— 400 nA Automatic Sleep mode current
— 400 nA standby mode current
— 15 mA read current
— Superior inadvertent write protection
■ Data# Polling and toggle bits
— 40 mA program/erase current
— Provides a software method of detecting program
or erase operation completion
■ Flexible sector architecture
— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and
thirty-one 64 Kbyte sectors
■ Ready/Busy# pin (RY/BY#)
— Provides a hardware method of detecting
program or erase cycle completion
— Supports full chip erase
— Sector Protection features:
■ Erase Suspend/Erase Resume
A hardware method of locking a sector to prevent
any program or erase operations within that sector
— Suspends an erase operation to read data from,
or program data to, a sector that is not being
erased, then resumes the erase operation
Sectors can be locked in-system or via
programming equipment
■ Hardware reset pin (RESET#)
Temporary Sector Unprotect feature allows code
changes in previously locked sectors
— Hardware method to reset the device to reading
array data
■ Unlock Bypass Program Command
— Reduces overall programming time when issuing
multiple program command sequences
■ Top or bottom boot block configurations
available
This Data Sheet states AMD’s current technical specifications regarding the Product described herein. This Data
Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
Publication# 26008 Rev: A Amendment/+3
Issue Date: April 7, 2003
P E N D I N G
GENERAL DESCRIPTION
The Am29LV116M is a 16 Mbit, 3.0 Volt-only Flash
memory organized as 2,097,152 bytes. The device is
offered in a 40-pin TSOP package. The byte-wide (x8)
data appears on DQ7–DQ0. All read, program, and
erase operations are accomplished using only a single
power supply. The device can also be programmed in
standard EPROM programmers.
pin, or by reading the DQ7 (Data# Polling) and DQ6
(toggle) status bits. After a program or erase cycle
has been completed, the device is ready to read array
data or accept another command.
The sector erase architecture allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
The standard device offers access times of 70, 90, and
120 ns, allowing high speed microprocessors to
operate without wait states. To eliminate bus conten-
tion the device has separate chip enable (CE#), write
enable (WE#) and output enable (OE#) controls.
Hardware data protection measures include a low
VCC detector that automatically inhibits write opera-
tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of the sectors of mem-
ory. This can be achieved in-system or via program-
ming equipment.
The device requires only a single 3.0 volt power sup-
ply for both read and write functions. Internally gener-
ated and regulated voltages are provided for the
program and erase operations.
The Erase Suspend feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved.
The Program Suspend/Program Resume feature en-
ables the host system to pause a program operation in
a given sector to read any other sector and then com-
plete the program operation.
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard. Com-
mands are written to the command register using stan-
dard microprocessor write timings. Register contents
serve as input to an internal state-machine that con-
trols the erase and programming circuitry. Write cycles
also internally latch addresses and data needed for the
programming and erase operations. Reading data out
of the device is similar to reading from other Flash or
EPROM devices.
The hardware RESET# pin terminates any operation
in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.
Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithm—an internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin. The Unlock Bypass mode facili-
tates faster programming times by requiring only two
write cycles to program data instead of four.
The device offers two power-saving features. When
addresses have been stable for a specified amount of
time, the device enters the automatic sleep mode.
The system can also place the device into the standby
mode. Power consumption is greatly reduced in both
these modes.
Device erasure occurs by executing the erase com-
mand sequence. This initiates the Embedded Erase
algorithm—an internal algorithm that automatically pre-
programs the array (if it is not already programmed) be-
fore executing the erase operation. During erase, the
device automatically times the erase pulse widths and
verifies proper cell margin.
AMD’s MirrorBit flash technology combines years of
Flash memory manufacturing experience to produce
the highest levels of quality, reliability and cost effec-
tiveness. The device electrically erases all bits
within a sector simultaneously via Fowler-Nordheim
tunneling. The data is programmed using hot electron
injection.
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
2
Am29LV116M
April 7, 2003
P E N D I N G
TABLE OF CONTENTS
Table 9. Am29LV116M Command Definitions .............................. 25
Write Operation Status . . . . . . . . . . . . . . . . . . . . 26
DQ7: Data# Polling .................................................................26
Figure 6. Data# Polling Algorithm .................................................. 26
RY/BY#: Ready/Busy# ............................................................27
DQ6: Toggle Bit I ....................................................................27
DQ2: Toggle Bit II ...................................................................27
Reading Toggle Bits DQ6/DQ2 ...............................................27
DQ5: Exceeded Timing Limits ................................................28
DQ3: Sector Erase Timer .......................................................28
Figure 7. Toggle Bit Algorithm........................................................ 28
Table 10. Write Operation Status ................................................... 29
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 30
Figure 8. Maximum Negative Overshoot Waveform ...................... 30
Figure 9. Maximum Positive Overshoot Waveform........................ 30
Operating Ranges. . . . . . . . . . . . . . . . . . . . . . . . . 30
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 31
CMOS Compatible ..................................................................31
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 10. Test Setup..................................................................... 32
Table 11. Test Specifications ......................................................... 32
Key to Switching Waveforms ..................................................32
Figure 11. Input Waveforms and Measurement Levels ................. 32
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 33
Read Operations ....................................................................33
Figure 12. Read Operation Timing................................................. 33
Hardware Reset (RESET#) ....................................................34
Figure 13. RESET# Timings .......................................................... 34
Erase/Program Operations .....................................................35
Figure 14. Program Operation Timings.......................................... 36
Figure 15. Chip/Sector Erase Operation Timings .......................... 36
Figure 16. Data# Polling Timings (During Embedded Algorithms). 37
Figure 17. Toggle Bit Timings (During Embedded Algorithms)...... 37
Figure 18. DQ2 vs. DQ6................................................................. 38
Temporary Sector Unprotect ..................................................38
Figure 19. Temporary Sector Unprotect Timing Diagram .............. 38
Figure 20. Sector Protect/Unprotect Timing Diagram .................... 39
Figure 21. Alternate CE# Controlled Write Operation Timings ...... 41
Erase and Programming Performance . . . . . . . 42
Latchup Characteristics. . . . . . . . . . . . . . . . . . . . 42
TSOP Pin Capacitance . . . . . . . . . . . . . . . . . . . . . 42
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 43
TS 040—40-Pin Standard TSOP ............................................43
TSR040—40-Pin Reverse TSOP ...........................................44
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 45
Revision A (June 24, 2002) ....................................................45
Revision A + 1 (July 3, 2002) ..................................................45
Revision A + 2 (February 6, 2003) ..........................................45
Revision A + 3 (April 7, 2003) .................................................45
Product Selector Guide . . . . . . . . . . . . . . . . . . . . .4
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . .5
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . .6
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Ordering Information . . . . . . . . . . . . . . . . . . . . . . .7
Standard Products ....................................................................7
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . .8
Table 1. Am29LV116M Device Bus Operations ................................8
Requirements for Reading Array Data .....................................8
Writing Commands/Command Sequences ..............................8
Program and Erase Operation Status ......................................9
Standby Mode ..........................................................................9
Automatic Sleep Mode .............................................................9
RESET#: Hardware Reset Pin .................................................9
Output Disable Mode ................................................................9
Table 2. Am29LV116MT Top Boot Sector Address Table ..............10
Table 3. Am29LV116MB Bottom Boot Sector Address Table .........11
Autoselect Mode .....................................................................12
Table 4. Am29LV116M Autoselect Codes (High Voltage Method) .12
Sector Protection/Unprotection ...............................................13
Temporary Sector Unprotect ..................................................13
Figure 1. Temporary Sector Unprotect Operation........................... 13
Figure 1. In-System Single High Voltage Sector Protect/Unprotect Al-
gorithms .......................................................................................... 14
SecSi (Secured Silicon) Sector Flash Memory Region ..........15
Table 1. SecSi Sector Contents ......................................................15
Figure 2. SecSi Sector Protect Verify.............................................. 16
Hardware Data Protection ......................................................16
Low VCC Write Inhibit ..............................................................16
Write Pulse “Glitch” Protection ...............................................16
Logical Inhibit ..........................................................................16
Power-Up Write Inhibit ............................................................16
Common Flash Memory Interface (CFI) . . . . . . . 16
Table 5. CFI Query Identification String ..........................................17
Table 6. System Interface String .....................................................17
Table 7. Device Geometry Definition ..............................................18
Table 8. Primary Vendor-Specific Extended Query ........................19
Command Definitions . . . . . . . . . . . . . . . . . . . . . .20
Reading Array Data ................................................................20
Reset Command .....................................................................20
Autoselect Command Sequence ............................................20
Byte Program Command Sequence .......................................20
Unlock Bypass Command Sequence .....................................21
Figure 3. Program Operation .......................................................... 21
Chip Erase Command Sequence ...........................................22
Sector Erase Command Sequence ........................................22
Erase Suspend/Erase Resume Commands ...........................22
Figure 4. Erase Operation............................................................... 23
Program Suspend/Program Resume Command Sequence ...24
Figure 5. Program Suspend/Program Resume............................... 24
Command Definitions .............................................................25
April 7, 2003
Am29LV116M
3
P E N D I N G
PRODUCT SELECTOR GUIDE
Family Part Number
Am29LV116M
VCC = 2.7–3.6 V
Speed Options
70
70R
70
90
90R
90
120
120R
120
120
50
VCC = 3.0–3.6 V
Max access time, ns (tACC
Max CE# access time, ns (tCE
Max OE# access time, ns (tOE
)
)
70
90
)
30
35
Note: See “AC Characteristics” for full specifications.
BLOCK DIAGRAM
DQ0–DQ7
RY/BY#
VCC
Sector Switches
VSS
Erase Voltage
Generator
Input/Output
Buffers
RESET#
State
Control
WE#
Command
Register
PGM Voltage
Generator
Data
Latch
Chip Enable
Output Enable
Logic
STB
CE#
OE#
Y-Decoder
Y-Gating
STB
VCC Detector
Timer
Cell Matrix
X-Decoder
A0–A20
4
Am29LV116M
April 7, 2003
P E N D I N G
CONNECTION DIAGRAMS
A17
VSS
A16
A15
A14
A13
A12
A11
A9
1
2
3
4
5
6
7
8
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A20
A19
A10
DQ7
DQ6
DQ5
DQ4
VCC
VCC
A8
WE#
RESET#
NC
RY/BY#
A18
A7
9
10
11
12
13
14
15
16
17
18
19
20
40-Pin Standard TSOP
NC
DQ3
DQ2
DQ1
DQ0
OE#
VSS
A6
A5
A4
A3
A2
A1
CE#
A0
A17
VSS
1
2
3
4
5
6
7
8
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A16
A15
A14
A13
A12
A11
A9
A20
A19
A10
DQ7
DQ6
DQ5
DQ4
VCC
VCC
NC
DQ3
DQ2
DQ1
DQ0
A8
9
WE#
RESET#
NC
RY/BY#
A18
A7
A6
A5
A4
A3
10
11
12
13
14
15
16
17
18
19
20
40-Pin Reverse TSOP
OE#
VSS
CE#
A0
A2
A1
April 7, 2003
Am29LV116M
5
P E N D I N G
PIN CONFIGURATION
LOGIC SYMBOL
A0–A20
= 21 addresses
21
DQ0–DQ7 = 8 data inputs/outputs
A0–A20
8
CE#
= Chip enable
DQ0–DQ7
OE#
= Output enable
WE#
= Write enable
CE#
OE#
RESET#
RY/BY#
VCC
= Hardware reset pin, active low
= Ready/Busy output
WE#
RESET#
= 3.0 volt-only single power supply
(see Product Selector Guide for speed
options and voltage supply tolerances)
RY/BY#
VSS
NC
=
Device ground
= Pin not connected internally
6
Am29LV116M
April 7, 2003
P E N D I N G
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combi-
nation) is formed by a combination of the elements below.
Am29LV116M
T
70
E
C
TEMPERATURE RANGE
C
I
=
=
Commercial (0°C to +70°C)
Industrial (–40°C to +85°C)
PACKAGE TYPE
E
=
40-Pin Thin Small Outline Package (TSOP)
Standard Pinout (TS 040)
F
=
40-Pin Thin Small Outline Package (TSOP)
Reverse Pinout (TSR040)
SPEED OPTION
See Product Selector Guide and Valid Combinations
BOOT CODE SECTOR ARCHITECTURE
T
B
=
=
Top Sector
Bottom Sector
DEVICE NUMBER/DESCRIPTION
Am29LV116M
16 Megabit (2 M x 8-Bit) CMOS Flash Memory
3.0 Volt-only Read, Program and Erase
Production Pending
Production subject to customer demand. Contact your
local AMD sale representative for ordering information.
Valid Combinations
Valid Combinations list configurations planned to be sup-
ported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.
April 7, 2003
Am29LV116M
7
P E N D I N G
DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register itself
does not occupy any addressable memory location.
The register is composed of latches that store the com-
mands, along with the address and data information
needed to execute the command. The contents of the
register serve as inputs to the internal state machine.
The state machine outputs dictate the function of the
device. Table 1 lists the device bus operations, the in-
puts and control levels they require, and the resulting
output. The following subsections describe each of
these operations in further detail.
Table 1. Am29LV116M Device Bus Operations
Operation
CE#
L
OE#
L
WE#
H
RESET#
Addresses
AIN
DQ0–DQ7
DOUT
Read
Write
H
H
L
H
L
AIN
DIN
VCC
0.3 V
±
VCC ±
0.3 V
Standby
X
X
X
High-Z
Output Disable
Reset
L
H
X
H
X
H
L
X
X
High-Z
High-Z
X
Sector Addresses,
A6 = L, A1 = H, A0 = L
Sector Protect (See Note)
L
H
L
VID
DIN, DOUT
Sector Addresses
A6 = H, A1 = H, A0 = L
Sector Unprotect (See Note)
L
H
X
L
VID
VID
DIN, DOUT
DIN
Temporary Sector Unprotect
X
X
AIN
Legend:
L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’t Care, AIN = Address In, DIN = Data In, DOUT = Data Out
Note: The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector
Protection/Unprotection” section.
Requirements for Reading Array Data
Writing Commands/Command Sequences
To read array data from the outputs, the system must
drive the CE# and OE# pins to VIL. CE# is the power
control and selects the device. OE# is the output con-
trol and gates array data to the output pins. WE#
should remain at VIH.
To write a command or command sequence (which in-
cludes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to VIL, and OE# to VIH.
The device features an Unlock Bypass mode to facil-
itate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are re-
quired to program a byte, instead of four. The “Byte
Program Command Sequence” section has details on
programming data to the device using both standard
and Unlock Bypass command sequences.
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory con-
tent occurs during the power transition. No command is
necessary in this mode to obtain array data. Standard
microprocessor read cycles that assert valid addresses
on the device address inputs produce valid data on the
device data outputs. The device remains enabled for
read access until the command register contents are
altered.
An erase operation can erase one sector, multiple sec-
tors, or the entire device. Tables 2 and 3 indicate the
address space that each sector occupies. A “sector ad-
dress” consists of the address bits required to uniquely
select a sector. The “Command Definitions” section
has details on erasing a sector or the entire chip, or
suspending/resuming the erase operation.
See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifica-
tions and to Figure 12 for the timing diagram. ICC1 in
the DC Characteristics table represents the active cur-
rent specification for reading array data.
After the system writes the autoselect command se-
quence, the device enters the autoselect mode. The
system can then read autoselect codes from the inter-
nal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in this
8
Am29LV116M
April 7, 2003
P E N D I N G
mode. Refer to the Autoselect Mode and Autoselect
Command Sequence sections for more information.
dard address access timings provide new data when
addresses are changed. While in sleep mode, output
data is latched and always available to the system. ICC5
in the DC Characteristics table represents the auto-
matic sleep mode current specification.
ICC2 in the DC Characteristics table represents the ac-
tive current specification for the write mode. The “AC
Characteristics” section contains timing specification
tables and timing diagrams for write operations.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of reset-
ting the device to reading array data. When the RE-
SET# pin is driven low for at least a period of tRP, the
device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the internal state ma-
chine to reading array data. The operation that was in-
terrupted should be reinitiated once the device is ready
to accept another command sequence, to ensure data
integrity.
Program and Erase Operation Status
During an erase or program operation, the system may
check the status of the operation by reading the status
bits on DQ7–DQ0. Standard read cycle timings and ICC
read specifications apply. Refer to “Write Operation
Status” for more information, and to “AC Characteris-
tics” for timing diagrams.
Standby Mode
When the system is not reading or writing to the device,
it can place the device in the standby mode. In this
mode, current consumption is greatly reduced, and the
outputs are placed in the high impedance state, inde-
pendent of the OE# input.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at VSS±0.3 V, the device
draws CMOS standby current (ICC4). If RESET# is held
at VIL but not within VSS±0.3 V, the standby current will
be greater.
The device enters the CMOS standby mode when the
CE# and RESET# pins are both held at VCC ± 0.3 V.
(Note that this is a more restricted voltage range than
VIH.) If CE# and RESET# are held at VIH, but not within
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
VCC ± 0.3 V, the device will be in the standby mode, but
the standby current will be greater. The device requires
standard access time (tCE) for read access when the
device is in either of these standby modes, before it is
ready to read data.
If RESET# is asserted during a program or erase oper-
ation, the RY/BY# pin remains a “0” (busy) until the in-
ternal reset operation is complete, which requires a
time of tREADY (during Embedded Algorithms). The
system can thus monitor RY/BY# to determine whether
the reset operation is complete. If RESET# is asserted
when a program or erase operation is not executing
(RY/BY# pin is “1”), the reset operation is completed
within a time of tREADY (not during Embedded Algo-
rithms). The system can read data tRH after the RE-
SET# pin returns to VIH.
The device also enters the standby mode when the
RESET# pin is driven low. Refer to the next section,
“RESET#: Hardware Reset Pin”.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
ICC3 in the DC Characteristics table represents the
standby current specification.
Refer to the AC Characteristics tables for RESET# pa-
rameters and to Figure 13 for the timing diagram.
Automatic Sleep Mode
Output Disable Mode
The automatic sleep mode minimizes Flash device
energy consumption. The device automatically
enables this mode when addresses remain stable for
tACC + 30 ns. The automatic sleep mode is indepen-
dent of the CE#, WE#, and OE# control signals. Stan-
When the OE# input is at VIH, output from the device is
disabled. The output pins are placed in the high imped-
ance state.
April 7, 2003
Am29LV116M
9
P E N D I N G
Table 2. Am29LV116MT Top Boot Sector Address Table
Sector Size
Address Range
(in hexadecimal)
Sector
SA0
A20
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A19
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
A18
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
A17
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
1
A16
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
A15
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
A14
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
A13
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
(Kbytes)
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
32
8
000000–00FFFF
010000–01FFFF
020000–02FFFF
030000–03FFFF
040000–04FFFF
050000–05FFFF
060000–06FFFF
070000–07FFFF
080000–08FFFF
090000–09FFFF
0A0000–0AFFFF
0B0000–0BFFFF
0C0000–0CFFFF
0D0000–0DFFFF
0E0000–0EFFFF
0F0000–0FFFFF
100000–10FFFF
110000–11FFFF
120000–12FFFF
130000–13FFFF
140000–14FFFF
150000–15FFFF
160000–16FFFF
170000–17FFFF
180000–18FFFF
190000–19FFFF
1A0000–1AFFFF
1B0000–1BFFFF
1C0000–1CFFFF
1D0000–1DFFFF
1E0000–1EFFFF
1F0000–1F7FFF
1F8000–1F9FFF
1FA000–1FBFFF
1FC000–1FFFFF
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
1
1
0
1
8
1
1
X
16
10
Am29LV116M
April 7, 2003
P E N D I N G
Table 3. Am29LV116MB Bottom Boot Sector Address Table
Sector Size
Address Range
(in hexadecimal)
Sector
SA0
A20
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A19
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A18
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A17
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A16
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
A15
A14
A13
X
0
(Kbytes)
16
8
0
0
000000–003FFF
004000–005FFF
006000–007FFF
008000–00FFFF
010000–01FFFF
020000–02FFFF
030000–03FFFF
040000–04FFFF
050000–05FFFF
060000–06FFFF
070000–07FFFF
080000–08FFFF
090000–09FFFF
0A0000–0AFFFF
0B0000–0BFFFF
0C0000–0CFFFF
0D0000–0DFFFF
0E0000–0EFFFF
0F0000–0FFFFF
100000–10FFFF
110000–11FFFF
120000–12FFFF
130000–13FFFF
140000–14FFFF
150000–15FFFF
160000–16FFFF
170000–17FFFF
180000–18FFFF
190000–19FFFF
1A0000–1AFFFF
1B0000–1BFFFF
1C0000–1CFFFF
1D0000–1DFFFF
1E0000–1EFFFF
1F0000–1FFFFF
SA1
0
1
SA2
0
1
1
8
SA3
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
32
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
SA4
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
April 7, 2003
Am29LV116M
11
P E N D I N G
Table 4. In addition, when verifying sector protection,
Autoselect Mode
the sector address must appear on the appropriate
highest order address bits (see Tables 2 and 3). Table
4 shows the remaining address bits that are don’t care.
When all necessary bits have been set as required, the
programming equipment may then read the corre-
sponding identifier code on DQ7-DQ0.
The autoselect mode provides manufacturer and de-
vice identification, and sector protection verification,
through identifier codes output on DQ7–DQ0. This
mode is primarily intended for programming equipment
to automatically match a device to be programmed with
its corresponding programming algorithm. However,
the autoselect codes can also be accessed in-system
through the command register.
To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in Table 9. This method
does not require VID. See “Command Definitions” for
details on using the autoselect mode.
When using programming equipment, the autoselect
mode requires VID (11.5 V to 12.5 V) on address pin
A9. Address pins A6, A1, and A0 must be as shown in
Table 4. Am29LV116M Autoselect Codes (High Voltage Method)
A20 A12
to to
OE# WE# A13 A10
A8
to
A7
A5
to
A2
DQ7
to
DQ0
Description
CE#
A9
A6
A1
A0
Manufacturer ID: AMD
L
L
L
H
H
X
X
X
X
VID
X
X
L
X
X
L
L
01h
Device ID: Am29LV116M
(Top Boot Block)
L
L
VID
VID
L
L
L
L
H
H
C7h
Device ID: Am29LV116M
(Bottom Boot Block)
L
L
H
H
X
X
X
X
X
X
X
4Ch
01h
(protected)
Sector Protection Verification
L
SA
VID
L
H
L
00h
(unprotected)
L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.
12
Am29LV116M
April 7, 2003
P E N D I N G
SET# pin, all the previously protected sectors are
Sector Protection/Unprotection
protected again. Figure 1 shows the algorithm, and
Figure 19 shows the timing diagrams, for this feature.
The hardware sector protection feature disables both
program and erase operations in any sector. The hard-
ware sector unprotection feature re-enables both pro-
gram and erase operations in previously protected
sectors.
START
Sector protection/unprotection requires VID on the RE-
SET# pin only, and can be implemented either in-sys-
tem or via programming equipment. Figure 1 shows the
algorithms and Figure 20 shows the timing diagram.
This method uses standard microprocessor bus cycle
timing. For sector unprotect, all unprotected sectors
must first be protected prior to the first sector unprotect
write cycle.
RESET# = VID
(Note 1)
Perform Erase or
Program Operations
RESET# = VIH
The device is shipped with all sectors unprotected.
AMD offers the option of programming and protecting
sectors at its factory prior to shipping the device
through AMD’s ExpressFlash™ Service. Contact an
AMD representative for details.
Temporary Sector
Unprotect Completed
(Note 2)
It is possible to determine whether a sector is protected
or unprotected. See “Autoselect Mode” for details.
Temporary Sector Unprotect
Notes:
This feature allows temporary unprotection of previ-
ously protected sectors to change data in-system. The
Sector Unprotect mode is activated by setting the RE-
SET# pin to VID. During this mode, formerly protected
sectors can be programmed or erased by selecting the
sector addresses. Once VID is removed from the RE-
1. All protected sectors unprotected.
2. All previously protected sectors are protected once
again.
Figure 1. Temporary Sector Unprotect Operation
April 7, 2003
Am29LV116M
13
P E N D I N G
START
START
Protect all sectors:
PLSCNT = 1
PLSCNT = 1
RESET# = VID
The indicated portion
of the sector protect
algorithm must be
performed for all
unprotected sectors
prior to issuing the
first sector
RESET# = VID
Wait 1 µs
Wait 1 µs
unprotect address
No
First Write
No
First Write
Cycle = 60h?
Temporary Sector
Unprotect Mode
Temporary Sector
Unprotect Mode
Cycle = 60h?
Yes
Yes
Set up sector
address
No
All sectors
protected?
Sector Protect:
Write 60h to sector
address with
A6 = 0, A1 = 1,
A0 = 0
Yes
Set up first sector
address
Sector Unprotect:
Wait 150 µs
Write 60h to sector
address with
A6 = 1, A1 = 1,
A0 = 0
Verify Sector
Protect: Write 40h
to sector address
with A6 = 0,
Reset
PLSCNT = 1
Increment
PLSCNT
Wait 15 ms
A1 = 1, A0 = 0
Verify Sector
Unprotect: Write
40h to sector
address with
A6 = 1, A1 = 1,
A0 = 0
Read from
sector address
with A6 = 0,
A1 = 1, A0 = 0
Increment
PLSCNT
No
No
PLSCNT
= 25?
Read from
sector address
with A6 = 1,
Data = 01h?
Yes
A1 = 1, A0 = 0
No
Yes
Set up
next sector
address
Yes
No
PLSCNT
= 1000?
Protect another
sector?
Data = 00h?
Yes
Device failed
No
Yes
Remove VID
from RESET#
No
Last sector
verified?
Device failed
Write reset
command
Yes
Remove VID
In System
from RESET#
In System
Sector Protect
complete
Single High Voltage
Sector Unprotect
Algorithm
Single High Voltage
Sector Protect
Algorithm
Write reset
command
Sector Unprotect
complete
Figure 1. In-System Single High Voltage Sector Protect/Unprotect Algorithms
14
Am29LV116M
April 7, 2003
P E N D I N G
Factory Locked: SecSi Sector Programmed and
SecSi (Secured Silicon) Sector Flash
Memory Region
Protected At the Factory
In devices with an ESN, the SecSi Sector is protected
when the device is shipped from the factory. The SecSi
Sector cannot be modified in any way. A factory locked
device has an 8-word/16-byte random ESN at ad-
dresses 000000h–000007h.
The SecSi (Secured Silicon) Sector feature provides a
Flash memory region that enables permanent part
identification through an Electronic Serial Number
(ESN). The SecSi Sector is 128 words/256 bytes in
length, and uses a SecSi Sector Indicator Bit (DQ7) to
indicate whether or not the SecSi Sector is locked
when shipped from the factory. This bit is permanently
set at the factory and cannot be changed, which pre-
vents cloning of a factory locked part. This ensures the
security of the ESN once the product is shipped to the
field.
Customers may opt to have their code programmed by
AMD through the AMD ExpressFlash service. The de-
vices are then shipped from AMD’s factory with the
SecSi Sector permanently locked. Contact an AMD
representative for details on using AMD’s Express-
Flash service.
AMD offers the device with the SecSi Sector either
factory locked or customer lockable. The factory-
locked version is always protected when shipped from
the factory, and has the SecSi (Secured Silicon) Sec-
tor Indicator Bit permanently set to a “1.” The cus-
tomer-lockable version is shipped with the SecSi
Sector unprotected, allowing customers to program
the sector after receiving the device. The customer-
lockable version also has the SecSi Sector Indicator
Bit permanently set to a “0.” Thus, the SecSi Sector In-
dicator Bit prevents customer-lockable devices from
being used to replace devices that are factory locked.
Customer Lockable: SecSi Sector NOT
Programmed or Protected At the Factory
As an alternative to the factory-locked version, the de-
vice may be ordered such that the customer may pro-
gram and protect the 128-word/256 bytes SecSi
sector.
The system may program the SecSi Sector using the
write-buffer, accelerated and/or unlock bypass meth-
ods, in addition to the standard programming com-
mand sequence. See Command Definitions.
Programming and protecting the SecSi Sector must be
used with caution since, once protected, there is no
procedure available for unprotecting the SecSi Sector
area and none of the bits in the SecSi Sector memory
space can be modified in any way.
The SecSi sector address space in this device is allo-
cated as follows:
Table 1. SecSi Sector Contents
SecSi Sector
Address Range
Standard
Factory
Locked
ExpressFlash
Factory Locked
Customer
Lockable
The SecSi Sector area can be protected using one of
the following procedures:
x16
x8
ESN or
determined by
customer
000000h– 000000h–
000007h 00000Fh
ESN
Determined by
customer
■ Write the three-cycle Enter SecSi Sector Region
command sequence, and then follow the in-system
sector protect algorithm as shown in Figure 1,
except that RESET# may be at either VIH or VID.
This allows in-system protection of the SecSi Sector
without raising any device pin to a high voltage.
Note that this method is only applicable to the SecSi
Sector.
000008h– 000010h–
00007Fh 0000FFh
Determined by
customer
Unavailable
The system accesses the SecSi Sector through a
command sequence (see “Enter SecSi Sector/Exit
SecSi Sector Command Sequence”). After the system
has written the Enter SecSi Sector command se-
quence, it may read the SecSi Sector by using the ad-
dresses normally occupied by the first sector (SA0).
This mode of operation continues until the system is-
sues the Exit SecSi Sector command sequence, or
until power is removed from the device. On power-up,
or following a hardware reset, the device reverts to
sending commands to sector SA0. Note that the ACC
function and unlock bypass modes are not available
when the SecSi Sector is enabled.
■ To verify the protect/unprotect status of the SecSi
Sector, follow the algorithm shown in Figure 2.
Once the SecSi Sector is programmed, locked and
verified, the system must write the Exit SecSi Sector
Region command sequence to return to reading and
writing within the remainder of the array.
April 7, 2003
Am29LV116M
15
P E N D I N G
against inadvertent writes (refer to Table 9 for com-
mand definitions). In addition, the following hardware
data protection measures prevent accidental erasure
or programming, which might otherwise be caused by
spurious system level signals during VCC power-up
and power-down transitions, or from system noise.
START
If data = 00h,
SecSi Sector is
unprotected.
If data = 01h,
SecSi Sector is
protected.
RESET# =
VIH or VID
Low V
Write Inhibit
CC
When VCC is less than VLKO, the device does not ac-
cept any write cycles. This protects data during VCC
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until VCC
is greater than VLKO. The system must provide the
proper signals to the control pins to prevent uninten-
Wait 1 µs
Write 60h to
any address
Remove VIH or VID
from RESET#
Write 40h to SecSi
Sector address
with A6 = 0,
Write reset
command
tional writes when VCC is greater than VLKO
.
A1 = 1, A0 = 0
Write Pulse “Glitch” Protection
SecSi Sector
Protect Verify
complete
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
Read from SecSi
Sector address
with A6 = 0,
Logical Inhibit
A1 = 1, A0 = 0
Write cycles are inhibited by holding any one of OE# =
VIL, CE# = VIH or WE# = VIH. To initiate a write cycle,
CE# and WE# must be a logical zero while OE# is a
logical one.
Figure 2. SecSi Sector Protect Verify
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power up, the
device does not accept commands on the rising edge
of WE#. The internal state machine is automatically
reset to reading array data on power-up.
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
data. The system can read CFI information at the
addresses given in Tables 5–8. To terminate reading
CFI data, the system must write the reset command.
COMMON FLASH MEMORY INTERFACE
(CFI)
The Common Flash Interface (CFI) specification out-
lines device and host system software interrogation
handshake, which allows specific vendor-specified
software algorithms to be used for entire families of
devices. Software support can then be device-indepen-
dent, JEDEC ID-independent, and forward- and back-
ward-compatible for the specified flash device families.
Flash vendors can standardize their existing interfaces
for long-term compatibility.
The system can also write the CFI query command
when the device is in the autoselect mode. The device
enters the CFI query mode, and the system can read
CFI data at the addresses given in Tables 5–8. The
system must write the reset command to return the
device to the read mode.
For further information, please refer to the CFI Specifi-
cation and CFI Publication 100, available via the World
Wide Web at http://www.amd.com/flash/cfi. Alterna-
tively, contact an AMD representative for copies of
these documents.
This device enters the CFI Query mode when the
system writes the CFI Query command, 98h, to
address 55h, any time the device is ready to read array
16
Am29LV116M
April 7, 2003
P E N D I N G
Table 5. CFI Query Identification String
Addresses
Data
Description
10h
11h
12h
51h
52h
59h
Query Unique ASCII string “QRY”
13h
14h
02h
00h
Primary OEM Command Set
15h
16h
40h
00h
Address for Primary Extended Table
17h
18h
00h
00h
Alternate OEM Command Set (00h = none exists)
Address for Alternate OEM Extended Table (00h = none exists)
19h
1Ah
00h
00h
Table 6. System Interface String
Description
Addresses
Data
V
CC Min. (write/erase)
1Bh
27h
D7–D4: volt, D3–D0: 100 millivolt
VCC Max. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Ch
36h
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
00h
00h
07h
00h
0Ah
00h
01h
00h
04h
00h
VPP Min. voltage (00h = no VPP pin present)
VPP Max. voltage (00h = no VPP pin present)
Typical timeout per single byte/word write 2N µs
Typical timeout for Min. size buffer write 2N µs (00h = not supported)
Typical timeout per individual block erase 2N ms
Typical timeout for full chip erase 2N ms (00h = not supported)
Max. timeout for byte/word write 2N times typical
Max. timeout for buffer write 2N times typical
Max. timeout per individual block erase 2N times typical
Max. timeout for full chip erase 2N times typical (00h = not supported)
April 7, 2003
Am29LV116M
17
P E N D I N G
Table 7. Device Geometry Definition
Addresses
Data
Description
27h
15h
Device Size = 2N byte
28h
29h
00h
00h
Flash Device Interface description (refer to CFI publication 100)
2Ah
2Bh
00h
00h
Max. number of byte in multi-byte write = 2N
(00h = not supported)
2Ch
04h
Number of Erase Block Regions within device
2Dh
2Eh
2Fh
30h
00h
00h
40h
00h
Erase Block Region 1 Information
(refer to the CFI specification or CFI publication 100)
31h
32h
33h
34h
01h
00h
20h
00h
Erase Block Region 2 Information
Erase Block Region 3 Information
Erase Block Region 4 Information
35h
36h
37h
38h
00h
00h
80h
00h
39h
3Ah
3Bh
3Ch
1Eh
00h
00h
01h
18
Am29LV116M
April 7, 2003
P E N D I N G
Table 8. Primary Vendor-Specific Extended Query
Addresses
Data
Description
40h
41h
42h
50h
52h
49h
Query-unique ASCII string “PRI”
43h
44h
31h
33h
Major version number, ASCII
Minor version number, ASCII
Address Sensitive Unlock (Bit 1-0)
0 = Required, 1 = Not Required
45h
46h
08h
02h
Process Technology (Bit 7-2)
10b = 0.23 µm MirrorBit
Erase Suspend
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
Sector Protect
0 = Not Supported, X = Number of sectors in per group
47h
48h
01h
01h
Sector Temporary Unprotect: 00 = Not Supported, 01 = Supported
Sector Protect/Unprotect scheme
49h
04h
01 = 29F040 mode, 02 = 29F016 mode,
03 = 29F400 mode, 04 = 29LV800A mode
4Ah
4Bh
00h
00h
Simultaneous Operation: 00 = Not Supported, 01 = Supported
Burst Mode Type: 00 = Not Supported, 01 = Supported
Page Mode Type: 00 = Not Supported, 01 = 4 Word Page,
02 = 8 Word Page
4Ch
00h
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Am29LV116M
19
P E N D I N G
COMMAND DEFINITIONS
Writing specific address and data commands or se-
quences into the command register initiates device op-
erations. Table 9 defines the valid register command
sequences. Writing incorrect address and data values
or writing them in the improper sequence may place
the device in an unknown state. A reset command is
then required to return the device to reading array data.
however, the device ignores reset commands until the
operation is complete.
The reset command may be written between the se-
quence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command must
be written to return to reading array data (also applies
to autoselect during Erase Suspend).
All addresses are latched on the falling edge of WE# or
CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in the
“AC Characteristics” section.
If DQ5 goes high during a program or erase operation,
writing the reset command returns the device to read-
ing array data (also applies during Erase Suspend).
Autoselect Command Sequence
The autoselect command sequence allows the host
system to access the manufacturer and devices codes,
and determine whether or not a sector is protected.
Table 9 shows the address and data requirements.
This method is an alternative to that shown in Table 4,
which is intended for PROM programmers and requires
VID on address bit A9.
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array
data after completing an Embedded Program or Em-
bedded Erase algorithm.
After the device accepts an Erase Suspend command,
the device enters the Erase Suspend mode. The sys-
tem can read array data using the standard read tim-
ings, except that if it reads at an address within erase-
suspended sectors, the device outputs status data.
After completing a programming operation in the Erase
Suspend mode, the system may once again read array
data with the same exception. See “Erase Sus-
pend/Erase Resume Commands” for more information
on this mode.
The autoselect command sequence is initiated by writ-
ing two unlock cycles, followed by the autoselect com-
mand. The device then enters the autoselect mode,
and the system may read at any address any number
of times, without initiating another command sequence.
A read cycle at address XX00h retrieves the manufac-
turer code. A read cycle at address XX01h returns the
device code. A read cycle containing a sector address
(SA) and the address XX02h returns XX01h if that sec-
tor is protected, or 00h if it is unprotected. Refer to Ta-
bles 2 and 3 for valid sector addresses.
The system must issue the reset command to re-en-
able the device for reading array data if DQ5 goes high,
or while in the autoselect mode. See the “Reset Com-
mand” section, next.
The system must write the reset command to exit the
autoselect mode and return to reading array data.
Byte Program Command Sequence
See also “Requirements for Reading Array Data” in the
“Device Bus Operations” section for more information.
The Read Operations table provides the read parame-
ters, and Figure 12 shows the timing diagram.
The device programs one byte of data for each pro-
gram operation. The command sequence requires four
bus cycles, and is initiated by writing two unlock write
cycles, followed by the program set-up command. The
program address and data are written next, which in
turn initiate the Embedded Program algorithm. The
system is not required to provide further controls or tim-
ings. The device automatically generates the program
pulses and verifies the programmed cell margin. Table
9 shows the address and data requirements for the
byte program command sequence.
Reset Command
Writing the reset command to the device resets the de-
vice to reading array data. Address bits are don’t care
for this command.
The reset command may be written between the se-
quence cycles in an erase command sequence before
erasing begins. This resets the device to reading array
data. Once erasure begins, however, the device ig-
nores reset commands until the operation is complete.
When the Embedded Program algorithm is complete,
the device then returns to reading array data and ad-
dresses are no longer latched. The system can deter-
mine the status of the program operation by using
DQ7, DQ6, or RY/BY#. See “Write Operation Status”
for information on these status bits.
The reset command may be written between the se-
quence cycles in a program command sequence be-
fore programming begins. This resets the device to
reading array data (also applies to programming in
Erase Suspend mode). Once programming begins,
Any commands written to the device during the Em-
bedded Program Algorithm are ignored. Note that a
20
Am29LV116M
April 7, 2003
P E N D I N G
hardware reset immediately terminates the program-
don’t cares for both cycles. The device then returns to
reading array data.
ming operation. The Byte Program command se-
quence should be reinitiated once the device has reset
to reading array data, to ensure data integrity. Note that
the SecSi Sector, autoselect, and CFI functions are un-
available when a program operation is in progress.
Figure 3 illustrates the algorithm for the program oper-
ation. See the Erase/Program Operations table in “AC
Characteristics” for parameters, and to Figure 14 for
timing diagrams
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
from a “0” back to a “1”. Attempting to do so may halt
the operation and set DQ5 to “1,” or cause the Data#
Polling algorithm to indicate the operation was suc-
cessful. However, a succeeding read will show that the
data is still “0”. Only erase operations can convert a “0”
to a “1”.
START
Write Program
Command Sequence
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to pro-
gram bytes to the device faster than using the standard
program command sequence. The unlock bypass com-
mand sequence is initiated by first writing two unlock
cycles. This is followed by a third write cycle containing
the unlock bypass command, 20h. The device then en-
ters the unlock bypass mode. A two-cycle unlock by-
pass program command sequence is all that is
required to program in this mode. The first cycle in this
sequence contains the unlock bypass program com-
mand, A0h; the second cycle contains the program ad-
dress and data. Additional data is programmed in the
same manner. This mode dispenses with the initial two
unlock cycles required in the standard program com-
mand sequence, resulting in faster total programming
time. Table 9 shows the requirements for the command
sequence.
Data Poll
from System
Embedded
Program
algorithm
in progress
Verify Data?
No
Yes
No
Increment Address
Last Address?
Yes
Programming
Completed
During the unlock bypass mode, only the Unlock By-
pass Program and Unlock Bypass Reset commands
are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset com-
mand sequence. The first cycle must contain the data
90h; the second cycle the data 00h. Addresses are
Note: See Table 9 for program command sequence.
Figure 3. Program Operation
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Am29LV116M
21
P E N D I N G
otherwise the last address and command might not be
Chip Erase Command Sequence
accepted, and erasure may begin. It is recommended
that processor interrupts be disabled during this time to
ensure all commands are accepted. The interrupts can
be re-enabled after the last Sector Erase command is
written. If the time between additional sector erase
commands can be assumed to be less than 50 µs, the
system need not monitor DQ3. Any command other
than Sector Erase or Erase Suspend during the
time-out period resets the device to reading array
data. The system must rewrite the command sequence
and any additional sector addresses and commands.
Note that the SecSi Sector, autoselect, and CFI func-
tions are unavailable when an erase operation is in
progress.
Chip erase is a six bus cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algo-
rithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
trols or timings during these operations. Table 9 shows
the address and data requirements for the chip erase
command sequence.
Any commands written to the chip during the Embed-
ded Erase algorithm are ignored. Note that a hardware
reset during the chip erase operation immediately ter-
minates the operation. The Chip Erase command se-
quence should be reinitiated once the device has
returned to reading array data, to ensure data integrity.
Note that the SecSi Sector, autoselect, and CFI func-
tions are unavailable when an erase operation is in
progress.
The system can monitor DQ3 to determine if the sector
erase timer has timed out. (See the “DQ3: Sector
Erase Timer” section.) The time-out begins from the ris-
ing edge of the final WE# pulse in the command se-
quence.
Once the sector erase operation has begun, only the
Erase Suspend command is valid. All other commands
are ignored. Note that a hardware reset during the
sector erase operation immediately terminates the op-
eration. The Sector Erase command sequence should
be reinitiated once the device has returned to reading
array data, to ensure data integrity.
The system can determine the status of the erase op-
eration by using DQ7, DQ6, DQ2, or RY/BY#. See
“Write Operation Status” for information on these sta-
tus bits. When the Embedded Erase algorithm is com-
plete, the device returns to reading array data and
addresses are no longer latched.
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses are
no longer latched. The system can determine the sta-
tus of the erase operation by using DQ7, DQ6, DQ2, or
RY/BY#. (Refer to “Write Operation Status” for informa-
tion on these status bits.)
Figure 4 illustrates the algorithm for the erase opera-
tion. See the Erase/Program Operations tables in “AC
Characteristics” for parameters, and to Figure 15 for
timing diagrams.
Figure 4 illustrates the algorithm for the erase opera-
tion. Refer to the Erase/Program Operations tables in
the “AC Characteristics” section for parameters, and to
Figure 15 for timing diagrams.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two ad-
ditional unlock write cycles are then followed by the ad-
dress of the sector to be erased, and the sector erase
command. Table 9 shows the address and data re-
quirements for the sector erase command sequence.
Erase Suspend/Erase Resume Commands
The Erase Suspend command allows the system to in-
terrupt a sector erase operation and then read data
from, or program data to, any sector not selected for
erasure. This command is valid only during the sector
erase operation, including the time-out period 50 µs
during the sector erase command sequence. The
Erase Suspend command is ignored if written during
the chip erase operation or Embedded Program algo-
rithm. Writing the Erase Suspend command during the
Sector Erase time-out immediately terminates the
time-out period and suspends the erase operation. Ad-
dresses are “don’t-cares” when writing the Erase Sus-
pend command.
The device does not require the system to preprogram
the memory prior to erase. The Embedded Erase algo-
rithm automatically programs and verifies the sector for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or tim-
ings during these operations.
After the command sequence is written, a sector erase
time-out of 50 µs begins. During the time-out period,
additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of sec-
tors may be from one sector to all sectors. The time be-
tween these additional cycles must be less than 50 µs,
When the Erase Suspend command is written during a
sector erase operation, the device requires a maximum
of 20 µs to suspend the erase operation. However,
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Am29LV116M
April 7, 2003
P E N D I N G
when the Erase Suspend command is written during
Erase Suspend command can be written after the de-
vice has resumed erasing.
the sector erase time-out, the device immediately ter-
minates the time-out period and suspends the erase
operation.
After the erase operation has been suspended, the
system can read array data from or program data to
any sector not selected for erasure. (The device “erase
suspends” all sectors selected for erasure.) Normal
read and write timings and command definitions apply.
Reading at any address within erase-suspended sec-
tors produces status data on DQ7–DQ0. The system
can use DQ7, or DQ6 and DQ2 together, to determine
if a sector is actively erasing or is erase-suspended.
See “Write Operation Status” for information on these
status bits.
START
Write Erase
Command Sequence
Data Poll
from System
Embedded
After an erase-suspended program operation is com-
plete, the system can once again read array data within
non-suspended sectors. The system can determine the
status of the program operation using the DQ7 or DQ6
status bits, just as in the standard program operation.
See “Write Operation Status” for more information.
Erase
algorithm
in progress
No
Data = FFh?
The system may also write the autoselect command
sequence when the device is in the Erase Suspend
mode. The device allows reading autoselect codes
even at addresses within erasing sectors, since the
codes are not stored in the memory array. When the
device exits the autoselect mode, the device reverts to
the Erase Suspend mode, and is ready for another
valid operation. See “Autoselect Command Sequence”
for more information.
Yes
Erasure Completed
Notes:
1. See Table 9 for erase command sequence.
The system must write the Erase Resume command
(address bits are “don’t care”) to exit the erase suspend
mode and continue the sector erase operation. Further
writes of the Resume command are ignored. Another
2. See “DQ3: Sector Erase Timer” for more information.
Figure 4. Erase Operation
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Am29LV116M
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P E N D I N G
The system must write the Program Resume com-
Program Suspend/Program Resume
Command Sequence
mand (address bits are don’t care) to exit the Program
Suspend mode and continue the programming opera-
tion. Further writes of the Resume command are ig-
nored. Another Program Suspend command can be
written after the device has resume programming.
The Program Suspend command allows the system to
interrupt a programming operation or a Write to Buffer
programming operation so that data can be read from
any non-suspended sector. When the Program Sus-
pend command is written during a programming pro-
cess, the device halts the program operation within 15
µs maximum (5µs typical) and updates the status bits.
Addresses are not required when writing the Program
Suspend command.
Program Operation
or Write-to-Buffer
Sequence in Progress
Write Program Suspend
Command Sequence
After the programming operation has been sus-
pended, the system can read array data from any non-
suspended sector. The Program Suspend command
may also be issued during a programming operation
while an erase is suspended. In this case, data may
be read from any addresses not in Erase Suspend or
Program Suspend. If a read is needed from the SecSi
Sector area (One-time Program area), then user must
use the proper command sequences to enter and exit
this region.
Write address/data
XXXh/B0B0h
Command is also valid for
Erase-suspended-program
operations
Wait 15 µs
Autoselect and SecSi Sector
read operations are also allowed
Read data as
required
Data cannot be read from erase- or
program-suspended sectors
The system may also write the autoselect command
sequence when the device is in the Program Suspend
mode. The system can read as many autoselect
codes as required. When the device exits the autose-
lect mode, the device reverts to the Program Suspend
mode, and is ready for another valid operation. See
Autoselect Command Sequence for more information.
Done
reading?
No
Yes
Write Program Resume
Command Sequence
Write address/data
XXXh/3030h
After the Program Resume command is written, the
device reverts to programming. The system can deter-
mine the status of the program operation using the
DQ7 or DQ6 status bits, just as in the standard pro-
gram operation. See Write Operation Status for more
information.
Device reverts to
operation prior to
Program Suspend
Figure 5. Program Suspend/Program Resume
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Am29LV116M
April 7, 2003
P E N D I N G
Command Definitions
Table 9. Am29LV116M Command Definitions
Bus Cycles (Notes 2–4)
Command Sequence
(Note 1)
First
Second
Third
Fourth
Fifth
Sixth
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read (Note 5)
Reset (Note 6)
1
1
4
RA
XXX
555
RD
F0
Manufacturer ID
AA
2AA
2AA
55
55
555
555
90
90
X00
X01
01
Device ID,
Top Boot Block
C7
4
555
555
AA
Device ID,
Bottom Boot Block
4C
00
01
Sector Protect
Verify (Note 8)
SA
X02
4
AA
2AA
55
555
90
CFI Query (Note 9)
1
4
3
55
98
AA
AA
Byte Program
Unlock Bypass
555
555
2AA
2AA
55
55
555
555
A0
20
PA
PD
Unlock Bypass Program
(Note 10)
2
2
XXX
XXX
A0
90
PA
PD
00
Unlock Bypass Reset
(Note 11)
XXX
Chip Erase
6
6
555
555
AA
AA
2AA
2AA
55
55
555
555
80
80
555
555
AA
AA
2AA
2AA
55
55
555
SA
10
30
Sector Erase
Program/Erase Suspend
(Note 12)
1
1
XXX
XXX
B0
30
Program/Erase Resume
(Note 13)
Legend:
X = Don’t care
PD = Data to be programmed at location PA. Data is latched
on the rising edge of WE# or CE# pulse.
RA = Address of the memory location to be read.
SA = Address of the sector to be erased or verified. Address
bits A20–A13 uniquely select any sector.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed.
Addresses are latched on the falling edge of the WE# or CE#
pulse.
Notes:
1. See Table 1 for descriptions of bus operations.
8. The data is 00h for an unprotected sector and 01h for a
protected sector.
2. All values are in hexadecimal.
9. Command is valid when device is ready to read array data
or when device is in autoselect mode.
3. Except when reading array or autoselect data, all bus
cycles are write operations.
10. The Unlock Bypass command is required prior to the
Unlock Bypass Program command.
4. Address bits A20–A11 are don’t care for unlock and
command cycles, except when PA or SA is required.
11. The Unlock Bypass Reset command is required to return
to reading array data when the device is in the Unlock
Bypass mode.
5. No unlock or command cycles required when device is in
read mode.
6. The Reset command is required to return to the read
mode when the device is in the autoselect mode or if DQ5
goes high.
12. The system may read and program functions in non-
erasing sectors, or enter the autoselect mode, when in
the Erase Suspend mode. The Erase Suspend command
is valid only during a sector erase operation.
7. The fourth cycle of the autoselect command sequence is
a read cycle.
13. The Erase Resume command is valid only during the
Erase Suspend mode.
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Am29LV116M
25
P E N D I N G
WRITE OPERATION STATUS
The device provides several bits to determine the sta-
tus of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7,
and RY/BY#. Table 10 and the following subsections
describe the functions of these bits. DQ7, RY/BY#, and
DQ6 each offer a method for determining whether a
program or erase operation is complete or in progress.
These three bits are discussed first.
Table 10 shows the outputs for Data# Polling on DQ7.
Figure 6 shows the Data# Polling algorithm.
START
DQ7: Data# Polling
Read DQ7–DQ0
Addr = VA
The Data# Polling bit, DQ7, indicates to the host sys-
tem whether an Embedded Algorithm is in progress or
completed, or whether the device is in Erase Suspend.
Data# Polling is valid after the rising edge of the final
WE# pulse in the program or erase command se-
quence.
Yes
DQ7 = Data?
During the Embedded Program algorithm, the device
outputs on DQ7 the complement of the datum pro-
grammed to DQ7. This DQ7 status also applies to pro-
gramming during Erase Suspend. When the
Embedded Program algorithm is complete, the device
outputs the datum programmed to DQ7. The system
must provide the program address to read valid status
information on DQ7. If a program address falls within a
protected sector, Data# Polling on DQ7 is active for
approximately 1 µs, then the device returns to reading
array data.
No
No
DQ5 = 1?
Yes
Read DQ7–DQ0
Addr = VA
During the Embedded Erase algorithm, Data# Polling
produces a “0” on DQ7. When the Embedded Erase al-
gorithm is complete, or if the device enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7.
This is analogous to the complement/true datum output
described for the Embedded Program algorithm: the
erase function changes all the bits in a sector to “1”;
prior to this, the device outputs the “complement,” or
“0.” The system must provide an address within any of
the sectors selected for erasure to read valid status in-
formation on DQ7.
Yes
DQ7 = Data?
No
PASS
FAIL
After an erase command sequence is written, if all sec-
tors selected for erasing are protected, Data# Polling
on DQ7 is active for approximately 100 µs, then the de-
vice returns to reading array data. If not all selected
sectors are protected, the Embedded Erase algorithm
erases the unprotected sectors, and ignores the se-
lected sectors that are protected.
Notes:
1. VA = Valid address for programming. During a sector
erase operation, a valid address is an address within any
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = “1” because
DQ7 may change simultaneously with DQ5.
When the system detects DQ7 has changed from the
complement to true data, it can read valid data at DQ7–
DQ0 on the following read cycles. This is because DQ7
may change asynchronously with DQ0–DQ6 while
Output Enable (OE#) is asserted low. Figure 16, Data#
Polling Timings (During Embedded Algorithms), in the
“AC Characteristics” section illustrates this.
Figure 6. Data# Polling Algorithm
26
Am29LV116M
April 7, 2003
P E N D I N G
Table 10 shows the outputs for Toggle Bit I on DQ6.
RY/BY#: Ready/Busy#
Figure 7 shows the toggle bit algorithm in flowchart
form, and the section “Reading Toggle Bits DQ6/DQ2”
explains the algorithm. Figure 17 in the “AC Character-
istics” section shows the toggle bit timing diagrams.
Figure 18 shows the differences between DQ2 and
DQ6 in graphical form. See also the subsection on
DQ2: Toggle Bit II.
The RY/BY# is a dedicated, open-drain output pin that
indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY# status is valid after
the rising edge of the final WE# pulse in the command
sequence. Since RY/BY# is an open-drain output, sev-
eral RY/BY# pins can be tied together in parallel with a
pull-up resistor to VCC. (The RY/BY# pin is not avail-
able on the 44-pin SO package.)
DQ2: Toggle Bit II
If the output is low (Busy), the device is actively erasing
or programming. (This includes programming in the
Erase Suspend mode.) If the output is high (Ready),
the device is ready to read array data (including during
the Erase Suspend mode), or is in the standby mode.
The “Toggle Bit II” on DQ2, when used with DQ6, indi-
cates whether a particular sector is actively erasing
(that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of the final WE# pulse in
the command sequence.
Table 10 shows the outputs for RY/BY#. Figures 12, 14
and 15 shows RY/BY# for reset, program, and erase
operations, respectively.
DQ2 toggles when the system reads at addresses
within those sectors that have been selected for era-
sure. (The system may use either OE# or CE# to con-
trol the read cycles.) But DQ2 cannot distinguish
whether the sector is actively erasing or is erase-sus-
pended. DQ6, by comparison, indicates whether the
device is actively erasing, or is in Erase Suspend, but
cannot distinguish which sectors are selected for era-
sure. Thus, both status bits are required for sector and
mode information. Refer to Table 10 to compare out-
puts for DQ2 and DQ6.
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or complete,
or whether the device has entered the Erase Suspend
mode. Toggle Bit I may be read at any address, and is
valid after the rising edge of the final WE# pulse in the
command sequence (prior to the program or erase op-
eration), and during the sector erase time-out.
During an Embedded Program or Erase algorithm op-
eration, successive read cycles to any address cause
DQ6 to toggle (The system may use either OE# or CE#
to control the read cycles). When the operation is com-
plete, DQ6 stops toggling.
Figure 7 shows the toggle bit algorithm in flowchart
form, and the section “Reading Toggle Bits DQ6/DQ2”
explains the algorithm. See also the DQ6: Toggle Bit I
subsection. Figure 17 shows the toggle bit timing dia-
gram. Figure 18 shows the differences between DQ2
and DQ6 in graphical form.
After an erase command sequence is written, if all sec-
tors selected for erasing are protected, DQ6 toggles for
approximately 100 µs, then returns to reading array
data. If not all selected sectors are protected, the Em-
bedded Erase algorithm erases the unprotected sec-
tors, and ignores the selected sectors that are
protected.
Reading Toggle Bits DQ6/DQ2
Refer to Figure 7 for the following discussion. When-
ever the system initially begins reading toggle bit sta-
tus, it must read DQ7–DQ0 at least twice in a row to
determine whether a toggle bit is toggling. Typically, the
system would note and store the value of the toggle bit
after the first read. After the second read, the system
would compare the new value of the toggle bit with the
first. If the toggle bit is not toggling, the device has com-
pleted the program or erase operation. The system can
read array data on DQ7–DQ0 on the following read cy-
cle.
The system can use DQ6 and DQ2 together to deter-
mine whether a sector is actively erasing or is erase-
suspended. When the device is actively erasing (that
is, the Embedded Erase algorithm is in progress), DQ6
toggles. When the device enters the Erase Suspend
mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing
or erase-suspended. Alternatively, the system can use
DQ7 (see the subsection on DQ7: Data# Polling).
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the sys-
tem also should note whether the value of DQ5 is high
(see the section on DQ5). If it is, the system should
then determine again whether the toggle bit is toggling,
since the toggle bit may have stopped toggling just as
DQ5 went high. If the toggle bit is no longer toggling,
the device has successfully completed the program or
erase operation. If it is still toggling, the device did not
completed the operation successfully, and the system
If a program address falls within a protected sector,
DQ6 toggles for approximately 1 µs after the program
command sequence is written, then returns to reading
array data.
DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded Pro-
gram algorithm is complete.
April 7, 2003
Am29LV116M
27
P E N D I N G
must write the reset command to return to reading
array data.
START
The remaining scenario is that the system initially de-
termines that the toggle bit is toggling and DQ5 has not
gone high. The system may continue to monitor the
toggle bit and DQ5 through successive read cycles, de-
termining the status as described in the previous para-
graph. Alternatively, it may choose to perform other
system tasks. In this case, the system must start at the
beginning of the algorithm when it returns to determine
the status of the operation (top of Figure 7).
Read DQ7–DQ0
(Note 1)
Read DQ7–DQ0
Table 10 shows the outputs for Toggle Bit I on DQ6.
Figure 7 shows the toggle bit algorithm. Figure 17 in the
“AC Characteristics” section shows the toggle bit timing
diagrams. Figure 18 shows the differences between
DQ2 and DQ6 in graphical form. See also the subsec-
tion on DQ2: Toggle Bit II.
No
Toggle Bit
= Toggle?
Yes
DQ5: Exceeded Timing Limits
No
DQ5 = 1?
Yes
DQ5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under
these conditions DQ5 produces a “1.” This is a failure
condition that indicates the program or erase cycle was
not successfully completed.
(Notes
1, 2)
Read DQ7–DQ0
Twice
The DQ5 failure condition may appear if the system
tries to program a “1” to a location that is previously
programmed to “0.” Only an erase operation can
change a “0” back to a “1.” Under this condition, the
device halts the operation, and when the operation has
exceeded the timing limits, DQ5 produces a “1.”
Toggle Bit
= Toggle?
No
Under both these conditions, the system must issue
the reset command to return the device to reading
array data.
Yes
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not an
erase operation has begun. (The sector erase timer
does not apply to the chip erase command.) If addi-
tional sectors are selected for erasure, the entire time-
out also applies after each additional sector erase com-
mand. When the time-out is complete, DQ3 switches
from “0” to “1.” If the time between additional sector
erase commands from the system can be assumed to
be less than 50 µs, the system need not monitor DQ3.
See also the “Sector Erase Command Sequence” sec-
tion.
Notes:
1. Read toggle bit twice to determine whether or not it is
toggling. See text.
2. Recheck toggle bit because it may stop toggling as DQ5
changes to “1”. See text.
Figure 7. Toggle Bit Algorithm
are ignored until the erase operation is complete. If
DQ3 is “0”, the device will accept additional sector
erase commands. To ensure the command has been
accepted, the system software should check the status
of DQ3 prior to and following each subsequent sector
erase command. If DQ3 is high on the second status
check, the last command might not have been ac-
cepted. Table 10 shows the outputs for DQ3.
After the sector erase command sequence is written,
the system should read the status on DQ7 (Data# Poll-
ing) or DQ6 (Toggle Bit I) to ensure the device has ac-
cepted the command sequence, and then read DQ3. If
DQ3 is “1”, the internally controlled erase cycle has be-
gun; all further commands (other than Erase Suspend)
28
Am29LV116M
April 7, 2003
P E N D I N G
Table 10. Write Operation Status
DQ7
DQ5
DQ2
Status
(Note 2)
DQ6
(Note 1)
DQ3
N/A
1
(Note 2)
DQ1 RY/BY#
Embedded Program Algorithm
Embedded Erase Algorithm
Program-Suspended
DQ7#
0
Toggle
Toggle
0
0
No toggle
Toggle
0
0
0
Standard
Mode
N/A
Invalid (not allowed)
Data
1
1
1
1
0
Program
Suspend
Mode
Program-
Sector
Suspend
Non-Program
Read
Suspended Sector
Erase-Suspended
1
No toggle
Toggle
0
N/A
Toggle
N/A
N/A
N/A
Erase-
Sector
Suspend
Erase
Suspend
Mode
Non-EraseSuspended
Read
Data
Sector
Erase-Suspend-Program
(Embedded Program)
DQ7#
0
N/A
Busy (Note 3)
Abort (Note 4)
DQ7#
DQ7#
Toggle
Toggle
0
0
N/A
N/A
N/A
N/A
0
1
0
0
Write-to-
Buffer
1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
See “DQ5: Exceeded Timing Limits” for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
April 7, 2003
Am29LV116M
29
P E N D I N G
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
Plastic Packages . . . . . . . . . . . . . . . –55°C to +150°C
20 ns
20 ns
Ambient Temperature
with Power Applied . . . . . . . . . . . . . –65°C to +125°C
+0.8 V
Voltage with Respect to Ground
–0.5 V
–2.0 V
VCC (Note 1) . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V
A9, OE#, and
RESET# (Note 2) . . . . . . . . . . . .–0.5 V to +12.5 V
20 ns
All other pins (Note 1) . . . . . . –0.5 V to VCC+0.5 V
Output Short Circuit Current (Note 3) . . . . . . 200 mA
Figure 8. Maximum Negative
Overshoot Waveform
Notes:
1. Minimum DC voltage on input or I/O pins is –0.5 V. During
voltage transitions, input or I/O pins may overshoot VSS
to –2.0 V for periods of up to 20 ns. See Figure 8.
Maximum DC voltage on input or I/O pins is VCC +0.5 V.
During voltage transitions, input or I/O pins may
overshoot to VCC +2.0 V for periods up to 20 ns. See
Figure 9.
20 ns
VCC
+2.0 V
VCC
2. Minimum DC input voltage on pins A9, OE#, and RESET#
is –0.5 V. During voltage transitions, A9, OE#, and
RESET# may overshoot VSS to –2.0 V for periods of up
to 20 ns. See Figure 8. Maximum DC input voltage on pin
A9 is +12.5 V which may overshoot to 14.0 V for periods
up to 20 ns.
+0.5 V
2.0 V
20 ns
20 ns
Figure 9. Maximum Positive
Overshoot Waveform
3. No more than one output may be shorted to ground at a
time. Duration of the short circuit should not be greater
than one second.
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This
is a stress rating only; functional operation of the device at
these or any other conditions above those indicated in the
operational sections of this data sheet is not implied.
Exposure of the device to absolute maximum rating
conditions for extended periods may affect device reliability.
OPERATING RANGES
Commercial (C) Devices
Ambient Temperature (TA) . . . . . . . . . . . 0°C to +70°C
Industrial (I) Devices
Ambient Temperature (TA) . . . . . . . . . –40°C to +85°C
VCC Supply Voltages
VCC (full voltage range) . . . . . . . . . . . .+2.7 V to 3.6 V
VCC (regulated voltage range) . . . . . . .+3.0 V to 3.6 V
Operating ranges define those limits between which the
functionality of the device is guaranteed.
30
Am29LV116M
April 7, 2003
P E N D I N G
DC CHARACTERISTICS
CMOS Compatible
Parameter
Description
Test Conditions
Min
Typ
Max
±1.0
35
Unit
µA
VIN = VSS to VCC
,
ILI
Input Load Current
VCC = VCC max
ILIT
ILO
ILR
A9 Input Load Current
Output Leakage Current
Reset Leakage Current
VCC = VCC max; A9 = 12.5 V
µA
VOUT = VSS to VCC
VCC = VCC max
,
±1.0
µA
VCC = VCC max; RESET# = 12.5 V
35
30
10
µA
5 MHz
CE# = VIL, OE# = VIH
1 MHz
15
2
VCC Active Read Current
(Notes 1, 2)
ICC1
mA
mA
VCC Active Write Current
(Notes 2, 3, 4)
ICC2
CE# = VIL, OE# = VIH
40
60
ICC3
ICC4
VCC Standby Current (Note 2)
VCC Reset Current (Note 2)
CE#, RESET# = VCC±0.3 V
RESET# = VSS ± 0.3 V
0.4
0.8
5
5
µA
µA
Automatic Sleep Mode
(Notes 2, 5)
V
IH = VCC ± 0.3 V;
ICC5
0.4
5
µA
VIL = VSS ± 0.3 V
VIL1
VIH1
VIL2
VIH2
Input Low Voltage 1(6, 7)
Input High Voltage 1 (6, 7)
Input Low Voltage 2 (6, 8)
Input High Voltage 2 (6, 8)
–0.5
1.9
0.8
V
V
V
V
VCC + 0.5
0.3 x VIO
VIO + 0.5
–0.5
1.9
Voltage for Autoselect and
Temporary Sector Unprotect
VID
VCC = 3.3 V
11.5
12.5
V
VOL
VOL
Output Low Voltage
IOL = 4.0 mA, VCC = VCC min
0.45
V
V
Output Low Voltage (10)
IOL = 4.0 mA, VCC = VCC min = VIO
0.15 x VIO
I
OH = –2.0 mA, VCC = VCC min
=
VOH1
0.85 VIO
VIO–0.4
2.3
V
V
V
VIO
Output High Voltage
IOH = –100 µA, VCC = VCC min
VIO
=
VOH2
Low VCC Lock-Out Voltage
(Note 4)
VLKO
2.5
Notes:
1. On the WP#/ACC pin only, the maximum input load current when
5. Automatic sleep mode enables the low power mode when
addresses remain stable for t + 30 ns.
WP# = V is ± 5.0 µA.
IL
ACC
2. The I current listed is typically less than 2 mA/MHz, with OE# at
6. If V < V , maximum V for CE# and DQ I/Os is 0.3 V .
IO
CC
IO
CC
IL
V
.
Maximum V for these connections is V + 0.3 V
IH
IH
IO
3. Maximum I specifications are tested with V = V max.
7.
8.
V
V
voltage requirements.
CC
CC
CC
CC
IO
4.
I
active while Embedded Erase or Embedded Program is in
voltage requirements.
CC
progress.
9. Not 100% tested.
10. Includes RY/BY#
April 7, 2003
Am29LV116M
31
P E N D I N G
TEST CONDITIONS
Table 11. Test Specifications
90, 90R
3.3 V
Test Condition
70, 70R 120, 120R Unit
2.7 kΩ
Output Load
1 TTL gate
Device
Under
Test
Output Load Capacitance,
CL (including jig
capacitance)
30
100
pF
C
L
6.2 kΩ
Input Rise and Fall Times
Input Pulse Levels
5
ns
V
0.0–3.0
Input timing measurement
reference levels
1.5
1.5
V
V
Note: Diodes are IN3064 or equivalent
Output timing
measurement reference
levels
Figure 10. Test Setup
Key to Switching Waveforms
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Does Not Apply
Changing, State Unknown
Center Line is High Impedance State (High Z)
3.0 V
0.0 V
1.5 V
1.5 V
Input
Measurement Level
Output
Figure 11. Input Waveforms and Measurement Levels
32
Am29LV116M
April 7, 2003
P E N D I N G
AC CHARACTERISTICS
Read Operations
Parameter
Speed Option
70,
90,
120,
JEDEC
Std
Description
Test Setup
70R
90R 120R Unit
tAVAV
tRC
Read Cycle Time (Note 1)
Min
70
90
90
120
120
ns
ns
CE# = VIL
OE# = VIL
tAVQV
tACC
Address to Output Delay
Max
70
tELQV
tGLQV
tEHQZ
tGHQZ
tCE
tOE
tDF
tDF
Chip Enable to Output Delay
Output Enable to Output Delay
OE# = VIL
Max
Max
Max
Max
Min
70
30
25
25
90
35
30
30
0
120
50
ns
ns
ns
ns
ns
Chip Enable to Output High Z (Note 1)
Output Enable to Output High Z (Note 1)
30
30
Read
Output Enable
Hold Time (Note 1)
tOEH
Toggle and
Data# Polling
Min
Min
10
0
ns
ns
Output Hold Time From Addresses, CE# or
OE#, Whichever Occurs First (Note 1)
tAXQX
tOH
Notes:
1. Not 100% tested.
2. See Figure 10 and Table 11 for test specifications
3. AC Specifications are tested with VIO=VCC. Contact AMD for information on AC operations with VIO≠VCC.
tRC
Addresses Stable
tACC
Addresses
CE#
tDF
tOE
OE#
tOEH
WE#
tCE
tOH
HIGH Z
HIGH Z
Output Valid
Outputs
RESET#
RY/BY#
0 V
Figure 12. Read Operation Timing
April 7, 2003
Am29LV116M
33
P E N D I N G
AC CHARACTERISTICS
Hardware Reset (RESET#)
Parameter
JEDEC
Std
Description
Test Setup
All Speed Options
Unit
RESET# Pin Low (During Embedded Algorithms)
to Read or Write (See Note)
tREADY
Max
Max
20
µs
RESET# Pin Low (NOT During Embedded
Algorithms) to Read or Write (See Note)
tREADY
500
ns
tRP
tRH
RESET# Pulse Width
Min
Min
Min
Min
500
50
20
0
ns
ns
µs
ns
RESET# High Time Before Read (See Note)
tRPD RESET# Low to Standby Mode
tRB RY/BY# Recovery Time
Note: Not 100% tested.
RY/BY#
CE#, OE#
RESET#
tRH
tRP
tReady
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
tReady
RY/BY#
tRB
CE#, OE#
RESET#
tRP
Figure 13. RESET# Timings
34
Am29LV116M
April 7, 2003
P E N D I N G
AC CHARACTERISTICS
Erase/Program Operations
Parameter
Speed Options
JEDEC
tAVAV
Std
tWC
tAS
Description
70, 70R 90, 90R 120, 120R
Unit
ns
Write Cycle Time (Note 1)
Address Setup Time
Address Hold Time
Data Setup Time
Data Hold Time
Min
Min
Min
Min
Min
Min
70
90
120
tAVWL
tWLAX
tDVWH
tWHDX
0
ns
tAH
45
35
45
45
50
50
ns
tDS
ns
tDH
tOES
0
ns
Output Enable Setup Time (Note 1)
0
0
ns
Read Recovery Time Before Write
(OE# High to WE# Low)
tGHWL
tGHWL
Min
ns
tELWL
tWHEH
tCS
tCH
CE# Setup Time
Min
Min
Min
Min
Typ
Typ
Min
Min
Min
0
0
ns
ns
ns
ns
µs
sec
µs
ns
ns
CE# Hold Time
tWLWH
tWHWL
tWHWH1
tWHWH2
tWP
Write Pulse Width
Write Pulse Width High
35
35
50
tWPH
30
TBD
0.7
50
tWHWH1 Programming Operation (Note 2)
tWHWH2 Sector Erase Operation (Note 2)
tVCS
tRB
VCC Setup Time (Note 1)
Recovery Time from RY/BY#
Program/Erase Valid to RY/BY# Delay
0
tBUSY
90
Notes:
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more information.
April 7, 2003
Am29LV116M
35
P E N D I N G
AC CHARACTERISTICS
Program Command Sequence (last two cycles)
Read Status Data (last two cycles)
tAS
tWC
Addresses
555h
PA
PA
PA
tAH
CE#
OE#
tCH
tWHWH1
tWP
WE#
Data
tWPH
tCS
tDS
tDH
PD
DOUT
A0h
Status
tBUSY
tRB
RY/BY#
VCC
tVCS
Note: PA = program address, PD = program data, DOUT is the true data at the program address.
Figure 14. Program Operation Timings
Erase Command Sequence (last two cycles)
Read Status Data
VA
tAS
SA
tWC
VA
Addresses
CE#
2AAh
555h for chip erase
tAH
tCH
OE#
tWP
WE#
tWPH
tWHWH2
tCS
tDS
tDH
In
Data
Complete
55h
30h
Progress
10 for Chip Erase
tBUSY
tRB
RY/BY#
VCC
tVCS
Note: SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”).
Figure 15. Chip/Sector Erase Operation Timings
36
Am29LV116M
April 7, 2003
P E N D I N G
AC CHARACTERISTICS
tRC
VA
Addresses
VA
VA
tACC
tCE
CE#
tCH
tOE
OE#
tOEH
WE#
tDF
tOH
High Z
High Z
DQ7
Valid Data
Complement
Complement
Status Data
True
DQ0–DQ6
Status Data
True
Valid Data
tBUSY
RY/BY#
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data
read cycle.
Figure 16. Data# Polling Timings (During Embedded Algorithms)
tRC
Addresses
CE#
VA
tACC
tCE
VA
VA
VA
tCH
tOE
OE#
WE#
tOEH
tDF
tOH
High Z
DQ6/DQ2
RY/BY#
Valid Status
(first read)
Valid Status
Valid Status
Valid Data
(second read)
(stops toggling)
tBUSY
Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status
read cycle, and array data read cycle.
Figure 17. Toggle Bit Timings (During Embedded Algorithms)
April 7, 2003
Am29LV116M
37
P E N D I N G
AC CHARACTERISTICS
Enter
Embedded
Erasing
Erase
Suspend
Enter Erase
Suspend Program
Erase
Resume
Erase
Erase Suspend
Read
Erase
Suspend
Program
Erase
Complete
WE#
Erase
Erase Suspend
Read
DQ6
DQ2
Note: The system can use OE# or CE# to toggle DQ2/DQ6. DQ2 toggles only when read at an address within an
erase-suspended sector.
Figure 18. DQ2 vs. DQ6
Temporary Sector Unprotect
Parameter
JEDEC
Std
Description
All Speed Options
Unit
tVIDR
VID Rise and Fall Time (See Note)
Min
Min
500
ns
RESET# Setup Time for Temporary Sector
Unprotect
tRSP
4
µs
Note: Not 100% tested.
12 V
RESET#
0 or 3 V
tVIDR
tVIDR
Program or Erase Command Sequence
CE#
WE#
tRSP
RY/BY#
Figure 19. Temporary Sector Unprotect Timing Diagram
38
Am29LV116M
April 7, 2003
P E N D I N G
AC CHARACTERISTICS
VID
VIH
RESET#
SA, A6,
A1, A0
Valid*
Sector Protect/Unprotect
60h 60h
Valid*
Valid*
Status
Verify
40h
Data
Sector Protect: 150 µs
Sector Unprotect: 15 ms
1 µs
CE#
WE#
OE#
Note: For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.
Figure 20. Sector Protect/Unprotect Timing Diagram
April 7, 2003
Am29LV116M
39
P E N D I N G
AC CHARACTERISTICS
Alternate CE# Controlled Erase/Program Operations
Parameter
Speed Options
120,
JEDEC
tAVAV
Std
tWC
tAS
Description
70, 70R 90, 90R 120R
Unit
ns
Write Cycle Time (Note 1)
Address Setup Time
Address Hold Time
Data Setup Time
Min
Min
Min
Min
Min
Min
70
90
0
120
tAVEL
ns
tELAX
tDVEH
tEHDX
tAH
45
35
45
45
0
50
50
ns
tDS
ns
tDH
tOES
Data Hold Time
ns
Output Enable Setup Time
0
ns
Read Recovery Time Before Write
(OE# High to WE# Low)
tGHEL
tGHEL
Min
0
ns
tWLEL
tEHWH
tELEH
tWS
tWH
WE# Setup Time
Min
Min
Min
Min
Typ
Typ
0
0
ns
ns
WE# Hold Time
tCP
CE# Pulse Width
35
35
50
ns
tEHEL
tCPH
CE# Pulse Width High
Programming Operation (Note 2)
Sector Erase Operation (Note 2)
30
ns
tWHWH1
tWHWH2
Notes:
tWHWH1
tWHWH2
TBD
0.4
µs
sec
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more information.
40
Am29LV116M
April 7, 2003
P E N D I N G
AC CHARACTERISTICS
555 for program
PA for program
2AA for erase
SA for sector erase
555 for chip erase
Data# Polling
Addresses
PA
tWC
tWH
tAS
tAH
WE#
OE#
tGHEL
tWHWH1 or 2
tCP
CE#
Data
tWS
tCPH
tDS
tBUSY
tDH
DQ7#
DOUT
tRH
A0 for program
55 for erase
PD for program
30 for sector erase
10 for chip erase
RESET#
RY/BY#
Note: PA = program address, PD = program data, DQ7# = complement of the data written to the device, DOUT = data written to
the device. Figure indicates the last two bus cycles of the command sequence.
Figure 21. Alternate CE# Controlled Write Operation Timings
April 7, 2003
Am29LV116M
41
P E N D I N G
ERASE AND PROGRAMMING PERFORMANCE
Parameter
Typ (Note 1)
Max (Note 2)
Unit
s
Comments
Sector Erase Time
0.4
25
15
Excludes 00h programming
prior to erasure (Note 4)
Chip Erase Time
s
Byte Programming Time
Chip Programming Time (Note 3)
TBD
TBD
TBD
TBD
µs
s
Excludes system level
overhead (Note 5)
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 3.0 V VCC, 100,000 cycles. Additionally,
programming typicals assume checkerboard pattern.
2. Under worst case conditions of 90°C, VCC = 2.7 V, 100,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum program times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the four- or two-bus-cycle sequence for the program command. See
Table 9 for further information on command definitions.
6. The device has a guaranteed minimum erase and program cycle endurance of 100,000 cycles per sector.
LATCHUP CHARACTERISTICS
Description
Min
Max
Input voltage with respect to VSS on all pins except I/O pins
(including A9, OE#, and RESET#)
–1.0 V
12.5 V
Input voltage with respect to VSS on all I/O pins
–1.0 V
VCC + 1.0 V
+100 mA
VCC Current
–100 mA
Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time.
TSOP PIN CAPACITANCE
Parameter
Symbol
Parameter Description
Input Capacitance
Test Setup
VIN = 0
Typ
6
Max
7.5
12
Unit
pF
CIN
COUT
CIN2
Output Capacitance
Control Pin Capacitance
VOUT = 0
VIN = 0
8.5
7.5
pF
9
pF
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.
DATA RETENTION
Parameter
Test Conditions
Min
10
Unit
Years
Years
150°C
125°C
Minimum Pattern Data Retention Time
20
42
Am29LV116M
April 7, 2003
P E N D I N G
PHYSICAL DIMENSIONS*
TS 040—40-Pin Standard TSOP
Dwg rev AA; 10/99
* For reference only. BSC is an ANSI standard for Basic Space Centering.
April 7, 2003
Am29LV116M
43
P E N D I N G
PHYSICAL DIMENSIONS
TSR040—40-Pin Reverse TSOP
Dwg rev AA; 10/99
* For reference only. BSC is an ANSI standard for Basic Space Centering.
44
Am29LV116M
April 7, 2003
P E N D I N G
REVISION SUMMARY
Table 10. Write Operation Status
Revision A (June 24, 2002)
Added program suspend mode.
Initial release.
Operating Ranges
Revision A + 1 (July 3, 2002)
Corrected typos in VIO ranges.
Changed DC characteristics current numbers.
DC Characteristics Zero Power Flash tables removed,
currently TBD.
CMOS Compatible
Changed VIH1 and VIH2 minimum to 1.9.
Changed erase and programming performance times.
Removed typos in notes.
Corrected minimum erase and page cycle specifica-
tion.
Hardware Reset, Erase and Program Operations,
Temporary Sector Unprotect, and Alternate CE#
Controlled Erase and Program Operations
Revision A + 2 (February 6, 2003)
Added Note.
Global
CMOS Compatible
Added regulated speed options and updated effected
tables in datasheet.
Removed VIL, VIH, VOL, and VOH from table and
added VIL1, VIH1, VIL2, VIH2, VOL, VOH1, and VOH2
from the CMOS table in the Am29LV640MH/L
datasheet.
Destinctive Characteristics
Added SecSi text.
Customer Lockable: SecSi Sector NOT
Programmed or Protected at the factory.
General Description
Added page suspend text.
Added second bullet, SecSi sector-protect verify text
and figure 3.
Product Selector Guide
Byte/Word Program Command Sequence, Sector
Erase Command Sequence, and Chip Erase Com-
mand Sequence
Added another Vcc range and regulated speed
options.
Ordering Information
Noted that the SecSi Sector, autoselect, and CFI
functions are unavailable when a program or erase
operation is in progress.
Added regulated speed options.
Table 8. Primary Vendor-Specific Extend Query
Added proccess technology reference to the 45h ad-
dress and corrected data variable.
Erase/Program Operations and Alternate CE#
Controlled Erase/Program Operations
Changed Programming operation for all speed options
to TBD.
Common Flash Memory Interface (CFI)
Changed wording in last sentence of third paragraph
from, “...the autoselect mode.” to “...reading array
data.”
Revision A + 3 (April 7, 2003)
Global
Changed CFI website address
Converted to “Production Pending” version.
Figure 6. Program Suspend/Program Resume
Added text and flowchart.
Corrected typo in wait time.
Trademarks
Copyright © 2003 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, MirrorBitTM and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.
ExpressFlash is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
April 7, 2003
Am29LV116M
45
Representatives in U.S. and Canada
Sales Offices and Representatives
ARIZONA,
North America
Tempe - Centaur . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(480)839-2320
CALIFORNIA,
ALABAMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .( 256)830-9192
ARIZONA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(602)242-4400
CALIFORNIA,
Calabasas - Centaur . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(818)878-5800
Irvine - Centaur . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (949)261-2123
San Diego - Centaur. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(858)278-4950
Santa Clara - Fourfront. . . . . . . . . . . . . . . . . . . . . . . . . . . .(408)350-4800
CANADA,
Burnaby, B.C. - Davetek Marketing. . . . . . . . . . . . . . . . . . . .(604)430-3680
Calgary,Alberta - Davetek Marketing. . . . . . . . . . . . . . . . .(403)283-3577
Kanata, Ontario - J-Squared Tech. . . . . . . . . . . . . . . . . . . .(613)592-9540
Mississauga, Ontario - J-Squared Tech. . . . . . . . . . . . . . . . . .(905)672-2030
St Laurent, Quebec - J-Squared Tech. . . . . . . . . . . . . . . . ( 5 1 4 ) 74 7 - 1 2 1 1
COLORADO,
Irvine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(949)450-7500
Sunnyvale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(408)732-2400
COLORADO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .( 303)741-2900
CONNECTICUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(203)264-7800
FLORIDA,
Clearwater . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(727)793-0055
Miami (Lakes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 3 0 5 ) 8 2 0 - 1 1 1 3
GEORGIA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(770)814-0224
ILLINOIS,
Chicago . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(630)773-4422
MASSACHUSETTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (781)2 13-6400
MICHIGAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(248)471-6294
MINNESOTA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(612)745- 0005
NEW JERSEY,
Chatham . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 97 3 ) 7 0 1 - 1 7 7 7
NEWYORK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(716)425- 8050
NORTH CAROLINA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(919)840-8080
OREGON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(503)245-0080
PENNSYLVANIA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 2 1 5 ) 3 4 0 - 1 1 8 7
SOUTH DAKOTA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(605)692-5777
TEXAS,
Golden - Compass Marketing . . . . . . . . . . . . . . . . . . . . . .(303)277-0456
FLORIDA,
Melbourne - Marathon Technical Sales . . . . . . . . . . . . . . . .(321)728- 7706
Ft. Lauderdale - Marathon Technical Sales . . . . . . . . . . . . . .(954)527-4949
Orlando - Marathon Technical Sales . . . . . . . . . . . . . . . . . .(407)872-5775
St. Petersburg - Marathon Technical Sales . . . . . . . . . . . . . .(727)894-3603
GEORGIA,
Duluth - Quantum Marketing . . . . . . . . . . . . . . . . . . . . . (678) 584-1128
ILLINOIS,
Skokie - Industrial Reps, Inc. . . . . . . . . . . . . . . . . . . . . . . . .(847)967-8430
INDIANA,
Kokomo - SAI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (765)457-7241
IOWA,
Cedar Rapids - Lorenz Sales . . . . . . . . . . . . . . . . . . . . . . (319)294-1000
KANSAS,
Lenexa - Lorenz Sales . . . . . . . . . . . . . . . . . . . . . . . . . ( 9 1 3 ) 4 69 - 1 3 1 2
MASSACHUSETTS,
Austin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(512)346-7830
Dallas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(972)985-1344
Houston . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(281)376-8084
VIRGINIA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(703)736-9568
Burlington - Synergy Associates . . . . . . . . . . . . . . . . . . . . .(781)238-0870
MICHIGAN,
Brighton - SAI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(810)227-0007
MINNESOTA,
St. Paul - Cahill, Schmitz & Cahill, Inc. . . . . . . . . . . . . . . . . .(651)699-0200
MISSOURI,
St. Louis - Lorenz Sales . . . . . . . . . . . . . . . . . . . . . . . . . . (314)997-4558
NEW JERSEY,
International
AUSTRALIA, North Ryde . . . . . . . . . . . . . . . . . . . . . . .TEL(61)2-88-777-222
BELGIUM,Antwerpen . . . . . . . . . . . . . . . . . . . . . . . . TEL(32)3-248-43-00
BRAZIL, San Paulo . . . . . . . . . . . . . . . . . . . . . . . . . .TEL(55)11-5501-2105
CHINA,
Beijing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TEL(86)10-6510-2188
Shanghai . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TEL(86)21-635-00838
Shenzhen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TEL(86)755-246-1550
FINLAND, Helsinki . . . . . . . . . . . . . . . . . . . . . . T E L ( 3 5 8 ) 8 8 1 - 3 1 1 7
FRANCE, Paris . . . . . . . . . . . . . . . . . . . . . . . . . . . . T E L ( 3 3 ) - 1 - 4 975 1 0 1 0
GERMANY,
Bad Homburg . . . . . . . . . . . . . . . . . . . . . . . . . . . TEL(49)-6172-92670
Munich . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T E L ( 4 9 ) - 8 9 - 4 5 0 5 3 0
HONG KONG, Causeway Bay . . . . . . . . . . . . . . . . . . .TEL(85)2-2956-0388
ITALY, Milan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T E L ( 3 9 ) - 0 2 - 3 8 1 9 6 1
INDIA, New Delhi . . . . . . . . . . . . . . . . . . . . . . . . . . T E L ( 9 1 ) 1 1 - 62 3 - 8 62 0
JAPAN,
es
Mt. Laurel - SJ Associates . . . . . . . . . . . . . . . . . . . . . . . . .(856)866-1234
NEWYORK,
Buffalo - Nycom, Inc. . . . . . . . . . . . . . . . . . . . . . . . . . ( 7 1 6 ) 74 1 - 7 1 1 6
East Syracuse - Nycom, Inc. . . . . . . . . . . . . . . . . . . . . . . (315)437-8343
Pittsford - Nycom, Inc. . . . . . . . . . . . . . . . . . . . . . . . . . .(716)586-3660
Rockville Centre - SJ Associates . . . . . . . . . . . . . . . . . . . . (516) 536-4242
NORTH CAROLINA,
Raleigh - Quantum Marketing . . . . . . . . . . . . . . . . . . . . . .(919)846-5728
OHIO,
Middleburg Hts - Dolfuss Root & Co. . . . . . . . . . . . . . . . .(440)816-1660
Powell - Dolfuss Root & Co. . . . . . . . . . . . . . . . . . . . . . . (614)781-0725
Vandalia - Dolfuss Root & Co. . . . . . . . . . . . . . . . . . . . . .(937)898-9610
Westerville - Dolfuss Root & Co. . . . . . . . . . . . . . . . . . . (614)52 3-1990
OREGON,
Lake Oswego - I Squared, Inc. . . . . . . . . . . . . . . . . . . . . . .(503)670-0557
UTAH,
Murray - Front Range Marketing . . . . . . . . . . . . . . . . . . . .(801)288-2500
VIRGINIA,
Osaka . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TEL(81)6-6243-3250
Tokyo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TEL(81)3-3346-7600
KOREA, Seoul . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TEL(82)2-3468-2600
RUSSIA, Moscow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TEL(7)-095-795-06-22
SWEDEN, Stockholm . . . . . . . . . . . . . . . . . . . . . . . . . . .TEL(46)8-562-540-00
TAIWAN,Taipei . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TEL(886)2-8773-1555
UNITED KINGDOM,
Frimley . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TEL(44)1276-803100
Haydcock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TEL(44)1942-272888
Glen Burnie - Coherent Solution, Inc. . . . . . . . . . . . . . . . . ( 4 1 0 ) 76 1 - 2 2 5 5
WASHINGTON,
Kirkland - I Squared, Inc. . . . . . . . . . . . . . . . . . . . . . . . . . .(425)822-9220
WISCONSIN,
Pewaukee - Industrial Representatives . . . . . . . . . . . . . . . .(262)574-9393
Advanced Micro Devices reserves the right to make changes in its product without notice
in order to improve design or performance characteristics.The performance
characteristics listed in this document are guaranteed by specific tests, guard banding,
design and other practices common to the industry. For specific testing details, contact
your local AMD sales representative.The company assumes no responsibility for the use of
any circuits described herein.
Representatives in Latin America
ARGENTINA,
Capital Federal Argentina/WW Rep. . . . . . . . . . . . . . . . . . . .54-11)4373-0655
CHILE,
Santiago - LatinRep/WWRep. . . . . . . . . . . . . . . . . . . . . . . . . .(+562)264-0993
COLUMBIA,
Bogota - Dimser. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 5 7 1 ) 4 1 0 - 4 1 8 2
MEXICO,
Guadalajara - LatinRep/WW Rep. . . . . . . . . . . . . . . . . . . .(523)817-3900
Mexico City - LatinRep/WW Rep. . . . . . . . . . . . . . . . . . . .(525)752-2727
Monterrey - LatinRep/WW Rep. . . . . . . . . . . . . . . . . . . . .(528)369-6828
PUERTO RICO,
© Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD Arrow logo and combination thereof, are trademarks of
Advanced Micro Devices, Inc. Other product names are for informational purposes only
and may be trademarks of their respective companies.
Boqueron - Infitronics. . . . . . . . . . . . . . . . . . . . . . . . . . . . (787)851-6000
One AMD Place, P.O. Box 3453, Sunnyvale, CA 94088-3453 408-732-2400
TWX 910-339-9280 TELEX 34-6306 800-538-8450 http://www.amd.com
©2003 Advanced Micro Devices, Inc.
01/03
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