AM29LV160DT70FF [SPANSION]
Flash, 1MX16, 70ns, PDSO48, REVERSE, MO-142DD, TSOP-48;型号: | AM29LV160DT70FF |
厂家: | SPANSION |
描述: | Flash, 1MX16, 70ns, PDSO48, REVERSE, MO-142DD, TSOP-48 光电二极管 |
文件: | 总52页 (文件大小:1786K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Am29LV160D
Data Sheet
RETIRED
PRODUCT
This product has been retired and is not recommended for designs. For new and current designs,
S29AL016D supersedes Am29LV160D and is the factory-recommended migration path for this
device. Please refer to the S29AL016D data sheet for specifications and ordering information. Avail-
ability of this document is retained for reference and historical purposes only.
The following document contains information on Spansion memory products.
Continuity of Specifications
There is no change to this data sheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal data sheet improvement and are noted in the
document revision summary.
For More Information
Please contact your local sales office for additional information about Spansion memory solutions.
Publication Number 22358 Revision B Amendment 7 Issue Date May 5, 2006
THIS PAGE LEFT INTENTIONALLY BLANK.
DATA SHEET
Am29LV160D
16 Megabit (2 M x 8-Bit/1 M x 16-Bit)
CMOS 3.0 Volt-only Boot Sector Flash Memory
This product has been retired and is not recommended for designs. For new and current designs, S29AL016D supersedes Am29LV160D and is the factory-recommended migration path
for this device. Please refer to the S29AL016D data sheet for specifications and ordering information. Availability of this document is retained for reference and historical purposes only.
DISTINCTIVE CHARACTERISTICS
■ Single power supply operation
■ Embedded Algorithms
— Full voltage range: 2.7 to 3.6 volt read and write
operations for battery-powered applications
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
— Regulated voltage range: 3.0 to 3.6 volt read and
write operations and for compatibility with high
performance 3.3 volt microprocessors
— Embedded Program algorithm automatically
writes and verifies data at specified addresses
■ Manufactured on 0.23 µm process technology
■ Minimum 1,000,000 write cycle guarantee
per sector
— Fully compatible with 0.32 µm Am29LV160B device
■ 20-year data retention at 125°C
— Reliable operation for the life of the system
■ Package option
■ High performance
— Access times as fast as 70 ns
■ Ultra low power consumption (typical values at
— 48-ball FBGA
5 MHz)
— 48-pin TSOP
— 200 nA Automatic Sleep mode current
— 200 nA standby mode current
— 9 mA read current
— 44-pin SO
■ CFI (Common Flash Interface) compliant
— 20 mA program/erase current
— Provides device-specific information to the
system, allowing host software to easily
reconfigure for different Flash devices
■ Flexible sector architecture
— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and
thirty-one 64 Kbyte sectors (byte mode)
■ Compatibility with JEDEC standards
— Pinout and software compatible with single-
power supply Flash
— One 8 Kword, two 4 Kword, one 16 Kword, and
thirty-one 32 Kword sectors (word mode)
— Superior inadvertent write protection
— Supports full chip erase
— Sector Protection features:
■ Data# Polling and toggle bits
— A hardware method of locking a sector to prevent any
program or erase operations within that sector
— Provides a software method of detecting program
or erase operation completion
— Sectors can be locked in-system or via programming
equipment
■ Ready/Busy# pin (RY/BY#)
— Provides a hardware method of detecting
program or erase cycle completion (not available
on 44-pin SO)
Temporary Sector Unprotect feature allows code
changes in previously locked sectors
■ Unlock Bypass Program Command
■ Erase Suspend/Erase Resume
— Reduces overall programming time when issuing
multiple program command sequences
— Suspends an erase operation to read data from,
or program data to, a sector that is not being
erased, then resumes the erase operation
■ Top or bottom boot block configurations
available
■ Hardware reset pin (RESET#)
— Hardware method to reset the device to reading
array data
This Data Sheet states AMD’s current technical specifications regarding the Product described herein. This Data
Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
Publication# 22358
Issue Date: May 5, 2006
Rev: B Amendment: 7
D A T A S H E E T
GENERAL DESCRIPTION
The Am29LV160D is a 16 Mbit, 3.0 Volt-only Flash
memory organized as 2,097,152 bytes or 1,048,576
words. The device is offered in 48-ball FBGA, 44-pin
SO, and 48-pin TSOP packages. The word-wide data
(x16) appears on DQ15–DQ0; the byte-wide (x8) data
appears on DQ7–DQ0. This device is designed to be
programmed in-system with the standard system 3.0
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, or by reading the DQ7 (Data# Polling) and DQ6
(toggle) status bits. After a program or erase cycle
has been completed, the device is ready to read array
data or accept another command.
The sector erase architecture allows memory sec-
tors to be erased and reprogrammed without affecting
the data contents of other sectors. The device is fully
erased when shipped from the factory.
volt V
supply. A 12.0 V V or 5.0 V
are not re-
CC
PP
CC
quired for write or erase operations. The device can
also be programmed in standard
EPROM programmers.
Hardware data protection measures include a low
The device offers access times of 70, 90, and 120 ns,
allowing high speed microprocessors to operate with-
out wait states. To eliminate bus contention the device
has separate chip enable (CE#), write enable (WE#)
and output enable (OE#) controls.
V
detector that automatically inhibits write opera-
CC
tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of the sectors of mem-
ory. This can be achieved in-system or via
programming equipment.
The device requires only a single 3.0 volt power sup-
ply for both read and write functions. Internally
generated and regulated voltages are provided for the
program and erase operations.
The Erase Suspend/Erase Resume feature enables
the user to put erase on hold for any period of time to
read data from, or program data to, any sector that is
not selected for erasure. True background erase can
thus be achieved.
The Am29LV160D is entirely command set compatible
with the JEDEC single-power-supply Flash stan-
dard. Commands are written to the command register
using standard microprocessor write timings. Register
contents serve as input to an internal state-machine
that controls the erase and programming circuitry.
Write cycles also internally latch addresses and data
needed for the programming and erase operations.
Reading data out of the device is similar to reading
from other Flash or EPROM devices.
The hardware RESET# pin terminates any operation
in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to
the system reset circuitry. A system reset would thus
also reset the device, enabling the system micropro-
cessor to read the boot-up firmware from the Flash
memory.
The device offers two power-saving features. When
addresses have been stable for a specified amount of
time, the device enters the automatic sleep mode.
The system can also place the device into the
standby mode. Power consumption is greatly re-
duced in both these modes.
Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithm—an internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin. The Unlock Bypass mode facili-
tates faster programming times by requiring only two
write cycles to program data instead of four.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective-
ness. The device electrically erases all bits within a
sector simultaneously via Fowler-Nordheim tunnel-
ing. The data is programmed using hot electron
injection.
Device erasure occurs by executing the erase com-
mand sequence. This initiates the Embedded Erase
algorithm—an internal algorithm that automatically
preprograms the array (if it is not already programmed)
before executing the erase operation. During erase,
the device automatically times the erase pulse widths
and verifies proper cell margin.
2
Am29LV160D
May 5, 2006 22358B7
D A T A S H E E T
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . .4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . .5
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . .7
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Ordering Information . . . . . . . . . . . . . . . . . . . . . . .8
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . .9
Table 1. Am29LV160D Device Bus Operations ................................9
Word/Byte Configuration .......................................................... 9
Requirements for Reading Array Data ..................................... 9
Writing Commands/Command Sequences .............................. 9
Program and Erase Operation Status .................................... 10
Standby Mode ........................................................................ 10
Automatic Sleep Mode ........................................................... 10
RESET#: Hardware Reset Pin ............................................... 11
Output Disable Mode .............................................................. 11
Table 2. Sector Address Tables (Am29LV160DT) ..........................12
Table 3. Sector Address Tables (Am29LV160DB) ..........................13
Autoselect Mode ..................................................................... 14
Table 4. Am29LV160D Autoselect Codes (High Voltage Method) ..14
Sector Protection/Unprotection ............................................... 14
Temporary Sector Unprotect .................................................. 15
Figure 1. Temporary Sector Unprotect Operation........................... 15
Figure 2. In-System Sector Protect/Unprotect Algorithms .............. 16
Common Flash Memory Interface (CFI) . . . . . . .17
Table 5. CFI Query Identification String ..........................................17
Table 6. System Interface String .....................................................18
Table 7. Device Geometry Definition ..............................................18
Table 8. Primary Vendor-Specific Extended Query ........................19
Hardware Data Protection ...................................................... 19
DQ3: Sector Erase Timer ....................................................... 28
Table 10. Write Operation Status ................................................... 28
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 29
Figure 7. Maximum Negative Overshoot Waveform ...................... 30
Figure 8. Maximum Positive Overshoot Waveform........................ 30
Operating Ranges. . . . . . . . . . . . . . . . . . . . . . . . . 30
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 9. I
Current vs. Time (Showing Active and
CC1
Automatic Sleep Currents)............................................................. 32
Figure 10. Typical I vs. Frequency ........................................... 32
CC1
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 11. Test Setup..................................................................... 33
Table 11. Test Specifications ......................................................... 33
Figure 12. Input Waveforms and Measurement Levels ................. 33
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 34
Read Operations .................................................................... 34
Figure 13. Read Operations Timings ............................................. 34
Hardware Reset (RESET#) .................................................... 35
Figure 14. RESET# Timings .......................................................... 35
Word/Byte Configuration (BYTE#) ........................................ 36
Figure 15. BYTE# Timings for Read Operations............................ 36
Figure 16. BYTE# Timings for Write Operations............................ 36
Erase/Program Operations ..................................................... 37
Figure 17. Program Operation Timings.......................................... 38
Figure 18. Chip/Sector Erase Operation Timings .......................... 39
Figure 19. Data# Polling Timings (During Embedded Algorithms). 40
Figure 20. Toggle Bit Timings (During Embedded Algorithms)...... 40
Figure 21. DQ2 vs. DQ6 for Erase and
Erase Suspend Operations............................................................ 41
Figure 22. Temporary Sector Unprotect/Timing Diagram .............. 41
Figure 23. Sector Protect/Unprotect Timing Diagram .................... 42
Figure 24. Alternate CE# Controlled Write Operation Timings ...... 44
Erase and Programming Performance . . . . . . . 45
Latchup Characteristics. . . . . . . . . . . . . . . . . . . . 45
TSOP and SO Pin Capacitance . . . . . . . . . . . . . . 45
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 46
TS 048—48-Pin Standard TSOP ............................................ 46
TSR048—48-Pin Reverse TSOP ........................................... 47
FBC048—48-Ball Fine-Pitch Ball Grid Array (FBGA)
Low V Write Inhibit .............................................................. 19
CC
Write Pulse “Glitch” Protection ............................................... 19
Logical Inhibit .......................................................................... 19
Power-Up Write Inhibit ............................................................ 19
Command Definitions . . . . . . . . . . . . . . . . . . . . . .20
Reading Array Data ................................................................ 20
Reset Command ..................................................................... 20
Autoselect Command Sequence ............................................ 20
Word/Byte Program Command Sequence ............................. 20
Unlock Bypass Command Sequence ..................................... 21
Figure 3. Program Operation .......................................................... 21
Chip Erase Command Sequence ........................................... 21
Sector Erase Command Sequence ........................................ 22
Erase Suspend/Erase Resume Commands ........................... 22
Figure 4. Erase Operation............................................................... 23
Command Definitions ............................................................. 24
Table 9. Am29LV160D Command Definitions ................................24
Write Operation Status . . . . . . . . . . . . . . . . . . . . .25
DQ7: Data# Polling ................................................................. 25
Figure 5. Data# Polling Algorithm ................................................... 25
RY/BY#: Ready/Busy# ........................................................... 26
DQ6: Toggle Bit I .................................................................... 26
DQ2: Toggle Bit II ................................................................... 26
Reading Toggle Bits DQ6/DQ2 .............................................. 26
Figure 6. Toggle Bit Algorithm......................................................... 27
8 x 9 mm ................................................................................ 48
SO 044—44-Pin Small Outline Package ................................ 49
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 50
Revision A (January 1999) ..................................................... 50
Revision A+1 (April 19, 1999) ................................................. 50
Revision B (November 23, 1999) ............................................50
Revision B+1 (February 22, 2000) .......................................... 50
Revision B+2 (November 7, 2000) ......................................... 50
Revision B+3 (November 10, 2000) ....................................... 50
Revision B+4 (April 5, 2004) ................................................... 50
Revision B+5 (June 4, 2004) .................................................. 50
Revision B+6 (October 7, 2004) ............................................. 50
Revision B7 (May 5, 2006) ..................................................... 50
22358B7 May 5, 2006
Am29LV160D
3
D A T A S H E E T
PRODUCT SELECTOR GUIDE
Family Part Number
Am29LV160D
Speed Option
Voltage Range: V = 2.7–3.6 V
-70
70
70
30
-90
90
90
35
-120
120
120
50
CC
Max access time, ns (t
)
ACC
Max CE# access time, ns (t
)
CE
Max OE# access time, ns (t
)
OE
Note: See “AC Characteristics” for full specifications.
BLOCK DIAGRAM
DQ0–DQ15 (A-1)
RY/BY#
V
CC
Sector Switches
V
SS
Erase Voltage
Generator
Input/Output
Buffers
RESET#
State
Control
WE#
BYTE#
Command
Register
PGM Voltage
Generator
Data
Latch
Chip Enable
Output Enable
Logic
STB
CE#
OE#
Y-Decoder
Y-Gating
STB
V
Detector
Timer
CC
Cell Matrix
X-Decoder
A0–A19
4
Am29LV160D
May 5, 2006 22358B7
D A T A S H E E T
CONNECTION DIAGRAMS
A15
A14
A13
A12
A11
A10
A9
1
2
3
4
5
6
7
8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE#
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
A8
A19
NC
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
WE#
RESET#
NC
Standard TSOP
NC
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
A15
A14
A13
A12
A11
A10
A9
48
A16
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
BYTE#
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
A8
A19
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
WE#
RESET#
NC
Reverse TSOP
NC
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
OE#
VSS
CE#
A0
22358B7 May 5, 2006
Am29LV160D
5
D A T A S H E E T
CONNECTION DIAGRAMS
RESET#
A18
A17
A7
1
2
3
4
5
6
7
8
9
44 WE#
43 A19
42 A8
41 A9
A6
40 A10
39 A11
38 A12
37 A13
36 A14
35 A15
34 A16
33 BYTE#
32 VSS
A5
A4
A3
A2
A1 10
A0 11
CE# 12
VSS 13
SO
OE# 14
DQ0 15
DQ8 16
DQ1 17
DQ9 18
DQ2 19
DQ10 20
DQ3 21
DQ11 22
31 DQ15/A-1
30 DQ7
29 DQ14
28 DQ6
27 DQ13
26 DQ5
25 DQ12
24 DQ4
23 VCC
FBGA
Top View, Balls Facing Down
A6
B6
C6
D6
E6
F6
G6
H6
A13
A12
A14
A15
A16
BYTE# DQ15/A-1 VSS
A5
A9
B5
A8
C5
D5
E5
F5
G5
H5
A10
A11
DQ7
DQ14
DQ13
DQ6
A4
B4
C4
D4
E4
F4
G4
H4
WE# RESET#
NC
A19
DQ5
DQ12
VCC
DQ4
A3
B3
C3
D3
E3
F3
G3
H3
RY/BY#
NC
A18
NC
DQ2
DQ10
DQ11
DQ3
A2
A7
B2
C2
A6
D2
A5
E2
F2
G2
H2
A17
DQ0
DQ8
DQ9
DQ1
A1
A3
B1
A4
C1
A2
D1
A1
E1
A0
F1
G1
H1
CE#
OE#
VSS
Flash memory devices in FBGA packages may be
damaged if exposed to ultrasonic cleaning methods.
The package and/or data integrity may be compromised
if the package body is exposed to temperatures above
150°C for prolonged periods of time.
Special Handling Instructions
Special handling is required for Flash Memory
products in FBGA packages.
6
Am29LV160D
May 5, 2006 22358B7
D A T A S H E E T
PIN CONFIGURATION
LOGIC SYMBOL
A0–A19
=20 addresses
20
DQ0–DQ14 =15 data inputs/outputs
A0–A19
16 or 8
DQ15/A-1 =DQ15 (data input/output, word mode),
A-1 (LSB address input, byte mode)
DQ0–DQ15
(A-1)
BYTE#
CE#
=Selects 8-bit or 16-bit mode
=Chip enable
CE#
OE#
OE#
=Output enable
WE#
=Write enable
WE#
RESET#
RY/BY#
=Hardware reset pin
RESET#
BYTE#
=Ready/Busyoutput
(N/A SO 044)
RY/BY#
(N/A SO 044)
V
=3.0 volt-only single power supply
(see Product Selector Guide for speed
options and voltage supply tolerances)
CC
V
=Device ground
SS
NC
=Pin not connected internally
22358B7 May 5, 2006
Am29LV160D
7
D A T A S H E E T
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combi-
nation) is formed by a combination of the elements below.
Am29LV160D
T
-70
E
C
TEMPERATURE RANGE
C
D
I
=
=
=
=
Commercial (0°C to +70°C)
Commercial (0°C to +70°C) with Pb-Free Package
Industrial (–40°C to +85°C)
Industrial (–40°C to +85°C) with Pb-Free Package
F
PACKAGE TYPE
E
=
=
=
=
48-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 048)
48-Pin Thin Small Outline Package (TSOP) Reverse Pinout (TSR048)
44-Pin Small Outline Package (SO 044)
F
S
WC
48-ball Fine-Pitch Ball Grid Array (FBGA)
0.80 mm pitch, 8 x 9 mm package (FBC048)
SPEED OPTION
See Product Selector Guide and Valid Combinations
BOOT CODE SECTOR ARCHITECTURE
T
B
=
=
Top sector
Bottom sector
DEVICE NUMBER/DESCRIPTION
Am29LV160D
16 Megabit (2M x 8-Bit/1M x 16-Bit) CMOS Flash Memory
3.0 Volt-only Read, Program, and Erase
Valid Combinations For TSOP and SO Packages
Valid Combinations for FBGA Packages
Order Number Package Marking
Am29LV160DT-70,
Am29LV160DT-70,
Am29LV160DB-70
L160DT70V,
L160DB70V
EC, EI, ED, EF
Am29LV160DT-90,
FC, FI
Am29LV160DB-70
WCC,
WCI,
Am29LV160DB-90
SC, SI, SD, SF
Am29LV160DT-90,
Am29LV160DB-90
L160DT90V,
L160DB90V
C, I,
D, F
Am29LV160DT-120,
Am29LV160DB-120
WCD,
WCF
Am29LV160DT-120,
Am29LV160DB-120
L160DT12V,
L160DB12V
Valid Combinations
Valid Combinations list configurations planned to be sup-
ported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.
8
Am29LV160D
May 5, 2006 22358B7
D A T A S H E E T
DEVICE BUS OPERATIONS
This section describes the requirements and use of
the device bus operations, which are initiated through
the internal command register. The command register
itself does not occupy any addressable memory loca-
tion. The register is composed of latches that store the
commands, along with the address and data informa-
tion needed to execute the command. The contents of
the register serve as inputs to the internal state ma-
chine. The state machine outputs dictate the function
of the device. Table 1 lists the device bus operations,
the inputs and control levels they require, and the re-
sulting output. The following subsections describe
each of these operations in further detail.
Table 1. Am29LV160D Device Bus Operations
DQ8–DQ15
BYTE#
= V
Addresses
(Note 1)
DQ0– BYTE#
Operation
CE# OE# WE# RESET#
DQ7
= V
IH
IL
Read
Write
L
L
L
H
L
H
H
A
D
D
DQ8–DQ14 = High-Z,
DQ15 = A-1
IN
OUT
OUT
H
A
D
D
IN
IN
IN
V
0.3 V
±
V
0.3 V
±
CC
CC
Standby
X
X
X
High-Z High-Z
High-Z
Output Disable
Reset
L
H
X
H
X
H
L
X
X
High-Z High-Z
High-Z High-Z
High-Z
High-Z
X
Sector Address,
A6 = L, A1 = H,
A0 = L
Sector Protect (Note 2)
L
H
L
V
D
X
X
X
ID
IN
Sector Address,
A6 = H, A1 = H,
A0 = L
Sector Unprotect (Note 2)
L
H
X
L
V
V
D
D
X
ID
ID
IN
IN
Temporary Sector
Unprotect
X
X
A
D
High-Z
IN
IN
Legend:
L = Logic Low = V , H = Logic High = V , V = 12.0 ± 0.5 V, X = Don’t Care, A = Address In, D = Data In, D = Data Out
IL
IH
ID
IN
IN
OUT
Notes:
1. Addresses are A19:A0 in word mode (BYTE# = V ), A19:A-1 in byte mode (BYTE# = V ).
IH
IL
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector
Protection/Unprotection” section.
The internal state machine is set for reading array
Word/Byte Configuration
data upon device power-up, or after a hardware re-
The BYTE# pin controls whether the device data I/O
set. This ensures that no spurious alteration of the
pins DQ15–DQ0 operate in the byte or word configura-
memory content occurs during the power transition.
tion. If the BYTE# pin is set at logic ‘1’, the device is in
No command is necessary in this mode to obtain
word configuration, DQ15–DQ0 are active and con-
array data. Standard microprocessor read cycles that
trolled by CE# and OE#.
assert valid addresses on the device address inputs
If the BYTE# pin is set at logic ‘0’, the device is in byte
configuration, and only data I/O pins DQ0–DQ7 are
active and controlled by CE# and OE#. The data I/O
pins DQ8–DQ14 are tri-stated, and the DQ15 pin is
used as an input for the LSB (A-1) address function.
produce valid data on the device data outputs. The
device remains enabled for read access until the
command register contents are altered.
See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifica-
tions and to Figure 13 for the timing diagram. I
the DC Characteristics table represents the active cur-
rent specification for reading array data.
in
CC1
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to V . CE# is the power
IL
control and selects the device. OE# is the output control
and gates array data to the output pins. WE# should re-
Writing Commands/Command Sequences
To write a command or command sequence (which in-
cludes programming data to the device and erasing
main at V . The BYTE# pin determines whether the
IH
device outputs array data in words or bytes.
22358B7 May 5, 2006
Am29LV160D
9
D A T A S H E E T
sectors of memory), the system must drive WE# and
CE# to V , and OE# to V .
and I read specifications apply. Refer to “Write Op-
CC
eration Status” for more information, and to “AC
IL
IH
Characteristics” for timing diagrams.
For program operations, the BYTE# pin determines
whether the device accepts program data in bytes or
words. Refer to “Word/Byte Configuration” for more
information.
Standby Mode
When the system is not reading or writing to the de-
vice, it can place the device in the standby mode. In
this mode, current consumption is greatly reduced,
and the outputs are placed in the high impedance
state, independent of the OE# input.
The device features an Unlock Bypass mode to facili-
tate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are re-
quired to program a word or byte, instead of four. The
“Word/Byte Program Command Sequence” section
has details on programming data to the device using
both standard and Unlock Bypass command
sequences.
The device enters the CMOS standby mode when the
CE# and RESET# pins are both held at V ± 0.3 V.
(Note that this is a more restricted voltage range than
CC
V
.) If CE# and RESET# are held at V , but not
IH
IH
within V
± 0.3 V, the device will be in the standby
CC
An erase operation can erase one sector, multiple sec-
tors, or the entire device. Tables 2 and 3 indicate the
address space that each sector occupies. A “sector
address” consists of the address bits required to
uniquely select a sector. The “Command Definitions”
section has details on erasing a sector or the entire
chip, or suspending/resuming the erase operation.
mode, but the standby current will be greater. The de-
vice requires standard access time (t ) for read
access when the device is in either of these standby
modes, before it is ready to read data.
CE
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
After the system writes the autoselect command se-
quence, the device enters the autoselect mode. The
system can then read autoselect codes from the inter-
nal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in
this mode. Refer to the “Autoselect Mode” and “Au-
toselect Command Sequence” sections for more
information.
In the DC Characteristics table, I
sents the standby current specification.
and I
repre-
CC4
CC3
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device
energy consumption. The device automatically
enables this mode when addresses remain stable for
t
+ 30 ns. The automatic sleep mode is
ACC
I
in the DC Characteristics table represents the ac-
CC2
independent of the CE#, WE#, and OE# control
signals. Standard address access timings provide new
data when addresses are changed. While in sleep
mode, output data is latched and always available to
tive current specification for the write mode. The “AC
Characteristics” section contains timing specification
tables and timing diagrams for write operations.
the system. I
represents the automatic sleep mode current
specification.
in the DC Characteristics table
CC4
Program and Erase Operation Status
During an erase or program operation, the system
may check the status of the operation by reading the
status bits on DQ7–DQ0. Standard read cycle timings
10
Am29LV160D
May 5, 2006 22358B7
D A T A S H E E T
memory, enabling the system to read the boot-up firm-
RESET#: Hardware Reset Pin
ware from the Flash memory.
The RESET# pin provides a hardware method of re-
setting the device to reading array data. When the
If RESET# is asserted during a program or erase op-
eration, the RY/BY# pin remains a “0” (busy) until the
internal reset operation is complete, which requires a
system drives the RESET# pin to V for at least a pe-
IL
riod of t , the device immediately terminates any
RP
operation in progress, tristates all data output pins,
and ignores all read/write attempts for the duration of
the RESET# pulse. The device also resets the internal
state machine to reading array data. The operation
that was interrupted should be reinitiated once the de-
vice is ready to accept another command sequence,
to ensure data integrity.
time of t
(during Embedded Algorithms). The
READY
system can thus monitor RY/BY# to determine
whether the reset operation is complete. If RESET#
is asserted when a program or erase operation is not
executing (RY/BY# pin is “1”), the reset operation is
completed within a time of t
ded Algorithms). The system can read data t
(not during Embed-
READY
after
RH
the RESET# pin returns to V .
IH
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V
draws CMOS standby current (I
0.3 V, the device
Refer to the AC Characteristics tables for RESET# pa-
rameters and to Figure 14 for the timing diagram.
SS
). If RESET# is
CC4
held at V but not within V
rent will be greater.
0.3 V, the standby cur-
IL
SS
Output Disable Mode
When the OE# input is at V , output from the device is
disabled. The output pins are placed in the high im-
pedance state.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
IH
22358B7 May 5, 2006
Am29LV160D
11
D A T A S H E E T
Table 2. Sector Address Tables (Am29LV160DT)
Sector Size
(Kbytes/
Address Range (in hexadecimal)
Sector A19 A18 A17 A16 A15 A14 A13 A12
Kwords)
Byte Mode (x8)
000000–00FFFF
010000–01FFFF
020000–02FFFF
030000–03FFFF
040000–04FFFF
050000–05FFFF
060000–06FFFF
070000–07FFFF
080000–08FFFF
090000–09FFFF
0A0000–0AFFFF
0B0000–0BFFFF
0C0000–0CFFFF
0D0000–0DFFFF
0E0000–0EFFFF
0F0000–0FFFFF
100000–10FFFF
110000–11FFFF
120000–12FFFF
130000–13FFFF
140000–14FFFF
150000–15FFFF
160000–16FFFF
170000–17FFFF
180000–18FFFF
190000–19FFFF
1A0000–1AFFFF
1B0000–1BFFFF
1C0000–1CFFFF
1D0000–1DFFFF
1E0000–1EFFFF
1F0000–1F7FFF
1F8000–1F9FFF
1FA000–1FBFFF
1FC000–1FFFFF
Word Mode (x16)
00000–07FFF
08000–0FFFF
10000–17FFF
18000–1FFFF
20000–27FFF
28000–2FFFF
30000–37FFF
38000–3FFFF
40000–47FFF
48000–4FFFF
50000–57FFF
58000–5FFFF
60000–67FFF
68000–6FFFF
70000–77FFF
78000–7FFFF
80000–87FFF
88000–8FFFF
90000–97FFF
98000–9FFFF
A0000–A7FFF
A8000–AFFFF
B0000–B7FFF
B8000–BFFFF
C0000–C7FFF
C8000–CFFFF
D0000–D7FFF
D8000–DFFFF
E0000–E7FFF
E8000–EFFFF
F0000–F7FFF
F8000–FBFFF
FC000–FCFFF
FD000–FDFFF
FE000–FFFFF
SA0
SA1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
32/16
8/4
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
1
1
0
1
8/4
1
1
X
16/8
Note: Address range is A19:A-1 in byte mode and A19:A0 in word mode. See “Word/Byte Configuration” section.
12
Am29LV160D
May 5, 2006 22358B7
D A T A S H E E T
Table 3. Sector Address Tables (Am29LV160DB)
Sector Size
(Kbytes/
Address Range (in hexadecimal)
Sector A19 A18 A17 A16 A15 A14 A13 A12
Kwords)
Byte Mode (x8)
000000–003FFF
004000–005FFF
006000–007FFF
008000–00FFFF
010000–01FFFF
020000–02FFFF
030000–03FFFF
040000–04FFFF
050000–05FFFF
060000–06FFFF
070000–07FFFF
080000–08FFFF
090000–09FFFF
0A0000–0AFFFF
0B0000–0BFFFF
0C0000–0CFFFF
0D0000–0DFFFF
0E0000–0EFFFF
0F0000–0FFFFF
100000–10FFFF
110000–11FFFF
120000–12FFFF
130000–13FFFF
140000–14FFFF
150000–15FFFF
160000–16FFFF
170000–17FFFF
180000–18FFFF
190000–19FFFF
1A0000–1AFFFF
1B0000–1BFFFF
1C0000–1CFFFF
1D0000–1DFFFF
1E0000–1EFFFF
1F0000–1FFFFF
Word Mode (x16)
00000–01FFF
02000–02FFF
03000–03FFF
04000–07FFF
08000–0FFFF
10000–17FFF
18000–1FFFF
20000–27FFF
28000–2FFFF
30000–37FFF
38000–3FFFF
40000–47FFF
48000–4FFFF
50000–57FFF
58000–5FFFF
60000–67FFF
68000–6FFFF
70000–77FFF
78000–7FFFF
80000–87FFF
88000–8FFFF
90000–97FFF
98000–9FFFF
A0000–A7FFF
A8000–AFFFF
B0000–B7FFF
B8000–BFFFF
C0000–C7FFF
C8000–CFFFF
D0000–D7FFF
D8000–DFFFF
E0000–E7FFF
E8000–EFFFF
F0000–F7FFF
F8000–FFFFF
SA0
SA1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
1
X
0
16/8
8/4
SA2
0
1
1
8/4
SA3
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
32/16
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
SA4
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
Note: Address range is A19:A-1 in byte mode and A19:A0 in word mode. See the “Word/Byte Configuration” section.
22358B7 May 5, 2006
Am29LV160D
13
D A T A S H E E T
Table 4. In addition, when verifying sector protection,
Autoselect Mode
the sector address must appear on the appropriate
highest order address bits (see Tables 2 and 3). Table
4 shows the remaining address bits that are don’t
care. When all necessary bits have been set as re-
quired, the programming equipment may then read the
corresponding identifier code on DQ7-DQ0.
The autoselect mode provides manufacturer and de-
vice identification, and sector protection verification,
through identifier codes output on DQ7–DQ0. This
mode is primarily intended for programming equip-
ment to automatically match a device to be
programmed with its corresponding programming al-
gorithm. However, the autoselect codes can also be
accessed in-system through the command register.
To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in Table 9. This method
When using programming equipment, the autoselect
mode requires V (11.5 V to 12.5 V) on address pin
does not require V . See “Command Definitions” for
ID
ID
details on using the autoselect mode.
A9. Address pins A6, A1, and A0 must be as shown in
Table 4. Am29LV160D Autoselect Codes (High Voltage Method)
A19 A11
to to
Mode CE# OE# WE# A12 A10 A9
A8
to
A7
A5
to
A2
DQ8
to
A0 DQ15
DQ7
to
DQ0
Description
A6
A1
Manufacturer ID: AMD
L
L
L
L
H
H
X
X
V
X
X
L
X
X
L
L
X
01h
C4h
ID
Device ID:
Am29LV160D
(Top Boot Block)
Word
Byte
Word
Byte
22h
X
X
V
L
L
L
L
H
ID
L
L
L
L
L
L
H
H
H
X
22h
X
C4h
49h
49h
Device ID:
Am29LV160D
(Bottom Boot Block)
X
X
X
V
V
X
X
X
X
H
L
ID
ID
01h
(protected)
X
X
Sector Protection Verification
L
L
H
SA
L
H
00h
(unprotected)
L = Logic Low = V , H = Logic High = V , SA = Sector Address, X = Don’t care.
IL
IH
Note: The autoselect codes may also be accessed in-system via command sequences. See Table 9.
The primary method requires V on the RESET# pin
Sector Protection/Unprotection
ID
only, and can be implemented either in-system or via
programming equipment. Figure 2 shows the algo-
rithms and Figure 23 shows the timing diagram. This
method uses standard microprocessor bus cycle tim-
ing. For sector unprotect, all unprotected sectors must
first be protected prior to the first sector unprotect
write cycle.
The hardware sector protection feature disables both
program and erase operations in any sector. The hard-
ware sector unprotection feature re-enables both
program and erase operations in previously protected
sectors.
The device is shipped with all sectors unprotected.
AMD offers the option of programming and protecting
sectors at its factory prior to shipping the device
through AMD’s ExpressFlash™ Service. Contact an
AMD representative for details.
The alternate method intended only for programming
equipment requires V on address pin A9 and OE#.
ID
This method is compatible with programmer routines
written for earlier 3.0 volt-only AMD flash devices. De-
tails on this method are provided in a supplement,
publication number 21468. Contact an AMD represen-
tative to request a copy.
It is possible to determine whether a sector is pro-
tected or unprotected. See “Autoselect Mode” for
details.
Sector protection/unprotection can be implemented
via two methods.
14
Am29LV160D
May 5, 2006 22358B7
D A T A S H E E T
Temporary Sector Unprotect
This feature allows temporary unprotection of previ-
ously protected sectors to change data in-system. The
Sector Unprotect mode is activated by setting the RE-
START
SET# pin to V . During this mode, formerly protected
sectors can be programmed or erased by selecting the
ID
RESET# = V
(Note 1)
ID
sector addresses. Once V is removed from the RE-
ID
SET# pin, all the previously protected sectors are
protected again. Figure shows the algorithm, and Fig-
ure 22 shows the timing diagrams, for this feature.
Perform Erase or
Program Operations
RESET# = V
IH
Temporary Sector
Unprotect Completed
(Note 2)
Notes:
1. All protected sectors unprotected.
2. All previously protected sectors are protected once
again.
Figure 1. Temporary Sector Unprotect Operation
22358B7 May 5, 2006
Am29LV160D
15
D A T A S H E E T
START
START
Protect all sectors:
The indicated portion
of the sector protect
algorithm must be
performed for all
PLSCNT = 1
PLSCNT = 1
RESET# = VID
RESET# = VID
unprotected sectors
prior to issuing the
first sector
Wait 1 μs
Wait 1 μs
unprotect address
No
First Write
Cycle = 60h?
No
First Write
Cycle = 60h?
Temporary Sector
Unprotect Mode
Temporary Sector
Unprotect Mode
Yes
Yes
Set up sector
address
No
All sectors
protected?
Sector Protect:
Write 60h to sector
address with
A6 = 0, A1 = 1,
A0 = 0
Yes
Set up first sector
address
Sector Unprotect:
Wait 150 µs
Write 60h to sector
address with
A6 = 1, A1 = 1,
A0 = 0
Verify Sector
Protect: Write 40h
to sector address
with A6 = 0,
Reset
PLSCNT = 1
Increment
PLSCNT
Wait 15 ms
A1 = 1, A0 = 0
Verify Sector
Unprotect: Write
40h to sector
address with
A6 = 1, A1 = 1,
A0 = 0
Read from
sector address
with A6 = 0,
A1 = 1, A0 = 0
Increment
PLSCNT
No
No
PLSCNT
= 25?
Read from
sector address
with A6 = 1,
Data = 01h?
Yes
A1 = 1, A0 = 0
No
Yes
Set up
next sector
address
Yes
No
PLSCNT
= 1000?
Protect another
sector?
Data = 00h?
Yes
Device failed
No
Yes
Remove VID
from RESET#
No
Last sector
verified?
Device failed
Write reset
command
Yes
Remove VID
Sector Unprotect
Algorithm
from RESET#
Sector Protect
Algorithm
Sector Protect
complete
Write reset
command
Sector Unprotect
complete
Figure 2. In-System Sector Protect/Unprotect Algorithms
16
Am29LV160D
May 5, 2006 22358B7
D A T A S H E E T
tem can read CFI information at the addresses given
COMMON FLASH MEMORY INTERFACE
(CFI)
in Tables 5–8. In word mode, the upper address bits
(A7–MSB) must be all zeros. To terminate reading CFI
data, the system must write the reset command.
The Common Flash Interface (CFI) specification out-
lines device and host system software interrogation
handshake, which allows specific vendor-specified
software algorithms to be used for entire families of
devices. Software support can then be device-inde-
pendent, JEDEC ID-independent, and forward- and
backward-compatible for the specified flash device
families. Flash vendors can standardize their existing
interfaces for long-term compatibility.
The system can also write the CFI query command
when the device is in the autoselect mode. The device
enters the CFI query mode, and the system can read
CFI data at the addresses given in Tables 5–8. The
system must write the reset command to return the
device to the autoselect mode.
For further information, please refer to the CFI Specifi-
cation and CFI Publication 100, available via the World
Wide Web at http://www.amd.com/products/nvd/over-
view/cfi.html. Alternatively, contact an AMD
representative for copies of these documents.
This device enters the CFI Query mode when the sys-
tem writes the CFI Query command, 98h, to address
55h in word mode (or address AAh in byte mode), any
time the device is ready to read array data. The sys-
Table 5. CFI Query Identification String
Addresses
Addresses
(Word Mode)
(Byte Mode)
Data
Description
10h
11h
12h
20h
22h
24h
0051h
0052h
0059h
Query Unique ASCII string “QRY”
13h
14h
26h
28h
0002h
0000h
Primary OEM Command Set
15h
16h
2Ah
2Ch
0040h
0000h
Address for Primary Extended Table
17h
18h
2Eh
30h
0000h
0000h
Alternate OEM Command Set (00h = none exists)
Address for Alternate OEM Extended Table (00h = none exists)
19h
1Ah
32h
34h
0000h
0000h
22358B7 May 5, 2006
Am29LV160D
17
D A T A S H E E T
Table 6. System Interface String
Data Description
Addresses
(Word Mode)
Addresses
(Byte Mode)
V
Min. (write/erase)
CC
1Bh
1Ch
36h
38h
0027h
0036h
D7–D4: volt, D3–D0: 100 millivolt
V
Max. (write/erase)
CC
D7–D4: volt, D3–D0: 100 millivolt
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
3Ah
3Ch
3Eh
40h
42h
44h
46h
48h
4Ah
4Ch
0000h
0000h
0004h
0000h
000Ah
0000h
0005h
0000h
0004h
0000h
V
V
Min. voltage (00h = no V pin present)
PP
PP
PP
Max. voltage (00h = no V pin present)
PP
N
Typical timeout per single byte/word write 2 µs
N
Typical timeout for Min. size buffer write 2 µs (00h = not supported)
N
Typical timeout per individual block erase 2 ms
N
Typical timeout for full chip erase 2 ms (00h = not supported)
N
Max. timeout for byte/word write 2 times typical
N
Max. timeout for buffer write 2 times typical
N
Max. timeout per individual block erase 2 times typical
N
Max. timeout for full chip erase 2 times typical (00h = not supported)
Table 7. Device Geometry Definition
Addresses
Addresses
(Word Mode)
(Byte Mode)
Data
Description
N
27h
4Eh
0015h
Device Size = 2 byte
28h
29h
50h
52h
0002h
0000h
Flash Device Interface description (refer to CFI publication 100)
N
2Ah
2Bh
54h
56h
0000h
0000h
Max. number of byte in multi-byte write = 2
(00h = not supported)
2Ch
58h
0004h
Number of Erase Block Regions within device
2Dh
2Eh
2Fh
30h
5Ah
5Ch
5Eh
60h
0000h
0000h
0040h
0000h
Erase Block Region 1 Information
(refer to the CFI specification or CFI publication 100)
31h
32h
33h
34h
62h
64h
66h
68h
0001h
0000h
0020h
0000h
Erase Block Region 2 Information
Erase Block Region 3 Information
Erase Block Region 4 Information
35h
36h
37h
38h
6Ah
6Ch
6Eh
70h
0000h
0000h
0080h
0000h
39h
3Ah
3Bh
3Ch
72h
74h
76h
78h
001Eh
0000h
0000h
0001h
18
Am29LV160D
May 5, 2006 22358B7
D A T A S H E E T
Table 8. Primary Vendor-Specific Extended Query
Addresses
Addresses
(Word Mode)
(Byte Mode)
Data
Description
40h
41h
42h
80h
82h
84h
0050h
0052h
0049h
Query-unique ASCII string “PRI”
43h
44h
86h
88h
0031h
0030h
Major version number, ASCII
Minor version number, ASCII
Address Sensitive Unlock
0 = Required, 1 = Not Required
45h
46h
47h
48h
8Ah
8Ch
8Eh
90h
0000h
0002h
0001h
0001h
Erase Suspend
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
Sector Protect
0 = Not Supported, X = Number of sectors in per group
Sector Temporary Unprotect
00 = Not Supported, 01 = Supported
Sector Protect/Unprotect scheme
49h
92h
0004h
01 = 29F040 mode, 02 = 29F016 mode,
03 = 29F400 mode, 04 = 29LV800A mode
Simultaneous Operation
00 = Not Supported, 01 = Supported
4Ah
4Bh
4Ch
94h
96h
98h
0000h
0000h
0000h
Burst Mode Type
00 = Not Supported, 01 = Supported
Page Mode Type
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to Table 9 for com-
mand definitions). In addition, the following hardware
data protection measures prevent accidental erasure
or programming, which might otherwise be caused by
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE#
or WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
spurious system level signals during V
power-up
CC
V , CE# = V or WE# = V . To initiate a write cycle,
IL
IH
IH
and power-down transitions, or from system noise.
CE# and WE# must be a logical zero while OE# is a
logical one.
Low V
Write Inhibit
CC
When V
is less than V
, the device does not ac-
LKO
Power-Up Write Inhibit
CC
cept any write cycles. This protects data during V
CC
If WE# = CE# = V and OE# = V during power up,
IL
IH
power-up and power-down. The command register
and all internal program/erase circuits are disabled,
and the device resets. Subsequent writes are ignored
the device does not accept commands on the rising
edge of WE#. The internal state machine is automati-
cally reset to reading array data on power-up.
until V
is greater than V
. The system must pro-
CC
LKO
vide the proper signals to the control pins to prevent
unintentional writes when V is greater than V
.
CC
LKO
22358B7 May 5, 2006
Am29LV160D
19
D A T A S H E E T
COMMAND DEFINITIONS
Writing specific address and data commands or se-
quences into the command register initiates device
operations. Table 9 defines the valid register command
sequences. Writing incorrect address and data val-
ues or writing them in the improper sequence resets
the device to reading array data.
The reset command may be written between the se-
quence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command
must be written to return to reading array data (also
applies to autoselect during Erase Suspend).
If DQ5 goes high during a program or erase operation,
writing the reset command returns the device to read-
ing array data (also applies during Erase Suspend).
All addresses are latched on the falling edge of WE#
or CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in the
“AC Characteristics” section.
Autoselect Command Sequence
The autoselect command sequence allows the host
system to access the manufacturer and devices
codes, and determine whether or not a sector is pro-
tected. Table 9 shows the address and data
requirements. This method is an alternative to that
shown in Table 4, which is intended for PROM pro-
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array
data after completing an Embedded Program or Em-
bedded Erase algorithm.
grammers and requires V on address bit A9.
ID
The autoselect command sequence is initiated by writ-
ing two unlock cycles, followed by the autoselect
command. The device then enters the autoselect
mode, and the system may read at any address any
number of times, without initiating another command
sequence.
After the device accepts an Erase Suspend com-
mand, the device enters the Erase Suspend mode.
The system can read array data using the standard
read timings, except that if it reads at an address
within erase-suspended sectors, the device outputs
status data. After completing a programming opera-
tion in the Erase Suspend mode, the system may
once again read array data with the same exception.
See “Erase Suspend/Erase Resume Commands” for
more information on this mode.
A read cycle at address XX00h retrieves the manufac-
turer code. A read cycle at address XX01h returns the
device code. A read cycle containing a sector address
(SA) and the address 02h in word mode (or 04h in
byte mode) returns 01h if that sector is protected, or
00h if it is unprotected. Refer to Tables 2 and 3 for
valid sector addresses.
The system must issue the reset command to re-en-
able the device for reading array data if DQ5 goes
high, or while in the autoselect mode. See the “Reset
Command” section, next.
The system must write the reset command to exit the
autoselect mode and return to reading array data.
See also “Requirements for Reading Array Data” in
the “Device Bus Operations” section for more informa-
tion. The Read Operations table provides the read
parameters, and Figure 13 shows the timing diagram.
Word/Byte Program Command Sequence
The system may program the device by word or byte,
depending on the state of the BYTE# pin. Program-
ming is a four-bus-cycle operation. The program
command sequence is initiated by writing two unlock
write cycles, followed by the program set-up com-
mand. The program address and data are written
next, which in turn initiate the Embedded Program al-
gorithm. The system is not required to provide further
controls or timings. The device automatically gener-
ates the program pulses and verifies the programmed
cell margin. Table 9 shows the address and data re-
quirements for the byte program command
sequence.
Reset Command
Writing the reset command to the device resets the
device to reading array data. Address bits are don’t
care for this command.
The reset command may be written between the se-
quence cycles in an erase command sequence before
erasing begins. This resets the device to reading array
data. Once erasure begins, however, the device ig-
nores reset commands until the operation is complete.
The reset command may be written between the se-
quence cycles in a program command sequence
before programming begins. This resets the device to
reading array data (also applies to programming in
Erase Suspend mode). Once programming begins,
however, the device ignores reset commands until the
operation is complete.
When the Embedded Program algorithm is complete,
the device then returns to reading array data and ad-
dresses are no longer latched. The system can
determine the status of the program operation by
using DQ7, DQ6, or RY/BY#. See “Write Operation
Status” for information on these status bits.
20
Am29LV160D
May 5, 2006 22358B7
D A T A S H E E T
Any commands written to the device during the Em-
90h; the second cycle the data 00h. Addresses are
don’t care for both cycles. The device then returns to
reading array data.
bedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the program-
ming operation. The Byte Program command
sequence should be reinitiated once the device has
reset to reading array data, to ensure data integrity.
Figure 3 illustrates the algorithm for the program oper-
ation. See the Erase/Program Operations table in “AC
Characteristics” for parameters, and to Figure 17 for
timing diagrams.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
from a “0” back to a “1”. Attempting to do so may
halt the operation and set DQ5 to “1,” or cause the
Data# Polling algorithm to indicate the operation was
successful. However, a succeeding read will show that
the data is still “0”. Only erase operations can convert
a “0” to a “1”.
START
Write Program
Command Sequence
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to pro-
gram bytes or words to the device faster than using the
standard program command sequence. The unlock
bypass command sequence is initiated by first writing
two unlock cycles. This is followed by a third write
cycle containing the unlock bypass command, 20h.
The device then enters the unlock bypass mode. A
two-cycle unlock bypass program command sequence
is all that is required to program in this mode. The first
cycle in this sequence contains the unlock bypass pro-
gram command, A0h; the second cycle contains the
program address and data. Additional data is pro-
grammed in the same manner. This mode dispenses
with the initial two unlock cycles required in the stan-
dard program command sequence, resulting in faster
total programming time. Table 9 shows the require-
ments for the command sequence.
Data Poll
from System
Embedded
Program
algorithm
in progress
Verify Data?
No
Yes
No
Increment Address
Last Address?
Yes
During the unlock bypass mode, only the Unlock By-
pass Program and Unlock Bypass Reset commands
are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset com-
mand sequence. The first cycle must contain the data
Programming
Completed
Note: See Table 9 for program command sequence.
Figure 3. Program Operation
the address and data requirements for the chip erase
command sequence.
Any commands written to the chip during the Embed-
ded Erase algorithm are ignored. Note that a
hardware reset during the chip erase operation im-
mediately terminates the operation. The Chip Erase
command sequence should be reinitiated once the de-
vice has returned to reading array data, to ensure data
integrity.
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algo-
rithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
trols or timings during these operations. Table 9 shows
The system can determine the status of the erase op-
eration by using DQ7, DQ6, DQ2, or RY/BY#. See
“Write Operation Status” for information on these sta-
tus bits. When the Embedded Erase algorithm is
complete, the device returns to reading array data and
addresses are no longer latched.
22358B7 May 5, 2006
Am29LV160D
21
D A T A S H E E T
Figure 4 illustrates the algorithm for the erase opera-
status of the erase operation by using DQ7, DQ6,
DQ2, or RY/BY#. (Refer to “Write Operation Status” for
information on these status bits.)
tion. See the Erase/Program Operations tables in “AC
Characteristics” for parameters, and to Figure 18 for
timing diagrams.
Figure 4 illustrates the algorithm for the erase opera-
tion. Refer to the Erase/Program Operations tables in
the “AC Characteristics” section for parameters, and to
Figure 18 for timing diagrams.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two ad-
ditional unlock write cycles are then followed by the
address of the sector to be erased, and the sector
erase command. Table 9 shows the address and data
requirements for the sector erase command
sequence.
Erase Suspend/Erase Resume
Commands
The Erase Suspend command allows the system to in-
terrupt a sector erase operation and then read data
from, or program data to, any sector not selected for
erasure. This command is valid only during the sector
erase operation, including the 50 µs time-out period
during the sector erase command sequence. The
Erase Suspend command is ignored if written during
the chip erase operation or Embedded Program algo-
rithm. Writing the Erase Suspend command during the
Sector Erase time-out immediately terminates the
time-out period and suspends the erase operation. Ad-
dresses are “don’t-cares” when writing the Erase
Suspend command.
The device does not require the system to preprogram
the memory prior to erase. The Embedded Erase al-
gorithm automatically programs and verifies the sector
for an all zero data pattern prior to electrical erase.
The system is not required to provide any controls or
timings during these operations.
After the command sequence is written, a sector erase
time-out of 50 µs begins. During the time-out period,
additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of sec-
tors may be from one sector to all sectors. The time
between these additional cycles must be less than 50
µs, otherwise the last address and command might
not be accepted, and erasure may begin. It is recom-
mended that processor interrupts be disabled during
this time to ensure all commands are accepted. The
interrupts can be re-enabled after the last Sector
Erase command is written. If the time between addi-
tional sector erase commands can be assumed to be
less than 50 µs, the system need not monitor DQ3.
Any command other than Sector Erase or Erase
Suspend during the time-out period resets the de-
vice to reading array data. The system must rewrite
the command sequence and any additional sector ad-
dresses and commands.
When the Erase Suspend command is written during a
sector erase operation, the device requires a maxi-
mum of 20 µs to suspend the erase operation.
However, when the Erase Suspend command is writ-
ten during the sector erase time-out, the device
immediately terminates the time-out period and sus-
pends the erase operation.
After the erase operation has been suspended, the
system can read array data from or program data to
any sector not selected for erasure. (The device “erase
suspends” all sectors selected for erasure.) Normal
read and write timings and command definitions apply.
Reading at any address within erase-suspended sec-
tors produces status data on DQ7–DQ0. The system
can use DQ7, or DQ6 and DQ2 together, to determine
if a sector is actively erasing or is erase-suspended.
See “Write Operation Status” for information on these
status bits.
The system can monitor DQ3 to determine if the sec-
tor erase timer has timed out. (See the “DQ3: Sector
Erase Timer” section.) The time-out begins from the
rising edge of the final WE# pulse in the command
sequence.
After an erase-suspended program operation is com-
plete, the system can once again read array data
within non-suspended sectors. The system can deter-
mine the status of the program operation using the
DQ7 or DQ6 status bits, just as in the standard pro-
gram operation. See “Write Operation Status” for more
information.
Once the sector erase operation has begun, only the
Erase Suspend command is valid. All other com-
mands are ignored. Note that a hardware reset
during the sector erase operation immediately termi-
nates the operation. The Sector Erase command
sequence should be reinitiated once the device has re-
turned to reading array data, to ensure data integrity.
The system may also write the autoselect command
sequence when the device is in the Erase Suspend
mode. The device allows reading autoselect codes
even at addresses within erasing sectors, since the
codes are not stored in the memory array. When the
device exits the autoselect mode, the device reverts to
the Erase Suspend mode, and is ready for another
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses
are no longer latched. The system can determine the
22
Am29LV160D
May 5, 2006 22358B7
D A T A S H E E T
valid operation. See “Autoselect Command Sequence”
for more information.
START
The system must write the Erase Resume command
(address bits are “don’t care”) to exit the erase sus-
pend mode and continue the sector erase operation.
Further writes of the Resume command are ignored.
Another Erase Suspend command can be written after
the device has resumed erasing.
Write Erase
Command Sequence
Data Poll
from System
Embedded
Erase
algorithm
in progress
No
Data = FFh?
Yes
Erasure Completed
Notes:
1. See Table 9 for erase command sequence.
2. See “DQ3: Sector Erase Timer” for more information.
Figure 4. Erase Operation
22358B7 May 5, 2006
Am29LV160D
23
D A T A S H E E T
Command Definitions
Table 9. Am29LV160D Command Definitions
Bus Cycles (Notes 2–5)
Command
Sequence
(Note 1)
First
Second
Third
Addr
Fourth
Data Addr Data
Fifth
Sixth
Addr Data Addr Data
Addr Data Addr Data
Read (Note 6)
Reset (Note 7)
1
1
RA
XXX
555
RD
F0
Word
2AA
555
2AA
555
2AA
555
555
AAA
555
Manufacturer ID
4
4
4
AA
AA
AA
55
55
55
90
90
90
X00
01
Byte
Word
Byte
Word
Byte
AAA
555
X01
X02
X01
X02
22C4
C4
Device ID,
Top Boot Block
AAA
555
AAA
555
2249
49
Device ID,
Bottom Boot Block
AAA
AAA
XX00
XX01
00
(SA)
X02
Word
Byte
555
2AA
555
555
Sector Protect Verify
(Note 9)
4
AA
55
90
(SA)
X04
AAA
AAA
01
Word
Byte
Word
Byte
Word
Byte
55
CFI Query (Note 10)
1
4
3
98
AA
AA
AA
555
2AA
555
2AA
555
PA
555
AAA
555
Program
55
55
A0
20
PA
PD
AAA
555
AAA
XXX
XXX
555
Unlock Bypass
AAA
Unlock Bypass Program (Note 11)
Unlock Bypass Reset (Note 12)
2
2
A0
90
PD
00
XXX
2AA
555
2AA
555
Word
555
AAA
555
555
AAA
555
2AA
555
2AA
555
555
Chip Erase
Byte
6
6
AA
AA
55
55
80
80
AA
AA
55
55
10
30
AAA
555
AAA
Word
Sector Erase
Byte
SA
AAA
XXX
XXX
AAA
AAA
Erase Suspend (Note 13)
Erase Resume (Note 14)
1
1
B0
30
Legend:
X = Don’t care
PD = Data to be programmed at location PA. Data latches on the rising
edge of WE# or CE# pulse, whichever happens first.
RA = Address of the memory location to be read.
SA = Address of the sector to be verified (in autoselect mode) or
erased. Address bits A19–A12 uniquely select any sector.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses
latch on the falling edge of the WE# or CE# pulse, whichever happens
later.
Notes:
1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
9. The data is 00h for an unprotected sector and 01h for a
protected sector. See “Autoselect Command Sequence” for
more information.
3. Except for the read cycle and the fourth cycle of the autoselect
command sequence, all bus cycles are write cycles.
10. Command is valid when device is ready to read array data or
when device is in autoselect mode.
4. Data bits DQ15–DQ8 are don’t cares for unlock and command
cycles.
11. The Unlock Bypass command is required prior to the Unlock
Bypass Program command.
5. Address bits A19–A11 are don’t cares for unlock and
command cycles, unless SA or PA required.
12. The Unlock Bypass Reset command is required to return to
reading array data when the device is in the unlock bypass
mode.
6. No unlock or command cycles required when reading array
data.
7. The Reset command is required to return to reading array data
when device is in the autoselect mode, or if DQ5 goes high
(while the device is providing status data).
13. The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Erase Suspend mode.
The Erase Suspend command is valid only during a sector
erase operation.
8. The fourth cycle of the autoselect command sequence is a
read cycle.
14. The Erase Resume command is valid only during the Erase Suspend mode.
24
Am29LV160D
May 5, 2006 22358B7
D A T A S H E E T
WRITE OPERATION STATUS
The device provides several bits to determine the sta-
tus of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7,
and RY/BY#. Table 10 and the following subsections
describe the functions of these bits. DQ7, RY/BY#,
and DQ6 each offer a method for determining whether
a program or erase operation is complete or in
progress. These three bits are discussed first.
Table 10 shows the outputs for Data# Polling on DQ7.
Figure 5 shows the Data# Polling algorithm.
START
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host sys-
tem whether an Embedded Algorithm is in progress or
completed, or whether the device is in Erase Suspend.
Data# Polling is valid after the rising edge of the final
WE# pulse in the program or erase command
sequence.
Read DQ7–DQ0
Addr = VA
Yes
DQ7 = Data?
During the Embedded Program algorithm, the device
outputs on DQ7 the complement of the datum pro-
grammed to DQ7. This DQ7 status also applies to
programming during Erase Suspend. When the Em-
bedded Program algorithm is complete, the device
outputs the datum programmed to DQ7. The system
must provide the program address to read valid status
information on DQ7. If a program address falls within a
protected sector, Data# Polling on DQ7 is active for
approximately 1 µs, then the device returns to reading
array data.
No
No
DQ5 = 1?
Yes
During the Embedded Erase algorithm, Data# Polling
produces a “0” on DQ7. When the Embedded Erase
algorithm is complete, or if the device enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7.
This is analogous to the complement/true datum out-
put described for the Embedded Program algorithm:
the erase function changes all the bits in a sector to
“1”; prior to this, the device outputs the “complement,”
or “0.” The system must provide an address within any
of the sectors selected for erasure to read valid status
information on DQ7.
Read DQ7–DQ0
Addr = VA
Yes
DQ7 = Data?
No
PASS
FAIL
After an erase command sequence is written, if all
sectors selected for erasing are protected, Data# Poll-
ing on DQ7 is active for approximately 100 µs, then the
device returns to reading array data. If not all selected
sectors are protected, the Embedded Erase algorithm
erases the unprotected sectors, and ignores the se-
lected sectors that are protected.
Notes:
1. VA = Valid address for programming. During a sector
erase operation, a valid address is an address within
any sector selected for erasure. During chip erase, a
valid address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = “1” because
DQ7 may change simultaneously with DQ5.
When the system detects DQ7 has changed from the
complement to true data, it can read valid data at
DQ7–DQ0 on the following read cycles. This is be-
cause DQ7 may change asynchronously with DQ0–
DQ6 while Output Enable (OE#) is asserted low. Fig-
Figure 5. Data# Polling Algorithm
ure
19,
Data#
Polling
Timings
(During Embedded Algorithms), in the “AC Character-
istics” section illustrates this.
22358B7 May 5, 2006
Am29LV160D
25
D A T A S H E E T
DQ6 also toggles during the erase-suspend-program
RY/BY#: Ready/Busy#
mode, and stops toggling once the Embedded Pro-
gram algorithm is complete.
The RY/BY# is a dedicated, open-drain output pin that
indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY# status is valid after
the rising edge of the final WE# pulse in the command
sequence. Since RY/BY# is an open-drain output, sev-
eral RY/BY# pins can be tied together in parallel with a
Table 10 shows the outputs for Toggle Bit I on DQ6.
Figure 6 shows the toggle bit algorithm in flowchart
form, and the section “Reading Toggle Bits DQ6/DQ2”
explains the algorithm. Figure 20 in the “AC Character-
istics” section shows the toggle bit timing diagrams.
Figure 21 shows the differences between DQ2 and
DQ6 in graphical form. See also the subsection on
“DQ2: Toggle Bit II”.
pull-up resistor to V . (The RY/BY# pin is not avail-
CC
able on the 44-pin SO package.)
If the output is low (Busy), the device is actively eras-
ing or programming. (This includes programming in
the Erase Suspend mode.) If the output is high
(Ready), the device is ready to read array data (includ-
ing during the Erase Suspend mode), or is in the
standby mode.
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indi-
cates whether a particular sector is actively erasing
(that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of the final WE# pulse in
the command sequence.
Table 10 shows the outputs for RY/BY#. Figures 13,
14, 17 and 18 shows RY/BY# for read, reset, program,
and erase operations, respectively.
DQ2 toggles when the system reads at addresses
within those sectors that have been selected for era-
sure. (The system may use either OE# or CE# to
control the read cycles.) But DQ2 cannot distinguish
whether the sector is actively erasing or is erase-sus-
pended. DQ6, by comparison, indicates whether the
device is actively erasing, or is in Erase Suspend, but
cannot distinguish which sectors are selected for era-
sure. Thus, both status bits are required for sector and
mode information. Refer to Table 10 to compare out-
puts for DQ2 and DQ6.
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or com-
plete, or whether the device has entered the Erase
Suspend mode. Toggle Bit I may be read at any ad-
dress, and is valid after the rising edge of the final
WE# pulse in the command sequence (prior to the
program or erase operation), and during the sector
erase time-out.
During an Embedded Program or Erase algorithm op-
eration, successive read cycles to any address cause
DQ6 to toggle. (The system may use either OE# or
CE# to control the read cycles.) When the operation is
complete, DQ6 stops toggling.
Figure 6 shows the toggle bit algorithm in flowchart
form, and the section “Reading Toggle Bits DQ6/DQ2”
explains the algorithm. See also the DQ6: Toggle Bit I
subsection. Figure 20 shows the toggle bit timing dia-
gram. Figure 21 shows the differences between DQ2
and DQ6 in graphical form.
After an erase command sequence is written, if all
sectors selected for erasing are protected, DQ6 tog-
gles for approximately 100 µs, then returns to reading
array data. If not all selected sectors are protected, the
Embedded Erase algorithm erases the unprotected
sectors, and ignores the selected sectors that are
protected.
Reading Toggle Bits DQ6/DQ2
Refer to Figure 6 for the following discussion. When-
ever the system initially begins reading toggle bit
status, it must read DQ7–DQ0 at least twice in a row
to determine whether a toggle bit is toggling. Typi-
cally, the system would note and store the value of
the toggle bit after the first read. After the second
read, the system would compare the new value of the
toggle bit with the first. If the toggle bit is not toggling,
the device has completed the program or erase oper-
ation. The system can read array data on DQ7–DQ0
on the following read cycle.
The system can use DQ6 and DQ2 together to deter-
mine whether a sector is actively erasing or is erase-
suspended. When the device is actively erasing (that
is, the Embedded Erase algorithm is in progress), DQ6
toggles. When the device enters the Erase Suspend
mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing
or erase-suspended. Alternatively, the system can use
DQ7 (see the subsection on “DQ7: Data# Polling”).
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the sys-
tem also should note whether the value of DQ5 is high
(see the section on DQ5). If it is, the system should
then determine again whether the toggle bit is tog-
gling, since the toggle bit may have stopped toggling
just as DQ5 went high. If the toggle bit is no longer
If a program address falls within a protected sector,
DQ6 toggles for approximately 1 µs after the program
command sequence is written, then returns to reading
array data.
26
Am29LV160D
May 5, 2006 22358B7
D A T A S H E E T
toggling, the device has successfully completed the
program or erase operation. If it is still toggling, the de-
vice did not complete the operation successfully, and
the system must write the reset command to return to
reading array data.
START
The remaining scenario is that the system initially de-
termines that the toggle bit is toggling and DQ5 has
not gone high. The system may continue to monitor
the toggle bit and DQ5 through successive read cy-
cles, determining the status as described in the
previous paragraph. Alternatively, it may choose to
perform other system tasks. In this case, the system
must start at the beginning of the algorithm when it re-
turns to determine the status of the operation (top of
Figure 6).
Read DQ7–DQ0
Read DQ7–DQ0
(Note 1)
No
Toggle Bit
= Toggle?
Yes
No
DQ5 = 1?
Yes
Read DQ7–DQ0
Twice
(Notes
1, 2)
Toggle Bit
= Toggle?
No
Yes
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Notes:
1. Read toggle bit twice to determine whether or not it is
toggling. See text.
2. Recheck toggle bit because it may stop toggling as DQ5
changes to “1”. See text.
Figure 6. Toggle Bit Algorithm
22358B7 May 5, 2006
Am29LV160D
27
D A T A S H E E T
tional sectors are selected for erasure, the entire time-
DQ5: Exceeded Timing Limits
out also applies after each additional sector erase com-
mand. When the time-out is complete, DQ3 switches
from “0” to “1.” The system may ignore DQ3 if the sys-
tem can guarantee that the time between additional
sector erase commands will always be less than 50
μs. See also the “Sector Erase Command Sequence”
section.
DQ5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under
these conditions DQ5 produces a “1.” This is a failure
condition that indicates the program or erase cycle
was not successfully completed.
The DQ5 failure condition may appear if the system
tries to program a “1” to a location that is previously
programmed to “0.” Only an erase operation can
change a “0” back to a “1.” Under this condition, the
device halts the operation, and when the operation
has exceeded the timing limits, DQ5 produces a “1.”
After the sector erase command sequence is written,
the system should read the status on DQ7 (Data# Poll-
ing) or DQ6 (Toggle Bit I) to ensure the device has
accepted the command sequence, and then read
DQ3. If DQ3 is “1”, the internally controlled erase cycle
has begun; all further commands (other than Erase
Suspend) are ignored until the erase operation is com-
plete. If DQ3 is “0”, the device will accept additional
sector erase commands. To ensure the command has
been accepted, the system software should check the
status of DQ3 prior to and following each subsequent
sector erase command. If DQ3 is high on the second
status check, the last command might not have been
accepted. Table 10 shows the outputs for DQ3.
Under both these conditions, the system must issue
the reset command to return the device to reading
array data.
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not an
erase operation has begun. (The sector erase timer
does not apply to the chip erase command.) If addi-
Table 10. Write Operation Status
DQ7
DQ5
DQ2
Operation
(Note 2)
DQ6
(Note 1)
DQ3
N/A
1
(Note 2)
RY/BY#
Embedded Program Algorithm
Embedded Erase Algorithm
DQ7#
0
Toggle
Toggle
0
0
No toggle
Toggle
0
0
Standard
Mode
Reading within Erase
Suspended Sector
1
No toggle
0
N/A
Toggle
1
Erase
Suspend Reading within Non-Erase
Data
Data
Data
0
Data
N/A
Data
N/A
1
0
Mode
Suspended Sector
Erase-Suspend-Program
DQ7#
Toggle
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
See “DQ5: Exceeded Timing Limits” for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further
details.
28
Am29LV160D
May 5, 2006 22358B7
D A T A S H E E T
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
V
(Note 1) . . . . . . . . . . . . . . . . . –0.5 V to +4.0 V
CC
Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C
A9, OE#, and RESET# (Note 2) . –0.5 V to +12.5 V
Ambient Temperature
with Power Applied. . . . . . . . . . . . . . –65°C to +125°C
All other pins (Note 1) . . . . . . . –0.5 V to V +0.5 V
CC
Output Short Circuit Current (Note 3) . . . . . . . 200 mA
Voltage with Respect to Ground
Notes:
1. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, input or I/O pins may overshoot V to –2.0 V
SS
for periods of up to 20 ns. See Figure 7. Maximum DC voltage on input or I/O pins is VCC +0.5 V. During voltage transitions,
input or I/O pins may overshoot to V +2.0 V for periods up to 20 ns. See Figure 8.
CC
2. Minimum DC input voltage on pins A9, OE#, and RESET#
is -0.5 V. During voltage transitions, A9, OE#, and RESET#
3. No more than one output may be shorted to ground at a
time. Duration of the short circuit should not be greater than
one second.
may overshoot V to –2.0 V for periods of up to 20 ns. See
SS
Figure 7. Maximum DC input voltage on pin A9 is +12.5 V
which may overshoot to 14.0 V for periods up to 20 ns.
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections
of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect
device reliability.
22358B7 May 5, 2006
Am29LV160D
29
D A T A S H E E T
20 ns
20 ns
20 ns
+0.8 V
V
CC
+2.0 V
–0.5 V
–2.0 V
V
CC
+0.5 V
2.0 V
20 ns
20 ns
20 ns
Figure 8. Maximum Positive
Overshoot Waveform
Figure 7. Maximum Negative
Overshoot Waveform
OPERATING RANGES
Commercial (C) Devices
Ambient Temperature (T ) . . . . . . . . . . . 0°C to +70°C
A
Industrial (I) Devices
Ambient Temperature (T ) . . . . . . . . . –40°C to +85°C
A
V
Supply Voltages
CC
V
for all devices . . . . . . . . . . . . . . . . .2.7 V to 3.6 V
CC
Operating ranges define those limits between which the functionality of the device is guaranteed.
30
Am29LV160D
May 5, 2006 22358B7
D A T A S H E E T
DC CHARACTERISTICS
CMOS Compatible
Parameter
Description
Test Conditions
= V to V
Min
Typ
Max
±1.0
35
Unit
µA
V
V
,
CC
IN
SS
I
Input Load Current
LI
= V
CC
CC max
I
A9 Input Load Current
Output Leakage Current
V
= V
; A9 = 12.5 V
µA
LIT
CC
CC max
V
V
= V to V
,
OUT
SS
CC
I
±1.0
µA
LO
= V
CC
CC max
5 MHz
1 MHz
5 MHz
1 MHz
9
2
9
2
16
4
CE# = V OE#
Byte Mode
V
V
IL,
=
=
IH,
IH,
V
Active Read Current
CC
I
mA
CC1
(Notes 1, 2)
16
4
CE# = V OE#
IL,
Word Mode
V
Active Write Current
CC
I
I
I
CE# = V OE# = V
IH
20
0.2
0.2
30
5
mA
µA
µA
CC2
CC3
CC4
IL,
(Notes 2, 3, 5)
V
Standby Current (Notes 2, 4) CE#, RESET# = V ±0.3 V
CC
CC
V
Standby Current During Reset
CC
RESET# = V ± 0.3 V
5
SS
(Notes 2, 4)
Automatic Sleep Mode
(Notes 2, 4, 6)
V
V
= V ± 0.3 V;
CC
IH
IL
I
0.2
5
µA
CC5
= V ± 0.3 V
SS
V
Input Low Voltage
Input High Voltage
–0.5
0.8
V
V
IL
V
V
0.7 x V
V
+ 0.3
CC
IH
CC
Voltage for Autoselect and
Temporary Sector Unprotect
V
= 3.3 V
11.5
12.5
0.45
V
ID
CC
V
Output Low Voltage
I
I
I
= 4.0 mA, V = V
CC min
V
V
OL
OL
OH
OH
CC
V
= -2.0 mA, V = V
0.85 x V
CC
OH1
OH2
CC
CC min
CC min
Output High Voltage
V
= -100 µA, V = V
V
–0.4
CC
CC
V
Low V Lock-Out Voltage (Note 4)
2.3
2.5
V
LKO
CC
Notes:
1. The I current listed is typically less than 2 mA/MHz, with OE# at V . Typical V is 3.0 V.
CC
IH
CC
2. Maximum I specifications are tested with V = V max.
CC
CC
CC
3. I active while Embedded Erase or Embedded Program is in progress.
CC
4. At extended temperature range (>+85°C), typical current is 5 µA and maximum current is 10 µA.
5. Automatic sleep mode enables the low power mode when addresses remain stable for t
200 nA.
+ 30 ns. Typical sleep mode current is
ACC
6. Not 100% tested.
22358B7 May 5, 2006
Am29LV160D
31
D A T A S H E E T
DC CHARACTERISTICS (Continued)
Zero Power Flash
25
20
15
10
5
0
0
500
1000
1500
2000
2500
3000
3500
4000
Time in ns
Note: Addresses are switching at 1 MHz
Figure 9.
I
Current vs. Time (Showing Active and Automatic Sleep Currents)
CC1
10
8
3.6 V
2.7 V
6
4
2
0
1
2
3
4
5
Frequency in MHz
Note: T = 25 °C
Figure 10. Typical I
vs. Frequency
CC1
32
Am29LV160D
May 5, 2006 22358B7
D A T A S H E E T
TEST CONDITIONS
Table 11. Test Specifications
3.3 V
Test Condition
Output Load
-70
-90, -120 Unit
1 TTL gate
2.7 kΩ
Device
Under
Test
Output Load Capacitance, C
(including jig capacitance)
L
30
100
pF
C
L
Input Rise and Fall Times
Input Pulse Levels
5
0.0–3.0
ns
V
6.2 kΩ
Input timing measurement
reference levels
1.5
1.5
V
V
Output timing measurement
reference levels
Note: Diodes are IN3064 or equivalent
Figure 11. Test Setup
Key to Switching Waveforms
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Does Not Apply
Changing, State Unknown
Center Line is High Impedance State (High Z)
3.0 V
0.0 V
1.5 V
1.5 V
Input
Measurement Level
Output
Figure 12. Input Waveforms and Measurement Levels
22358B7 May 5, 2006
Am29LV160D
33
D A T A S H E E T
AC CHARACTERISTICS
Read Operations
Parameter
Speed Options
JEDEC
Std
Description
Test Setup
-70
-90
-120
Unit
t
t
Read Cycle Time (Note 1)
Min
70
70
90
120
120
ns
AVAV
RC
CE# = V
OE# = V
IL
IL
t
t
Address to Output Delay
Max
90
ns
AVQV
ACC
t
t
Chip Enable to Output Delay
OE# = V
Max
Max
Max
Max
Min
70
30
25
25
90
35
30
30
0
120
50
ns
ns
ns
ns
ns
ELQV
GLQV
EHQZ
GHQZ
CE
IL
t
t
t
Output Enable to Output Delay
OE
t
t
Chip Enable to Output High Z (Note 1)
Output Enable to Output High Z (Note 1)
30
DF
t
30
DF
Read
Output Enable
Hold Time (Note 1)
t
OEH
Toggle and
Data# Polling
Min
Min
10
0
ns
ns
Output Hold Time From Addresses, CE# or
OE#, Whichever Occurs First (Note 1)
t
t
OH
AXQX
Notes:
1. Not 100% tested.
2. See Figure 11 and Table 11 for test specifications.
tRC
Addresses Stable
tACC
Addresses
CE#
tDF
tOE
OE#
tOEH
WE#
tCE
tOH
HIGH Z
HIGH Z
Output Valid
Outputs
RESET#
RY/BY#
0 V
Figure 13. Read Operations Timings
34
Am29LV160D
May 5, 2006 22358B7
D A T A S H E E T
AC CHARACTERISTICS
Hardware Reset (RESET#)
Parameter
JEDEC
Std
Description
Test Setup
Max
All Speed Options
Unit
RESET# Pin Low (During Embedded Algorithms)
to Read or Write (See Note)
t
t
20
µs
READY
RESET# Pin Low (NOT During Embedded
Algorithms) to Read or Write (See Note)
Max
500
ns
READY
t
RESET# Pulse Width
Min
Min
Min
Min
500
50
20
0
ns
ns
µs
ns
RP
t
RESET# High Time Before Read (See Note)
RESET# Low to Standby Mode
RY/BY# Recovery Time
RH
t
RPD
t
RB
Note: Not 100% tested.
RY/BY#
CE#, OE#
RESET#
tRH
tRP
tReady
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
tReady
RY/BY#
tRB
CE#, OE#
RESET#
tRP
Figure 14. RESET# Timings
22358B7 May 5, 2006
Am29LV160D
35
D A T A S H E E T
AC CHARACTERISTICS
Word/Byte Configuration (BYTE#)
Parameter
Speed Options
JEDEC
Std
Description
-70
-90
5
-120
Unit
ns
t
t
t
t
CE# to BYTE# Switching Low or High
BYTE# Switching Low to Output HIGH Z
BYTE# Switching High to Output Active
Max
Max
Min
ELFL/ ELFH
FLQZ
25
70
30
90
30
ns
120
ns
FHQV
CE#
OE#
BYTE#
t
ELFL
Data Output
(DQ0–DQ14)
Data Output
(DQ0–DQ7)
BYTE#
DQ0–DQ14
DQ15/A-1
Switching
from word
to byte
Address
Input
DQ15
Output
mode
t
FLQZ
t
ELFH
BYTE#
BYTE#
Switching
from byte
to word
Data Output
(DQ0–DQ7)
Data Output
(DQ0–DQ14)
DQ0–DQ14
DQ15/A-1
mode
Address
Input
DQ15
Output
t
FHQV
Figure 15. BYTE# Timings for Read Operations
CE#
The falling edge of the last WE# signal
WE#
BYTE#
t
SET
(t
)
AS
t
(t
)
HOLD AH
Note: Refer to the Erase/Program Operations table for t and t specifications.
AS
AH
Figure 16. BYTE# Timings for Write Operations
Am29LV160D
36
May 5, 2006 22358B7
D A T A S H E E T
AC CHARACTERISTICS
Erase/Program Operations
Parameter
Speed Options
JEDEC
Std
Description
-70
-90
90
0
-120
Unit
ns
t
t
Write Cycle Time (Note 1)
Address Setup Time
Address Hold Time
Data Setup Time
Min
Min
Min
Min
Min
Min
70
120
AVAV
WC
t
t
ns
AVWL
WLAX
DVWH
WHDX
AS
AH
DS
DH
t
t
45
35
45
45
0
50
50
ns
t
t
ns
t
t
Data Hold Time
ns
t
Output Enable Setup Time
0
ns
OES
Read Recovery Time Before Write
(OE# High to WE# Low)
t
t
Min
0
ns
GHWL
GHWL
t
t
CE# Setup Time
Min
Min
Min
Min
Typ
Typ
Typ
Min
Min
Max
0
0
ns
ns
ns
ns
ELWL
WHEH
WLWH
WHWL
CS
CH
WP
t
t
CE# Hold Time
t
t
Write Pulse Width
Write Pulse Width High
35
35
30
5
50
t
t
WPH
Byte
t
t
t
t
Programming Operation (Note 2)
µs
WHWH1
WHWH2
WHWH1
Word
7
Sector Erase Operation (Note 2)
0.7
50
0
sec
µs
WHWH2
t
V
Setup Time (Note 1)
CC
VCS
t
Recovery Time from RY/BY#
ns
RB
t
Program/Erase Valid to RY/BY# Delay
90
ns
BUSY
Notes:
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more information.
22358B7 May 5, 2006
Am29LV160D
37
D A T A S H E E T
AC CHARACTERISTICS
Program Command Sequence (last two cycles)
Read Status Data (last two cycles)
tAS
tWC
Addresses
555h
PA
PA
PA
tAH
CE#
OE#
tCH
tWHWH1
tWP
WE#
Data
tWPH
tCS
tDS
tDH
PD
DOUT
A0h
Status
tBUSY
tRB
RY/BY#
VCC
tVCS
Notes:
1. PA = program address, PD = program data, D
is the true data at the program address.
OUT
2. Illustration shows device in word mode.
Figure 17. Program Operation Timings
38
Am29LV160D
May 5, 2006 22358B7
D A T A S H E E T
AC CHARACTERISTICS
Erase Command Sequence (last two cycles)
Read Status Data
VA
tAS
SA
tWC
VA
Addresses
CE#
2AAh
555h for chip erase
tAH
tCH
OE#
tWP
WE#
tWPH
tWHWH2
tCS
tDS
tDH
In
Data
Complete
55h
30h
Progress
10 for Chip Erase
tBUSY
tRB
RY/BY#
VCC
tVCS
Notes:
1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”).
2. Illustration shows device in word mode.
Figure 18. Chip/Sector Erase Operation Timings
22358B7 May 5, 2006
Am29LV160D
39
D A T A S H E E T
AC CHARACTERISTICS
tRC
VA
Addresses
VA
VA
tACC
tCE
CE#
tCH
tOE
OE#
tOEH
WE#
tDF
tOH
Complement
High Z
High Z
DQ7
Valid Data
Complement
Status Data
True
DQ0–DQ6
Status Data
True
Valid Data
tBUSY
RY/BY#
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data
read cycle.
Figure 19. Data# Polling Timings (During Embedded Algorithms)
tRC
Addresses
CE#
VA
tACC
tCE
VA
VA
VA
tCH
tOE
OE#
WE#
tOEH
tDF
tOH
High Z
DQ6/DQ2
RY/BY#
Valid Status
(first read)
Valid Status
Valid Status
Valid Data
(second read)
(stops toggling)
tBUSY
Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read
cycle, and array data read cycle.
Figure 20. Toggle Bit Timings (During Embedded Algorithms)
40
Am29LV160D
May 5, 2006 22358B7
D A T A S H E E T
AC CHARACTERISTICS
Enter
Embedded
Erasing
Erase
Suspend
Enter Erase
Suspend Program
Erase
Resume
Erase
Erase Suspend
Read
Erase
Suspend
Program
Erase
Complete
WE#
Erase
Erase Suspend
Read
DQ6
DQ2
Note: The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an
erase-suspended sector.
Figure 21. DQ2 vs. DQ6 for Erase and
Erase Suspend Operations
Temporary Sector Unprotect
Parameter
JEDEC
Std
Description
Rise and Fall Time (See Note)
All Speed Options
Unit
t
V
Min
Min
500
ns
VIDR
ID
RESET# Setup Time for Temporary Sector
Unprotect
t
4
µs
RSP
Note: Not 100% tested.
12 V
RESET#
0 or 3 V
tVIDR
tVIDR
Program or Erase Command Sequence
CE#
WE#
tRSP
RY/BY#
Figure 22. Temporary Sector Unprotect/Timing Diagram
22358B7 May 5, 2006
Am29LV160D
41
D A T A S H E E T
AC CHARACTERISTICS
VID
VIH
RESET#
SA, A6,
A1, A0
Valid*
Sector Protect/Unprotect
60h 60h
Valid*
Valid*
Status
Verify
40h
Data
Sector Protect: 150 µs
Sector Unprotect: 15 ms
1 µs
CE#
WE#
OE#
Note: For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.
Figure 23. Sector Protect/Unprotect Timing Diagram
42
Am29LV160D
May 5, 2006 22358B7
D A T A S H E E T
AC CHARACTERISTICS
Alternate CE# Controlled Erase/Program Operations
Parameter
Speed Options
JEDEC
Std
Description
-70
-90
90
0
-120
Unit
ns
t
t
Write Cycle Time (Note 1)
Address Setup Time
Address Hold Time
Data Setup Time
Min
Min
Min
Min
Min
Min
70
120
AVAV
AVEL
ELAX
DVEH
EHDX
WC
t
t
ns
AS
AH
DS
DH
t
t
45
35
45
45
0
50
50
ns
t
t
ns
t
t
Data Hold Time
ns
t
Output Enable Setup Time
0
ns
OES
Read Recovery Time Before Write
(OE# High to WE# Low)
t
t
t
Min
0
ns
GHEL
WLEL
GHEL
t
WE# Setup Time
WE# Hold Time
Min
Min
Min
Min
Typ
Typ
Typ
0
0
ns
ns
ns
ns
WS
t
t
EHWH
WH
t
t
CE# Pulse Width
CE# Pulse Width High
35
35
30
5
50
ELEH
CP
t
t
CPH
EHEL
Byte
t
t
t
t
Programming Operation (Note 2)
Sector Erase Operation (Note 2)
µs
WHWH1
WHWH1
Word
7
0.7
sec
WHWH2
WHWH2
Notes:
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more information.
22358B7 May 5, 2006
Am29LV160D
43
D A T A S H E E T
AC CHARACTERISTICS
555 for program
PA for program
2AA for erase
SA for sector erase
555 for chip erase
Data# Polling
Addresses
PA
tWC
tWH
tAS
tAH
WE#
OE#
tGHEL
tWHWH1 or 2
tCP
CE#
Data
tWS
tCPH
tDS
tBUSY
tDH
DQ7#
DOUT
tRH
A0 for program
55 for erase
PD for program
30 for sector erase
10 for chip erase
RESET#
RY/BY#
Notes:
1. PA = program address, PD = program data, DQ7# = complement of the data written to the device, D
device.
= data written to the
OUT
2. Figure indicates the last two bus cycles of the command sequence.
3. Word mode address used as an example.
Figure 24. Alternate CE# Controlled Write Operation Timings
44
Am29LV160D
May 5, 2006 22358B7
D A T A S H E E T
ERASE AND PROGRAMMING PERFORMANCE
Parameter
Typ (Note 1)
Max (Note 2)
Unit
s
Comments
Sector Erase Time
Chip Erase Time
0.7
25
5
15
Excludes 00h programming
prior to erasure (Note 4)
s
Byte Programming Time
Word Programming Time
150
210
33
µs
µs
s
7
Excludes system level
overhead (Note 5)
Byte Mode
Word Mode
11
7.2
Chip Programming Time
(Note 3)
21.6
s
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 3.0 V V , 1,000,000 cycles. Additionally,
CC
programming typicals assume checkerboard pattern.
2. Under worst case conditions of 90°C, V = 2.7 V, 1,000,000 cycles.
CC
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum program times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 9
for further information on command definitions.
6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles.
LATCHUP CHARACTERISTICS
Description
Min
Max
Input voltage with respect to V on all pins except I/O pins
(including A9, OE#, and RESET#)
SS
–1.0 V
12.5 V
Input voltage with respect to V on all I/O pins
–1.0 V
V
+ 1.0 V
CC
SS
V
Current
–100 mA
+100 mA
CC
Includes all pins except V . Test conditions: V = 3.0 V, one pin at a time.
CC
CC
TSOP AND SO PIN CAPACITANCE
Parameter
Symbol
Parameter Description
Input Capacitance
Test Setup
Typ
6
Max
7.5
12
Unit
pF
C
V
= 0
IN
IN
C
Output Capacitance
Control Pin Capacitance
V
= 0
8.5
7.5
pF
OUT
OUT
C
V
= 0
IN
9
pF
IN2
Notes:
1. Sampled, not 100% tested.
2. Test conditions T = 25°C, f = 1.0 MHz.
A
DATA RETENTION
Parameter
Test Conditions
150°C
Min
10
Unit
Years
Years
Minimum Pattern Data Retention Time
125°C
20
22358B7 May 5, 2006
Am29LV160D
45
D A T A S H E E T
PHYSICAL DIMENSIONS*
TS 048—48-Pin Standard TSOP
Dwg rev AA; 10/99
* For reference only. BSC is an ANSI standard for Basic Space Centering.
46
Am29LV160D
May 5, 2006 22358B7
D A T A S H E E T
PHYSICAL DIMENSIONS
TSR048—48-Pin Reverse TSOP
Dwg rev AA; 10/99
* For reference only. BSC is an ANSI standard for Basic Space Centering.
22358B7 May 5, 2006
Am29LV160D
47
D A T A S H E E T
PHYSICAL DIMENSIONS
FBC048—48-Ball Fine-Pitch Ball Grid Array (FBGA)
8 x 9 mm
Dwg rev AF; 10/99
48
Am29LV160D
May 5, 2006 22358B7
D A T A S H E E T
PHYSICAL DIMENSIONS
SO 044—44-Pin Small Outline Package
Dwg rev AC; 10/99
22358B7 May 5, 2006
Am29LV160D
49
D A T A S H E E T
REVISION SUMMARY
Ordering Information
Revision A (January 1999)
Added dash to OPN.
The Am29LV160D is fully form, fit, and function com-
patible with the Am29LV160B device, with the
following differences:
Revision B+2 (November 7, 2000)
Global
A 70 ns device at full voltage range is now available.
The 80 ns speed option has been deleted.
Deleted Preliminary status from data sheet. Deleted
burn-in option. Added table of contents.
Byte and word programming times, and byte- and
word-mode chip programming times are now reduced.
Revision B+3 (November 10, 2000)
Command Definitions
At extended temperatures (>+85°C), sleep and
standby currents increase.
Reset Command: Deleted reference to Figure 14, RE-
SET# Timings, which applies only to hardware reset.
Revision A+1 (April 19, 1999)
Global
Revision B+4 (April 5, 2004)
Erase/Program Operations
Reclassified the document from advance information
to preliminary.
Changed standard parameter t
from Min to Max.
BUSY
The 70 ns speed option is now also available with the
industrial and extended temperature range ratings.
Revision B+5 (June 4, 2004)
Ordering Information
Revision B (November 23, 1999)
Added Pb-Free OPNs.
AC Characteristics—Figure 17. Program
Operations Timing and Figure 18. Chip/Sector
Erase Operations
Revision B+6 (October 7, 2004)
Cover Sheet and Title Page
Deleted t
high.
and changed OE# waveform to start at
GHWL
Added notation to superseding document.
Physical Dimensions
Revision B7 (May 5, 2006)
Updated migration and obsolescence statement on
cover page and first page of data sheet.
Replaced figures with more detailed illustrations.
Revision B+1 (February 22, 2000)
Global
Updated trademarks.
Added dash to speed options.
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without limita-
tion, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as con-
templated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the
public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,
aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for
any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to
you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor de-
vices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design mea-
sures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating
conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign
Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior au-
thorization by the respective government entity will be required for export of those products.
Trademarks
Copyright © 1999–2006 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.
ExpressFlash is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
50
Am29LV160D
May 5, 2006 22358B7
相关型号:
©2020 ICPDF网 联系我们和版权申明